Interfacing PICmicros™ to an LCD Module - AN587

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    1997 Microchip Technology Inc. DS00587B-page 1

    M

    INTRODUCTION

    This application note interfaces a micrange PICmicro

    device to a Hitachi

    LM032L LCD character display

    module, with a two line by twenty character display. LCD

    modules are useful for displaying text information from a

    system. In large volume applications, the use of custom

    LCD displays becomes economical. The routines pro-vided should be a good starting point for users whose

    applications implement a custom LCD. This source code

    should be compatible with the PIC16C5X devices, after

    modifications for the special function register

    initialization, but has not been verified on those devices.

    OPERATION

    The Hitachi LM032L LCD character display module can

    operate in one of two modes. The first (and default)

    mode is the 4-bit data interface mode. The second is

    the 8-bit data interface mode. When operating in 4-bit

    mode, two transfers per character / command are

    required. 8-bit mode, though easier to implement (less

    program memory) requires four additional I/O lines.

    The use of 8-bit mode is strictly a program memory size

    vs. I/O trade-off. The three most common data inter-

    faces from the microcontroller are:

    1. An 8-bit interface.

    2. A 4-bit interface, with data transfers on the high

    nibble of the port.

    3. A 4-bit interface, with data transfers on the low

    nibble of the port.

    The LCD module also has three control signals, Enable

    (E), Read/Write (R_W), and Register Select (RS). The

    function of each control signal is shown in Table 1.

    Author: Mark Palmer

    Code: Mark Palmer/Scott Fink

    Microchip Technology Inc.

    TABLE 1: CONTROL SIGNAL FUNCTIONS

    A single source file, with conditional assembly is used

    to generate each of these three options. This requires

    two flags. The flags and their results are shown in

    Table 2.

    TABLE 2: CONDITIONAL ASSEMBLYFLAGS

    Control

    SIgnalFunction

    E Causes data/control state to be latched

    Rising Edge = Latches control state

    (RS and R_W)

    Falling Edge = Latches data

    RS Register Select Control

    1 = LCD in data mode

    0 = LCD in command mode

    R_W Read / Write control1 = LCD to write data

    0 = LCD to read data

    Flags

    Four_bit Data_HI

    Result

    1 0

    4-bit mode. Data

    transferred on the low

    nibble of the port.

    1 1

    4-bit mode. Data

    transferred on the high

    nibble of the port.

    0 x

    8-bit mode.

    AN587

    Interfacing PICmicros to an LCD Module

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    AN587

    DS00587B-page 2

    1997 Microchip Technology Inc.

    Figure 1, Figure 2, and Figure 3 show the block dia-

    grams for the three different data interfaces. The

    LCD_CNTL and LCD_DATA lines are user definable to

    their port assignment. This is accomplished with

    EQUate statements in the source code. See Appendi-

    ces B, C, and D.

    FIGURE 1: 8-BIT DATA INTERFACE

    FIGURE 2: 4-BIT MODE; DATA TRANSFERRED ON THE HIGH NIBBLE OF THE PORT

    FIGURE 3: 4-BIT MODE; DATA TRANSFERRED ON THE LOW NIBBLE OF THE PORT

    LCD_CNTL

    LCD_DATA

    R1 (10 k)

    R2 (330)

    LM032L

    RS (4)

    R_W (5)

    E (6)

    DB7 (14) : DB0 (7)

    VCC (2)

    VO (3)

    VSS (1)

    PIC16CXXX

    Port

    Port

    LCD_CNTL

    LCD_DATA

    R1 (10 k)

    R2 (330)

    LM032L

    RS (4)

    R_W (5)

    E (6)

    DB7 (14) : DB4 (11)

    VCC(2)

    VO(3)

    VSS(1)

    PIC16CXXX

    Port

    Port

    DB3 (10) : DB0 (7)

    LCD_CNTL

    LCD_DATA

    R1 (10 k)

    R2 (330)

    LM032L

    RS (4)

    R_W (5)

    E (6)

    DB7 (14) : DB4 (11)

    VCC (2)

    VO (3)

    VSS (1)

    PIC16CXXX

    Port

    Port

    DB3 (10) : DB0 (7)

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    1997 Microchip Technology Inc. DS00587B-page 3

    AN587

    LCDs (drivers) are slow devices when compared to

    microcontrollers. Care must be taken from having

    communication occur too quickly. The software will

    need to control communicaton speed and timing to

    ensure the slow LCD and fast microcontroller can stay

    synchronized. The timing requirements of the LM032L

    are shown in Appendix A. We recommend that the

    complete specifications of the LM032L be acquiredfrom Hitachi or a Hitachi distributor. The literature num-

    bers are CE-E613Q and M24T013 for a LM032L dis-

    play driver.

    When the module powers up, the default data transfer

    mode is 8-bit. The initialization sequence only requires

    commands that are 4-bit in length. The last initialization

    command needs to specify the data transfer width (4-or

    8-bit). Then a delay of 4.6 ms must be executed before

    the LCD module can be initialized. Some of the LCD

    module commands are:

    1 or 2 lines of characters

    Display on /off

    Clear display Increment / do not increment character address

    pointer after each character

    Load character address pointer

    The initialization flow for the module is shown in

    Figure 4.

    FIGURE 4: INITIALIZATION FLOW FOR LCD MODULE

    Power ON

    1) When interface is 8 bits long:

    Wait more than 1.5 msafter VDD rises to 4.5V

    RS0

    R/W0

    DB70

    DB60

    DB51

    DB41

    DB3x

    DB2x

    DB1x

    DB0x

    Wait more than 4.1 ms

    RS0 R/W0 DB70 DB60 DB51 DB41 DB3x DB2x DB1x DB0x

    Wait more than 100 s

    RS0

    R/W0

    DB70

    DB60

    DB51

    DB41

    DB3x

    DB2x

    DB1x

    DB0x

    RS0

    R/W0

    DB70

    DB60

    DB51

    DB41

    DB3N

    DB2F

    DB1x

    DB0x

    0 0 0 0 0 0 1 0 0 0

    0 0 0 0 0 0 0 0 0 1

    0 0 0 0 0 0 0 1 I/D S

    Initialization ends

    Power ON

    Wait more than 1.5 msafter VDD rises to 4.5V

    RS0

    R/W0

    DB70

    DB60

    DB51

    DB41

    Wait more than 4.1 ms

    RS0

    R/W0

    DB70

    DB60

    DB51

    DB41

    Wait more than 100 s

    RS0

    R/W0

    DB70

    DB60

    DB51

    DB41

    RS0

    R/W0

    DB70

    DB60

    DB51

    DB40

    0 0 0 0 1 00 0 N F x x

    0 0 0 0 0 00 0 1 0 0 0

    0 0 0 0 0 00 0 0 1 0 1

    0 0 0 0 0 00 0 0 1 I/D S

    Initialization ends

    1) When interface is 4 bits long:

    BF cannot be checked before this instruction

    Function set (interface is 8 bits long)

    Function set (set interface to be 4 bits long).

    Function Set

    Display OFF

    Display ON

    Entry Mode Set

    Interface is 8/4 bits long.Specify the number ofdisplay lines and characterfont.

    The number of display linesand character font cannotbe changed afterwards.

    Interface is 8 bits long.

    BF cannot be checked before this instruction

    Function set (interface is 8 bits long)

    BF cannot be checked before this instruction

    Function set (interface is 8 bits long)

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    1997 Microchip Technology Inc. DS00587B-page 5

    AN587

    APPENDIX A:LM032L TIMING REQUIREMENTS

    TABLE A-1: TIMING CHARACTERISTICS

    FIGURE A-1: DATA WRITE INTERFACE TIMING

    FIGURE A-2: DATA READ INTERFACE TIMING

    Parameter # Symbol Characteristics Min. Typ. Max. Unit

    1 TCYC Enable cycle time 1.0 s

    2 PWEH Enable pulse width 450 s3 TER, TEF Enable rise / fall time 25 s

    4 TAS RS, R/W set-up time 140 s

    5 TDDR Data delay time 320 s

    6 TDSU Data setup time 195 s

    7 TH Hold time 20 s

    Note: Refer to Hitachi documentation for the most current timing specifications.

    RS

    R/W

    E

    DB7:DB0

    2.2V0.6V

    4

    0.6V

    2

    0.6V

    2.2V 2.2V

    2.2V

    0.6V

    0.6V 0.6V

    0.6V0.6V

    0.6V

    2.2V 2.2V

    6

    37

    7

    3

    1

    ValidData

    RS

    R/W

    E

    DB7:DB0

    2.2V0.6V

    4

    0.6V

    2

    2.2V

    2.2V 2.2V

    2.2V

    2.2V

    0.6V 0.6V

    0.4V0.4V

    0.6V

    2.2V 2.2V

    5

    3

    7

    7

    3

    1

    ValidData

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    AN587

    DS00587B-page 6 1997 Microchip Technology Inc.

    TABLE A-2: LM032L PIN CONNECTION

    Pin No. Symbol Level Function

    1 VSS 0V Ground

    2 VDD +5V Power Supply(+)

    3 VO Ground

    4 RS H/L L: Instruction Code InputH: Data Input

    5 R/W H/L H: Data Read (LCD moduleMPU)

    L: Data Write (LCD moduleMPU)

    6 E H,HL Enable Signal

    7 DB0 H/L

    8 DB1 H/L

    9 DB2 H/L

    10 DB3 H/L Data Bus Line

    11 DB4 H/L Note (1), (2)

    12 DB5 H/L

    13 DB6 H/L

    14 DB7 H/L

    In the HD44780, the data can be sent in either two 4-bit operations or one 8-bit operation, This flexibility allows an

    interface to both 4- and 8-bit MPUs.

    Note 1: When interface data is 4-bits long, data is transferred using only 4 lines of DB7:DB4 (DB3:DB0 are not

    used). Data transfer between the HD44780 and the MPU completes when 4-bits of data is transferred twice.

    Data of the higher order 4 bits (contents of DB7:DB4 when interface data is 8-bits long) is transferred first

    and then lower order 4 bits (contents of DB3:DB0 when interface data is 8-bits long).

    2: When interface data is 8-bits long, data is transferred using 8 data lines of DB7:DB0.

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    DS00587B-page

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    APPENDIX B:8-BIT DATA INTERFACE LISTINGMPASM 01.40.01 Intermediate LM032L.ASM 4-7-1997 9:43:02 PAGE 1

    LOC OBJECT CODE LINE SOURCE TEXT

    VALUE

    00001 LIST P=16C64

    00002 ERRORLEVEL -302

    00003 ;

    00004 ; This program interfaces to a Hitachi (LM032L) 2 line by 20 character display

    00005 ; module. The program assembles for either 4-bit or 8-bit data interface, depen

    00006 ; on the value of the 4bit flag. LCD_DATA is the port which supplies the data t

    00007 ; the LM032L, while LCD_CNTL is the port that has the control lines ( E, RS, RW

    00008 ; In 4-bit mode the data is transfer on the high nibble of the port ( PORT

    00009 ;

    00010 ; Program = LM032L.ASM

    00011 ; Revision Date: 5-10-94

    00012 ; 1-22-97 Compatibility with MPASMWIN 1.40

    00013 ;

    00014 ;

    00015 include

    00001 LIST

    00002 ; P16C64.INC Standard Header File, Version 1.01 Microchip Technology, Inc.

    00238 LIST

    00016

    0000009F 00017 ADCON1 EQU 9F

    00018

    00000000 00019 FALSE EQU 0

    00000001 00020 TRUE EQU 1

    00021

    00022 include

    00069 list

    00023 ;00000001 00024 Four_bit EQU TRUE ; Selects 4- or 8-bit data transfers

    00000000 00025 Data_HI EQU FALSE ; If 4-bit transfers, Hi or Low nibble

    00026 ;

    00027 ;

    00028 if ( Four_bit && !Data_HI )

    00029 ;

    00000006 00030 LCD_DATA EQU PORTB

    00000086 00031 LCD_DATA_TRIS EQU TRISB

    Please check the Microchip BBS for the latest version of the source code. Microchips Worldwide Web Address: www.microchip

    MCHIPBBS using CompuServe(CompuServe membership not required).

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    00032 ;

    00033 else

    00034 ;

    00035 LCD_DATA EQU PORTD

    00036 LCD_DATA_TRIS EQU TRISD

    00037 ;

    00038 endif

    00039 ;

    00000005 00040 LCD_CNTL EQU PORTA

    00041 ;

    00042 ;

    00043 ;

    00044 ; LCD Display Commands and Control Signal names.

    00045 ;

    00046 if ( Four_bit && !Data_HI )

    00047 ;

    00000000 00048 E EQU 0 ; LCD Enable control line

    00000001 00049 RW EQU 1 ; LCD Read/Write control line

    00000002 00050 RS EQU 2 ; LCD Register Select control line

    00051 ;

    00052 else

    00053 ;

    00054 E EQU 3 ; LCD Enable control line

    00055 RW EQU 2 ; LCD Read/Write control line

    00056 RS EQU 1 ; LCD Register Select control line00057 ;

    00058 endif

    00059 ;

    00060 ;

    00000030 00061 TEMP1 EQU 0x030

    00062 ;

    0000 00063 org RESET_V ; RESET vector location

    0000 2808 00064 RESET GOTO START ;

    00065 ;

    00066 ; This is the Periperal Interrupt routine. Should NOT get here

    00067 ;

    00068 page

    0004 00069 org ISR_V ; Interrupt vector location

    0004 00070 PER_INT_V

    0004 1283 00071 ERROR1 BCF STATUS, RP0 ; Bank 00005 1407 00072 BSF PORTC, 0

    0006 1007 00073 BCF PORTC, 0

    0007 2804 00074 GOTO ERROR1

    00075 ;

    00076 ;

    00077 ;

    0008 00078 START ; POWER_ON Reset (Beginning of program

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    00502 page

    00503 ;

    0099 00504 Table

    0099 0782 00505 addwf PCL, F ;Jump to char pointed to in W reg

    009A 344D 00506 retlw M

    009B 3469 00507 retlw i

    009C 3463 00508 retlw c

    009D 3472 00509 retlw r

    009E 346F 00510 retlw o

    009F 3463 00511 retlw c

    00A0 3468 00512 retlw h

    00A1 3469 00513 retlw i

    00A2 3470 00514 retlw p

    00A3 3420 00515 retlw

    00A4 3454 00516 retlw T

    00A5 3465 00517 retlw e

    00A6 3463 00518 retlw c

    00A7 3468 00519 retlw h

    00A8 346E 00520 retlw n

    00A9 346F 00521 retlw o

    00AA 346C 00522 retlw l

    00AB 346F 00523 retlw o

    00AC 3467 00524 retlw g

    00AD 3479 00525 retlw y

    00AE 00526 Table_End00AE 3400 00527 retlw 0

    00528 ;

    00529 if ( (Table & 0x0FF) >= (Table_End & 0x0FF) )

    00530 MESSG Warning - User Definded: Table Table crosses page boundry in co

    00531 endif

    00532 ;

    00533

    00534

    00535

    00536 end

    MEMORY USAGE MAP (X = Used, - = Unused)

    0000 : X---XXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX

    0040 : XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX0080 : XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXX- ----------------

    All other memory blocks unused.

    Program Memory Words Used: 172

    Program Memory Words Free: 1876

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    Errors : 0

    Warnings : 0 reported, 0 suppressed

    Messages : 0 reported, 12 suppressed

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    DS00587B-page

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    APPENDIX C: 4-BIT DATA INTERFACE, HIGH NIBBLE LISTINGMPASM 01.40.01 Intermediate LM032L.ASM 4-7-1997 9:50:32 PAGE 1

    LOC OBJECT CODE LINE SOURCE TEXTVALUE

    00001 LIST P=16C64

    00002 ERRORLEVEL -302

    00003 ;

    00004 ; This program interfaces to a Hitachi (LM032L) 2 line by 20 character display

    00005 ; module. The program assembles for either 4-bit or 8-bit data interface, depen

    00006 ; on the value of the 4bit flag. LCD_DATA is the port which supplies the data t

    00007 ; the LM032L, while LCD_CNTL is the port that has the control lines ( E, RS, RW

    00008 ; In 4-bit mode the data is transfer on the high nibble of the port ( PORT

    00009 ;

    00010 ; Program = LM032L.ASM

    00011 ; Revision Date: 5-10-94

    00012 ; 1-22-97 Compatibility with MPASMWIN 1.40

    00013 ;

    00014 ;

    00015 include

    00001 LIST

    00002 ; P16C64.INC Standard Header File, Version 1.01 Microchip Technology, Inc.

    00238 LIST

    00016

    0000009F 00017 ADCON1 EQU 9F

    00018

    00000000 00019 FALSE EQU 0

    00000001 00020 TRUE EQU 1

    00021

    00022 include

    00069 list

    00023 ;

    00000000 00024 Four_bit EQU FALSE ; Selects 4- or 8-bit data transfers

    00000001 00025 Data_HI EQU TRUE ; If 4-bit transfers, Hi or Low nibble

    00026 ;

    00027 ;

    00028 if ( Four_bit && !Data_HI )

    00029 ;

    00030 LCD_DATA EQU PORTB

    00031 LCD_DATA_TRIS EQU TRISB

    Please check the Microchip BBS for the latest version of the source code. Microchips Worldwide Web Address: www.microchip

    MCHIPBBS using CompuServe(CompuServe membership not required).

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    00502 page

    00503 ;

    0083 00504 Table

    0083 0782 00505 addwf PCL, F ; Jump to char pointed to in W reg

    0084 344D 00506 retlw M

    0085 3469 00507 retlw i

    0086 3463 00508 retlw c

    0087 3472 00509 retlw r

    0088 346F 00510 retlw o

    0089 3463 00511 retlw c

    008A 3468 00512 retlw h

    008B 3469 00513 retlw i

    008C 3470 00514 retlw p

    008D 3420 00515 retlw

    008E 3454 00516 retlw T

    008F 3465 00517 retlw e

    0090 3463 00518 retlw c

    0091 3468 00519 retlw h

    0092 346E 00520 retlw n

    0093 346F 00521 retlw o

    0094 346C 00522 retlw l

    0095 346F 00523 retlw o

    0096 3467 00524 retlw g0097 3479 00525 retlw y

    0098 00526 Table_End

    0098 3400 00527 retlw 0

    00528 ;

    00529 if ( (Table & 0x0FF) >= (Table_End & 0x0FF) )

    00530 MESSG Warning - User Definded: Table Table crosses page boundry in co

    00531 endif

    00532 ;

    00533

    00534

    00535

    00536 end

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    MEMORY USAGE MAP (X = Used, - = Unused)

    0000 : X---XXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX

    0040 : XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX

    0080 : XXXXXXXXXXXXXXXX XXXXXXXXX------- ---------------- ----------------

    All other memory blocks unused.

    Program Memory Words Used: 150

    Program Memory Words Free: 1898

    Errors : 0

    Warnings : 0 reported, 0 suppressed

    Messages : 0 reported, 12 suppressed

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    5/8/97

    All rights rese rved. 1997, Microchi p Technology Inco rpor ated, USA. 6/97

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