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DEPARTMENT OF THE AIR FORCE

CoAIR UNIVERSITY (ATC)

AIR FORCE INSTITUTE OF TECHNOLOGY

Wright-Patterson Air Force Base, Ohio

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CONTINUED DEVELOPMENT

OF THE

UNIVERSAL NETWORK INTERFACE DEVICE

'PHES IS

Presented to the Faculty of the School of Enineering

of the Air Force Insti.tute of Technology

Air U1niversity

in Partial Fulfillment of the

Requirements for the Degree ot

Master of Science ~ c95~l~W -

STAB

Distriuin

IIL

f l e c ti'i', 1 a

Ap ro e for t0'hli i ,j ;,ri i' i t ft,'

4'

The purpose of this investigation was to continue the

development of the Universal. Network Interface Device (UNTI').

This involved the design and construction of a new memory

board which incorporated two previously constructed memory

boards. This investigation was limited to the developnient

and testing of, that new board and the UNID itself.

I would like to thank my thesis advisor, Dr. Ga.ry

Lamont, for his assistance and encouragement durini Owp

course of this investigation. I would also like to thaink .iy

readers for their valuable comments and aid in this stu0y.

The high quality support of the lab engineers and techni.can.;

saved me much valuable time and I would like to thank ;rl

particular, Cpt. Lee Baker, Dan Zambon, and Orville wriohl.:

tor their excellent support during the construction ..*IjI

* testing phases of this study. Finally, I wish to acknow-, it.

my gratitude to my wife, Linda, frr her encourageiit-uL fnti

understanding during this effort.

.1

'I

Page

Preface . . . . . . . . . . .. . . . . . . . . . .o o o

List of Pigures . . . . . . a o a . # o . . .o * v

a cntroduct n . . . . . . . . . . . .................

B a c k g r o u n d , .. . . . .. . o o 0 0 * 0 0. . 0 . . . . . .

Scope . . . . . . o . . . . * . . ..- A p p r o a c h .. . . . . . . .....0 0 0 0 0 0 . .0 0 . . .Overview. . . . . . . .. .. . . . . . . . . 0

II. Requirements and Design. . . . .. . .. . *1

UNID Requirements Summary . . .

DELNET Requirements Summary ...... .........DELNET Design Summary . . .... ..............UNID Design Summary . o . . ....... ',:." UNID Implementation .. .... . .. ')'"Documentatio o a * 0. .0 .

Summ *y. 00 * pIII UDIpeeton Moift.n . . . . . . . .... . ...

Power Supply. . . . . . . . . . . . . . .. ..... 1V I.UNID pdeat .on .Modifcton o 2.!....

Construction of the System Memory Card. . o. o.

Design of the Memory Cards. o ...... .....Construction of the Memory Cards. ...... .

[ iSumma ry . . . . . ... . . . . . . . . . . .

IV. Testing . . . . . . . . . . . .... .. ........

UNID Testing Methods. . . ...........Power-off Testing . . . . . . . .. . . ...... . ..Power-on Testing . . . . . . . . ....... 'Functional. Testn ". . ............... ..Local Processor Co.r(! "esting ............Shared Memory Carct ',eftino. .................Network Processor (,tr(I '"-ting ................Local Card 'st:in. ...................System Memory Cart( "' .. . . ..............Memory C(ird 'IeP',f; (. .. .... . . . ........ .

-. Des itqn ''au~ts............................

Integrated Cirvu't- . ...... ..Memory "'iminq 'a' ................. ..YN1 '!'estinq. . . . . ................Smnary o . .. . ...............

i ii

., Page

V. Summary and Recommendations .. .38

UNID Completion . . .... . . .... ... . .38UNID Testing . . . . 38Recommendations . . . . 39

Bibliography. . . . . . . . . . . . . . . . . . . . . . . .41

Appendix A: Circuit Card Layouts . . . . . . . . . . . . .44

Appendix B: Circuit Card Schematics. . . . . . . . . . .

Appendix C: Wiring List Program . . . . . . . . . . . . . .60

.

- .-

Figure hq C

2-1 DELNET Topology. ......... *....* **.16

2-2 Proposed DELNET Configuration. .. . . . . . . ...

2-3 UNID Block Diagram . ....... 1

OF.

Abstract

NThe objective of this investigation was to design and

construct two memory boards for the Digital Engineerinq

Laboratory Network's (DELNET's) Universal Network Intet.ace

Devices (UNIDs). The UNID is a flexible message processor

designed for computer communications network applicatii ,.;.

The new memory boards incorporated the proto'. vjp.

microcomputer based message processor memory boards of tt1e

previous theses. Using the existing memory boaro,., ,,.

memory boards were designed, constructed, tested, J,,

documented. The results of this effort were the e iuiir,, fi-

of unreliable RAM the reduction ii h. number o 0 t-r-u'it

boards used in the NJD, and two operational UNlIl.;.

"°""

CONTINUED DEVELOPMENTOF THE

UNIVERSAL NETIWORK INTERFACE DEVICE

I. Introduction

The purpose of this investigation was to continue the

development of an operational microcomputer based rnes.ia(1e

processor with the inherent flexibility to permit itLs

utilization in different types of data communications network

applications. The need for a universal network device wos

first proposed by the Air Force Communication Service (A1',;c1

(28). There have been four previous investio'iiot

(22,5,1,17) into the development of a universal tiet-wUrk

interface device, and this irnvestiqaiL"1-- represents the fifth

phase of the study effort towards an operating devicki.

The remaining sections of this chapter will ed~

*background information, foll owed by the scope, aipproach, orkl

overview of the work covered i~n this thesis.

Bacgrund1

Computer network theory and app]i icat. i on, Is~v

over the past decade, enjoys widespread attcnti

Computer networks have htcoome an att racti vIe aH I L I

increasing computat ionol DOWe 1. -r.id ,;!Ia r i nI

resources. Undoubtedly the most. iuc~Ce,,;'1*L1 -x II-,

computer networks is 'the cur rect:t Pc -ft-1se AI1V~jn.:.-

Project Aqrencies Network ".. ''t

n.ttwork not: )II ro.*r -:,It it III tt

.. ?..

but also establishes network theory for later applicatiorts

(14:5-23) . One application of that theory is the CFIF:',

(Computer Science Network). While the ARPANET is, or at

*[ least tries to be, a closed society limited to people who are

working on Department of Defense contracts, CSNEI' o

provide network services to the entire U.S. computer ,114A!

community (2).

Unfortunately, an internatlonai network of thi Ize

cannot be tailored to the needs of all potential network

users. Using the ARPANET as a simple computer network

interconnecting various minicom,uters and microcomputers 1:;

impractical. These machines riay not need the reg;oiirc,:.,

available through the ARPANT. A cost-ef Fect- i ve HI,,

efficient computer network, dedicated to the;, ,''.

machines, would be more desirable. Such a compute, nt-"!,.'.

is commonly known as a local network (23:286-323).

Local networks talored to a pai jicular organlzi I im,.8.,

interconnecting minicomputers became practical with .

advent of the microprocesor, r. Thu. microprocessor w,;

first development in su,!or t- or local networks hj,'l.

- allowed economic network nodes to be developed. These r',

" were cost-cffective i(4 v-t of 1 oaded much 0 F tht. . ,

-protocol t)rocessinq overht id( r oni the COmptluter ht.; ',

network. ''hi S inad(e i t o c ti( (-,:i' for orq., ;.tj. I:

Slocal networ k of microcoru iverr t 1 i r n u o-

mainframe comt)tt pr.

A 5f '4 ', (" - i. n c,,F,- .II

* 2

A 7

networks was research into the design of routing algorithms

and the techniques of flow control. Obviously, routing

algorithms and flow control have direct impact on 1r,c1.

network applications. An efficient routing algorithn, insur-s

that messages reach their destinations with a miniRtI,, d.1ay

(20:213-241). Likewise, sound flow control techniques wi.il

limit congestion on the network (20:242-258). Cur rentl,

these research efforts are yielding positive result-s for

network applications.

A third important development for local networks came

with an understanding of the need For network protocols.

Protocols permit one machine to communicate with another

machine through rules governinq the timing and formatting of

the data to be exchanged (1 :35). Many dil-fvrent protocols

and associated levels are now available wi th some mowv-meit

toward standardization. The tirst p, ot:oco!s were dove 1(l,,

.,

" *as part of scientific research projects under ARPANF,' mi

French Cyclades network (]3:67-69). Commercial manfir,,'turr:

have also developed various protocols. T B M deI o1), 1,

binary synchronous communication (BirSYNC) protoco.1 (')': 1:101

and the System Network Architecttire (SNA) (1.3:70), lint'

introduced DECnet (Di (Ii to I FuI ple 11t Co rpor at.i o n n -

(13:69-70) . These art. vxamilo:i (it niachine deperidthi .

networks.

However, within the lmstt four year.-, wnte $ , i , -,

networks have become avai.1 ,Atre. lWhe:,fie t .

• --'. '.ct n t: ~. fnt:erf:zict ll y 4I f1 ". 'r t, n' U U II ",.

.:,, '..., .".,"-._. jL,,,. 2. .,.,

... ..-.. ,- .. -. ,. . ,. .'--.. . . ,, ,. . , . _ ,

examples are Ungermann-Bass's NET/ONE and Xerox's F:'!IIIJI.:TI'

(15,3). NET/ONE uses a network interface unit (NWU) bi It.It

around the Z80A microprocessor. The transmission medium is a

baseband coaxial cable capable of transmission speeds up to 4

*Mbps. The NIU is a significant feature of this network. A

single NIU can connect to the network any one of a 1 ,r',e

number of dissimilar machines. Reconfiguration of th,. ,,

for different machines is accomplished easily by 1 oiiii-

different software. Additionally, each NTW is i solatler ,i,

the network. Should one N TI fail, the rest of the ne vtuu

will not be affected. Further, NET/ONE NI[s contain Pio W-

the network protocols, making the network o i. . '1,

essentially transparent to both the user and the host (i.

The XTH ERNFT,' is si mil ar to NET/ONh, hut 'I('

resourceful (15). EI!HFl Th'!' does not use network intr,, 'It-I

units. This requires the ubscr1..L to hou.;e the netwtirk

overhead in his machine. Instead, a transceiver interfa:

each user t:o the network. '11i s transcei ver isol at-es t l.

network fromn user faLlI t 5 d!; W i (- s d ; COt 10t Is 1 2 ter

the baseband cable.

A base band ca hble I s (I t j re.. e 'lid1 si (lid I n(- i o Il

which sic ial.s are encoded ont: o t-he cahle. it. (,II!y

sinqi e dat-a channel and1 ul:t, bhe sIn)n.emerited wit. t,

of wirinq t o prov i. lon-t ,i-owiu ltl i ' ti (ca t Il

tvie si nol.u !dta char- l n (,,,..id nl worki Ir.

iav.nq c a i r a t e I t, ov r :dmrl 1. 11 C,

0 4iP

but reduced data rates from the effects of disnersjon

results. This is in contrast to a broadband cable which is a

unidirectional signal path. Both a transmit path and a

receive path must exist. This .s accomplished either by

splitting the available bandwidth into transmit and receive

channels on the same cable or by providing separate cables

for signal transmission and reception. Broadband supports

multi-mode communications, including audio, video, and data

on one cable pathway. Broadband networks have greatIr

distance capability (from over 1O00 feet up to sevural m.iltes

while retaining full bandwidth because they use zictivt.

amplifiers to distribute and extend the signal r..

Broadband allows for qreater distances than haselhand '-tit t,,:

data-rate decreases below 10 Mbps after several miles .

m u1In many countries, the covernment or private j,i,. 't

. began offering network services to any organizatioun

wished to subscribe (23:2H). These networks are ..o' I,,d

public networks similar to, and often part of, the r,'Wiic

telephone and utiliti es :;yst oetis. Such w id,(1 v av. i I ,

networks needed common atireement on some forn of bI t,, ,

With this approach many usets onerating di.i;i.ilar ti , r,'w' ,-

. could subscribe to fhis .;urv ce. I.n an effort tt . ,

standardized and compdti,!(' :erv ices throughout ' ,,.w

these countries coopierate throutih the I nt e Y Tat ona " 1 ',and Tele ~rarh Consit I taf-i vt- ij ek (CCT'."'. t .

recom!mendat4on.s" fo'r ov ' n vrit: 'yt.i citi

Setic e 1~'I c~ 97) 1 Cu, k I 41wr:

switching network operations have been adopted in recent

years, such as IBM's SNA, DEC's DECnet, Honeywell's

Distributed Systems Environment (DSE), the United Kingdom's

National Physics Laboratory (NPL) net and France's Cyclades

net (4). Most notably is the X.25 recommendation s:k!J 1yi i

the interface or protocol to be voluntarily adopted by i l.

manufacturers and users (13:71-73).

As local networks became more efficient and htt.-r

understood, the U. S. Air Force began evaluating ftnir

potential usefulness. In the past, telecommunicatioi:;

requirements on an Air Force base were met in a sin(oe ottl

straight forward manner by providing voice communication!- ,.,

telephone facilities, plus a few low-speed teletypewriii-, H,!

data circuits over base cable systems (28:2). Hfowevr, r ' ,

the tendency toward use of di. ita, processor,; to dcc' ,,ir '

base-level functions, the base-.evel. fie eco mni v' ,,wi

facilities needed to be reevaluated to insure tht. , ,

sipport the increased data communications needs (28:',

reevaluation was accomplished in the 1842 EPG/.."TC ', "

report TR 78-5 (28).

One facet of the 'R 7P-5 technical report i nv,.,

method of accompl i sh i nq the base-level. messa(,.t.

swi tchinn and distr!bution f,ctlons. At the- Ii:

0 stri uti on of: d at.a , n' ,)f ot-her tt'aff ic i i:n W

cnsideoration si nce it e 'lirxi ~tQ U.iu r I ( i • ,n

CO(M!iun Cztt ion r)a S.hs conntet: ro t-.helt ii- 0 , th.

*". L" . '"'1t ' t.L d rit"* , * ) t .: i.

* 6

anything else in the network and thus costs associated with

them are multiplied by a large factor.

To satisfy the base-level message and data switching,

and distribution functions, the report postulated the need to

connect any of the base digital processing devices to any

terminal on the base and also the need to connect any base

terminal to any other base terminal. To accomplish t h's

interconnection, the "1842" report suggested three differt.

types of network interconnectionsl the first was ii :Atr

communication network with a centralized dig.ital. .it i

* *- (28:162-163); the second was based upon the concepts l;(-,i in

the Advanced Research Proiect Agency (ARPA) network (28:',r. ,

and the last was the loop or ring network (28:164).

configuration the report finally recommended fwr 1',.

base-level data distribution network was a modificat!)i 9

the ring concept ca.led a multi-ring network. This-, ,-l.-. ,'

consisted of a number of rinq networks with a node i.t)v ,

interconnectivity between the rings. This muiti-rino it.,w,"

concept offered part.icui r advantages in teri,,; o ,

development, application, and flexibility. A key 4 o ttL

, multi-ring concept was the deve], ;...:i of five tyr" f

devices which could interface the fm i ie ri nos *:oe e:her

* o ,Rome Air Development Center wn.; t-Jisked w i inr::i,,

the problem of the interf ,it. Yvt , t WN-viS I-)ln !ot*

the various interface devi,.: i, ,,w:.(' t 4 ' :0 I. ,..t .

and were required to D)t-L 1)1 , $ r I ., .. '1'117:1 J I

apteared reasonable thi at+v,, ' , , 1

, . .7

device (UNID) could be developed which could meet the

separate requirements of each of the five proposed interface

.V devices of the multi-ring concept. The subseouent

development of the UNTD and a local network application

became the basis for numerous investigations. A preliminary

design for the UNID was written in 1978 (22). The buii!dinq

of a prototype UNID based on this design was begun in 1979

(5). In 1980, the building of the prototype continued,

modifications added, and the design refined (]). Also it,

1980, the development and deusiqn of a local computer network

for AFIT's Digital Engineering Laboratory Network (OEIA.")

was begun using the UNID and the loop network cornceptf- f' ).

In 1981, concurrent investigations (9,17) co,,I I'

development of the software for the DPLNIT, I

constructinq the prototype 11NID), nu i.1t a Second i''!,~j

implemented a prototype DF.1,NET.

The two UNIDs were used as nodes, forming a s inW.

network following a previous design (11). The pr,,, ,,.

network included two comptiter i and several terminal ,

fiberoptic communications link. Tohe major component i (-0

UNID were a card cage, nioht.rhoard, local proces;,, ,

network processor ca r d, -ha r ed memory c c, sO ,

card, local. card, an(' ricn w,, k crd (.7:2)

At present, a crlinir r rivesti (hI t] ()n V ,

development of sof twi tr Pi''I, ' I( - .,

investigat:ion, compl :',t'! ii, 1. 1v, t t vi,,te f.:

-- -- ~which the tUrt(!Vi LIS .,:ib I., ,,i I, ! , ,, . , ; .

r-J

"7 7

numerous quantity of dynamic RAM chips used in the system

memory produced transient signals caused by the continual

refresh. Circuit coupling and switching noise due to the

wire wraps also created problems.

The basic hardware for the UNID is constrained by the

design and implementation of previous investigators. -'is

investigation remained within these constraints and cotirIHu,.*d

the development of the UNTD. The recommendations in nreviot.s

theses were identified and implemented. These result,,} iri

the design and implementation of a new memory boatr ,',

S. combines the shared memory hoard with the system ,Iw &.,y

board.

This investigation elected to concentrate on ftsrtw.,,i.

implementation and to write software only as neces,%.-,v 4,

test that implementation. A co-investigator (10) s,,,i, ,i,,

most of the software support. Previously developed oX"wat,

was also used.

The development of the hINTD) suffered from the ',,,k ,

current documentation. ThIh, inrvcstiqation updated a :

connections, schematics, lists, et. , necessary Fr furlht:i

development. This int,o, ht ion Ij contaien e ;1 tho

nppendicies.

First, an opetat) *f. I , ti h

this investination no !w% "-j", W.; I V,, , i

fZI Or eS. Ijoxt, the It-flu'!'0! wIi'I Wrt: 0

9__.1 * - -

static RAM chips, reducing the number of ICs and elinmintirng

~j the circuit coupling and switching noise associated wit-h the

wire wraps. The reduction in TCs also el iminate d the

transient signals, caused by the continual refresh, wliich

were seriously affecting the reliabil1ity' of memory cont* rit.

Finally, both the system memory and shared memory boards were

combined onto one memory board reducing 112 memory chips used

*to only 10 memory chips. Sininle tests proved that the 11INTrT.;

* memory was now reliable.

This report covers hardware oi~esc of the 11111)

Chapter IT presents a summary of established reqjn.rt! ri&19 ; t

design followed by a discussion of modifications. f.uU'1 it<

*durinci this investiqation. C'hapter T111 Ov ti~

construction modifications made to the UNIT).r

testing of components iS dOCUntented in Chapter TV. C'h,,r r

summarizes the resul.ts of: th is investi'ljati on anti rc-comwi.

areas for further Study. P~i nil] Ty, the Appendi ciesi coi.,.ii

all hardware documentation.

10

This chapter summarizes the requirements and de:iqn

decisions established by previous theses (22,11,17). these

requirements come from the initial design as discusserd in

Chapter I. These decisions formed the guidelines for Thi.

investigation. This chapter is divided into six section;:

UNID requirements summary, DELNET requirements .. ;1 LIr 11dy,

DELNET design summary, UNITD design summary, ,!NjI)

implementation, and Documentation.

IMID Rezuremnts sau=Y_

In 1978, the 1842 EI.:G re!oort was used to Motivate t he

design of the UNID (22). 'Phe HINIM, being universal', w's

based on the followinq qenet~i coi' (t-tS 22113

-The UNID functions as a . tore-jn0---forwar1concentrator with lwssae rotti ( ,,:t'' ' ,

-The UNITD includes srwcialized I/O ports tohandle unique communicotion requirements.

-The IN.T.T) easily han,11 ,es vdricis networko p-raf-ing sy.' ems a,,d commmnirition protocol.;.

Using these concepts', st-ri)t:d ananl yis "

(SAT) , N!J T. ffunct i oni I (.1t,,I, 1; W:r (f

*(2 9, 22: 1.-1~) This anproic't i't-vt. 1 oi'ed an act i v i

consisting of a ;t-r t. s 0 n'! d orat,:i -,iow w '

functions and their ntu i ' t ' %V 1h

* sumnlarizino thiesne f'irtc'tiAF , ,' tf.iiIi .

* i

1. Communication Interface.

A. Flexibility.B. Signal Characteristics.C. Port Conficiuration.D. Protocol Software.

II. Local Information Processn.q

A. Receive local jflfouit,itj.on.B. Store information.C. Process local. inihirmation.D. Trransmiit informatLiorn to net work.

III. Network Information Processino.

A. Receive information from network.B. Process informatio from, network.C. Petransmit networke informai-ion on network.D. 'Transmit information to loc-al receiver.

I . Process coiitril. information.2. Transmit info)rmation to stibscriber.

Once these general ftunct- (Dna 1 ret-iiiireiuents wurc

broad UNID bounds necessary for subs~equent t141I n

allocation and desigqn phasies were establisheO. Pe'tW .,-

list of these initial- systemi hounds. just-if ic it'll

presented in (22:34-46')

-Unid modula rity Yba.-cO on ei rcuiL ca rd4,;

-SJynch tolotts se r 1a1 -' i 0,0a tiv) 11 *'i R1

-?.Iini. 1iiwilt of- one !- i' e)( +-wr~lrk T/i) I~-)

-RS-32Cinterf-ace(s f-mr 'occitI/ oort :

-One 1 oca 1. T/O nr! f r-2 '.(1 T-P -.% r r (.-n t: I1

The functional. rowii iti-wt~ l' ocation t i MI

and' sofftwcdrt was comWe' -- 4 1'Y", ' f " aTi:h l

A t ':!

i: Or:1t'

fu l w n -. s s m ,2;f (i

: '. .o .. _- .. • . . ° . . . . ° . . .. .-° - - - .'- ,. . - . . °...., .b. .* _ J _ .

FLocal Com znDet AMBIdwaLel

Recognize start of local information.Recognize end of local information.Recognize end of local message.Transmit local information.

'" ,.Netwogrk IZO -CoM. .ng. 1PR Udwaxt..

Recognize start of network information.Recopnize end of network information.

. Change serial information to parallel.-"'ransmit.network information.

21-" -SZQX coIuparneat .(if tws e).

Information to be transmi.ted.

Store outgoing local information.Convert to net.work character set.Identify ready to be processed information.Process informati on to be transmitted.Determine routini.Tnitialize t-ran",',itter.identify jnforina" on as sent.Deallocate storagje -pcice.

Information rece.ived.

Store incoming network i nfurmation.Determine i -1 error f ree.Process informp n,, "ro network.fifentify as re~t,-y to he tran:;mitted..denti fy ty'pe (itt, w i,, ,,P.

VE-.niove Pro,:)co. it. 'VI . ,) .

Drocess control .r'": ansnmit i.nt-oryi-al' i ' " tod ' i be '

Each entry corre ,n I,; to Iat , ictilal (ii g(? ,'

activity model (22:48-41)).

LII . l.! 9 l, F ~ l i l .. ,, . 9 9 *.. ,9!~ l oo(ip' *',. * . ' i

I~k tjj )a ,i I) 0 ( () )t1 l .W *, ', 9 , ~ . II:; [ iI !I, I

, f9l )Tr21 (a r W t ~l l 1 r ,. ',,.' . ' r. .' .j. P I, I ")' ,., 1 .,'°

WWI'

(5,1,17) . Two aspects of local networks rnotivatt-0 ti'w

investigation. First, local networks can increase prooesiino(

power without adding more c'oriputer, .. .g resource sha i nq.

* ~Secondly, researchers and d( nier.1 need a flexible local

network testbed capable ot supporting network thevor y

development.

The DEIJNET desigin was i too down (level opnient using S;AT.

Design began by estabi sh Ii n,_ usiner reciiii rements f () t IIe

development network .in the D.i tal EflliiieeY .i oq( !,ubhoro~t Ili y. A

* .three-part user survey c'~tahli ished these requi remen,

following is a summary of the most important requiracit !-j

the DETJNET (11:19-23):

-Ability to transfer files across the nietwork.-Ablity to shoirr peripherals attached to other

hosts on t-he rnetwork.-Plexibil1 1-y in net-worle cont iqwrati on andooper at ion.

-!!' ~h !)ercentdtle of availability.-Perforpiance morl, toriniry cainai.ty.

These functional reoni rements we re thin 11"i. I

-- establ ish D1Wi!.P systemt repii rl-eentsi, I III, I'o h~joth1 'k~

and1 software. Thle SW"3eI'I hiir dwdjr L- r-mi reIti'w

*es sent tall y common sens t~cirU'r o)a (Ues to n It-~ w c,

- * hosts, fle.; andI ta~m (I~ 1f j'7j

Muttst !:e f lexi'c-* ill(,' ** y exonOI.11c., If "

ttlteneckt- !haf Oil" * , *i(Olli t*'

easil y addeId +:o Ih: !t C:.' o;Ii1't 141 e

* 14

L ~ ~-~ .-.4 -. -. - - " -. ".$

° ' ' ,.,, - - ,w , i =

nodes should not degrade host performance, keeping the DFLNET

nearly transparent to the user. Nodes must re(cot:j,:itiu e

easily, accommodate different topologies and protocol:;, and

meet network throughput. The transmission medium.,; ,ii:;t

support data rates based on networ - throughput, rr',I; ,,,e

time, and bit error rate requirements. Finally, the DPHN.'r

should include a fiber optic link for research uses. ;vs..,,

software requirements were more rigorously develone,! ,icti

several SAT's (11:29-30). Since this investigation *

limited to UNID hardware components, the reader is r,.

to other investigations for a complete devei.opnent (' r '',I'"

software (1. ,9,10) , Thie software dev-_or)ed f, ,:

investigation was only that necessary to perform a C0,,,,,,;t,

test.

- Topology, hosts, noes, and transmission neie .

specified in the DFLNI'I' hardrlware desion (21) The

selected is shown in Fiq 2-1. "'he basic r nq archiIect,'s

a simple versi on of the I (,' 1 network pror~osed i t ,

EErG report (28). Thte stis t.o,)I oqy for the locl-. 1 ,(it.

network was chosen for t ir,-e reasons (11: S-R(. .

a r ranoement decreases th,. n, mr-e r of nodes r .(lli i Y t

each node niore cost t'.* ftct j .. Tht. to 1p o i y I ',

pr ,e.i a i ntor F ce f o r ,,ott h t e ' 1iI)1 ' d P-4 ,

,oi,,)uters in the ! di 4,!" .t ,'. I,- ' 1 " ,

i nteract w_ t h each )th,!! , ',. I,,n t! . . ( ,i , -l.,'

OF

HOST' HOST 7ST iOST

HOST

146

UN I DU)I

HOST )

U: t I DIU" r, .

i 13HOS fICOSTl

, ' 2-1, Topo Loty.

Three hosts f or th 1 nit aI irmin 1 e, n a

speci fied (1: q6-87) t 111, t m 1 , i i i r C-1)r-(se 3 n t-(- 0

cole!tion ha t wo 03 sLf f i i y x e rc i Fe networ

whil e prov.'Qi nq the moxi w'w' rk;'f'r IJI ii~r m ,'

S 0 c f 1 n , a n 0

r rom' h' ('4

,*y 7 L(( 0 !I~ . ~ viE 1

4 , ;Three -y, -ho t 'or h:;~' r i t . a,.ivl Iv no t t o. ..,

L !Tafld~t.r)v" y.: ov1 C4 0I 4 lv 14

• h . , I

1 ~l . e Dr v (~lq he uX~l!,T, r,. ---;,) .-r(,, . ..r rl '. . . -, i . ..

% %" .

The node specif ied for the DELNET is the ,Nt D

(11:87-88) . Currently available commercial noc(e,; and

p .~'. networks are too expensive and not flexible enough for L- .r''

requirements. The UNTD, however, offered several advani.:,i :,.

Complete documentation on development and design is av,,il ht.

and non-proprietary. The use of two Z80 processors t-,,.n,,'LS parallel processino, minimizino throughput and re

delays. Finally, a high level language, PL/Z, and a ,ltw.tr,:

development system, MCZ 1/25, are in place and avaiUt,, ',,r

further development.

The transmission medi un belected I or tht ni:,!,:'i' inclid

both local and network channel.s (.1.1:88-89) . I oco1

channels will use twisted I,-i rs. One network I ink be t.wu.II

two UNIDs will use a f iber ,ott ic communi J cati n 'dr, ni.

Fig 2-2 shows the .m t .i a 1 )I 1, ,', i' ino1 I. !t & i on w t I

the components discussed ahovu.

'".- D Deisn Suminzry

With the DELN.T design comrpete, attention tUrn,-C ' P

design of the UJNID. The 1 is.ic Oesio:- of the 0ev ,ce . .

two Z80 mi croprocesrior bor!.; wh.ich tuhare a 32K 1,"

static RAM memory. Ac .. Io -.;hared memory i:; ,

arbitrator ci rcuiwt ( I , ni,,. ory I)oaY0. " I ",

interface to u se r. ,,.,., .tit. .', r , t. V,

comnl i.nlca I ori F network i-I,),.u ' (:ircl ; inld ie

The 1 o ' c'ard iV'(, ,; t '. ir 1 , , It

four ., -2 ?' u ;er!" w i' l ', ,' , ,. -iti ,, . ...

- -if, rv v tv 1 ,

DATA 19.2Kbps UNTI) 19.2Kbps DWA

56Kb-ps(FfR1;JZ OPTIC LINK)

TJID2

19.2Kbps

T TW1l'PT, ) SR T ES IT

Ficj 2-2 Proposed DEI5TNE' Conf iciuration.

T'he network card was desigcned arounOl f- -io , Z8-lr.i4I(

SIC) provided sigjnif icant c pa b i 1 i. ty ft'r jfltIi li wit"

different network prot-ocolr; . '"Vo net-work ca rds woO0 ....

in a device if the WTT)I wii, t o :sct ,_;.ilir r-ri nIo i nter

modle. Figi 2-3 shows3 the b 4*),.~~ Of t . t

Reforp a useable form 0)f* thie n'Li' 'W 'I

l.east two onerational fINI I).; were fleede! . h~.

shown in Fio 2-?, were .e'to for m j Itr '

soanni tp t ree (M. 1 ri e f w it Vp F r .:

51 i m) F- r io n etwor' ~ c 9 9 i 1

.Wo nodes (20~:1.71- /-. (it Vf ''H

L::7

.USER

LOCAL LOCAL SH !AR ED N'RK P'1211 1? KCARD Z80 MEMORY Z80 CA I,

USER

U SER 7

LOCAL NETWORK I

Fig 2-3 UNID Block Diagram.

shown in Fig 2-1. But, the MST approach requires a ,, ri ,,

of hardware to build a usecible network.

A UNID prototyv* was completed by the end of '11) i)

Since there was only one device, no . eal desi r ia (iJ, 1 w,.,

assigned to it at that tinie. This deviice, however, did riot

meet the original design requi remenl s. Spec fica' ly, I1 411

memory still needed to -he !,xpandet? to 64K hytes and two

additional I/O ports added. '!'lie H exl y eo r ;w the , d0el;j ,II

requirements satisfied, a ;tc 1 ir r n (on t ii et:j t] / , ,

numbers assigned. The first IINfD hti! t W.:: 'i- ; ,jt ,

p. and each of its cards were assigned the ntiiiiwr I ,

Local Card 1 and Network Processor ' "h ,

completed was assi (ifled 'Ie f1lII,e r 2 snuch as Nit t

an(d Local Proce.,sor '!'1! tw(j o I ,r; or- j(j.,rnt.' ( ',4

other excuf~t iri n rr 'i .;,-,10 1.: t ,t. 4 t ,

,hoa rd!s a rt. te c}(T ,, , ,•

, , ,l, , , . tl l!) i

, keerr) e a ch r ,1 l. (i7 I t . .I, I. - I

19

a simple network was formed, a few problem areas h:,'

eliminated. The numerous quantity of dynamic RAM cviira.; 't,-0&

in the system memory produced transient signals causeo !,V tfiv

continual refresh. Th is Problem was correctet! hy tiinq

static RAM chips. This also eliminated the oc.

circuit coupling and switch ing noise due to the wire Wr'i-f:,.

The details of these improvements are presented in ' ' r

ITI.

D! lQmJntaU Qfli

This ongoing i n v vf .Iqa ti o n rel ies o n 1)r 0 Vt: 1

documentation to provide a clez~r unde rstandj n q of )pzi St- work

and future needs. Th us, a n i nino r t ant pa rt o f t h i.s r epo rt vii:3

* .complete documentation r)f eurrient 11a rdwa r C!.

documentation includes vit i m o t cl tenw I i ies , te

layout charts, and wire wrorb li.1sts. Th'"is inioriit i U

* found in the Appendicies.

This chapter summarizedl the reqtu.rementh.; od i

the LINT!) and DTN!,NET. Phesce r enresent the con t r a iii;

on this investigation. These s'imari es, were fol& 1

and !)E!LNET! design impl ennta1i or and t.-v' 1 ation!,c~

during this investiycatior;.

20

III. flI z JtImptotion Mvdificati,,n!

This chapter detai]s the i Iip 1 en(It-l'-a t i on

modifications of the two UNIDs completed duri hl :

investigation. As mentioned earlier, there was no opu.,,it,'.a

UNID available at the beginning of this thesis effort (,,J: *o

IC failures. The work accomplished to obtain such a "till, , ;

discussed. Next, the design and construction of: C, :, t,

memory card is described. Thi; led to the de.,, ,,,

construction of two memory boards which consit ,, .. !

system and shared memory. That work is described ii, ,:if

chapter.

Eventually, each UIN.IU wil. he powert,' by a : ' ,

power supply, the Power/Mate FSM-200-40)01, rotted at. '

(18,17:27). One power s1ligly was received; tinfortin,', .

had no power cables. An A/C Ylowr cord, connected .(

switch, fuse, and indicator l1ioht was attached to the ,

supply. The four vol tit._ ; (itV.r C, - V)C,+I 2VI)C,-' '

ground were then connect-cl to iNl 1.. With th ..

grounded, each time t}( i)e nw,. r ;i,,vily was turned oln( o , .

would qo to zero. Tt wo, (',,ter nilned that- the i)(,w ,

was swi tchi no interpilit:, te t !v. u'1ter oI e, i Wda i .!

a replacemerit power ;imIpi' y )I e d redl . T1 j 1f, . '

UN! T) was pow eC( -- y d 0 n k<',,I ,' IV IAkWei- 1 1t),'y. ','

.,Iectronics' Model Kltif)--,0 ,'N. ,w i :; j,'Y w,,!) !1.,,-,-,4

>: ' Ii [C # I # ~ t ; i~ : ll'! ," .l. , ;! I, : li~ l i , I , ! .2 1

capacity. The three-section Powertec Model 6C300n o,,,:r

supply was used to supply the other three voltages.

The laboratory power supplies provided good regqlit-ion

with essentially noise free power. An important featurt. ,

these two power supplies is their isolated DC ground.:. ",h

isolation prevents AC ripple and simi?'ar (o)u, i'1(l

interference reaching the UNTD. Al! DC grouns were ri

together at the power supplies to further l.i,.it power.',,

interference. If different power supplies are suht- ,,

care must be used to insure they are noise free at,,

isolated DC grounds. The reylacement Power/Mate oow.r !;'i ,

was received; it was confai,iird as the first and recon',, -

to a UNID.

* At the start of this investigation, neither I,,,,

working on the local or the network si.e. S ince edci

mcomponents are interchanneabl e (although nuif',)i.,

previously mentioned), an or,rat)le INTID was obtdn,.!

UNID 2 Motherboard, MC! r,ori PrcCssor Card I, Shart.,'

Card 1 and Local Ca r:(1 . 'his UNIT) wa; onv ct,,.., ,

fili. ling and reading stidred n ,lnfl,(y ,isiInq a .1oca! moni, .

won 1. d not allow shard t,.i,, t , to 1-,* f ftd frl , ,

to an improner bit- pct--d - j) nit f~ r l n if-f tt t () I

reqliestjng a pro l r, :t am i t, V1(/ i ,i .I' ' I I ,.

bit 2 was a cOf.stint hiol. I, t l,; ,tF, . I ,.

trdnster fit ritor lIt

i I t, n I i -0

22 :.~

T. DEM07. This was due to a fa.led data driver chi, on H,

shared memory cards. One driver chip on each of the sh,,,r-d

._N memory cards had failed. Replacement of these chips ,,v. ohf,

*'- UNID two operable shared memory cards when a local mot,rLor

was used.

After the defective shared memory cards were fi xed, !.uCIi

Local Processor Card 1, Shared Memory Card 1, and Local (,.'.

1 were placed into !,NTT) I cage. This configuratior! ',,r'..:fl

properly.

When attempting to operate the MCB Network 1, 'o:. (,z

cards with a network monitor, the cal processor card was

not installed. This was duo to the fact that bo+h procuisisur

boards were supposed to be identi (-Xal Tn this Con? i iqmr a ioln,

L wi th only a network T)r o(:(.1o r and sh a red lwemur1 t:'/ ci

installed, the tINID would not wo)rk. Ph 1i wo!.; ,, ,,: ,i

network processor had j. t ,i sys t-, ( ot k 0 , nw n v ,(1 ed ,n , ,

. using the local processors' clock routed tli,,,wih an

on the shared memory hoard. After thii was (d,.,.

K.> (shared memory card Installed for network si(de to .

the jNID ha d operah f, M(Ch !,o ! and etwor k ,r oc'':,r c c v

Shared Memory cards, and t!,ocal and Network car c1 :;.

.Conztxu..cti.9, f -. McJ1-, y Card

System Memory CX .irc4 -(,).,;t r'g('9 o ,n 0 C01.

Gdrry wi re wrap c r! wic rd.rwan nmTod i fi kc t' -i ort;.

each hoard contai ned ( .'i' ' , o' , *t* .

so ke , 4t-( ys .' lt ' 9 ,' ' I (' Y S f + i "('I

Copy Qvailoble v TT C de not2 p e m it fUl,, ! .g ,~ : , .u tio n

..- ., .. . : ? . _ : _ .. ... . .. . . . .: , . .. .. ... . . ...2.3. . .

ft-.- S

edge. The IC sockets for the network portion of rertiuy were

installed and glued into place.

System memory, built f rom static YAM jC:;, requ, rt ,V,,'

and DC ground (8). The component surface of each ,(t, i,'

connected to ground and physically connected to pin 8 .

16-pin socket. Where a 1 4-pin socket was used, pit,iIto

wire wrapped to pin 7 to irov-de around. "he wi,-w r,

surface is likewise connected to +5V')C and conrctt , ti, t ,,,

16 of each 1.6-pin socket. The system memory card co, i,., .

all control logic and. memory TCs necessary for operatio-r.

After buil di nq and testing the new system me,,orv I. , ,1

it was discovered that- when the boundaries between ,r,,,s.:

system, and shared memoric-s were crossed, snch t: ,

memory from lOnO (H) to PP.'(P) , the ;yste m, ..

* unreliable. The reason was that the two sepirat. ,

(system and shared) used tWO (lif, addr ; luculer- f

select the individual memory chips. .'or this rcds.n, it W. i

decided to design a new mr, tv boatO which WOU' ! r.ce

the system memory boar(I ,rnd )et b ",art-d memory !,,,-rd and ,1 ;:k

the new PK X 8 statAi R A"' ,. "'h,, r, ,, , ..:; ', ' U ,, ,t] , ,,

the control and .on : .0 I, ,

,.. C~nr t. ,*.(~;_.ij. (2. 9L- *t-h,. ,'': ,., y ' ,'. ,.2

M emory cards I ,.I ',, r!lO. .1 [' v r,

\' : ~ I(, flot y ai r (r . I I I ., ,

T'he on( v (Ii

Copy available to DT!C does notpeimit fully legible t.productionii 24

. .

large enough to hold seven memory 7Cs. Memor, cards . 2

function identical and are completely intercli.iiigeablu.

The memory board was wire wranped after the 4 r nti.,0

design of the memory card was conpleted and a wo, LI,,1

schematic was avail ale. The first wire wrapped l.oti '1

not work properly, as will he explained in Chapter TV,

Testing. A second schematic was drawn based o .

testing. (Isinq this schenit c (see Appendix 1) , a w; I

program was generated anO a second memory hoarO ..

wrapped in accordance with t-his program. The r~root,

wire list are shown in ATpendix C. Rased on the r,.-.,i ,

this second board testi nq and the wire Iist, the t rQ I....

board was disassembled and rewired.

. he memory card contains all. control logic an(!I.......

ICs necessary for operation. Appendix A shows the If '.

for the card. The top seven 2P-nin v,ir -, s are net wor'..

memory (2000(H) to 7 PV'.(!,)I and s,,,red mom,,iry (8000(1,!) to

'PF'FF ( 0 11#A ow these ar th - re ].oc , ,S,;t .- ' lI l,iior,

chips 200n0(1 ) to 71.'V,' ',:)ie .,u (f- ht,. c ip,:; on ,

board are for control..

Th lJ s ch1n)ter prov i Oe i (I.';cr I ,

of the ,,*, rI memory ca r(',;. 'te ( l)ch w'-'r i , , t

.4h dwitr r tfi , . : w . ' ,; (Ii ':;. . , .: :,

Copy avoii. . -.... ' .

pemit fully Ic pLo _,c .. i .

25

F.V

The final portion of this thesis investi Jation i ,v. v, d

K- hardware testing the TIN and, in partl cular, the ntw i,,.,,,,

cards. UNT) testing was necessary in the beginnin( ., Ihi operable system. ,"ITT) testinq invol.ved va].idation o w,

'. on the motherboards ari a1 l caris, functton-l loqi , '

functional memory tests, and Incal. carc1 tests. '',* .- '

of the ti me was s ent on tesfinq the new mefiorvi-.

Hareware problems encountert.(d are discussed alono wit- ,

corrective actions. All1 teisti nq was accoii-W i T

accordance with Previous th-scs (,,7)

!-.. 'IJT!'_ Tertfn ethQd

The tests used to vt-r i y mTI'D opertation were- -:, .,

primarily as incre i,,nta' , : .Ih !.c t-I t . 1 ,,

chosen for .its sever..' CidVantagce. :.r, i d.,t;'Fy)I , ,4 ,,

Once the i niit.i a conportn art- ch.c t?, . v n-w ,,i i ,1-1

encountered are often cIt'.. ), uil l ',.1r rte r ;(4 tl~t , ,,

ad( l coIm )onent or on t.- r( i ,9 ,I ',i i. . i ' I '

com Ion..nt. Also, th(f iii .1, II,, 1,1 ! .'. ,l ,

incrementdl approach rt ric.,!*.rly ,?tfi.,(., 'W.; "':,-

of the test inJ can ,, ,4,:'(oi)r shtis ,1 wi I , ' )it

i rnvoved harwa re or ,;of I wit i- t

.'T,)9fy I0 FI ) C2 -i V iI Q Wt. I i .'

1* n)cr ),.)F e!e ' i .()'It)O flt,t) . . ' , , I I', ' -: \, I "

n rr , o I IS t 17_

Copy ovaUablc to DTIC does not26 permit ItUy 12, gibki r..pi:ductioj.

| o°

of card operation. At the outset of th ! ; ,,v,<1 ,., ,

there was no opiurable tINYD. With this in mind and net, *,,I'<

starting poilnt, all cards were first given a power-nP' ""' ' ".

* -. The next tests were power-on checks without TC ;. , .

followed by power-on checkwi tli ICs added. As v.,". 1,

passed its checks another card was added. The t' ' if.

* sections describe each maior ctrea of testinq and di :;c,,:.:

results.

Each board used in the I'INTL was chc'k.d for cOt i .'+t

wiring. This check wZIs Ls(t 't'li ish ld when if ,':,I t..

tha+ the !IJN f was lt Itl ! i t 'I #t it . l,!,ht' i , ' ,

investiciation. A -t-hoilth fhe," , '9--! ,)- ll, 9,, ,. ..

J d d not detect any wirini '-1 i:', -r, 9. ' 't

not apTp.fl d directly to orunt,,df AdW v 1,t C4,!t ' ,t

were routed to the, corret.t i'' ii. 'Phi' C1('t1.% ~

learning wha-t si na .' wtlr(, tin tiChl h,id anI litw '

F ~ ~ ,)e, ,r it t e ,;

V(! ri p V t llt-.etlioW !. t: '4. t:ti (9 V l ] .! . ' 9.

Tn So -e ca Wi it.w r n w v: , il I , t

thef- w; rtn(i (ert si ty wo.aK ti,() ki , . !' ' V't'V'.' jt-f' 't

cht-e:ck coni rnti ty bet-w,.ei ryi n"

Sris at , 1 ed c , / V,''' W.: !!j',. t , V ''

V('l f.a if' :lt'1 11 ( el - r i i ' .

ilil f l t

Copy a&l!:l- " D ,-" n|.-: ~~~~permit fLdIl7 Ik.L. .:dco-

UNID, adding one card at a ti.nie and checking it befor,. '!,e

next card was added. Each card was checked for exc,:;:,1ve

heating when power was appl..ed.

Once the majority of wiring errors and faulty T,'; .

detected, each circuit card was tested to insure fu,,,t .

ooeration. The fol.ow.nc sections describe this fiinj.,- ,

testing for each circiv.t car,. The sequence of: the ,'' ,' .

sections is the order in whIch the cards were tested.

"The local nroces,;or c rr. were , functionally t..'; ,:

installinq them in the cart' cage, connecting ), .

circuitry, and attach.inq an AY'-3 terminal as th-

nrocessor monitor terminal. 'hese cards contained ,

nmon.tor prnorammed durinn an #arl. .er thesis (1). "'. .

also contained 4K bytes o f dynamic TAM . It C!

testing .involved resettinq pe processor card arid *.' '

the various commands in t9l' monitor I,

operation of thesp comnd t (', w af, consi.(ere '

evidence that the proce7r was or atinn corr tc ,

; ..... stringent testing, suchi a: -.!.n ~ c to move and loiw L:

wa ac compl. ished. as !i~ W-rt- 'o hem1111'.

nrocessor to'<s becaviue ,ltr i- 'o,'r,-W .X. .'or exdflI, t , I:, , ,

1,OAD cornrar,I w f h thie ' , t '.1 *, r ] I tist- 1'it, I( no, t , ., .' , ,.

the on-card memory, oiu 11 FI I

*"stcab' -she(4 28e iot *f v i; '

Ct" oF f-i fl)(f

Must perform correctly !)t ore file vcan he

*Successfully loadling data into memory was, therefort., .

as an indicati on that Hiu- local processor ft

* properly.

The next ca r 0!; tit.e were the sh ared nievior vry

Fach local.. moni tor (rre; ,r iwiland was roi nitij ct

time exec t l;ng th c- ft'ci+ w3 t hin the ho'tnd r i.

memory on the shared memoery, cat-ds. 'th e stI, a r e c!'ML! fit)

filled enti rely with W) (11.; tlien, the en ti r e ifI ...

di spl.ayed. ThiLs f 1 -0u W, oy roltJ ie was fO~

different hexirieciva kirhni-r4e11Jft~*. all nlent'rl

were switch(ed f romn vero toC ooe to zero. a C('I I fV fli - C.

was to be a zero, a one wos: i if~vyed. 'Th i 11(1; (',,1

to ther da ta driver ch i r,,; fi t ri c shr e mehmory ~.

chio clriv3no the network ' sliartl ireltory 'w(I

was5 holdino that: bit h'qh "'.'H!V A siTwilar Ifl(I

e nco un1:e re W_; tvi bo f-hII 1 shrt rtuor y ljo I-:c'.

si rl'.ar-iY'. Af tt'r rt-r o1(' i' 1f cl., i 1,; Y i:!

Sharird P~'efllor ' thif 9 1 1 lV i* 1 IV, I .''

*~ ~ f' 4. *r 0C* 9., -1

COpy availablo to DTIC id,s not29 permit full- c~'~Yj~o

installed. As stated previously, this hoard '., .

" similarly to the local processor card., The on!y (lit

between the two cards is that- f-he nttwork processot . ,

no clock and needs the loc& proc)sor card i nst.-,' ' . m

previous thesis di scovered the Iocj: ,I ndl networ" r

cards would operate tolether w i. hut: int.erfer i ,i,

network clock was disah!ed, ui.no ;nstead 4-1e I ivtur ,

from the local processor card 15:64-69. *!1his i f; ,r'I

was obtained by wirinq the cock i (m a. F Irn ,

processor card through an irvert~e on the :,,r ,,,

and back to the clock c.i rcc i t .in 'it- ti-twor k l o(:,..!: ,

With the propet hoards i rO.a II.d, the t ern i o.' jmoni,

described in the !,oca' Proce's;,;or (, rd Testio -sect

rer)eated for the ne two r k oroces sor (i rd.

f 4_1 1-cl- splay routines 1n t Ie .qiii red Memo)ry ('i " ,

section were performned on $he it Lwork. proc,'t; (,l ,',

!'ina!11y, th three ca rs we: ,' t-e ed OQOk:h-r's 't: t ,

f_;'. lina a portion of' the I-,,:' rOCe .C Ior on-c i,

mov' no that b'ock into memot r-'1 i t y aJ'l(I tliet,[ll .

same !)lock into the n,:ewor.: i)r,,ce'Sor' on-cor ( "

the network processor ,i, (,, . "q ) w. .t- te.

r(.vers, r;, s( - ,ri r , nn %v tI I si.- l ' w

rnf-r'- r' dsy l ( Wfl; r1 , . ' ,l n 0 enH ' w tit

0 0er uiminorv o

30

The l.ocal ca rd was a ~d c.d to the [IIT) whn ie n ~ ,

series of tests were coi*e .A data file on diik

MCZ was aIt t empt ed to I- (,,1 4-)dI(Y i nIt o t he 1'u L t h r (It

Channel 1 us i n the load coi ~rid * Th e f il~e WCI s if).

load due to the shd red miior v co.rd' s T:' ti~t Pim (rs ii:, 4'

in Chapter TTT, ryNTr) '.!da l.*- f- t- c:U C'lfi e vt i 1!~ 0. P I -

th e fle'Is contenfts and ec ,ti we-r e v o 1- ta(4 v i,;'.A, y.

L. ~in the heqi rn nq of t-h i &wI , "he ' 'i-'~

da ta duie to boundc, ry cru~i. ' e n hf.- it4'2* I. 4~.

ITI . This l ed to the desimui o!' a oiird1e.r

The muemory card woutil nrof olr ate_ prov)e 1-y

a a Er const r uc tion. . ,it c. y, three OJ f -r fr ,r i 4

orob3.erns wore foundl on t_4 i : Cd iu1lty cI,-; i It, ~4

an'J i- C' ft (0', %-1 I 111( 1 .' f

"!# 4 1

t.'44, y c'i rcl Wot (.f r., I ~ 441 .

* flt-"(T\'w , at'.4 Ii.4.wor~: 2 'tz. 41 /

Copy availalo- f2 P1 dcorm not

.31 pert,-it tiziiv .

XSFIJ and a YSFTIJ depending~ on wh Of proce-ssor ~(

arrived first. The irreseii'- inivestigjation MORed XAI1

and XA15 tociether and NOW-,A YA1, YA14, and] YA1.5

(see Fig R-2) . 'hIS Wa,' cCCOr11fl icShed to Create- 441

* YSFT, whenevtcr a memory lovL on ~ a~l ( ' nd iiiw,

selected eithier on tle .1 ocol side or the network sit

X.- !s'T, a nd YS!Q':1 si ori1 ~i Eire iised to enable the addr-!

MWt i ple xe rs *i Thie yv! F.:r an(' YYN 1-: we re use 0 to Lit -

clata line bi -di recti onal. -!r drvors.

The I ocal systevi THomicl y port Jonl ot: the miemlory I'(_

* ~~~conmleted f J~. Z' ft f t. -4! df~ 'U Te'I

diSCLuSsed te-St-itrIq mnethoOds l'orf.''m ~ of tile !jc d u :3 I.0

all1 tests. The next p'ot f m of- te b-Loar tI to he omtrA -fLe1 w

sh arec! leior y. WYwir t-h nor Iion wcs ,I.,*!

(I' cisove red t1ia t ho th thie br oc .Sc;f en't" oit sIr t* t em4

dr ivers wey e be . nq e n l) f' f t'e j 1ori ri ,' t % i f- 1 1,

read local ;ystemi mvieory. '140,; Swa3S caits' fil c ,!t ,.-

data lInes. '''o al levi at t$e~ nrolif-ern, f i rs :,h

I J flczs wO (-- r tc ia t a t 0 'it 0i f ' 4 5(*Q-t- (it (fl

zir)cI S I a re't ) hao0 t own Y . '~Il

wt r t, 4ea cl W~.'I) ( wi h *, I 'K '*, rc I4C V4.y

1 .1 v/

Copy avciilcblo to DTiC does not

pellmit fully legible repioduction.32-

because the same chip seflo-rct li1ne (Q~XY2OOOf YX40 ~id

CF-XY6000) was being Used t~o enabl.ie Pach d,,i t,, tL S dr ivcr.

The only difference be(tveen thw two wujs that ecch liak 4f- o%()411

read and write signals (YU W~,Y!,YVWFT tur Mf'!N ( !),i to it,

Enable Direction control) '1 cor rfect th is proh lem, 11it.

three chip select l ines were~ NANDed toqoj(ther i o) C'r .1

chip select signal, CB-XY, whi4ch was then NJAN~t.-d wJi 1:

XST, or YSET, dependli.no) on which por t: i on of: th il .u'

addressed. NJow the imlivi dnal nor '. ons of the! mew..t A

worked correctly.

Arn TC f auJ t occlirs i f it eh' i, t-;, ; to perforitt..

to its truth table or srtvci Iec f tnee: i ()n. T!y Ii 'x%'

f aU I tI where th e out wit r ei~t irn s ic i oiiindet r -11 . it( -

corrected easily. 'The chif io i si t~ii 1.y rc_-flOvtL4! j r

A fault where t17he oltr~i r ernm.1ns low unO!(ir o.

more diffictilt to Jident-_ fy. A low co11d~ 4 U on Fa it t

caused by anl nteri,, 1 1o f: OF :M t!x i-e r r I 1. Liiur

internal short in tl- nexf s f- -o C1 e . u te e ! t t

(etermie f TC fitil 1 ' i IFVWI Vf'fi 1-(-11) re io 11(7 dfl)( k-i

P. ;u;r ~ ~ f.e au a I X ' t'' 4\'( c f)(! r t-1) I'

fv4(oVt.( 1 ant'1 r ('44..:4C ~4- I v

3copy aivaible to DTIC does not

Vezmit faiy legible reploductiOR

wiring.

S.--- After redesigning the data bus drivers of the system

memories, it was discovered that when the local monitor was

used to fill shared memory with O0(H) and read, it displayed

00(H); but, when the network monitor was used to fill shared

memory with 00(H) and read, it displayed 40(H). Data line

DQ6 (pin 18) of the shared memory chips was only high when

filled by the network monitor. When the network shared

memory data bus drivers were removed, the shared memory

worked fine. These two chips were then reversed and returned

to their sockets. The result, when again filling with 00(H),

-" was a displayed 04(H). The original data bus driver for line

DQ6 was replaced with a good chip and the circuit functioned

correctly.

While testing the new memory board, the local processor

card failed. The only indication was that the local monitor

would not reset. After checking the address lines and their

associated chips, the data lines and their associated chips,

and the EPROMs, it was discovered that one of the EPROMs had

failed. This discovery was made by replacement with known

good chips. The problem was not eliminated. A logic

analyzer, in the memory map mode, attached to the CPU's

address lines showed that the monitor program in the EPROMs

was randomly addressing all of memory instead of remain in a

tight loop waiting for an interrupt. This indication led to

the stack pointer. The memory location of the stack point is

resident in RAM, so the memory chips were replaced one by one

* 34

to determine if they were causing the problem. These were

" the only chips on the board which had not been examined. One

chip had failed. It was removed and replaced with a good

memory chip and the processor board then worked properly.

Meor Timing Faults

After the above faults were detected and corrected, the

new memory card still failed to operate properly. The

network system memory and the shared memory each worked

correctly, but, the local system memory did not. During fill

and display memory operations, a set pattern of unchanged

data always occurred. The local and network sides were

designed and wired similarly, but the local side would not

create a chip select to any of its memory chips. All wiring

and chips were checked and found to be proper. A chip select

was forced by routing the CE-XY2000 signal to local memory

chip Gl. This allowed the chip to operate but resulted in

the same design problem as before (local and network memory

being selected at the same time). The forcing of a chip

select signal to Gl by-passed the ORing of CE-XY2000 and

XSEL. This indicated a timing problem. These two signals

were routed not from their sources but from other pins of the

same signals. To ease the timing problem, the two signals

were routed to the OR gate from their respective sources.

This helped, but some unreliability in memory remained. A

faster OR gate chip (74S32) was then used and the circuit

worked perfectly.

35

Once the memory card was found to be working by

performing the simple monitor commands, a test program

(L.VINT) was loaded into local system memory from the MCZ and

run successfully. Then, the same program was moved into

network system memory and run successfully. When this

program was attempted to run in both local and network system

memories simultaneously, only one side would run. Whichever

memory (local or network) was started first would run until

the other was started and then the first would stop. Not

only would it stop, but the contents of its memory locations

would be changed. Also, while running this program on the

network side, the local side was loaded again from the MCZ.

Loading caused noise interference to occur on the network

U monitor, and when the network side was then stopped and

attempted to be restarted, it would not run.

At this point all checks were again run on the memory

card and no errors were detected. This board was wire

wrapped in accordance with the original design schematic.

According to that diagram and the wiring of the board, the

local and network sides were completely independent and

showed no reason for interference. From the schematic a wire

list program was completed which gave the signals at each pin

and the routing of all wires. The board was then compared to

the wire list and no discrepancies were detected. Since

there seemed to be no differences between the board, the

schematic, and the wire listing, and no faulty ICs could be

36

detected, it was decided to go ahead and construct a second

memory card in accordance with only the wire list program.

When this second board was completed and tested it also had a

timing problem as mentioned earlier. The problem was

corrected with the previously stated modification to the wire

list (see Appendix C). The same program was then loaded into

both sides of this board and attempted to run simultaneously.

No interference was discovered and both sides ran

independently. The first memory board constructed was then

rewrapped in accordance with the wire list. Then, it was

tested, as previously stated, and found to operate properly.

Chapter Summary

This chapter describes the te.sting performed on the

*- UNID. The testing scheme chosen was organized from the

bottom-up and followed the procedures of previous theses

(1,5,17). The type of tests used were power-off, power-on,

and functional tests. Also discussed were types of circuit

problems encountered and solutions to the same.

4.

37

V. Smmary and Recommendations

The objective of this investigation was the continuation

of the development of two message processors (UNIDs). This

involved the designing, constructing, and testing of a new

memory card. The software used in this thesis investigation

either existed or was developed by a co-investigator (10).

This chapter summarizes the results of this effort and

suggests areas for further study.

.: Unid Cmp letion

When this investigation began, two UNIDs were complete

but neither was working. During this investigation, the two

prototypes were tested for faulty wiring and ICs. All

discrepancies found were corrected to produce two operable

UNIDs. Completing the UNIDs required that a new memory card

be constructed incorporating the circuitry of local and

network system memories, and shared memory. The memory card

was built using new technology, 8K X 8, static RAM chips.

These memory chips allowed all 80K of memory to be built

4 using only 10 memory chips and 33 control and logic chips.

UNIDTetn

Each UNID was tested using an incremental bottom-up

routine. Most of the UNID testing was limited to detecting

IC faults inherited from previous theses. The remainder of

the time was spent on testing the new memory card.

Functional testing of this card revealed serious design

4 38

T -77. T.- .- T * * 4

errors. These errors were finally corrected and two operable

UNIDs are now in effect.

Recommendations

These recommendations include suggestions from past

theses and involve further hardware development for the UNID

and DELNET. Implementation of the Z8OA processor is still a

requirement of the original design. This involves replacing

each Z80 MCB with the faster Z80A board. Unfortunately,

Zilog no longer produces a Z8OA MCB board. So, to upgrade

the UNID a processor board would have to be designed and wire

wrapped incorporating the Z80A CPU and associated circuitry.

If a new processor board was designed and constructed it

would be able to use the new static RAM chips and eliminate

the dynamic RAMs now used on the MCB boards.

Q Also for future investigation is the use of a new Zilog

8-bit micro-processor chip which should be available in 1984

(25). This Z8108 has a multiplexed address and data bus to

reduce the package pin count without sacrificing performance

(memory transactions still require only three clock cycles).

In addition, design with the Z8108 would be easy because of

the on-chip oscillator and programmable bus timing features.

The only external element required in the oscillator circuit

is a crystal (whose frequency is twice the desired internal

frequency). This chip can operate at speeds of 6 to 25 MHz

for increased throughput. The programmable bus timing

feature increases system throughput. Control-bit settings

allow the internal processor clock to be scaled for external

39

-,. bus accesses and wait states to be automatically inserted

during bus cycles. Consequently, the user can select very

high clock speeds to increase system performance without

requiring high-speed memories and I/O devices.

Another recommendation deals with the network card. The

original design goal for the network data rate is 1.5 Mbps.

The ZBOA-SIO can function at 880 Kbps in half duplex mode.

The desired rate could be reached using the Signetic's 2652

Multi-protocol Communication Controller (MPCC) (20). The

MPCC data rate is 2 Mbps and contains all Z80A-SIO features.

It can also interface with an 8-bit or 16-bit data bus.

Thus, this addition would be compatible with 16-bit message

processors.

Now that there are two operable UNIDs having reliable

static memories, future investigations will be able to

concentrate more on the development of the DELNET rather then

the hardware of the UNID.

4

1.

Bibliography

1. Baker, Lee R. Protyte and SRQtware DelopIent forUniversal Network Interfc Device. Unpublished MSThesis. Wright-Patterson AFB, Ohio: School ofEngineering, Air Force Institute of Technology, December1980.

2. Barney, Clifford. "CSNET Unites Computer Scientists,"Electronics, 5: 97-98 (October 20, 1982).

3. Bass, Charlie, &t Al. "Local Network Gives NewFlexibility to Distributed Processing," Electronics, 5U:114-122 (September 25, 1980).

4. Booth, Grayce M. The Distributed Systm Environment,Some Practica Approaces . New York City, New York:McGraw-Hill, Inc., 1981.

5. Brown, Eric F. P t Universal Network InterfaceDevice. Unpublished MS Thesis. Wright-Patterson AFB,Ohio: School of Engineering, Air Force Institute ofTechnology, December 1979.

6. Davies, Donald W., &t al. Computer Networks and TheirProtocol . New York: John Wiley and Sons, 1979.

7. Digital Equipment Corporation. Distributed P

* And Networks, A Technical Orview Df Digital'sNetworking Products And Capabilities. Manufacturer's

* data. Maynard, Massachusetts: Digital Equipment Corp.,1980.

8. Electronic Design Inc. Product Specification EDH8808.Ashland, Massachusetts: Electronic Design Inc., May1982.

9. Geist, John W. P Development QL JIM th niveral.N Network ntfa Device. Unpublished MS Thesis.

Wright-Patterson AFB, Ohio: School of Engineering, AirForce Institute of Technology, December 1981.

10. Hazelton, Craig H. Continued D epment 2ndImplem ntatiQn Qf Protocols for. Ille Digit l Enqineerxnq

0 Laboa ly Network. Unpublished MS Thesis.Wright-Patterson AFB, Ohio: School of Engineering, AirForce Institute of Technology, December 1982.

11. Hobart, William C. Dsign Qf A Local Comput e Networkfor the AiL Force lstitute of Technology DitlE ngineeing Laboratory. Unpublished MS Thesis.Wright-Patterson AFB, Ohio: School of Engineering, AirForce Institute of Technology, March 1981.

0e 41

12. Hopkins, Gregory T. and Norman B. Meisner. "ChoosingBetween Broadband and Baseband Local Networks,"

LMini- iro Sygem, E: 265-274 (June 1982)

13. Kuo, Franklin F. Protocols Anld Tacjhniques fr DataCommunication Networks. Englewood Cliffs, New Jersey:Prentice-Hall, Inc., 1981.

14. Liebowitz, Burt H. and John H. Carson. TutorialDistributed Proessng COMPN F£A.LL 21. New York: IEEEPress, 1977.

15. Metcalfe, Robert M. and David R. Boggs. Etherne:Distutd Packet foring LQL Local CompuNetwrks. Technical Report CSL-75. Xerox, Inc., PaloAlto, California. May 7, 1975.

16. Motorola, Inc. MC4027A Dynamic Random Access Mer.Phoenix, Arizona: Motorola, Inc., 1978.

17. Papp, Charles E. rQtoty e DELNET us heing universalNetwork Int c Di. Unpublished MS Thesis.Wright-Patterson AFB, Ohio: School of Engineering, AirForce Institute of Technology, December 1981.

18. Power/Mate, Inc., EIM-1200 Switching Power S lp .Hackensack, New Jersey: Power/Mate, Inc., 1982.

0 19. Saal, Harry J. "Local-Area Networks Possibilities forPersonal Computers," yt, k (10): 92-112 (October1981).

20. Schwartz, Mescha. Computer-Cmmnication NetLwrk Designand na y is. Englewood Cliffs, New Jersey:Prentice-Hall, Inc., 1977.

21. Signetics Corp. Product SpecificatiQn 265Multi-protocol Communication a2D 1. Sunnyvale,

California: Signetics Corp., 1975.

22. Sluzevich, Sam C. Preiinary Deign 9Qf d UniersalNetwork Intrfe Dei. Unpublished MS Thesis.Wright-Patterson AFB, Ohio: School of Engineering, AirForce Institute of Technology, December 1978.(AD-A064-059)

23. Tanenbaum, Andrew S. Compute Networks. Englewood

Cliffs, New Jersey: Prentice-Hall, Inc., 1981.

24. Valtec, Inc. Model E1--D.2 RS-232C Fiberplq DA _i iDDjInstruction Manal. West Boylston, Massachusetts:Valtec, Inc., 1980.

42

25. Whitcomb, Roger. "On-chip memory management comes to8-bit microprocessors," Eltronic Design, 30 (21):165-171 (October 14, 1982).

26. Zilog, Inc. Product Specification %80A-SaI. Cupertino,California: Zilog, Inc., March 1978.

- 27. Zilog, Inc. Z80-MCB Hardware Userls Manual. Cupertino,: California: Zilog, Inc., January 1980.

* 28. 1842 EEG/EEIC An Enginri g Assesment Toward Econmic,F, and aie Communicationsthrough the 1980's. Technical Report TR 78-5.Richards-Gebaur AFB, Missouri. October 31, 1977.

29. 9022-78R. An Introduction to SADT, StL rd Analys•and Design Technique. Waltham, Massachusetts: SofTech,Inc., November 1976.

9-.

0 43

= ....

K APPEDIX Ap.,

CIRCUIT CARD LAYOUTS

This appendix contains a collection of diagrams illustrating

the IC layout for three circuit cards used in the UNID,

including the motherboard. The local and network processor

cards are not included here, but are well documented in the

Z80 MCB User's Manual (27).

44

List of Figures

Figuze Page

A-1 Motherboard Layout. . . . . . . . . . . . . . . . . . 46

A-2 Memory Card Layout ......... .. 7

A-3 Local Card 1 Layout ............. .. 48

A-4 Local Card 2 Layout . . . . . . . . . . . . . . . . . 49

A-5 Network Card Layout ................. 50

45

L D L L L N L0 E 0 0 0 E 0C V C C C T CA I A A A W AL C L L L 0 L U

E R NC C M C K C UH C H 0 H H SA 0 A N A M A E UN N N I N 0 N D NN T N T N N N UE R E 0 E I E S

L 0 L R L T L EL 0 D

1 2 3 R 4

J21 J20 J19 J18 J17 J16 J15 J14

J2 NETWORK PROCESSOR CARD (Y) J13

J3 LOCAL PROCESSOR CARD (X)

J4 UNUEN

J5 MEMORY CARD US

J6 UNUSED ED

J7 NETWORK CARD

J8 UNUSED J26

J9 LOCAL CARD

G 5 1 1 5 (terminal block)NV 2 2 VD DV V D

C D D CC C

Fig A-I Motherboard Layout.

46

:: 'III/lIIIIIIIIIII/lIIBONDEDIIAREAIIIIIIIIII/lIIIIII/lli

49 50 51 52 53 54 55 56 57 58 59 60, 1 37 3r 6] 6i 6 6 6]37 38 39 41 43 45 48

27 30 32 34 36

14 16 19

1 3 6 8 10 1282" 821 1 1] 1, -1 1. 5o .o5 5

(VIEW FROM WIREWRAP SIDE)

vig A-2 Memory Card Layout.

47

P8214 P8212 USART# FIIR#24 24 24 24

50 : 5o 1 53 55 56 57 58

S T Cc T

*C c3

# 43 45 46

U221 1#1

LCs 31 32 33 34

# 48

K3

i.14 15 19 20 21 22 23 24

AR

1 2 3 T 7 10 11 12

: I WIRE WRAP AREA

EDGE CONNECTOR

SLOCAL CARD I LAYOUT.- (VIEW FROM WIREWRAP SIDE)

~Fig A-3 Local Card 1 Layout.

11

CTC 2 CTC# I28 28

USART#4 USART#3 USART#2 USART#I,-,i"28 28 28 28

60 61 62 63

50 51 64 65 55 56 57 58

43 45 46

P821424 32 34

19 20 21 22 23 24

124 0 11 12

1 2

.'-- WIRE WRAP AREA

_EGE C .. TO . .

LOCAL CARD 2 LAYOUT(VIEW FROM WIREWRAP SIDE)

Fig A-4 Local Card 2 Layout.

0 '49

77 7, -77777

Z80A-CTC 280A SIO/020 40

51 52 53 54 55 56

" 39 40 43 45

H- 31 32 33 34

r.

"4 6 70 9 0 1

NETWORK CARD 1 AND 2 LAYOUT

(VIEW FROM WIREWRAP SIDE)

Fig A-5 Network Card Layout.

~50

Circuit Card Schematics

This appendix contains the circuit schematics for three

of the UNID circuit cards, including the motherboard. The

circuit schematics for the local processor and network

processor cards are contained in the Z80 MCB User's Manual

(27).

51

* * " -* m

° -", . o" .- . * • • • • •, • •

. ° - • o

o o

. . . . . ° -

• " List of Figures

Figure Page

B-i Motherboard Wiring List .............. .53

B-2 Memory Card Schematic ............ . . . .57

B-3 Local Card Schematic . . . . . . . . . . . . . . . . .58

B-4 Network Card Schematic .... . . . . .59

52

This figure lists the wiring connections made on the

motherboard of UNIDs 1 and 2. The head of each column

corresponds to a connector cn the motherboard. The verticle

column at the left of the figure lists the particular signals

being described. The numbers in the figure represent the

wire wrap pin numbers where the signal is attached to the

given connector. All signals on the motherboard are grouped

according to function.

LOCAL PROCESSOR ADDRESS BUS (X)

XAO * 103 90 * 103 * * * * * * *XAl * 102 92 * 102 * * * * * * *XA2 * 101 94 * 101 * * * * * * *XA3 * 100 96 * 100 * * * * * * *XA4 * 98 91 * 98 * * * * * * *

0 ~XA5 * 29 93 * 29 * * * * * * *

XA6 * 30 95 * 30 * * * * * * *XA7 * 26 97 * 26 * * * * * * *XA8 * 27 29 * 27 * * * * * * *XA9 * 89 31 * 89 * * * * * * *XAIO * 91 33 * 91 * * * * * * *XA1I * 37 35 * 37 * * * * * * *XA12 * 97 30 * 97 * * * * * * *XA13 * 36 32 * 36 * * * * * * *XA14 * 94 34 * 94 * * * * * * *XA15 * 32 36 * 32 * * * * * * *

LOCAL PROCESSOR DATA BUS (X)

XDO * 13 68 * 13 * * * * * * *XD1 * 75 69 * 75 * * * * * * *XD2 * 71 7 * 71 * * * * * * *XD3 * 8 8 * 8 * * * * * * *XD•68 0 6 * * * * * * *XD4 *68 70 68XD5 5 71 5XD6 * 12 9 * 12 * * * * * * *XD7 * 73 10 * 73 * * * * * * *

Fig B-i Motherboard Wiring List.

53

-.'- -". "-,. . .. . ...

LOCAL PROCESSOR CONTROL SIGNALS (X)

XWR * 23 117 * 23 * * * * * * *XRFSH * 35 * * * * * * * * * *XRD * 116 111 * 116 * * * * * * *XMI * 115 * *115 * * * * * * *XMREQ * 85 110 * * * * * * * * *XIORQ * 4 * * 4 * * * * * * *XWAIT *119 55 * * * * * * * * *XINT * 79 * * 79 * * * * * * *XRESET * 10 * * 31 * * * * * 5 *XCLK 39 99 * * 99 * * * * * * *XCLK/2 *118 56 * * * * * * * * *

LOCAL PROCESSOR MONITOR CHANNEL (X)

'XTxD * 15 * * * * * * 2 * * *XRxD * 7 * * * * * * 3 * * *XRTS * 14 * * * * * * 4 * * *XCTS * 11 * * * * * * 5 * * *XDSR * 74 * * * * * * 6 * * *XGND * 64 * * * * * * 7 * * *

XLSD * 80 * * * * * * 8 * * *XDTR * 76 * * * * * * 20 * * *

OP'- NETWORK PROCESSOR ADDRESS BUS (Y)

YA0 103 * 100 103 * * * * * * * *YAl 102 * 102 102 * * * * * * * *YA2 101 *104 101 * * * * * * * *YA3 100 *106 100 * * * * * * * *YA4 98 *101 98 * * * * * * * *YA5 29 * 103 29 * * * * * * *YA6 30 * 105 30 * * * * * * * *YA7 26 * 107 26 * * * * * * * *YAB 27 * 39 * * * * * * * * *YA9 89 * 41 * * * * * * * * *YA10 91 * 43 * * * * * * * * *YAll 37 * 45 * * * * * * * * *YA12 97 * 40 * * * * * * * * *YA13 36 * 42 * * * * * * * * *YA14 94 * 44 * * * * * * * * *YA15 32 * 46 * * * * * * * * *

NETWORK PROCESSOR DATA BUS (Y)

YDO 13 * 74 13 * * * * * * * *YD1 75 * 75 75 * * * * * * * *

Fig B-I Motherboard Wiring List (cont).

U 54

YD2 71 * 13 71 * * * * * * * *YD3 8 * 14 8 * * * * * * * *YD4 68 * 76 68 * * * * * * * *YD5 5 * 77 5 * * * * * * * *YD6 12 * 15 12 * * * * * * * *YD7 73 * 16 73 * * * * * * * *

NETWORK PROCESSOR CONTROL SIGNALS (Y)

YWR 23 *119 23 * * * * * * * *YRFSH 35 * * * * * * * * * * *YRD 116 *113 116 * * * * * * * *YWAIT 119 * 57 119 * * * * * * * *YMI 115 * *115 * * * * * * * *YMRQ 85 *112 85 * * * * * * * *YIORQ 4 * * 4 * * * * * * * *YINT 79 * * 79 * * * * * * * *YRESET 10 * * 31 * * * * * * 10 *YCLK 99 * * 99 * * * * * * * *YCLK/2 118 * 58 * * * * * * * * *

NETWORK PROCESSOR MONITOR CHANNEL (Y)

YTxD 15 * * * * * 2 * * * * *YRxD 7 * * * * * 3 * * * * *YRTS 14 * * * * * 4 * * * * ,YCTS 11 * * * * * 5 * * * * *YDSR 74 * * * * * 6 * * * * *YGND 64 * * * * * 7 * * * * *YLSD 80 * * * * * 8 * * * * *YDTR 76 * * * * * 20 * * * * *

LOCAL CHANNEL 1

TxD * * * * 57 * * * * * * 2RxD * * * * 58 * * * * * * 3RTS * * * * 52 * * * * * * 4

* CTS * * * * 53 * * * * * * 5DSR * * * * 54 * * * * * * 6LSD * * * * 56 * * * * * * 8DTR * * * * 55 * * * * * * 20

LOCAL CHANNEL 2

TxD * * * * 49 * * * * 2 * *RxD * * * * 50 * * * * 3 * *RTS * * * * 44 * * * * 4 * *CTS * * * * 45 * * * * 5 * *

Fig B-I Motherboard Wiring List (cont).

e 55

-- DSR * * * 46 * * 6 * *W i.LSD * * * *48 * * * * 8 * *

DTR * * * * 47 * * * * 20

LOCAL CHANNEL 3

TxD * * * * 37 * 2 * * * *

RxD * * * * 38 * * 3 * * *

RTS * * * * 32 * * 4 * * *

CTS * * * * 33 * * 5 * * *

DSR * * * * 34 * * 6 * * * *

LSD * * * * 36 * 8 * * *

DTR * * * * 35 * * 20 * * * *

LOCAL CHANNEL 4

TxD * * * * 19 2 * * * * * *

RxD * * * * 20 3 * * * * *

RTS * * * * 14 4 * * * * * *

CTS * * * * 15 5 * * * * *

DSR * * * * 16 6 * * * * * *

LSD * * * * 18 8 * * * * * *

DTR * * * * 17 20 * * * * * *

96Fig B-i Motherboard wiring List (cont).

In addition to the wiring connections listed above, each

MCB processor card has a number of jumper connections on its

edge connector. See the Z80 MCB User's Manual (27) for

further information..0

* 56

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~ H ~i 459

App~ridix

Wiring List Program

This appendix contains the wire list users manual which

was used to generate the wire routing program included at the

end of this appendix. The card deck which must be loaded

into the CDC computer may be obtained from Dr. Lamont,

AFIT/ENG. That program must be loaded before the users'

program can be run.

06

0 L

r

[..0

Page

Wlist Users Manual. ....... *.. *.......62

-. I. General Description . . . . . . . . . . . . . . . . .62

How It Works . . . . . . . . . . . . . . . . . .62Output Forms . . . . . . . . . . . . . . . . . .62

II. How To Use The Program . . . . . . . . . . . . ... 62

Input Cards. . . . . . . . . . . . . . . . . . .62Executing The Program . . . . . . . . . . . . . .63

III. Interpreting The Output . . . . . . . . . . . . . . .64"'

Error Diagnostics. . . .. . . . . .65

IV. Conclusion v o o 9 o 0 . .66

Wire Routing Listing . . . . . . . . . . . . . . . . . . . .67

Unit Connections For UN4ID Memory Card . . . . . . . . . .6Signal List For UNID Memory Card . . . . . . . . . . . ..

Wire List For UNID Memory Card Level 1 . . . . . . . . . .9CWire List For UNID Memory Card Level 2 . . . . . . . . . .98

.0

61

m .. . . . . . ,. , . ... ... o . . .

WLIST USERS MANUAL

I. General Decito

The purpose of WLIST is to aid the hardware designer in

generating an error free wire list, provide a part of the

standard documentation of hardware design, and allow much

simplified updating of documentation after a change in design

has been made.

Aw It Works - The user provides a list of signal

connections to each IC, plug, jack or other similar device.

The data is sorted and collated in several different ways to

provide the various output formats. An approximation of the

best sequence of connections for each signal is generated.

Errors of certain types can be detected and diagnostic

messages are issued.

Outpu Forms - There are three output products. The

first is essentially a reformatting of the input data. By

unit (IC, etc.), the pin numbers and signals connected are

listed. The second product is a list of all unit/pin

connections by signal name, starting with the source of the

signal. Also listed is the fan-out of each signal. The

third product is a connection by connection wiring list, with

d separate lists for each level of wire wrap.

': 'II. EHow to Use 11m Program

Input Cards- There are three types of data card: 1) the

title card, 2) unit cards, and 3) connection cards.

62

The title card contains an asterisk followed by a title

of up to 20 characters. The title is printed on each page of

the output listing.

example *PROM BOARD

Unit cards cdntain the location, number of pins, and

name (or comment) of each IC, connector, etc., on the board.

One unit card is required per device. The first character is

a dollar sign; followed by location (e.g. A:4), number of

i pins (1-999) and up to 10 comment characters.

example $A:4,24,EPROM 2708

Connection cards contain the names of signals to be

connected to each pin of a device defined by a unit card. As

many connection cards as necessary follow each unit card.

Signal names of up to 10 characters are listed, separated by

commas, starting with pin 1. Pins intended to have no

connection must be named "NC". One signal source must be

specified for each signal name used on a board. The source

is identified by an asterisk preceeding the signal name.

Connection cards may only use the first 72 columns. Columns

73 through 80 are reserved for optional sequence numbers.

example $D:8,14,AND 7408

ENAI,CLK,*STBIENA2,CLK,*STB2,

GND,NCNCNC,NC,NC,NC,VCC

WLIST can be run using a card reader or a time-sharing

terminal.

63

If run using a card reader, the following control card

deck should be used.

$JOB H80 SYST BCDDMP PRIf15 OUT=0

K- *RJE 100 H80 *

3 initials,T15,CM77000,I020,.T820665,namebox #,phone #

ATTACH,WLISTID=E770050,SN=ASDENCY=l.

LIBRARY,COBOL. e

COPY, INPUT, WLDATA.

REWIND, WLDATA,WLIST.

WLIST.

REWIND,WLDATAWLIST.

7/8/9

data cards

6/7/8/9 See Fig C-1 for a sample card deck.

, If executed from a time-sharing terminal, the "deck"

should contain the same control cards used above, with "*EOR"

substituted for "7/8/9" and "*EOF" substituted for "6/7/8/9".

III. Interpreting the utu

Two header pages are printed identifying the circuit,

version of WLIST, and the date and time at which the job was

run. This allows immediate identification of the most recent

run.

The normal output is self-explanatory. Signal sources

are identified by a leading asterisk. The wire list output

is provided in wire wrap levels. All level one connections

should be made prior to proceeding to level two. This will

eliminate wiring level changes and make later modification of

4 64

$JOB H80 SYST BCDDMP PRI-15 OUT-0*RJE 100 H80 *

GFC,T15,CM77000,IO20, .T820665,bUOMO,4093,55533ATTACH,WLIST, ID-E770050 ,SN-ASDEN, CY-1.LIBRARY,COBOL.COPY, INPUT, WLDATA.REWIND, WLDATA, WLIST.WLIST.REWIND, WLDATA, WLIST.7/8/9*WLIST EXAMPLE$A:l,16,CNTR 74161CLRCLKD4 ,D5,D6,D7,ENA,GND,LD*,ENAAOA1,A2tA3, *CI,VCC$B:1,16,CNTR 74161CLRCLKDO,D1,D2,D3 ,C1 ,GND,LD*,Cl ,A4 ,A5 ,A6 ,A7, *OVR,VCC$C: 1,25 ,CONNECTOR*DO,*Dl,*D2,*D3,*D4,*D5,*D6,*D7,*LD*,*ENA,*CLK,NC,*VCC,*GND,*CLRNC,*AO,*AIr*A2,*A3 ,*A4,*A5 ,*A6,*A7,OVR6/7/8/9

Fig C-i Example Card Deck.

the circuit easier. Since the algorithm for determining the

sequence is a simple one, the results may not always be the

best possible. If there are signals that are sensitive to

excessive wire length, their routing should be checked before

the board is wired. Space is provided on the wire list to

enter information such as wire gauge and color or other

appropriate remarks. The list is designed to be cut down to

8 x 10 1/2 size for easy use at the lab bench.

Error Diagnostic - A moderate amount of error checkingIis done in the program. As with all such error diagnostics,

care must be used in interpretation because the actual error

may not be exactly that indicated. The commonly encounteredI _

error messages will be discussed briefly.

O 65

If a signal name occurs only once, an informative

diagnostic advises that the fan-out is zero. This may

result from a typographic error in the string name.

If no source is declared for a signal, an

informative diagnostic advises that there is no source.

This may also indicate a typographic error.

If more than one source has been declared for a

signal, an informative diagnostic advises such.

If an error has been detected, the wire list will

be aborted and a fatal diagnostic will be printed.

This is necessary because results of the wire list are

unpredictable if errors have been encountered.

Although it will probably be more work for the designer

N Oto generate a wire list with this program, it has been found

that it is useful in removing errors from the wire list and,

in some cases, pointing out design errors. It forces more

discipline on the designer, particularly in the often

neglected area of documentation. It is of particular

advantage in keeping documentation up-to-date when changesare made in the design after fabrication. The few cards

affected can be changed, the program rerun, and a completely

new, up-to-date set of documentation, without penciled

corrections, is available. If done properly, use of the

program can be well worth the time.

66

WIRE ROUTE LISTING

Following is the wire routing listing which was used to

wire wrap the new memory boards built for the UNIDs. On this

page is listed a guide to the correlation between the list's

chip locations and the card's chip socket labels.

A:l = Edge -Connector D:13 = 27 F:1l = 49B:l = 1 D:16 = 30 F:12 = 50B:13 = 3 D:18 = 32 F:13 = 51B:16 = 6 D:21 = 34 F:14 = 52B:18 = 8 D:23 = 36 F:15 = 53B:21 = 10 E:ll = 37 P:16 = 54B:23 = 12 E:12 = 38 F:17 = 55C:12 = 14 E:13 = 39 F:18 = 56C:14 = 16 E:15 = 41 F:19 = 57C:17 = 19 E:17 = 43 F:21 = 58

E:19 = 45 F:22 = 59E:23 = 48 F:23 = 60

67

5%

sstS$S$$$$$S $$$$O$GRASM$ $sssss

$$$$SS$$SS $S$SSSSSSSSSSSSS$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$S

S$$$WIRELIST PROGRAM $$$$$

$$$$%VERSION 3.1-(MAY 189 1978 )S$$$

$SS$SSWIRELIST FOR: S$$$SSSSU.ID MEMORY CARD $$$$$$$$$$ 11/26/2 15.11.26. $$$$$

|.6

$ 3 5SS 55 1 $ 51155555 5

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SIGN, AL LIST Fi,., U;.,D MEMORY CAPD PAGESIGNAL FA .CUT SOURCE SIN/KSA"tt 4 8:16/12 H:4/10 H:5/10 H:6/10 H:7/10

A1 4 Hi :16/5 H:'/9 H:5/9 H:6/9 H:7/9

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A2 4 i:16/7 H:4/8. H:5/8 H:6/8 H:7/8

A3 4 11I1Lr/4 H:4/7 H:5/7 H:6/7 H:71/7

A-4 4 11:/l12 H:4/6 H:5/6 H:6/6 H:7/6

4 A- U Iv./'; H:4/5 H1:5/5 H:6/5 H:7/5

Ab '4 H :1-/7 H:4/4 H:5/41 H:6/4 H:1/4

At ' t3:1.,/4 H:4/3 H:5/5 H:f/3 H:1/3

7

4 77

I 6N AL L IST Ff: UP. 0 MEMO RY CAR~D PAGE 2

S I GN AL F A CWT ~C UC F S I NKS

Ac 4 H1:21112 H:4/25 H1:5/25 H1:6/25 H1:7/25

Ac 4 H1:2115 H1:4/24 H1:5/24 H1:6/24 H1:7/24

CE-Sili o 1 D:23/11 H1:4/20

CF -S A0 )0 1-_ 0:23/10 H:5/20

CL-I C3'c 1 D:23/9 H1:6/20

CUI-SF 0 CO) 1 D:23/7 H1:7/20

CE-XY 2 F:22/6 E:17/2'.

CF-XY 2 %u 3 0: 2 3/14. E:12/1 F:12/1 F:22/5

CE-XY4,L0 3 0:2.3/13 E:12/4 F:12/4 F:22/4

CF-xv.; 03~ 3 D:23/12 F:12/9 F:12/9 F:22/3

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78

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' -SIGNAL LIST FO U%10 MEMORY CAPD F'AGE 3

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c -Y;u :C 1 E:12/3 H:1/20

CS-Y4'J1 1 F:12/6 H:2/20

1 C- L :12/e H:3/20

C'J-YDAIA 2 E:17/6 D:13/1 E:13/1

G 0iG. 57 A:1/12C ki 11 /8 B:13/8 H:16/8 H Il k./8

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D:21/7 D:23/4,598 E:11/7E:12/7 E:13/8 E:15/7 E:17/7E:19/7 E:23/8 F:11/7 F:12/7F:13/7 F: 14/198915 F:15/1F:15/8,15 F:16/118,15 F:17/7

[ . F:18/196915 F:19/lot 15

LINF:21/19'3915 F:2217 F:23/8

G:1/14 G:2/14 G:3/14 H:1/14H:2/14 H:3/14 H:4/14 H:5/14H:6/14 H:7/14

.fA A3 F:1,1/3 G:1/1O G:2/10 r,:3/10

L.X1 3 F: i-5 G:II G:2/9 G:3/9

S'. I AL 3 F: 1./11 (:1/21 G:2/21 G:3/21

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79

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I0:1./0 D:16/2

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t.X;.DSLL 1. 0:1 ./12 10:16/13

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r.YAlC 3 F:1',/1l H:1/21 H:2/21 H:3/21

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YA 3 F:i4/,3 H:1L/ H:2/4 , :.34

Y.y,.7 3 F:14/t 4:i/A H:2/3 H:3/3

* 81

',,aNAL LIlT Fuf, Ur.1i) MEMC, ,Y CAFD PAGE 6

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RD-A126-83i CONTINUED DEVELOPMENT OF THE UNIVERSAL NETWORC 2/2INTERFACE DEVICE(U) AIR FORCE INST OF TECHWRIGHT-PATTERSON AFBO SCHOOL OF ENGINEERIHG GCUM

UNCLASSIFIED DEC 82 AFIT/GE/E /1D-28 F/G 9/2OON

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tJL lIZT* F..l L.(J: PTMOFY CAPO P AGE 13:Gi.AL FA:CU' SOU#vCE SINK~S

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89

L:i:. L 7 FljR UNID PLMCRY CARD PAGELIVEL 1

A: 1/3s H: 23/.5 XA15A14' 8:2312 Y415

A:1/5::- F:13/: XWAITA:15-, c: 17/5i XCLK/2

A:1/57 F:13/3 YWAZT.A:/i C:l7/h YCLK/?

A:1/11C: D:lo/ XfrREUA:1/112 0:ilb/,) yvp EQ

H:111 C:2/11 CS-SXDATA11 1 / :11/4 5004

8:11/ E:23/3 XDQ4

H1:11/12 H1:11/14 SOOTH: 11 /13 E:2"'3/13 XD07

B~:13/1 C:14/1 CS-SYDATAH1:13 /2 B:13/4 SOG'.11 :13/ J D: 131.s TOO'.H: 13/5 8:13/111:13/11 D:13/6 YD05

61:13/16 0:13/1L YU07

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pl1/i F:i'h/14. YA-li 18/13'/ F:l12l' XAI1

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WILE L13T FOR UNIL) MEIJCRY CARD PAGE 3

C:14/12 C:14/14 S003*C:14/13 F:i23/13 Y003

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0:16/1 0:1614, iNXA131415n:16/2 0:18/;- tNXIIREQL:l1614 D:is?/:. NYMREQ

D:16/1 :- I NYkDSEL0:16/iC F: 17/9 YWPSEL0:16/12 F:17/4 XW?SEL

0:14/1 0:21/12 XA1314150:1"/5 D:21/I-. YA131415D:h,/ii F:17/9 -YRDSFL

D:-/ 1 F:171t XRcOSEL

C:Il F:21/12 XA15D:21/11 F:21/14 YAIS

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W -bFE L,.'T FOR Uf410 tEMCeAY CARD PAGE 4LEVEL 1

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U:15/3 E: 15i' XSELf,:15/5 F:13/10 YAriiI T

F:17/1 E:19/6 t4xSELF:17/2 E:1714. CF-XY

F1/5 F:11/1C NYSEL

E:1111 F:1/., XCEF :1 -3/2 F:22/2to

F ') F:17/1 XSELF'. )/Z F:11/2 NYOE

F:Il/13 F:17/2 YSEL

F::3l/. F:23/1 C!c-xOATAG:1116 rNXDQ4

-:l- F:21/13 y1 .r~ii/i . F:211/3yw

F: 12/ F:13/L X!,llL

93

WIFE L!ST FOR UNID ME'.OAY CARD FAGE 5LEVEL 1

F:12/3 G:1/2C CS-X20COF:12/5 E:15/3 XSEL'F : 121L G:2/2J CS-X4OGO

F:12/-! G:3/20 C4-X6C0

F:13/I. F:13/5 XYARHIT

F:14/3 H:1/4 I YA6F :14P) H:1/3 NYA7F :141l1 H: 1/21. r, YA 8

F:14/3 H:1/24 IYA9F:14/11 H:1/21 ?YA1CF:14/13 H:1/23 NYAll

F : 1t./3 H: 1/ltc NYAO

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1F : /'5 H:1/2 IYA12

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95

.,Wie- L-ST FO JIO MEMCRY CARD PAGE I

LEVEL I

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wr...E LIST FOR UNID ME!4CRY CAR.D PAGELEVEL

A:1/7 F:23/1 XDQ2A:1 F:23/13 XDO3A: I E:23/l1 xOQ6A:I/1-i E:23/13 XDQ7A:1/13 C:14/10 YU02A: 1/1,, C: 14/13 Y DQ(,3

A:1/15 B:13/10 YDC6A: 1/16, B:13/13 YU)07A :1/2-v B:21/13 XA-i

A:1/33 H:23/13 XA12A:1/31 H: 21/1 XAA:1/32 11:E3/1 XA13A:1/33 B:21/6 XA10

A :1/24 :23/6 XA14A:1133 B:?1/3 XAllA:l/33 8:21/14 YA..A:1/42 H:23/14 YA12A:!/41 8"2 1/11 Y A .

A:1/42 8: 23/11 YA13A:1i/43 B:2:1/5 YA10

A:!I/44 :23/t YA14A:1/45 8:21/2 YAI1A: I /U'- F:23/3 XoucA: 1/L-7 F:23/b -XuQ1A: 1/701 E:;3/3 XDQ .-A : 1 /71 E: 23/t XDQ5A:/71+ C:14/3 YDQCA:!/7) C: 14/i. YDQ1

A:1/7o B:13/3 y0Q0A:1177 H:13/1- YD05A:1/ 3 H:16/13 xACA:1/c. LB:16/13 XA4A: I / . B:16/1r: XAIA: I /IV iB: 1f/13 XA5A:I/c H:16/is XA2A: 11'j H: li/6 XAuA:!1,'- 8:16/3 xA3A:1/57 B1:11/6 XA7A:111," :16/14 YAuA:111-11 1j:: 1,l .,4

A:I/ II" B:16/11 YA!A 1 117 3 R: 1?3 11 Y YAr

A" 1, /1. 4 B: 16/.5 YA-'14A 1/ r. H : I -17 YA.A :11I / ir H: 16/.2 YA -

98

.. _ __. . .. . -.- .. . .. . - .- . . ..-

:..j. .'> - -- ,--._- - - ----. :'._. -- =. -...- -,.,- .-. .... - .* .. , . ..... -.... - ..- -.. -

-I'-E LIST FOR UNID ME,'.Y CARD PAGE 10LEVEL 2

A:11111 F:21/10 XRD"" A:11113: A::/117 F:21/4 XW-A : F:21 WR

H:11/4 H: 13/2 0 '04v"B:11/1 UL:13/5 SD05

11/11 - B:13/9 -SDQ6H:11/14 H:13/12 ,D?*

H:13/1 F:11/d CS-SYDATAH 8:13/ H:4/16 SDQ4" H :13/ 7 H:4/1 7. ED05

[1:13 /11 M:4/ld 3006H:13/14 H:4/19 SDQ7

H: 16./1 i: 2 1/1 ISEL

H: 16/4 H:4/7 A3H:16/7 H:4/6 A2(1:] 6 /9 H: 4/'Ai AlH :16/12 H :4/10 AO

:: H :16/1 , F: 17/3 T ;,.GBF

-: I 1 E: 11/13 YfFLP:16/4 H:4/3 A7: / I:4/4 A6

• :. H: 3/I H:4/5 A5• 11 R:11/li H:4/6 A4

1/1 H:21/1 STPOBE

B:21/4 H: 4/2. All8• U:1;/1 H:4/21 A1OSit: .1/0, H:4/24 A9

i 1 :;.1 /1 I H: 4 /25 At-

8:23 0:21/11 YAl.' H: 3 /3 0:2111 XA15 -

H : 3/ 2 H:4/2 A12

C:12/1 F:22/ C,-SX[IATAC:12/4 C:14/2 O

99

W: E LIST FOR U;.IID MEMCRY CARD PAGE .11LCVEL 2

c*:"2/7 C:1qh/ SDGI

C:12/14 C:14/12 S003:::'.;C :12/1 0 : 16/11 XSDIE'N

C:14/4 H1:4/11 soooC:14/7 H1:4/12 SDOlC:14/11 H:4/13 SDG2C:14/14 H:4/1'' SDQ3C:14/15 0:'-16&/., YSDIEN

0:13/2 0:13/4 t.YUQ4U: 13/5 D:13/7 NDQ5:13/ D:13/11 N YD6

0:13/12 0:13/4 Y 0,Q7

E-"/2 XAABITE:15/5 YARBIT

-0-f/i L E:11/, YWPSEL" ":"D: t1 12" E :11/3] XWRS[L

F:1I/1 F:12/16 XSELL:i 11 F: 11/1G XRDSEL

"E" :; I1 1t; E: 11/12 YSELt..: L: 11 1 1 F: 17/" YFDSEL

- 1 : 212- E:15/1 Y'FLF:12/. E:1211C YSEL

"F:131 E: 1 71/ CC-YDATA

E:13/ 2 E:13/ tYDQIb

f:13/t2 E:13/1~ f.v003"."-:F': 1 3/. E:13/11L t. YD02

" " " -: 13"112 E :13/14 t. YD03

fv :1 1 V: 11/12 D AF,

:F. :i 3 F:17/1 X FLF:.:/4 F:12/2 XLtL

"E : 5/:' F:17/2 YZELLE:15/4 F:12/5 XSEL

f:17/2 F:2-/"1 C -x Y

S100

w: tE L IST -FOR L.AO ME :MCY CARD PAGE .12

LeVEL 2

E:17/3 E:2311 CS-XDATAf: 17V E:19/12 ?,YSEL

E: 1 -/6 F:22/1 I,.YS EL

E:23/2 E:23/4 NxDQ4t':23/5 f.:23/I NXDQ5F : 2 / E:23/11 NXD6C:23/12 C:23/14 fdXDQ7

F :121 1 D:23/14 CE-XY2COO

F :21 4 D:23/13 CE-XY4000F: 12/" D:23/12 CE-XY60,]G

i.i i F:13/1 F:13/.- XYARH" T

".F : 1 'li. H: 4/2 7 WH'-$HAP r

F:17/i H: 4/22 PD-$HAt'E

F:ZI/3 H:1/21 YrErF:21/- F:22/13 XWEF:/ 1/1 H:1/2 2 YOE

F:11/' G:1/22 XCE

F:23/2 F:2/1 x I L

F :23/5 F :2317 lXUQlF ::3 ; F:'-'3/ii J PX Q2F :23/1 2 113/14 N JXDQ3

t;: 112 G: 2/2 t.,XA12

G:11.5 6:1,/ 3 NXA76: 1/,o G:2/4 YA6

I /,I G:2/5 f. X2A/1: ib G: 6 I, xA4

:I/f 6:'./17 X A3' . G~ /,- G 21 .N, ALI

- 101

• , -, " * i ,I i :l' L -

. .i "" . . ." i " " " i

W!,.E LIST FOR ;tNIlU MEMiY CAF.O PAGE 1i

LLVEL 2

G:1/17 G:2/9 NXA1(; 113 G: 2/11) NXAO

G: G:2/11 1.XDQOG:1/12 G:2/12 NXD01G:1/13 G::2/13 IAXDQ2• : 1/15 G:2/15 NXDQ3

-- G: 1 / 1 , G: 2/16 NxDQ4

G:1/i G:2/17 NXOQ5G: I / A G:2/l NXDQ(-G: 1 / 1i G:2/19 NXDQ7G : 1 /21 G: 2/21 '.£XALCG: 1/2.S G:2/23 NXA11G: 1/24. G:2/24 NAAS' : 125 G: 2/25 , xA FG : 1 /217 G:2/27 XWE

V. : 2 12 G: 3/22 XC'E

H: I H: 2/2 r.YAI2H:L/3 ,YA7

H:: /4 H:2/. NYA6H: I/t H:2/5 NYA5H:11 H:2/6 NYA4H:1/ H:2/7 f.YA3H:1i/c H : :/1, i YA2H: 1/;.- H:2/9 N Y AlH: 1/ 1, H: 211'LC NYAOH:1!/11 l: 2111 NJ YOOQ0

H:1/12 H:2/12 NYOQIIi: 1/13 H:2/13 '4YD0Q2H: I /I,) H:2/1; v %OQ3H: I/i6 H:2/1 f.YOQ 4.H:1 7 H:2/17 P.YDQ5

H: 1 H: 2/1-; h YDQ6

H: :2/1: '. y UQ ?H:'/21 H:2/21 ,YA1j11:1 ; H:2/23 YA 11H: 4/2c H:2/24 A

H:'/22 H:3/,2 Y FH :- r 4:3/27 Y ,

2 - H: /2 A12

102

uIE LIST FOR UNIO MEMORY CArD PAGE .14LEVEL 2

H:5/3 H : F3-3 A7

H: b/4 H:6/4 A6H t- H/5 H: G /5 A5H: c/6 H:6/6 A4H:F7 H: 6/7 A3

'T~ih-'/ H: u/e A?

H'5/' H:b/9 AlH: t /l' 11 H: G . A.H: */ H:6/11 SDQJH:rIl2 H:6/1? SIaL1

H:5/13 H:6/13 S002H: -/153 H: G/15 ICD03

I H:(16 SDQ4

H:j/l/ H:.611 / SDQ5'H:t/1 H : -6/1. SDQ6

H: 6/1'. CU071 H:6/21 A1.

H : / H 22 RO-SHAPEH:5/23 H:6/23 AllH: :)/24 4 : 6/24 A94 1.- /2. H:6/29 A

H:')12 H:L/27 W -SHAE

D:23/12 F:12/9 CE-XY6000D:23/13 F:12/4 CE-XY4000D:23/14 F:12/1 CE-XY2000

103

Gennaro Cuomo was born on 28 August 1947 in New York

City, New York. He graduated from Plainview High School, New

York in 1965 after which he attended Nassau Community

College, Garden City, New York. In May 1967, he entered the

U.S. Air Force. In July 1968, he entered the United States

Air Force Academy Preparatory School and was graduated from

the USAF Academy in June 1973 with a Bachelor of Science

degree in Electrical Engineering. Following graduation, he

attended Undergraduate Navigator Training (UNT) at Mather

AFB, California. Upon graduation from UNT, he entered

Electronic Warfare Training (EWT) also at Mather AFB. After

EWT, he was trained as an Electronic Warfare Officer (EWO)

aboard a B-52H at Castle AFBp California. He was then

assigned to Kincheloe AFe, Michigan from March 1975 through

June 1977. Upon the closure of Kincheloe AFB, he was

assigned to Ellsworth APE, South Dakota as an Instructor EWO,

from July 1977 through November 1980. He entered the Air

Force Institute of Technology in December 1980.

Permanent Address: 3 Forest Drive

Plainview# New York 11803

104

SECURITY CLASSIFICATION OF THIS PAGE (Mo Dole Saolre__

REPORT DOCUMENTATION PAGE BEFORE CNOMRUTIGORM

I. REPORT NUMBER ... GOVT ACCESSION NO. RECIPIENTS$ CATALOG NUMBER

AFIT/GE/.,/82D-28 14-A / 43 _

4. TITLE (and Su.li•,,J S. TYPE Of REPORT A PERIOD COVERED

"." NUED DeVELOR4T OP THE UNIVERSAL MS ThesisNEMMK INTERFACE DEVICE

S. PERFORMING ORG. REPORT NUMBER

7 AUTI4OR(s) 6. CONTRACT OR GRANT NuMNERCI)

Gennaro Cuno, Captain, USAF

9. PERFORMING ORGANIZATION NAME AND ADDRESS 10. PROGRAM ELEMENT. PROJECT. TASK

AREA & WORK UNIT NUMBERS

Air Force Institute of Technology (AFIT/EN)Wright-Patterson AFB, CH 45433

It. CONTROLLING OFFICE NAME AND ADDRESS 12. REPORT DATE

Decenber 1982

13. NUMBER OF PAGES

ill14 MONITORING AGENCY NAME A AOORESS(JI dillerent Iom Controlling Office) IS. SECURITY CLASS. (of this report)

Unclassified

15a. DECLASSIFICATION,'OWNGRADINGSCHEDULE

16. DISTRIBUTION STATEMENT (of thle Report)

Approved for public release; distribution unlimited

1?. OISTRIIUTION STATEMENT (of lhe astract entered in Block 20. It different ftom Report)

10 SUPPLEMENTARY NOTES L.Vra19-7

Daplot.st.:1 ecdc4'nd Prof-.911nnal Div1lome4nJA

19 KEY WORDS (Continue on reverse side II necessary and Identity by :-iox n~umaber)

Local Area NetworkLocal Computer NetworkMessage ProcessorsNetwork Interface Device

20. ABSTRACT (Continue on reves side It n.ceoaaq and identify by blck n. "r)

The object of this investigation was to :c.i .r and construct two manoryboards for the Digital Engineering Labor-toz. Networkts (DELNEt's) UniversalNetwork Interface Devices (UNIDs). The UNID is a flexibl iih-ssage procesordesigned for computer communications network applications. The new rvoryboards incorporated the prototype microcamputer based wessage proces!ur

*boards of the previous theses. Using the existing na&iory boards, now jil.oiy

boards were designed, constructed, tested, and dccunented. Thu rusults of this

effort were the elimination of unreliable RAM, the reduction in the nuii.er ofcircuit boards_ used in the UNTD. and two oreraticnal tNTD.;.

DD 1jAN7, 1473 EDITION OF I NOVOS IS OBSOLETE UNCLASSIFIEDSECUITY CLASIFICATIONtOF TOP S PAGE (*iol Vats Ent#,*