Interface Design Memory Modules
description
Transcript of Interface Design Memory Modules
![Page 2: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/2.jpg)
University of Tehran 2
Outline
• Memory variations
• The memory cell
![Page 3: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/3.jpg)
University of Tehran 3
Processor Timing Diagramfor any memory read machine cycle
IOR
IOW
MEMR
MEMW
___
____
_____
______
AddressBus
Data Bus
T1 T2 T3
CLOCK
memory address
datain
![Page 4: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/4.jpg)
University of Tehran 4
Processor Timing Diagramfor any memory write machine cycle
IOR
IOW
MEMR
MEMW
___
____
_____
______
AddressBus
Data Bus
T1 T2 T3
CLOCK
memory address
data out
![Page 5: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/5.jpg)
University of Tehran 5
Memory Terms
• Capacity – Kbit, Mbit, Gbit
• Organization– Address lines– Data lines
• Speed / Timing– Access time
• Write ability– ROM– RAM
![Page 6: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/6.jpg)
University of Tehran 6
ROM Variations
• Mask Rom
• PROM – OTP
• EPROM – UV_EPROM
• EEPROM
• Flash memory
![Page 7: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/7.jpg)
University of Tehran 7
RAM Variations
• SRAM
• DRAM
• NV-RAM– SRAM – CMOS
– Internal lithium battery
– Control circuitry to monitor Vcc
![Page 8: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/8.jpg)
University of Tehran 8
Memories in General
• Computers have mostly RAM
• ROM (or equivalent) needed to boot
• ROM is in same class as Programmable Logic Devices (PLDs), in which are also FPGAs
– Lots of memories in these devices
![Page 9: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/9.jpg)
University of Tehran 9
Simple View of RAM
• Of some word size n• Some capacity 2k
• k bits of address line• Maybe have read line• Have a write line• Have a CS (chip select)
![Page 10: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/10.jpg)
University of Tehran 10
1K x 16 memory
• Variety of sizes– From 1-bit wide
• Issue is no. of pins
• Memory size specified in bytes– This would be 2KB memory
• 10 address lines and 16 data lines
![Page 11: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/11.jpg)
University of Tehran 11
Writing
• Sequence of steps– Setup address lines– Setup data lines– Activate write line (maybe a pos edge)– Usually latch on the next edge
![Page 12: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/12.jpg)
University of Tehran 12
Reading
• Steps– Setup address lines– Activate read line– Data available after specified amt of time
![Page 13: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/13.jpg)
University of Tehran 13
Chip Select
• Usually a line to enable the chip
![Page 14: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/14.jpg)
University of Tehran 14
Writing
![Page 15: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/15.jpg)
University of Tehran 15
Reading
![Page 16: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/16.jpg)
University of Tehran 16
Minimum Mode
MEMORY
D7 - D0 Q7 - Q0
OELE 74LS373
D7 - D0 Q7 - Q0
OELE 74LS3738088
AD7 - AD0
A15 - A8
A19/S6 - A16/S3
DENDT / R
IO / M
RD
WR
ALE
D7 - D4 Q7 - Q4
OELE 74LS373
D3 - D0 Q3 - Q0
GND
GND
GND
D7 - D0A7 - A0 B7 - B0
EDIR 74LS245
A7 - A0A15 - A8A19 - A16
RD
WR
![Page 17: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/17.jpg)
University of Tehran 17
Minimum Mode
MEMORY
D7 - D0
A19 - A0
RD
WR
SimplifiedDrawing of
8088 MinimumMode
D7 - D0
A19 - A0
MEMR
MEMW
When Memory is selected?
![Page 18: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/18.jpg)
University of Tehran 18
Minimum Mode
MEMORY
D7 - D0
A19 - A0
RD
WR
SimplifiedDrawing of
8088 MinimumMode
D7 - D0
A19 - A0
MEMR
MEMWCS
220 bytes or 1MB
![Page 19: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/19.jpg)
University of Tehran 19
What are the memory locations of a 1MB (220 bytes) Memory?
A19 to A0
(HEX)
AAAA11119876
AAAA11115432
AAAA11981000
AAAA7654
AAAA3210
00000 0000 0000 0000 0000 0000
FFFFF 1111 1111 1111 1111 1111
Example: 34FD0 0011 0100 11111 1101 0000
![Page 20: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/20.jpg)
University of Tehran 20
Interfacing a 1MB Memory to the 8088 Microprocessor
230000000001
100001000110002100031000410005100061000710008
95
::
45982739428807F48A
::
20020200212002220023
FFFFDFFFFEFFFFF
29127D13
192536
::
::
::
::A19
A0:
D7
D0:
RD
WR
A19
A0:
D7
D0:
MEMR
MEMW
XXXX
BP
ESDSSS
CXBXAX
XXXXXXXX
XXXX2000
000000233F1C
FCA1
SP
DX
XXXXCS
SI
XXXX
XXXXIP
XXXXDI
CS
![Page 21: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/21.jpg)
University of Tehran 21
Instead of Interfacing 1MB, what will happen if you interface a 512KB Memory?
![Page 22: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/22.jpg)
University of Tehran 22
What are the memory locations of a 512KB (219 bytes) Memory?
A18 to A0
(HEX)
AAAA11119876
AAAA11115432
AAAA11981000
AAAA7654
AAAA3210
00000 0000 0000 0000 0000 0000
7FFFF 0111 1111 1111 1111 1111
![Page 23: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/23.jpg)
University of Tehran 23
Interfacing a 512KB Memory to the 8088 Microprocessor
A18
A0:
D7
D0:
MEMR
MEMWXXXX
BP
ESDSSS
CXBXAX
XXXXXXXX
XXXX2000
000000233F1C
FCA1
SP
DX
XXXXCS
SI
XXXX
XXXXIP
XXXXDI
230000000001 95
::
20020200212002220023
7FFFD7FFFE7FFFF
29127D13
192536
::
::
::
A18
A0:
D7
D0:
RD
WR
CS
A19What do we do with A19?
![Page 24: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/24.jpg)
University of Tehran 24
What if you want to read physical address A0023?
A18
A0:
D7
D0:
MEMR
MEMWXXXX
BP
ESDSSS
CXBXAX
XXXXXXXX
XXXXA000
000000233F1C
FCA1
SP
DX
XXXXCS
SI
XXXX
XXXXIP
XXXXDI
230000000001 95
::
20020200212002220023
7FFFD7FFFE7FFFF
29127D13
192536
::
::
::
A18
A0:
D7
D0:
RD
WR
CS
A19
![Page 25: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/25.jpg)
University of Tehran 25
What if you want to read physical address A0023?
A19 to A0
(HEX)
AAAA11119876
AAAA11115432
AAAA11981000
AAAA7654
AAAA3210
A0023 1010 0000 0000 0010 0011
A19 is not connected to the memory so even if the 8088 microprocessor outputs a logic “1”, the memory cannot “see” this.
![Page 26: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/26.jpg)
University of Tehran 26
What if you want to read physical address 20023?
A18 to A0
(HEX)
AAAA11119876
AAAA11115432
AAAA11981000
AAAA7654
AAAA3210
20023 0010 0000 0000 0010 0011
For memory it is the same as previous one.
![Page 27: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/27.jpg)
University of Tehran 27
Interfacing two 512KB Memory to the 8088 Microprocessor
A18
A0:
D7
D0:
MEMRMEMW
XXXX
BP
ESDSSS
CXBXAX
XXXXXXXX
XXXX2000
000000233F1C
FCA1
SP
DX
XXXXCS
SI
XXXX
XXXXIP
XXXXDI
A19
230000000001 95
:20020200212002220023
7FFFD7FFFE7FFFF
29127D13
192536
:
:
:
A18
A0:
D7
D0:
RDWRCS
970000000001 D4
:20020200212002220023
7FFFD7FFFE7FFFF
A3924533
2C9812
:
:
:
A18
A0:
D7
D0:
RDWRCS
![Page 28: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/28.jpg)
University of Tehran 28
Interfacing two 512KB Memory to the 8088 Microprocessor
• Problem: Bus Conflict. The two memory chips will provide data at the same time when microprocessor performs a memory read.
• Solution: Use address line A19 as an “arbiter”. If A19 outputs a logic “1” the upper memory is enabled (and the lower memory is disabled) and vice-versa.
![Page 29: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/29.jpg)
University of Tehran 29
Interfacing two 512KB Memory to the 8088 Microprocessor
A18
A0:
D7
D0:
MEMRMEMW
XXXX
BP
ESDSSS
CXBXAX
XXXXXXXX
XXXX2000
000000233F1C
FCA1
SP
DX
XXXXCS
SI
XXXX
XXXXIP
XXXXDI
A19
230000000001 95
:20020200212002220023
7FFFD7FFFE7FFFF
29127D13
192536
:
:
:
A18
A0:
D7
D0:
RDWRCS
970000000001 D4
:20020200212002220023
7FFFD7FFFE7FFFF
A3924533
2C9812
:
:
:
A18
A0:
D7
D0:
RDWRCS
![Page 30: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/30.jpg)
University of Tehran 30
What are the memory locations of two consecutive 512KB (219 bytes) Memory?
A19 to A0
(HEX)
AAAA11119876
AAAA11115432
AAAA11981000
AAAA7654
AAAA3210
00000 0000 0000 0000 0000 0000
7FFFF 0111 1111 1111 1111 1111
80000 1000 0000 0000 0000 0000
FFFFF 1111 1111 1111 1111 1111
![Page 31: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/31.jpg)
University of Tehran 31
A18
A0:
D7
D0:
MEMRMEMW
XXXX
BP
ESDSSS
CXBXAX
XXXXXXXX
XXXX2000
000000233F1C
FCA1
SP
DX
XXXXCS
SI
XXXX
XXXXIP
XXXXDI
A19
230000000001 95
:20020200212002220023
7FFFD7FFFE7FFFF
29127D13
192536
:
:
:
A18
A0:
D7
D0:
RDWRCS
970000000001 D4
:20020200212002220023
7FFFD7FFFE7FFFF
A3924533
2C9812
:
:
:
A18
A0:
D7
D0:
RDWRCS
Interfacing two 512KB Memory to the 8088 Microprocessor
When the P outputs an address between 80000 to FFFFF, this memory is selected
When the P outputs an address between 00000 to 7FFFF, this memory is selected
![Page 32: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/32.jpg)
University of Tehran 32
Interfacing two 512KB Memory to the 8088 Microprocessor
A18
A0:
D7
D0:
MEMRMEMW
XXXX
BP
ESDSSS
CXBXAX
XXXXXXXX
XXXX2000
000000233F1C
FCA1
SP
DX
XXXXCS
SI
XXXX
XXXXIP
XXXXDI
A19
230000000001 95
:20020200212002220023
7FFFD7FFFE7FFFF
29127D13
192536
:
:
:
A18
A0:
D7
D0:
RDWRCS
970000000001 D4
:20020200212002220023
7FFFD7FFFE7FFFF
A3924533
2C9812
:
:
:
A18
A0:
D7
D0:
RDWRCS
![Page 33: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/33.jpg)
University of Tehran 33
Interfacing two 512KB Memory to the 8088 Microprocessor
A18
A0:
D7
D0:
MEMRMEMW
XXXX
BP
ESDSSS
CXBXAX
XXXXXXXX
XXXX2000
000000233F1C
FCA1
SP
DX
XXXXCS
SI
XXXX
XXXXIP
XXXXDI
A19
230000000001 95
:20020200212002220023
7FFFD7FFFE7FFFF
29127D13
192536
:
:
:
A18
A0:
D7
D0:
RDWRCS
970000000001 D4
:20020200212002220023
7FFFD7FFFE7FFFF
A3924533
2C9812
:
:
:
A18
A0:
D7
D0:
RDWRCS
A18
A0:
D7
D0:
RDWR
A19
![Page 34: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/34.jpg)
University of Tehran 34
A18
A0:
D7
D0:
MEMRMEMW
XXXX
BP
ESDSSS
CXBXAX
XXXXXXXX
XXXX2000
000000233F1C
FCA1
SP
DX
XXXXCS
SI
XXXX
XXXXIP
XXXXDI
A19
230000000001 95
:20020200212002220023
7FFFD7FFFE7FFFF
29127D13
192536
:
:
:
A18
A0:
D7
D0:
RDWRCS
970000000001 D4
:20020200212002220023
7FFFD7FFFE7FFFF
A3924533
2C9812
:
:
:
A18
A0:
D7
D0:
RDWRCS
What if we remove the lower memory?
![Page 35: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/35.jpg)
University of Tehran 35
What if we remove the lower memory?
A18
A0:
D7
D0:
MEMRMEMW
XXXX
BP
ESDSSS
CXBXAX
XXXXXXXX
XXXX2000
000000233F1C
FCA1
SP
DX
XXXXCS
SI
XXXX
XXXXIP
XXXXDI
A19
230000000001 95
:20020200212002220023
7FFFD7FFFE7FFFF
29127D13
192536
:
:
:
A18
A0:
D7
D0:
RDWRCSWhen the P outputs
an address between 80000 to FFFFF, this memory is selected
When the P outputs an address between 00000 to 7FFFF, no memory chip is selected !
![Page 36: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/36.jpg)
University of Tehran 36
Full and Partial Decoding
• Full Decoding– When all of the “useful” address lines are connected the
memory/device to perform selection
• Partial Decoding– When some of the “useful” address lines are connected
the memory/device to perform selection– Using this type of decoding results into roll-over
addresses
![Page 37: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/37.jpg)
University of Tehran 37
Full Decoding
A18
A0:
D7
D0:
MEMRMEMW
XXXX
BP
ESDSSS
CXBXAX
XXXXXXXX
XXXX2000
000000233F1C
FCA1
SP
DX
XXXXCS
SI
XXXX
XXXXIP
XXXXDI
A19
230000000001 95
:20020200212002220023
7FFFD7FFFE7FFFF
29127D13
192536
:
:
:
A18
A0:
D7
D0:
RDWRCS
![Page 38: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/38.jpg)
University of Tehran 38
Full Decoding
A19 to A0
(HEX)
AAAA11119876
AAAA11115432
AAAA11981000
AAAA7654
AAAA3210
80000 1000 0000 0000 0000 0000
FFFFF 1111 1111 1111 1111 1111
A19 should be a logic “1” for the memory chip to be enabled
![Page 39: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/39.jpg)
University of Tehran 39
Full Decoding
A19 to A0
(HEX)
AAAA11119876
AAAA11115432
AAAA11981000
AAAA7654
AAAA3210
00000 0000 0000 0000 0000 0000
7FFFF 0111 1111 1111 1111 1111
Therefore if the microprocessor outputs an address between 00000 to 7FFFF, whose A19 is a logic “0”, the memory chip will not be selected
![Page 40: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/40.jpg)
University of Tehran 40
Partial Decoding
A18
A0:
D7
D0:
MEMR
MEMWXXXX
BP
ESDSSS
CXBXAX
XXXXXXXX
XXXX2000
000000233F1C
FCA1
SP
DX
XXXXCS
SI
XXXX
XXXXIP
XXXXDI
230000000001 95
::
20020200212002220023
7FFFD7FFFE7FFFF
29127D13
192536
::
::
::
A18
A0:
D7
D0:
RD
WR
CS
A19
![Page 41: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/41.jpg)
University of Tehran 41
Partial Decoding
A19 to A0
(HEX)
AAAA11119876
AAAA11115432
AAAA11981000
AAAA7654
AAAA3210
00000 0000 0000 0000 0000 0000
7FFFF 0111 1111 1111 1111 1111
80000 1000 0000 0000 0000 0000
FFFFF 1111 1111 1111 1111 1111The value of A19 is INSIGNIFICANT to the memory chip, therefore A19 has no bearing whether the memory chip will be enabled or not
![Page 42: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/42.jpg)
University of Tehran 42
Partial Decoding
A19 to A0
(HEX)
AAAA11119876
AAAA11115432
AAAA11981000
AAAA7654
AAAA3210
00000 0000 0000 0000 0000 0000
7FFFF 0111 1111 1111 1111 1111
80000 1000 0000 0000 0000 0000
FFFFF 1111 1111 1111 1111 1111
ACTUAL ADDRESS
![Page 43: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/43.jpg)
University of Tehran 43
Partial Decoding
A19 to A0
(HEX)
AAAA11119876
AAAA11115432
AAAA11981000
AAAA7654
AAAA3210
00000 0000 0000 0000 0000 0000
7FFFF 0111 1111 1111 1111 1111
80000 1000 0000 0000 0000 0000
FFFFF 1111 1111 1111 1111 1111
ACTUAL ADDRESS
![Page 44: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/44.jpg)
University of Tehran 44
Interfacing two 512K Memory Chips to the 8088 Microprocessor
8088Minimum
Mode
A18
A0:
D7
D0:
MEMRMEMW
A19
512KB#2
A18
A0:
D7
D0:
RDWRCS
512KB#1
A18
A0:
D7
D0:
RDWRCS
![Page 45: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/45.jpg)
University of Tehran 45
Interfacing one 512K Memory Chips to the 8088 Microprocessor
8088Minimum
Mode
A18
A0:
D7
D0:
MEMRMEMW
A19
512KB
A18
A0:
D7
D0:
RDWRCS
![Page 46: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/46.jpg)
University of Tehran 46
Interfacing one 512K Memory Chips to the 8088 Microprocessor (version 2)
8088Minimum
Mode
A18
A0:
D7
D0:
MEMRMEMW
A19
512KB
A18
A0:
D7
D0:
RDWRCS
![Page 47: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/47.jpg)
University of Tehran 47
Interfacing one 512K Memory Chips to the 8088 Microprocessor (version 3)
8088Minimum
Mode
A18
A0:
D7
D0:
MEMRMEMW
A19
512KB
A18
A0:
D7
D0:
RDWRCS
![Page 48: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/48.jpg)
University of Tehran 48
Interfacing four 256K Memory Chips to the 8088 Microprocessor
8088Minimum
Mode
A17
A0:
D7
D0:
MEMRMEMW
A18
256KB#3
A17
A0:
D7
D0:
RDWR
CS
A19
256KB#2
A17
A0:
D7
D0:
RDWR
CS
256KB#1
A17
A0:
D7
D0:
RDWR
CS
256KB#4
A17
A0:
D7
D0:
RDWR
CS
![Page 49: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/49.jpg)
University of Tehran 49
Interfacing four 256K Memory Chips to the 8088 Microprocessor
8088Minimum
Mode
A17
A0:
D7
D0:
MEMRMEMW
A18
256KB#3
A17
A0:
D7
D0:
RDWR
CS
A19
256KB#2
A17
A0:
D7
D0:
RDWR
CS
256KB#1
A17
A0:
D7
D0:
RDWR
CS
256KB#4
A17
A0:
D7
D0:
RDWR
CS
![Page 50: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/50.jpg)
University of Tehran 50
Interfacing four 256K Memory Chips to the 8088 Microprocessor
8088Minimum
Mode
A17
A0:
D7
D0:
MEMRMEMW
A18
256KB#3
A17
A0:
D7
D0:
RDWR
CS
A19
256KB#2
A17
A0:
D7
D0:
RDWR
CS
256KB#1
A17
A0:
D7
D0:
RDWR
CS
256KB#4
A17
A0:
D7
D0:
RDWR
CS
![Page 51: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/51.jpg)
University of Tehran 51
Interfacing four 256K Memory Chips to the 8088 Microprocessor
8088Minimum
Mode
A17
A0:
D7
D0:
MEMRMEMW
A18
256KB#3
A17
A0:
D7
D0:
RDWR
CS
A19
256KB#2
A17
A0:
D7
D0:
RDWR
CS
256KB#1
A17
A0:
D7
D0:
RDWR
CS
256KB#4
A17
A0:
D7
D0:
RDWR
CSI1I0 O3
O2
O1
O0
![Page 52: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/52.jpg)
University of Tehran 52
Interfacing several 8K Memory Chips to the 8088 P
8088Minimum
Mode
A12
A0:
D7
D0:
MEMRMEMW
A13A14
8KB#2
A12
A0:
D7
D0:
RDWR
CS
8KB#1
A12
A0:
D7
D0:
RDWR
CS
8KB#?
A12
A0:
D7
D0:
RDWR
CS
A15A16A17A18A19
::
![Page 53: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/53.jpg)
University of Tehran 53
8088Minimum
Mode
A12
A0:
D7
D0:
MEMRMEMW
A13A14
8KB#2
A12
A0:
D7
D0:
RDWR
CS
8KB#1
A12
A0:
D7
D0:
RDWR
CS
8KB#128
A12
A0:
D7
D0:
RDWR
CS
A15A16A17A18A19
::
Interfacing 1288K Memory Chips to the 8088 P
![Page 54: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/54.jpg)
University of Tehran 54
8088Minimum
Mode
A12
A0:
D7
D0:
MEMRMEMW
A13A14
8KB#2
A12
A0:
D7
D0:
RDWR
CS
8KB#1
A12
A0:
D7
D0:
RDWR
CS
8KB#128
A12
A0:
D7
D0:
RDWR
CS
A15A16A17A18A19
::
Interfacing 1288K Memory Chips to the 8088 P
![Page 55: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/55.jpg)
University of Tehran 55
Memory chip#__ is mapped to:
A19 to A0
(HEX)
AAAA11119876
AAAA11115432
AAAA11981000
AAAA7654
AAAA3210
----- ---- ---- ---- ---- ----
----- ---- ---- ---- ---- ----
![Page 56: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/56.jpg)
University of Tehran 56
Memory Chip
• 8K SRAM• to be specific:
– 8Kx8 bits SRAM
6264
A0A1A2A3A4A5A6A7A8A9A10A11A12
CS2
I/O0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7
CS1
OEWE
![Page 57: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/57.jpg)
University of Tehran 57
6264 Block Diagram
![Page 58: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/58.jpg)
University of Tehran 58
6264 Function Table
![Page 59: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/59.jpg)
University of Tehran 59
Memory Chip
• 8K EPROM• to be specific:
– 8Kx8 bits EPROM
2764
A0A1A2A3A4A5A6A7A8A9A10A11A12
VPP
Q0Q1Q2Q3Q4Q5Q6Q7
C
GP
![Page 60: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/60.jpg)
University of Tehran 60
2764 Block Diagram
Chip enable
Output enable
![Page 61: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/61.jpg)
University of Tehran 61
Operating Modes
![Page 62: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/62.jpg)
University of Tehran 62
Programming 2764
• after each erasure for UV-EPROM):– all bits of the M2764A are in the “1" state.
• The only way to change a “0" to a ”1" is by ultraviolet light erasure.
• Programming mode when:– VPP input is at 12.5V– E and P are at TTL low.
• The data to the data output pins. • The levels required for the address and data
inputs are TTL.
![Page 63: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/63.jpg)
University of Tehran 63
8088Minimum
Mode
A12
A0:
D7
D0:
MEMRMEMW
A13A14
8KB#2
A12
A0:
D7
D0:
RDWR
CS
8KB#1
A12
A0:
D7
D0:
RDWR
CS
8KB#128
A12
A0:
D7
D0:
RDWR
CS
A15A16A17A18A19
::
Interfacing 1288K Memory Chips to the 8088 P
![Page 64: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/64.jpg)
University of Tehran 64
When interfacing memory chips to a microprocessor, consider the following:
• TAVDV – address access time• TRLDV – read access time• TDVWH – memory setup time• TWHDX – data hold time• TWLWH – write pulse width
Refer to 8088 data manual
![Page 65: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/65.jpg)
University of Tehran 65
HM6264B Series Read Timing Diagram
tAA, tOE
![Page 66: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/66.jpg)
University of Tehran 66
HM6264B Series Write Timing Diagram
tDW, tDH, tWP
![Page 67: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/67.jpg)
University of Tehran 67
Timing Requirements for 6264 SRAM
• TAVDV = tAA
• TRLDV = tOE
• TDVWH = tDW
• TWHDX = tDH
• TWLWH = tWP
![Page 68: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/68.jpg)
University of Tehran 68
HM6264B Series Read TIMING REQUIREMENTS
HM6264B-8L HM6264B-10L Symbol Parameter Min Max Min Max Units
tRC Read cycle time 85 100 ns
tAA Address access time 85 100 ns
tCO1 Chip select access time (CS1’) 85 100 ns
tCO2 Chip select access time (CS2’) 85 100 ns
tOE Output enable to output valid 45 50 ns
tLZ1 Chip selection to output in low-Z (CS1) 10 10 ns
tLZ2 Chip selection to output in low-Z (CS2) 10 10 ns
tOLZ Output enable to output in low-Z 5 5 ns
tHZ1 Chip deselection in to output in high-Z (CS1’) 0 30 0 35 ns
tHZ2 Chip deselection in to output in high-Z (CS2’) 0 30 0 35 ns
tOHZ Output disable to output in high-Z 0 30 0 35 ns
tOH Output hold from address change 10 10 ns
![Page 69: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/69.jpg)
University of Tehran 69
HM6264B Series Write TIMING REQUIREMENTS
HM6264B-8L HM6264B-10L Symbol Parameter Min Max Min Max Units
tWC Write cycle time 85 100 ns
tCW Chip selection to end of write 75 80 ns
tAS Address setup time 0 0 ns
tAW Address valid to end of write 75 80 ns
tWP Write pulse width 55 60 ns
tWR Write recovery time 0 0
tWHZ WE’ to output in high-Z 0 30 0 35 ns
tDW Data to write time overlap 40 40 ns
tDH Data hold from write time 0 0 ns
tOW Output active from end of write 5 5 ns
tOHZ Output disable to output in high-Z 0 30 0 35 ns
![Page 70: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/70.jpg)
University of Tehran 70
Comparing Timing Requirements of 8088 (using 4 Mhz clock) and HM6264B-8L
8088 using 4MHz clk Timing Req. HM6264B-8L 610 ns TAVDV or tAA 85 ns 555 ns TRLDV or tOE 45 ns 400 ns TDVWH or tDW 40 ns 88 ns TWHDX or tDH 0 ns
440 ns TWLWH or tWP 55 ns
![Page 71: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/71.jpg)
University of Tehran 71
Timing Requirements for HM6264B-8L
• TAVDV = tAA = 85 ns• TRLDV = tOE = 45 ns• TDVWH = tDW = 40 ns• TWHDX = tDH = 0 ns• TWLWH = tWP = 55 ns
![Page 72: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/72.jpg)
University of Tehran 72
Can we interface a 2764 to the 8088 chip which uses a 4MHz clock?
![Page 73: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/73.jpg)
University of Tehran 73
M2764A Read Mode AC Characteristics
-3 -4 Symbol Alt Parameter Min Max Min Max Units
tAVQV tACC Address Valid to Output Valid 180 200 ns
tELQV tCE Chip Enable Low to Output Valid 180 200 ns
tGLQV tOE Output Enable Low to Output Valid 65 75 ns
tEHQZ tDF Chip Enable High to Ourput Hi-Z 0 55 0 55 ns
tGHQZ tDF Output Enable High to Output Hi-Z 0 55 0 55 ns
tAXQX tDH Address Transition to Output Transition 0 0 ns
![Page 74: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/74.jpg)
University of Tehran 74
M2764A Read Mode Timing Diagram
![Page 75: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/75.jpg)
University of Tehran 75
Timing Requirements for 2764 EPROM
• TAVDV = tAVQV
• TRLDV = tGLQV
• TDVWH = N/A • TWHDX = N/A• TWLWH = N/A
![Page 76: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/76.jpg)
University of Tehran 76
Timing Requirements for 2764 EPROM
• TAVDV = tAVQV = ?• TRLDV = tGLQV = ?• TDVWH = N/A• TWHDX = N/A • TWLWH = N/A
![Page 77: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/77.jpg)
University of Tehran 77
M2764A Read Mode AC Characteristics
-3 -4 Symbol Alt Parameter Min Max Min Max Units
tAVQV tACC Address Valid to Output Valid 180 200 ns
tELQV tCE Chip Enable Low to Output Valid 180 200 ns
tGLQV tOE Output Enable Low to Output Valid 65 75 ns
tEHQZ tDF Chip Enable High to Ourput Hi-Z 0 55 0 55 ns
tGHQZ tDF Output Enable High to Output Hi-Z 0 55 0 55 ns
tAXQX tDH Address Transition to Output Transition 0 0 ns
![Page 78: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/78.jpg)
University of Tehran 78
Timing Requirements for M2764A-3
• TAVDV = tAVQV = 180 ns• TRLDV = tGLQV = 65 ns• TDVWH = N/A• TWHDX = N/A • TWLWH = N/A
![Page 79: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/79.jpg)
University of Tehran 79
Comparing Timing Requirements of 8088 (using 4 Mhz clock) and M2764A-3
8088 using 4MHz clk Timing Req. HM6264B-8L 610 ns TAVDV or tAVQV 180 ns 555 ns TRLDV or tGLQV 65 ns
![Page 80: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/80.jpg)
University of Tehran 80
What if we need to interface a “slow” memory to the 8088?
![Page 81: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/81.jpg)
University of Tehran 81
Comparing Timing Requirements of 8088 (using 4 Mhz clock) and a certain “slow” memory chip
8088 using 4MHz clk Timing Req. memory chip 610 ns TAVDV or tAA 85 ns 555 ns TRLDV or tOE 45 ns 400 ns TDVWH or tDW 40 ns 88 ns TWHDX or tDH 0 ns
440 ns TWLWH or tWP 500 ns
![Page 82: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/82.jpg)
University of Tehran 82
8088Minimum
Mode
A12
A0:
D7
D0:
MEMRMEMW
A13A14
HM6264B-8L
A12
A0:
D7
D0:
OEWE
CS1 CS2
SLOWMEMORY
A12
A0:
D7
D0:
RDWR
CS
M2764A-3
A12
A0:
Q7
Q0:
G
C
A15A16A17A18A19
::
5V
READY
![Page 83: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/83.jpg)
University of Tehran 83
Recall:Write Pulse Width / Write-Time (TWLWH)
ALE
T1
CLOCK
T2 T3 T4
AD7 - AD0
A15 - A8
A19/S6 - A16/S3
DT/R __
IO/M __
_____
WR
DEN______
A19 - A0from 74LS373 to memory
A15 - A8
A19 - A16 S6 - S3
A19 - A0 from 74LS373
A7 - A0 D7 - D0 (to 74LS245)
D7 - D0from 74LS245 to memory
D7 - D0 (to memory)A7 - A0
TWLWH
2TCLCL
![Page 84: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/84.jpg)
University of Tehran 84
Write Pulse Width / Write-Time (TWLWH) w/ 1 wait state
ALE
T1
CLOCK
T2 T4
AD7 - AD0
A15 - A8
A19/S6 - A16/S3
READY
IO/M __
_____
WR
DEN______
A19 - A0from 74LS373 to memory
D7 - D0from 74LS245 to memory
TWLWH
A7 - A0 D7 - D0 (to memory)
A7 - A0 D7 - D0 (to 74LS245)
A15 - A8
A19 - A16 S6 - S3
A19 - A0 from 74LS373
DT/R __
TW T3
![Page 85: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/85.jpg)
University of Tehran 85
Comparing Timing Requirements of 8088 (using 4 Mhz clock) and a certain memory chip
8088 using 4MHz clk Timing Req. memory chip 610 ns TAVDV or tAA 85 ns 555 ns TRLDV or tOE 45 ns
400 ns + 250 ns TDVWH or tDW 40 ns 88 ns + 250 ns TWHDX or tDH 0 ns 440 ns + 250 ns TWLWH or tWP 500 ns
caused by 1 wait state during a memory write on the “slow” memory chip
![Page 86: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/86.jpg)
University of Tehran 86
How do we produce a wait state?
• By turning the READY input of the 8088 microprocessor to LOW
![Page 87: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/87.jpg)
University of Tehran 87
8088Minimum
Mode
A12
A0:
D7
D0:
MEMRMEMW
A13A14
HM6264B-8L
A12
A0:
D7
D0:
OEWE
CS1 CS2
SLOWMEMORY
A12
A0:
D7
D0:
RDWR
CS
M2764A-3
A12
A0:
Q7
Q0:
G
C
A15A16A17A18A19
::
5V
READY
![Page 88: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/88.jpg)
University of Tehran 88Requirements for the READY input of the 8088
ALE
T1
CLOCK
T2 T4
AD7 - AD0
A15 - A8
A19/S6 - A16/S3
READY
IO/M __
_____WR
DEN______
A19 - A0from 74LS373 to memory
D7 - D0from 74LS245 to memory
30 ns(min)
A7 - A0 D7 - D0 (to memory)
A7 - A0 D7 - D0 (to 74LS245)
A15 - A8
A19 - A16 S6 - S3
A19 - A0 from 74LS373
DT/R __
TW T3
119 ns(min)
![Page 89: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/89.jpg)
University of Tehran 89Requirements for the RDY of the 8284
T1
CLOCK
T2 T4
RDY1
35 ns(min)
TW T3
READY
![Page 90: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/90.jpg)
University of Tehran 90
Memory2 x m Bitn
m - Bit Data
n - Bit
Addressdecoder
Address
Memory - Global Organisation
![Page 91: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/91.jpg)
University of Tehran 91
Static vs Dynamic RAM
• SRAM vs DRAM
• DRAM stores charge in capacitor– Disappears over short period of time
– Must be refreshed
• SRAM easier to use– Faster
– More expensive per bit
– Smaller sizes
![Page 92: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/92.jpg)
University of Tehran 92
Structure of SRAM
• Control logic• One memory cell per bit
– Cell consists of one or more transistors– Not really a latch made of logic
• Logic equivalent
![Page 93: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/93.jpg)
University of Tehran 96
16 X 1 RAM
What is this?
![Page 94: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/94.jpg)
University of Tehran 97
Tri-State
• Have three states: H, L, and Hi-Z– High impedance– Behaves line no output connection if in Hi-Z state– Allows connecting multiple outputs
![Page 95: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/95.jpg)
University of Tehran 98
Multiplexed with Hi-Z
• Normal behavior is blue areaSmoke
![Page 96: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/96.jpg)
University of Tehran 99
Row/Column
• If RAM gets large, there is a large decoder• Also run into chip layout issues• Larger memories usually “2D” in a matrix
layout
![Page 97: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/97.jpg)
University of Tehran 100
16 X 1 as 4 X 4 Array
• Two decoders– Row– Column
• Address just broken up
• Not visible from outside
![Page 98: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/98.jpg)
University of Tehran 101
Change to 8 X 2 RAM
• Minor change in logic
• Also pinouts• Address 011 (for
example)
![Page 99: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/99.jpg)
University of Tehran 102
m - Bit DataColumn Address DecoderColumn selection
RowAddressDecoder
Memory cell
Quadratic
Memory Matrix
2 Lines (Bit Lines)n / 2
- Bit Column Addressn / 2
- Bitn / 2Row Address
n - Bit Address
2 Linesn / 2
(Word Lines)
m Level
W/E CS OE PGM
Control Logic
Memory - Internal Organisation
![Page 100: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/100.jpg)
University of Tehran 104
SRAM Performance
• Current ones have cycle times in low nanoseconds (say 2.5ns)
• Used as cache (typically offchip secondary cache)
• Sizes up to 8Mbit or so for fast chips• SRAMs:
– Asynchronous– Synchronous
![Page 101: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/101.jpg)
University of Tehran 105
Micron SRAMs
• SyncBurst
• ZBT
• QDR
• DDR (common IO)
• DDR (separate IO)
• Synchronous
• Control inputs are captured at clock edges
![Page 102: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/102.jpg)
University of Tehran 106
SRAM Categories
• SYNCBURST– Internal 2-bit burst counter– Appropriate for cache line size of four– Two bus master support (CPU and cache controller)– ADV# controls number of words– Not suited for more frequent bus turnaround applications
• ZBT (Zero Bus Turnaround)– Internal 2-bit burst counter– FLOW-Through ZBT
» One clock cycle delay» Less data latency and less frequency
– Pipelined ZBT» While data is delivered the memory array is free for the next
data access» Higher frequency
![Page 103: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/103.jpg)
University of Tehran 107
Pentium Cache System
![Page 104: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/104.jpg)
University of Tehran 108
SRAM QDR
• QDR (Quad Data Rate)– Low latency, higher frequency (network applications)– Less ASIC pin count– Separate read and write busses simultaneous read and
write– Clock pair (K,K#)
![Page 105: Interface Design Memory Modules](https://reader035.fdocuments.us/reader035/viewer/2022062810/56815cc8550346895dcad150/html5/thumbnails/105.jpg)
University of Tehran 109
SRAM DDR
• DDR (common IO)– In cases like 16 read then 16 write QDR is half wasted– Common IO busses for input and output
• DDR (separate IO)– Hybrid of DDR and QDR