Interdependent Latch Setup/Hold Time Characterization via ... · Setup/Hold Times in Timing...

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Presented at the Design Automation Conference, San Diego, 2007/06/05. Copyright © Shweta Srivastava and Jaijeet Roychowdhury, System Analysis and Verification Group, University of Minnesota, Twin Cities. Interdependent Latch Setup/Hold Time Characterization via Euler- Newton Curve Tracing on State- Transition Equations Shweta Srivastava, Jaijeet Roychowdhury Shweta Srivastava, Jaijeet Roychowdhury Dept of ECE, University of Minnesota, Twin Cities [email protected]

Transcript of Interdependent Latch Setup/Hold Time Characterization via ... · Setup/Hold Times in Timing...

Page 1: Interdependent Latch Setup/Hold Time Characterization via ... · Setup/Hold Times in Timing Analysis delay D1Q D3Q Logic D2Q Long path Short path clk R1 R3 clk 2 clk 3 R2 hold time

Presented at the Design Automation Conference, San Diego, 2007/06/05. Copyright © Shweta Srivastava and Jaijeet Roychowdhury, System Analysis and Verification Group, University of Minnesota, Twin Cities.

Interdependent Latch Setup/Hold Time Characterization via Euler-Newton Curve Tracing on State-

Transition Equations

Shweta Srivastava, Jaijeet RoychowdhuryShweta Srivastava, Jaijeet Roychowdhury

Dept of ECE, University of Minnesota, Twin Cities

[email protected]

Page 2: Interdependent Latch Setup/Hold Time Characterization via ... · Setup/Hold Times in Timing Analysis delay D1Q D3Q Logic D2Q Long path Short path clk R1 R3 clk 2 clk 3 R2 hold time

Presented at the Design Automation Conference, San Diego, 2007/06/05. Copyright © Shweta Srivastava and Jaijeet Roychowdhury, System Analysis and Verification Group, University of Minnesota, Twin Cities.

Setup/Hold Times in Timing Analysis

delay

D1 Q

D3 Q

Logic

D2 Q

Long path

Short path

clk

R1

R3 clk 2

clk 3R2 hold

time

clk-to-q + pathdelay

Hold Time constraint for short path

D2

Activeclock-edge

D3 be stable till here

Page 3: Interdependent Latch Setup/Hold Time Characterization via ... · Setup/Hold Times in Timing Analysis delay D1Q D3Q Logic D2Q Long path Short path clk R1 R3 clk 2 clk 3 R2 hold time

Presented at the Design Automation Conference, San Diego, 2007/06/05. Copyright © Shweta Srivastava and Jaijeet Roychowdhury, System Analysis and Verification Group, University of Minnesota, Twin Cities.

Setup/Hold Times: Important and Expensive

Finding setup/hold times isimportant but expensive

Finding setup/hold timesCrucial component of library characterizationAccuracy all-important

detailed ckt level simulation, best models

Takes months for a cell library Intel, IBM, AMD, ...

Page 4: Interdependent Latch Setup/Hold Time Characterization via ... · Setup/Hold Times in Timing Analysis delay D1Q D3Q Logic D2Q Long path Short path clk R1 R3 clk 2 clk 3 R2 hold time

Presented at the Design Automation Conference, San Diego, 2007/06/05. Copyright © Shweta Srivastava and Jaijeet Roychowdhury, System Analysis and Verification Group, University of Minnesota, Twin Cities.

Setup and Hold Times

clock

outputdata D Q

setup delay

time

Q:

ou

tpu

t w

ave

form

s

Clock-to-Q delay

FailedTransition

Clock Edge

time

Q output

Q output

Q output

Q output

hold delayclock

data

Activeclock-edge

Page 5: Interdependent Latch Setup/Hold Time Characterization via ... · Setup/Hold Times in Timing Analysis delay D1Q D3Q Logic D2Q Long path Short path clk R1 R3 clk 2 clk 3 R2 hold time

Presented at the Design Automation Conference, San Diego, 2007/06/05. Copyright © Shweta Srivastava and Jaijeet Roychowdhury, System Analysis and Verification Group, University of Minnesota, Twin Cities.

Is There Only ONE Setup and Hold Time?

Assumption made today for STA:

setup/hold times unique

Assumption NOT TRUE!Assumption NOT TRUE!There can be many pairs of

setup/hold times fora latch/register

Page 6: Interdependent Latch Setup/Hold Time Characterization via ... · Setup/Hold Times in Timing Analysis delay D1Q D3Q Logic D2Q Long path Short path clk R1 R3 clk 2 clk 3 R2 hold time

Presented at the Design Automation Conference, San Diego, 2007/06/05. Copyright © Shweta Srivastava and Jaijeet Roychowdhury, System Analysis and Verification Group, University of Minnesota, Twin Cities.

Setup/Hold Time Tradeoff Curves

E. Salman et al 2006 (Ref [1] in paper)

Each point on the curve results in target clock-to-q delay

setup delay

ho

ld d

elay

Setup/Hold Time Trade-off Curve

Reducing pessimism in timing analysisImpact

Each point on the curverepresents a valid pair of setup/hold times

Page 7: Interdependent Latch Setup/Hold Time Characterization via ... · Setup/Hold Times in Timing Analysis delay D1Q D3Q Logic D2Q Long path Short path clk R1 R3 clk 2 clk 3 R2 hold time

Presented at the Design Automation Conference, San Diego, 2007/06/05. Copyright © Shweta Srivastava and Jaijeet Roychowdhury, System Analysis and Verification Group, University of Minnesota, Twin Cities.

Interdependent Setup and Hold Times

clock

outputdata D Q

setup delay

time

Q:

ou

tpu

t w

ave

form

s

Clock Edge

time

Q output

hold delay

SameSame Q output

Same clock-to-Q delay fordifferent setup and hold delays

SameClock-to-Q delay

clock

data

Page 8: Interdependent Latch Setup/Hold Time Characterization via ... · Setup/Hold Times in Timing Analysis delay D1Q D3Q Logic D2Q Long path Short path clk R1 R3 clk 2 clk 3 R2 hold time

Presented at the Design Automation Conference, San Diego, 2007/06/05. Copyright © Shweta Srivastava and Jaijeet Roychowdhury, System Analysis and Verification Group, University of Minnesota, Twin Cities.

How to Exploit Setup/HoldInterdependence in Timing Analysis?

delay

D1 Q

D3 Q

D2 Q

Long path

Short path

clk

R1

R2

hold violation

R3

hold time is large

hold time is small

hold violation is removedExploit Setup/Hold Time Trade-off

at the expense of larger setup time may not be critical

Page 9: Interdependent Latch Setup/Hold Time Characterization via ... · Setup/Hold Times in Timing Analysis delay D1Q D3Q Logic D2Q Long path Short path clk R1 R3 clk 2 clk 3 R2 hold time

Presented at the Design Automation Conference, San Diego, 2007/06/05. Copyright © Shweta Srivastava and Jaijeet Roychowdhury, System Analysis and Verification Group, University of Minnesota, Twin Cities.

Finding Tradeoff Curve is Very Important!

Therefore:

Finding setup/hold tradeoff curve is very valuableBut:

Very computationally expensiveVery computationally expensive

Page 10: Interdependent Latch Setup/Hold Time Characterization via ... · Setup/Hold Times in Timing Analysis delay D1Q D3Q Logic D2Q Long path Short path clk R1 R3 clk 2 clk 3 R2 hold time

Presented at the Design Automation Conference, San Diego, 2007/06/05. Copyright © Shweta Srivastava and Jaijeet Roychowdhury, System Analysis and Verification Group, University of Minnesota, Twin Cities.

Why Expensive?

Constant clock-to-qdelay curve.

Q value vs setup and hold delays Problem: finding the full Q surface

Large number of transient simulationsi.e., infeasible in practice

Curve extractedfrom

Q output surface

Page 11: Interdependent Latch Setup/Hold Time Characterization via ... · Setup/Hold Times in Timing Analysis delay D1Q D3Q Logic D2Q Long path Short path clk R1 R3 clk 2 clk 3 R2 hold time

Presented at the Design Automation Conference, San Diego, 2007/06/05. Copyright © Shweta Srivastava and Jaijeet Roychowdhury, System Analysis and Verification Group, University of Minnesota, Twin Cities.

Our Contribution: Find the Curve Quickly

Contribution of this work

New setup/hold trade-off curve finding technique

much faster than prior brute-force technique

Key idea: trace the curve “directly”avoid looking at points far from curve

Page 12: Interdependent Latch Setup/Hold Time Characterization via ... · Setup/Hold Times in Timing Analysis delay D1Q D3Q Logic D2Q Long path Short path clk R1 R3 clk 2 clk 3 R2 hold time

Presented at the Design Automation Conference, San Diego, 2007/06/05. Copyright © Shweta Srivastava and Jaijeet Roychowdhury, System Analysis and Verification Group, University of Minnesota, Twin Cities.

Our Formulation of the Problem

A scalar equation with two unknowns (setup & hold time)One equation, two unknowns => many solutions (the curve)

Solve numerically using Newton-Raphson methodRapid convergence

setup delay

ho

ld d

elay

Page 13: Interdependent Latch Setup/Hold Time Characterization via ... · Setup/Hold Times in Timing Analysis delay D1Q D3Q Logic D2Q Long path Short path clk R1 R3 clk 2 clk 3 R2 hold time

Presented at the Design Automation Conference, San Diego, 2007/06/05. Copyright © Shweta Srivastava and Jaijeet Roychowdhury, System Analysis and Verification Group, University of Minnesota, Twin Cities.

Formulation:

D Q

clk

Differential equations for register

Q output waveform

Voltage threshold defining clock-to-Q delay

setup time and hold time (unknowns)

Target clock-to-Q delay SPICE-level circuit

Page 14: Interdependent Latch Setup/Hold Time Characterization via ... · Setup/Hold Times in Timing Analysis delay D1Q D3Q Logic D2Q Long path Short path clk R1 R3 clk 2 clk 3 R2 hold time

Presented at the Design Automation Conference, San Diego, 2007/06/05. Copyright © Shweta Srivastava and Jaijeet Roychowdhury, System Analysis and Verification Group, University of Minnesota, Twin Cities.

Contribution: Problem FormulationQ output waveform

Evaluation of is a transient simulation Solution of ONE point

special type of Newton-Raphson (NR) methodsuitable for underdetermined equationsMoore-Penrose Pseudo Inverse NR (MPPI-NR)

Finding the entire curveEuler-Newton curve tracing methodUses MPPI-NR for each point on curve

Page 15: Interdependent Latch Setup/Hold Time Characterization via ... · Setup/Hold Times in Timing Analysis delay D1Q D3Q Logic D2Q Long path Short path clk R1 R3 clk 2 clk 3 R2 hold time

Presented at the Design Automation Conference, San Diego, 2007/06/05. Copyright © Shweta Srivastava and Jaijeet Roychowdhury, System Analysis and Verification Group, University of Minnesota, Twin Cities.

Start with initial guess:

Corrector stepRun Newton-Raphson

Found a point on the curve

Predictor stepCompute Euler step

Predict a new point along the tangent of the curve

=

Setup time

Ho

ld t

ime

Newton Step + Euler Step

Constant clock-to-qdelay Curve

Intuition Behind Euler-Newton Method

Page 16: Interdependent Latch Setup/Hold Time Characterization via ... · Setup/Hold Times in Timing Analysis delay D1Q D3Q Logic D2Q Long path Short path clk R1 R3 clk 2 clk 3 R2 hold time

Presented at the Design Automation Conference, San Diego, 2007/06/05. Copyright © Shweta Srivastava and Jaijeet Roychowdhury, System Analysis and Verification Group, University of Minnesota, Twin Cities.

Solving by Euler-Newton

evaluate

evaluate

converged?yes

No

update

Start with initial guessFound a

point on the curve

Compute unit tangent vector

Predict a new point along tangentMoore-Penrose pseudo inverse

Transientsimulation

Page 17: Interdependent Latch Setup/Hold Time Characterization via ... · Setup/Hold Times in Timing Analysis delay D1Q D3Q Logic D2Q Long path Short path clk R1 R3 clk 2 clk 3 R2 hold time

Presented at the Design Automation Conference, San Diego, 2007/06/05. Copyright © Shweta Srivastava and Jaijeet Roychowdhury, System Analysis and Verification Group, University of Minnesota, Twin Cities.

Connections with “RF” Simulation

New Algorithm:

very similar to shooting method used in “RF” simulation

Implementation easy in RF simulatorsEg, SPECTRE-RF (Cadence), MICA (Freescale)

“RF” simulation capabilities important for:core characterization of digital circuits!

Page 18: Interdependent Latch Setup/Hold Time Characterization via ... · Setup/Hold Times in Timing Analysis delay D1Q D3Q Logic D2Q Long path Short path clk R1 R3 clk 2 clk 3 R2 hold time

Presented at the Design Automation Conference, San Diego, 2007/06/05. Copyright © Shweta Srivastava and Jaijeet Roychowdhury, System Analysis and Verification Group, University of Minnesota, Twin Cities.

Validation

Page 19: Interdependent Latch Setup/Hold Time Characterization via ... · Setup/Hold Times in Timing Analysis delay D1Q D3Q Logic D2Q Long path Short path clk R1 R3 clk 2 clk 3 R2 hold time

Presented at the Design Automation Conference, San Diego, 2007/06/05. Copyright © Shweta Srivastava and Jaijeet Roychowdhury, System Analysis and Verification Group, University of Minnesota, Twin Cities.

Positive-edge triggered

Validation on TSPC register

Points on constant clock-to-qdelay curve obtained byEuler-Newton method

Curve represents the pairs of setupand hold times – each point on curveresults in 10% increase in nominalclock-to-Q delay

Setup time (ps)

Ho

ld t

ime

(ps)

True Single-Phased Clocked register

Page 20: Interdependent Latch Setup/Hold Time Characterization via ... · Setup/Hold Times in Timing Analysis delay D1Q D3Q Logic D2Q Long path Short path clk R1 R3 clk 2 clk 3 R2 hold time

Presented at the Design Automation Conference, San Diego, 2007/06/05. Copyright © Shweta Srivastava and Jaijeet Roychowdhury, System Analysis and Verification Group, University of Minnesota, Twin Cities.

TSPC register validation

Q output surface as a functionof setup and hold delays

Points obtained byEuler-Newton method

Ho

ld t

ime

(ps)

Setup time (ps)

Curve extracted from Q output surface: Brute-force method

Speedup: ~12.5x (30min vs 6h 40min)

Page 21: Interdependent Latch Setup/Hold Time Characterization via ... · Setup/Hold Times in Timing Analysis delay D1Q D3Q Logic D2Q Long path Short path clk R1 R3 clk 2 clk 3 R2 hold time

Presented at the Design Automation Conference, San Diego, 2007/06/05. Copyright © Shweta Srivastava and Jaijeet Roychowdhury, System Analysis and Verification Group, University of Minnesota, Twin Cities.

C2MOS register: Validation

Positive -edge triggered

Ho

ld t

ime

(ps)

Points obtained byEuler-Newton method

Setup time (ps)

Curve extracted from Q output surface: Brute-force method

Speedup: ~10.5x (16min vs 2h 48min)

Page 22: Interdependent Latch Setup/Hold Time Characterization via ... · Setup/Hold Times in Timing Analysis delay D1Q D3Q Logic D2Q Long path Short path clk R1 R3 clk 2 clk 3 R2 hold time

Presented at the Design Automation Conference, San Diego, 2007/06/05. Copyright © Shweta Srivastava and Jaijeet Roychowdhury, System Analysis and Verification Group, University of Minnesota, Twin Cities.

Summary

New technique for fast setup/hold tradeoff curve characterization

Adapts ideas from “RF” simulation (shooting)

Importance/Impact:Importance/Impact:“free” elimination of violations/slack in timing analysisreduces unnecessary optimism or pessimism

Validated on TSPC and C2MOS registersSpeedups of an order of magnitude

Key advance in making setup/hold tradeoff exploitation

PRACTICAL

Page 23: Interdependent Latch Setup/Hold Time Characterization via ... · Setup/Hold Times in Timing Analysis delay D1Q D3Q Logic D2Q Long path Short path clk R1 R3 clk 2 clk 3 R2 hold time

Presented at the Design Automation Conference, San Diego, 2007/06/05. Copyright © Shweta Srivastava and Jaijeet Roychowdhury, System Analysis and Verification Group, University of Minnesota, Twin Cities.

Acknowledgments

Chandramouli Kashyap and Chirayu Amin,Chandramouli Kashyap and Chirayu Amin, Intel Strategic CAD LabsIntel Strategic CAD Labs

Sani Nassif,Sani Nassif, IBM Austin Research LaboratoryIBM Austin Research Laboratory


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