INTERACTIVE GRAPHICS IN LOW-NOISE CIRCUIT DESIGN

BY

MOHAMMAD YOUSUF

OCTOBER, 1978

A THESIS SUBMITTED FOR THE DEGREE OF

MASTER OF PHILOSOPHY OF THE UNIVERSITY

OF LONDON

DEPARTMENT OF ELECTRICAL ENGINEERING

IMPERIAL COLLEGE OF SCIENCE AND TECHNOLOGY

LONDON S.W.7

1

ABSTRACT

The thesis discusses a computer-aided low-noise electronic design facility which uses interactive graphics.

The dc-analysis has been made to form an integral part of the noise analysis, due to the additional importance of the quiescent point on circuit noise behaviour. After the dc-analysis, results are displayed as transistor currents and circuit node voltages on the CRT .screen (superimposed on the circuit diagram).

Hybrid-Tr models are formed for each transistor at the quiescent point. Of course, the circuit designer can simulate other models of transistor or of any other devices at any arbitrary quiescent point.

Two shot noise sources (at the quiescent point) and one thermal noise source are simulated for each transistor. Also, one thermal noise source (at room temp.) for each resistor in the circuit is simulated automatically.

The automatic noise source simulation can be overridden either by making a resistor noiseless or re-defining the noise temperature.

Also, simulation of shot noise sources at any arbitrary quiescent current value is possible.

Among the analysis facilities, are the small-signal gain-phase response and a plot of output noise voltage against frequency. All the noise sources in the circuit can be replaced by a single equivalent input noise source at the signal source point and its value plotted over any band of frequency. Both the noise voltage at the output and the equivalent input noise voltage can be integrated to give the total noise within a band. To enable the circuit designer to identify and to deal with the major noise contributing components, individual noise contributi-ons from each component can be displayed by value or by symbol (superimposed on the component). One analysis program plots noise figure against source resistance with the latter around its optimum value.

ACKNOWLEDGEMENT

I am deeply grateful to Dr. R. A. King for his

encouragement, help and useful criticisms throughout this

work. N

2

3

LIST OF SYMBOLS

SYMBOL

DEFINITION

k Boltzmann's constant

T Temperature

B Bandwidth

In Mean square noise current

Vn Mean square noise voltage

q Charge of an electron

If Mean square flicker noise current

C Correlation coefficient

G The gain from the input port to the output port

Gt The gain from input signal source to output port

VT (kT)/q

cv 2Trf

4

CONTENTS

PAGE

ABSTRACT

1

ACKNOWLEDGEMENT

2

LIST OF SYMBOLS

3

CHAPTER 1 INTRODUCTION

7

CHAPTER 2 NOISE MECHANISMS AND NOISE SOURCE

MODELLING 13

2.1 NOISE MECHANISMS 13

2.1.1 Thermal noise 13

2.1.2 Shot noise 15

2.1.3 Low-frequency noise 15

2.2 CORRELATION 16

2.3 SIMULATION OF NOISE SOURCES 17

2.3.1 Resistor 18

2.3.2 Semiconductor diode 18

2.3.3- Bipolar transistor 19

2.3.4 Field-effect transistor 20

2.4 SUMMARY 23

CHAPTER 3 INPUT OF CIRCUIT DATA, AND OUTPUT OF

ANALYSIS RESULTS BY USING INTERACTIVE

GRAPHICS 24

3.1 THE GRAPHIC-15 DISPLAY SYSTEM

24

3.2 THE GRAPHIC-15 INSTRUCTIONS

27

3.3 CIRCUIT DATA INPUT

29

3.3.1 The display file 2y

5

PAGE

3.3.2 Starting the circuit diagram drawing 31

3.3.3 The tracking cross operation 33

3.3.4 The grid-structure and circuit

diagram data management 36

3.3.5 Component selection from the 'menu' 40

3.3.6 Scaling the circuit diagram 42

3.3.7 Moving the circuit diagram on the

screen 42

3.3.8 Assignment of values to the circuit

elements 43

3.3.9 Deletion and erasing 43

3.4 NOISE DATA INPUT 44

3.4.1 Assignment of shot noise parameters 44

3.4.2 Assignment of thermal noise parameters 45

3.4.3 Deleting and clearing the assignments-- ssignments - 47

3.4.4 Simulation of noise sources for the

bipolar transistor 48

3.4.5 The noise parameter assignment program 48

3.4.6 The display file for displaying

assignments 55

3.5 ANALYSIS RESULTS OUTPUT 59

3.6 SUMMARY 60

CHAPTER 4 NONLINEAR DC-ANALYSIS

62

4.1. NEWTON-RAPHSON ITERATION TECHNIQUE 63

4.2 MODIFICATIONS TO THE NEWTON-RAPHSON ITERATION

TECHNIQUE 65

4.3 TRANSISTOR MODELLING FOR THE DC-ANALYSIS 67

PAGE

4.4 IMPLEMENTATION OF THE DC-ANALYSIS PROGRAM 69

4.5 SUMMARY 76

CHAPTER 5 NOISE AND GAIN-PHASE ANALYSES 77

5.1 SMALL-SIGNAL MODELLING OF THE BIPOLAR

TRANSISTOR 77

5.2 USE OF INTERRECIPROCITY CONCEPT FOR NOISE

ANALYSIS 79

5.3 ANALYSIS OPTIONS 85

5.3.1 .Noise at output 86

5.3.2 Noise contribution 88

5.3.3 Equivalent input noise 90'

5.3.4 Optimum source resistance 93

5.3.5 Integration of noise at the output

and of equivalent input noise 96

5.3.6 Small-signal gain and phase analysis 97

5.4 SUMMARY 99

CHAPTER 6 CONCLUSIONS 100

APPENDIX A THE OVERLAY STRUCTURE FOR THE

SUBROUTINES 103

APPENDIX B SEQUENCE OF PROGRAM SELECTION BY

THE USER 106

REFERENCES • 109

7

CHAPTER ONE

INTRODUCTION

Computer-aided circuit design is an iterative

process in which the circuit designer and the computer need

to work in close partnership to achive good results. Either

side has capablities that complement the other. After the

design objectives and the specifications have been set,

the circuit designer using his experience and imaginative

power synthesizes a trial circuit. Then he inputs the

circuit data to the computer and asks for an analysis. The

computer with its ability to work reliably and at a high'

speed and with its enormous capacity to hold information

in the memory is well suited for the job. The computer

analyses the trial circuit and outputs the analysis results

to the circuit designer, who compares the predicted circuit

performance with the set objectives and specifications.

It is highly likely that the objectives and the

specifications will not be met fully. Again, the circuit

designer will use his experience and creativeness to

modify the trial circuit and ask the computer for another

analysis. Thus the iterative loop (shown in Fig. 1.1 - by a

flow-chart) is repeated. To facilitate good design this

loop traversing should be smooth and speedy.

In a situation where the circuit designer is one

of the users in the 'queue' for a computer operating in a

batch mode he may have to wait for hours to get the circuit

analysis results or sometimes only to be told that the

designer circuit

Set objectives

and specifications

8

Circuit Synthesize a trial

Input circuit data

to the computer

Analyse

the circuit

Computer

Output results

to the designer

Circuit

performance

acceptable Circuit

designer Yes

Modify the

trial circuit

Design acceptable

Fig. 1.1 Flow-chart for the computer-aided circuit

design iterative loop.

9

analysis could not be carried out due to error in input

data. Apparently, undesireable delay is introduced in the

iterative design process loop.

By using an on-line computing facility (either

a small computer used by the circuit designer alone or a

large computer system used with other users on a

time-sharing basis) the delay can be considerably reduced

and a good interaction with the computer is achievēd.

Human beings perceive information easily when

presented in the pictorial form rather than in the

alphanumeric form. Engineers have been using 'drawing'

for design purposes for many years. But with a computer

system without any interactive graphics(a facility using

which one can exchange information with the computer via

the console of a CRT type display), it is necessary to

translate a circuit diagram into a (often quite rigidly)

formatted alphanumeric form to be fed into the computer.

It is a both unusual and troublesome job on the part of a

circuit designer. The possiblity of a mistake being commit-=

ted during this translation process is also present.

On the other hand, a computer system which has

interactive graphics facility and will allow the circuit

designer to 'draw' a circuit diagram on the face of a CRT

with a light-pen in very much the same way as he would do

on a piece of paper with a pencil, will save a lot of

trouble and time. The facility will also greatly reduce the

possiblity of feeding in erroneous input data. As an

example, if a mistake is made by putting a capacitor in

10

CE CE

Fig. 1.2 Capacitor placed in place of the emitter

resistor.

place of the emitter resistor (Fig. 1.2), it is highly un-

likely that this will escape the circuit designer's

notice when he makes a check on the circuit diagram. But

it is quite possible to overlook a 'C' typed by mistake

in place of 'R' in a mass of alphanumeric data.

Noise is a problem in communication, measurement

and control systems. Very often a signal carrying

essential information is weak. The weak signal needs to be

amplified before it can be used properly. Also some form of

transducer or sensing device is required to convert a

non-electrical signal into an electrical one (e.g. a

microphone to convert acoustic signal into electrical

signal) for the amplifier. The sensor that picks up the

11

signal alsd picks up noise. With an ideal noise-free

sensor and amplifier, the signal to noise ratio at the

output of the amplifier is the same as that at the input

of the sensor. But in the real world, both the sensor and

the amplifier will have noise mechanisms associated with

them. As a result, the signal to noise ratio at the output

will be degraded. A Je.signe7 of low-noise circuits tries to

keep this signal to noise ratio degradation to a minimum

and to achieve that he can use the power of a digital

computer.

Any ac-analysis program such as ECAP[1] can be

used for the noise analysis of a circuit. In such a case,

the noise sources are considered one at a time and the

circuit analysed by using superposition to obtain the

total output noise for all noise sources. Obviously, this

is a very expensive way. An experienced low-noise circuit

designer with his intuition can reduce the number of

analyses by considering only the important noise sources.

A much better way is to use the transpose circuit method [26]

which requires a- little more computation than that required

for one circuit analysis and still considers all the noise

sources in a circuit.

But for a low-noise design of electronic

circuits, noise calculation and presentation need to be

done in various forms (for example, the total output noise

within a frequency band, the equivalent input noise, etc.).

A computer program 'NOISE'[2] for low-noise

design is reported to have been found useful by the design

engineers. But 'NOISE' has some limitations. It can take

12 '

into account only the noise sources of the input stage.

for circuit noise calculation, resulting in loss of

accuracy. Also, the circuit data and the noise data have

to be inputted in a rigidly formatted alphanumeric form.

For example, an input data card must have values at all

specified locations, even if some of them may not be used

for noise analysis; and, to quote "Harmless constants must

be provided for those locations on the card". Also, the

output of the results are in a not-easily-comprehensible

form (i.e. in numbers).

The purpose of this research work was to design

a flexible and easy-to-use 'low-noise circuit design

facility' by exploiting the benefits offered by the

interactive graphics. Also, the noise sources of all the

stages are considered (the transpose circuit method is

used for noise analysis). The dc-analysis is made to form

an integral part of this noise analysis facility, because

of the dc-operating point's influence on both circuit

response and the noise mechanisms.

'Chapter two' is a brief discussion of different

kinds of noise mechanisms. 'Chapter three' describes how

the input of circuit data and noise data are made to the

computer; and also how the computer outputs the analysis

results. 'Chapter four' is on nonlinear dc-analysis,which

is carried out to find the dc-operating point. 'Chapter

five' describes how the small-signal hybrid-TC transistor

model is formed, at the dc-operating point. Also, the

different noise analyses and the gain-phase analysis

facilities are discussed. 'Chapter six' -is the conclusion.

13

CHAPTER TWO

NOISE MECHANISMMS AND NOISE SOURCE MODELLING

For the design of low-noise electronic circuits,

it is necessary to understand the characteristics of noise

sources and minimize their effects.

2.1 NOISE MECHANISMS

The main three noise mechanisms, namely—

the thermal noise, the shot noise and the low-frequency

noise are discussed. For more details references [3]to_[8]

may be consulted.

2.1.1 Thermal noise

Thermal noise is generated by the random motion

of charge carriers in an element whose impedance has a

resistive part. J. B. Johnson observed this noise first

in 1927 and the theoretical analysis was p:'oduced by H.

Nyquist in 1928. Thermal noise is also known as Nyquist

noise or Johnson noise. Nyquist found out that the

available noise power from a resistor is proportional to

the product of the temperature (in.K) o:Z the resistor and

the bandwidth over which the noise measurement is carried

out.

Available noise power= kTB

where, k= Boltzmann's constant

T= Temperature (°K)

B= Bandwidth (Hz)

14

The thermal noise spectral density (defined as

the mean square noise voltage per hertz of bandwidth) when

plotted against frequency, gives a flat curve A resistor

of resistance R ohm which has an open-circuit mean square

noise voltageVn can be modelled as a noiseless resistor

of value R ohm in series with a voltage source of value

V~ as shown in Fig. 2.1.1a.

(a) (b)

Fig. 2.1.1 Thermal noise source modelling;

(a) by voltage source and (b) by current source

The available noise power from the voltage source is the

power dissipated by a resistor of value R ohm connected

between the terminals 'A' and 'B', and is given by V„/4R

But as mentioned before, the available thermal noise

power from a resistor is equal to kTB.

Therefore, V, /(4R) = kTB

and hence,

'k 7he

`vn = 4kTRB

šz_Í flzeFuenay fev5anse 1s Õ'a* oL'elz cL Lin;tad /a.?cle-O alfl .

15

The thermal noise from the resistor R can, alternatively,

be represented by a noise current source (Fig. 2.1.1b)

having a mean square value given by the following expression

= 4kTB/R

2.1.2 Shot noise

The noise associated with the motion of charge

carriers across a potential barrier is called shot noise.

This noise is present in thermionic valves, semiconductor

diodes and transistors. As an example, in a vaccum tube

diode this noise is due to the fact that charge carriers

are discrete and their random arrival at the anode of the

valve causes small pulses of current.

The mean square shot noise current in a semi-

conductor diode is equal to 24IB

where, q = charge of an electron

I = quiescent current of the diode

B = bandwidth of noise measurement

Like thermal noise, shot noise power per hertz of

bandwidth is constant at all frequencies LT to uery, ki9h rectuenc;es .

2.1.3 Low-frequency noise

This is the type of noise which is dominant

below about 1 kHz. The spectral density is nearly

proportional to 1/f and therefore, this type of noise is

sometimes referred to as 1/f noise. This noise was first

observed in vaccum tubes and was referred to as 'flicker

16

effect' . Hence this noise is also called flicker noise.

The main cause of the low-frequency noise is

the generation and recombination of charge carriers on the

surface of and at discontinuities in the semiconductor

device material. Improved surface treatment of the,semi-

conductor material has reduced this type of noise. Unlike

thermal noise and shot noise, the flicker noise cannot be

predicted by a simple analytic expression.

Flicker noise in transistors has been investiga-

ted[9] . In a bipolar transistor this noise mechanism can

be represented by a current source connected across the

internal base-emitter junction having a mean square value

given by the following expression

If = KIB B

The value of IX is about 1. Although K and?' vary from unit

to unit, they can be measured[101 for several units,

typical values formed and used for a particular process.

2.2 CORRELATION

Noise sources resulting from independent physical

mechanisms are independent of each other or uncorrelated.

But inter-dependent physical mechanisms .or even the same

physical mechanism can give rise to noise sources which

may be correlated. If we consider two noise sources with

instantaneous voltage values of V1 and v. connected in

series as shown in Fig. 2.2, then the root mean square

voltage of the resultant equivalent noise source can be

17

Vr

V1

V2

Fig. 2.2 Two noise sources connected in series.

expressed as

Vr=Vi+VZ +2CI✓ \/

where, C = V,Vz

I/ 2

v' v22

I

C is called the correlation coefficient and its value lies

between -1 and +1. If two signal sources have voltage

waveforms of identical shape, then the sources are said to

be 100% correlated and the value of C becomes 1. For two

uncorrelated noise sources the correlation coefficient C is

equal to 0.

2.3 SIMULATION OF NOISE SOURCES

The noise mechanisms are simulated by noise

current sources because nodal analysis method has been used

18

for circuit solution. 1» -0,i's work attention is res4ricked fo low fre.luen fi re/ior where hL9k frequency s{fea-ts liave bee„ ignoted..

2.3.1 Resistor

The thermal noise of a resistor is simulated by

a noise current source In in parallel with the resistor

as shown in Fig. 2.3.1 .

Rhoisy)

Fig. 2.3.1 Simulation of noise source for a resistor.

2.3.2 Semiconductor diode

At the quiescent operating point, a semiconductor

diode can be represented by an ohmic resistance P1 in series

with a dynamic resistance P2 as shown in Fig. 2.3.2 .

The thermal noise due to the ohmic resistance and the shot

noise due to the quiescent diode current are simulated by two

noise current; sources Ini and Int respectively.

19

Idc

Fig. 2.3.2 Simulation of noise sources for a

semiconductor diode.

2.3.3 Bipolar transistor

A noise model for a bipolar transistor at

frequencies upto about 100MHz will include one thermal

noise source, one 1/f noise source and two shot noise

sources. The thermal noise source is due to the base

spreading resistancerbb, and is simulated by the noise

current source Inbb' (Fig. 2.3.3). One of the two shot

noise sources is due to the quiescent base current'B

and the other shot noise source is due to the

quiescent collector current Ic and they are simulated by

two noise current sourcesjnbez between the nodes }3',E and

Ince between the nodes.C,E respectively. The flicker noise

b' Intiei

A

is simulated by the noise current sourcelnbe1, between

the nodes B',E .

20

B rbb' B'

ce Dince

Vbbe

l E

Inbb' = 4 k TB/r6g

Intiez = 2gIB B

=KIB f B

Ince = 2q Ic B

Fig. 2.3.3 Simulation of noise sources for a bipolar

transistor.

2.3.4 Field-effect transistor

The field-effect transistor operates on the

principle of channel conductance modulation. And associated

with this channel conductance is the thermal noise mechani-

sm which can be simulated by a noise current source

connected between the drain and the source (Fig. 2.3.4) .

nb'ez

21

The mean square value of this current source is given by

Inc = 4 k T9mo ad B

9mo is the maximum value of gm (the FET transconductance)

and is given by

gmo ` Vp

where, IDSS is the value of drain current at saturation

for zero gate voltage and

Vp is the pinch-off voltage (the gate voltage

which is capable of reducing the channel

width to zero for small drain-source voltage).

For MOSFET ad is equal to 2/3 (approx.) and for JPET ad - is

a function of biasing condition and a typical value is 0.65.

2 IDSS

Drain Gate 0

Vg s

Source

Fig. 2.3.4 Simulation of noise sources for a field-effect

transistor.

In add tion to the above the thermal noise in the

IF Cgd

nc ant ds irds Cgs g vg5 ngi

22

channel induces noise in the gate due to the capacitive

coupling between the gate and the channel. This induced

gate noise has been analysed for the JFET (11] and the

MOSFET [12]. The mean square values of the noise currents

for the two types of devices (JFET and MOSFET) are given

by similar expressions

f 2

In9i = 4 k T L C99

ai B gmo

where, Cgc = gate to channel capacitance caused by

depletion layer in JFET and by oxide

layer in MOSFET.

ai = 0.12 (approx.) for MOSFET and is

dependendent on bias conditions with a

typical value of 0.3 for JFET.

This noise mechanism can be simulated by connecting a noise

current source between the gate and source (Fig. 2.3.4).

This induced gate noise becomes significant at high

frequencies (at about 1MHz).

The 1/f noise mechanism in a JFET is due to the

generation and recombination of charge carriers in the

depletion layer. While, the main cause of 1/f noise mechani-

sm in a MOSFET is related with the surface states at the

interface between the semiconductor and the oxide. This

noise mechanism can be simulated by connecting a noise

current source between the drain and the source. The low--

frequency noise in MOSFET devices are much higher compared

to that of the JFET and therefore, MOSFET devices are

unsuitable for low frequency operation.

23

The 1/f noise in a JFET can be simulated by a noise current

source connected between the drain and the source [13] ,

having a mean square value given_ by the following expression

en ID If =K

where, K is a constant for a given JFET (at a given

temperature),

Q is a constant for a particular JFET and

ID is quiescent drain current.

2.4 SUMMARY

The three main types of noise namely; thermal

noise (caused by the random motion of electrons), shot

noise (associated with the motion of charge carriers

across a potential barrier) and the low-frequency noise

(caused mainly by the generation and recombination of

charge carriers on the surface of the semiconductor device

material) are discussed. Then the equivalent noise source

resulting from the uncorrelated sources and the correlated

sources is discussed. And finally, the simulation of the

noise mechanisms by the noise current sources is discussed.

24

CHAPTER THREE

INPUT OF CIRCUIT AND NOISE DATA,

AND OUTPUT OF ANALYSIS RESULTS BY USING INTERACTIVE GRAPHICS

The input of circuit data and noise data to the

computer is made by using the light-pen and the CRT screen

as .much as possible and the use of the teletype is kept at

a minimum. This is done to take advantage of the ease and

speed offered by the interactive graphics in communicating

with the computer. Monitoring of the progress of analysis,

error message displays and analysis results displays are

made on the CRT screen...

In our noise analysis facility some graphics

subroutines, (for example, the subroutine for circuit data

input (sec. 3.3), the subroutine for producing the

octagonal symbols for noise contribution display

(Fig. 5.3.2a), etc.) with modifications where necessary

from a circuit analysis package MINNIE [14], have been

used. Some graphics programs, for example, the program

needed to monitor the progress of the nonlinear dc-analysis

(Fig. 4.4b), noise parameter assignment display (sub. sec.

3.4.5), etc. have been.designed to meet our requirements.

3.1 THE GRAPHIC-15 DISPLAY SYSTEM

The Graphic-15 display system [15] comprises the

VT15 graphic processor, VT04 graphic display console and a

light-pen. The VT15 graphic processor is a subordinate to

25

the PDP-15 computer. The photograph below (Fig. 3.1a)

shows an user using the Graphic-15 display system. The

light-pen is an input device and the display console is

an output device of the graphic processor. Fig.3.lb is a

block diagrammatic representation of the PDP-15 computer

and the Graphic-15 display system. Also, there are six

pushbuttons on the display console which give additional

control over the graphic system operation. The display

system of the Graphic-15 is a directed-stroke (unlike the

raster-type TV display) refreshed display system. The

directed-stroke system allows easy and quick generation

of CRT display of any real-time light-pen motion on the

CRT screen. The light-pen is connected via a flexible light

guide to a photomultiplier. This combination produces an

output only from the light

Fig. 3.1a Photograph showing an user using the Graphic-15 display system.

26

caused by the writing electron beam and not from the

after-glow light when the electron beam has moved past

the point. The light-pen has a mechanical shutter on it

which is used to prevent any unwanted light from entering

the light guide. The CRT screen on the display console

is 11* in the horizontal direction and 9h in the -

DATA AND CONTROL BUS

PDP-15 I/O BUS

C >

PDP-15

VT15

VT04

COMPUTER

GRAPHIC PROCESSOR

ANALOG BUS

DISPLAY' CONSOLE

Fig. 3.1b Block diagrammatic representation of the PDP-15 computer and the Graphic-15 display system.

vertical direction (Fig. 3.1c). The screen is divided into

two areas— the major image area (or the main area) and the

minor image area (or the offset area). By appropriate use

of the Graphic-15 instructions the movement of the CRT

electron beam is controlled and the necessary graphic

display is constructed.

As the Graphic-15 display is refresh type, for

MAJOR IMAGE AREA OR MAIN AREA

Y-axis

Origin

0///////j X-axis >

9 /2

MINOR IMAGE AREA

OR

OFFSET AREA

27

any graphic construction to be displayed on the screen,

there must be some local memory to hold the display file

(the display file is a program for the graphic processor),

so that the graphic processor can cycle through the display

file continuously. In this case, the local memory is the

main memory of the PDP-15 computer which is 32K of 18-bit

words of core memory.

Htc 11/24--->i

Fig. 3.1c CRT screen on the display console.

3.2 THE GRAPHIC-15 INSTRUCTIONS

These are the instructions that the VT15 graphic

processor executes. As an example, one of these instructions

is the basic vector instruction. This instruction is 18-bit

long and its bit format is shown in Fig, 3.2a . The three

bits in bit-positions 0-2 form the operation code and tell

the graphic processor what to do (in this case to draw a

basic vector). The vector can be made light-pen sensitive

or insensitive by setting the bit in bi(;-position 3,to 1 or

k 912

1 0 0

Vector direction

Vector length

28

0 respectively. If the bit in bit-position 4 is set to 1

then the vector is drawn visibly and if the bit is set to

0 the vector is drawn invisibly. By setting the three bits

in bit-positions 5-7 appropriately the vector can be drawn

2

1. 0

6

Fig. 3.2b Basic vector directions

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

Light-pen Intensity

Fig. 3.2a Basic vector instruction bit format.

in any one of the possible eight directions (Fig. 3.2b).

The 10 bits in bit-positions 8-17 are for the specification.

of the vector length. The vectors are drawn from the last

position of the electron beam on the CRT screen.

The 'point; plot' ins t ruction in its 10 bits in

29

bit-positions 8-17 specify the electron beam displacement

on the CRT screen, from the origin, either along the x-axis

or along the y-axis specified by the bit in bit-position 6.

This instruction is used to position the electron beam at

some desired point on the CRT screen. The VT15 graphic a

processor has Ahardware character generator. By using - the

'character string' instruction any 'text' can be displayed

on the screen.

Then there are 'parameter' instructions. Using

these instructions, the intensity of the vector(s) or

character(s) can be set to any one of the possible eight

levels. Any one of the 16. scale factors can be chosen (this

feature is used for scaling the graphic construction), The

vector(s) or character(s) can be blinked or rotated.

3.3 CIRCUIT DATA INPUT

3.3.1 The display file

The display file is the program for the graphic

processor and is- formed out of the graphic processor

instructions. The digital instructions are converted into

analog signals that drive the x- and y-axis deflection

circuits of the CRT display. As an example, the display

file needed to produce the capacitor symbol. of Fig. 3.3.1a

must contain seven vector instructions. The dotted lines

represent the unintesi.fied vectors. Like this capacitor

symbol, other component symbols are needed to be able

to 'draw' the circui .diagram on the CRT screen. A 'menu'

is formed with the component symbols and is displayed

in the offset area of the screen (Fig. 3.3.1b).

r

30

2A

1

3

6

7

5

Fig. 3.3.1a Capacitor symbol.

Component symbols will also appear in the circuit diagram

and usually more than once. Therefore, instead of repeating

the display files for the component symbols, they are made

in the form of subroutines.

Menu

Group 1

Group 2 Group 3

No. 4 No. 5

No. 6

No. 7

Fig. 3.3.1b Circuit diagram drawing with the light-pen.

} } 4- 4- r 4- }t 4,4

-7w

+ 4- t -y -s• 4- .4- t i J

31

These subroutines are called from a master display file

whenever a component symbol needs to be displayed One such

master file is the display file for the circuit diagram. -

3.3.2 Starting the circuit dia ram drawing

At the beginning of the circuit diagram drawing,

the user must select a point on the screen of the CRT at

which the drawing is to start. When a light-pen is pointed

(a) (b)

Fig. 3.3.2 'Nēt' pattern generated to find (a) the x-co- ordinate and (b) the y-coordinate of the light-pen hit point.

at the CRT screen with its shutter open, it 'see's a:-

circular area (the field of view of the light-pen). As the

light-pen is a passive device, the presence of a writing

electron beam on the screen and within its field of view is

necessary for it to serve any useful purpose. At the

beginning the CRT screen is blank. Therefore, a graphic

pattern is generated which is made up of a series of

32

vectors and looks like a 'net' (Fig. 3.3.2a). Now, if the

light-pen is pointed at the 'net' pattern (with its shutter

open), as soon as the writing electron beam comes within

the field of view of the light-pen, the light-pen flag is

raised by the graphic processor. Immediately, the PDP-15

causes the graphic processor to halt.

The graphic processor has two position registers

-- the x-position register and the y-position register.

When the graphic processor is halted these two registers

hold the x- and y-coordinate values of the end of the vector

that was being drawn. The PDP-15 reads the x-position

register to get the x-coordinate of the light-pen hit

point. Then the PDP-15 modifies the 'net' display file

and restarts the graphic processor. This time, a slightly

different 'net' pattern is produced (Fig. 3.3.2b), Now,

as soon as the writing electron beam comes within the

field of view of the light-pen, the graphic processor and

the PDP-15 take the same set of actions, with the only

•exception that the register is read by the

PDP-15 to get the y-coordinate of the light-pen hit point.

Now both the x-coordinate and the y-coordinate of the light-

pen hit point are known. The 'net' pattern is removed.

A 'tracking cross' is displayed at the point of

the light-pen hit. Also, the component 'menu' is displayed

in the offset area of the screen. If the light-pen is

pointed at the tracking cross (with the shutter open)

and moved on the CRT screen, the tracking cross follows

the light-pen.

Light-pen's field of view

Centre of light-pen's field of view

Tracking cross

X c -71 X X2 )/2

Yc =(Y, +Y2)/2

33

3.3.3 The tracking cross operation

The field of view of the light-pen is a circular

area (Fig. 3.3.3a). When the light-pen is moved away from

the tracking cross, the computer needs to know the new

position of the centre of the field of view of the light-pen

in order to be able to move the tracking cross there.

Fig. 3.3.3a The tracking cross and the field of view of the light-pen.

Following is a description of how the x- and the y-

coordinates Xc andYc respectively of the centre of the light-

pen's field of view aie determined.

Arm no.1 < < ( <

x

/

/ /

/

A

Start

< < < < < < <

34

The tracking cross has four intensified arms

(Fig. 3.3,3b). Arm no.2 and arm no.4 are drawn side by

side in the figure for the sake of clarity, but in the

actual case the electron beam draws them along the same line

on the CRT screen. That is also the case with arm no.1

and arm no.3

p4Finish i

/4

V

Arm no.2 Arm no.4 /

Arm no.3 • • \

• • • \

• •

/

`\ / \ / \ / ♦ / ♦R V .. )/

\ I • / \ \ Y A /

♦ / • / ♦

Fig, 3.3.3b The construction of the tracking cross.

The light-pen is switched on (using graphic

processor instruction) before drawing each of the four arms.

Now, if the light-pen is pointed at the tracking

35

cross (Fig. 3.3.3a and Fig. 3.3,3b), as soon as the

electron beam while drawing arm no.1 enters the field of

view of the light-pen, the graphic processor raises the

light-pen flag and the PDP-15 receives an interrupt signal.

Immediately, the light-pen is switched off and the graphic

processor is halted. The x-position register is read to get

the value of X2 (Fig.3.3.3a). Then the graphic processor

will resume operation and draw the rest of arm no.1, with

the light-pen still switched off, to prevent any more

light-pen interrupt taking place on this arm. At the

completion of the drawing of arm no.1, the light-pen is

switched on and 'arm no.2 is drawn. During the process of

arm no.2 drawing, the same set of events take place, with

the only exception that this time the y-position register

is read to get the value of Y2. (Fig. 3.3.3a). Then arm no.3

and finally arm no.4 are drawn to get the values of Xi and

Y . Now the coordinates Xc and Yc are calculated and the

tracking cross is moved to this new position.

The whole process is repeated over and over again

as the light-pen is moved over the CRT screen and the

tracking cross keeps on following the light-pen.

Although, the tracking cross can be moved to any

point on the screen by tracking cross operation, while

circuit drawing the movements of the tracking cross and the

circuit diagram are allowed only along the lines of a

grid-structure. This is done to facilitate the management

of the circuit diagram data.

36

3.3.4 Thegrid-structure and circuit diagram date.

management

The grid-structure is made up of 25 vertical

lines (each having a particular Ml value in the range from

1 to 25) and 25 horizontal lines (each having a particular

N'value in the range from 1 to 25). Four vertical and four

horizontal lines are shown by dotted lines in Fig. 3.3.4a.

I I I I I I I

1 1 1 1 1 1 I 1

N=g ----------1-- 1 -----+---- '

1 1 1 I 1 I I I I 1 1 I

N =g -- i -----t I I 1 1

ii

37

For a horizontal path K'is equal to 1 and for a vertical

path Ke is equal to 2. The M/ and Nfi index numbers for both

of the paths are the same as that of their intersection

point (i.e. M= 4 and N= 7) . A path can be a node or a branch.

In figure 3.3,4b three paths are shown, two of them are

branches and the third one is a node.

The information about a path is kept in an 18-

bit word and this is explained with reference to figure

3.3.4c.

4 5 6 7 8 9 10 11 12 13 14 15 16 17

J

Branch or node number.

A value to calculate the address corresponding to this path in the display file.

Branch or node.

Fig. 3.3.4c One 18-bit word containing information about a path.

The bit in bit-position 0 is set to 1 if the path is a

branch and 'is set to 0 if the path is a node. The seven bits

in bit-positions 1-7 contain the branch or node number. The

ten bits in bit-positions 8-17 contain a number which is

used to calculate the addresses of a group of words in the

master display file,for the circuit diagram. A path array

is formed with such 18-bit words (figure 3.3.4d).

10 bit

38

First word First word

Group of words corresponding

714th word

to a path

18 bit 18 bit >

Displa-cement value

This 10 bit contains the displac-ement value

Fig. 3.3.4e The master display file for the circuit diagram.

Fig. 3.3.4d The path array.

39

Corresponding to any path there are three path indices--

Mt, N and K. Using these three path indices, the address

of the word in the path array corresponding to the path

in question is calculated in the following way:

Address of the Address of the word in the = 50M + 2N

/+ K

/- 53 + first word in

path array the path array

As an example, let it be supposed that a capacitor symbol

is displayed at the position of the path having indices

M p =15, N~ =8 and K~ =1 as shown in Fig. 3.3.4d. The address

of the word in the path array corresponding to this path

is given by,

Address of the Required address = 50*15 + 2*8 + 1 -53 + first word in

the path array

= 714+ [Address of the first word in the path array

The 10 bits in the word at this address hold a 'displacement

value' (Fig. 3.34e) used to calculate the address of the

group of words corresponding to this path, in the master

display file for the circuit diagram. One word of this

group is a 'call' to subroutine. In this particular case,

the subroutine is the display file for the capacitor symbol.

The other words in L.he group contain such information as

whether to blink the component symbol or not, whether the

component symbol is to be drawn vertically or horizontally,

etc.

40 •

3.3.5 Component selection from the Menu'

During the circuit diagram drawing process,

components have to be selected from the component menu

displayed in the offset area of the screen (figure 3.3.1b).

There is a 7-bit hardware register called the 'name

register' in the graphic processor. Using graphic processor

instructions any number from 0 to 127 can be loaded into

this register. The content of this register can be read by

the PDP-15 and, depending on the value, appropriate

branching action can be taken in the program. The name

register is loaded with different values before drawing

each of the component symbols.

As an example, the name register can be loaded

with the number 1 by an instruction which is followed by an

instruction making a 'call' to the display file subroutine

for the capacitor symbol. Then another instruction causing

the number 2 to be loaded into the name register and follo-

wed by an instruction 'call ing the subroutine for the

resistor symbol display file. Let it be assumed, that these

four instructions form a part of a master display file

(for displaying offset area 'picture'). Now if the light-

pen is pointed at the capacitor symbol, then as soon as

the writing electron beam comes within the field of view of

the light-pen, the graphic processor is halted and the

content of the name register is read to find out which

component symbol was hit. This is illustrated by the

flow-chart of figure 3.3.5.

Halt the graphic processor

Yes

it component is a capacitor

Yes

Load the 'name register' with 1

41

Draw the capacitor symbol and wait for a light-pen hit

Light-pen hit

No light-pen hit

Load the 'name register' with 2

Draw the resistor symbol and wait for a light-pen hit

Light-pen hit

No light-pen hit'

Fig, 3.3.5 Flow-chart illustrating the identification of component symbols hit by the light-pen.

42

3.3.6 Scaling the circuit diagram

One of the instructions of the graphic processor

allows any vector to be repeated upto 15 times. Using this

facility a graphic construction can be enlarged upto 16

times its original size.

Normally the circuit diagram is drawn with a

scale factor of 2 (i.e. the vectors are three times their

original size). Using a light-button called ZOOM (button

no.5 in Fig. 3.3.1b), the scale factor can be increased or

decreased and thereby the circuit diagram enlarged or

reduced. If the left-hand side of the ZOOM button is hit

with the light-pen the scale factor is reduced by 1 and if

the right-hand side of this button is hit the scale factor

is increased by 1.

3.3.7 Moving the circuit diagram on the screen

When the scale factor is equal to 3 or greater,

the size of the grid-structure is larger than the CRT screen

area. With this !situation the screen acts as a 'window'. To

look at or to draw a circuit on the part of the grid-

structure which is not within the 'window', the grid-

structure has to be moved. Using the 'move circuit' light-

button (button no.7 in Fig. 3,3,1b), the grid-structure

and hence the circuit diagram can be moved on the CRT screen.

At first, the 'move circuit' light-button is selected with

the light-pen. Then, the light-pen is pointed at the circuit

diagram and the tracking cross appears under the light-pen.

Now, if the light-pen is moved on the screen of the CRT,

43

the tracking cross and the circuit diagram moves with the

light-pen.

3.3.3 Assignment of values to the circuit elements

Values to.the circuit elements can be assigned

either by using the light-pen and the light-buttons or the

light-pen and the teletype. The light-pen is used to select

the circuit elements and the light-buttons. The light-

buttons are in the offset area of the CRT screen and have

some preferred values on it (Group 1 in Fig. 3.3olb). Also

there are some light-buttons each having a multiplication

factor associated with it (Group 2 and Group 3 in

Fig. 3.3.1b). For example, selection of the light-button

4.7 from Group 1 and *100 from Group 2 will result in a

value of 470 and this can be assigned to a circuit element

by hitting the element with the light-pen.

3.3.9 Deletion and erasing

Any part of the circuit diagram can be deleted

using the light-button DELETE (No.4 in Fig. 3,3.1b).

Any component or line hit by the light-pen, with this light-

button selected will be deleted. There is another method of

. deletion which can be used while drawing the circuit diagram.

If the light-pen is moved back over any existing line or

component (excepting the three-terminal ones) from the open

end, the line or component is deleted,

The 'erase circuit' light--button (No.6 in

Fig. 3.3.1b) can be used Lu deleLe Lhe euLire circuit;

44

diagram at the same time. If a light-pen hit is made on

this light-button a warning message appears on the CRT

screen and the computer ask for confirmation. Now a second

hit on this button will result in the entire circuit diagram

being erased. While, any other action by the user will cause

the first hit (on the 'erase circuit' light-button) to be

ignored.

3.4 NOISE DATA INPUT

Thermal and shot noise sources are simulated for

the purpose of noise analysis. For each circuit component

which is responsible for causing either thermal or shot

noise mechanism, a noise current source is formed and

connected across the component. This noise current source

is not displayed with the circuit diagram. Noise parameters

are assigned to the circuit components and are used to

calculate the noise current source values.

3.4.1 Assignment of shot noise parameters

For the simulation of shot noise sources (sub.-

sec. 2.1.2) the value of the quiescent current is necessary.

In the offset area of the screen, there are light-buttons

for making the assignments of noise parameters. Under the

heading '*SIIOT NOISE' is the light-button 'NOISE CURRENT'

(No.3 in Fig. 3.4a). If this light-button is selected with

the light-pen, a 'box' (No.4 in Fig. 3.4a) appears under

the light-button indicating that a value is needed for the

quiescent current (to calculate the shot noise current).

Then this current value can be assigned to the intended

~---No.2

( No.5

( No.6

Fig. 3 0 4a Assignment of noise parameters to circuit components 0

45

component by hitting the component with the light-pen. The

assigned quiescent current value is displayed beside the

component as an indication to the user that the component

has received the value and also for future reference.

3.4.2 Assignrnent of thermal noise parameters

For the simulation of the thermal noise source

(sub.-sec. 2.1.1), the resistance and the temperature of the

resistor are needed. The resistance values are already

assigned to the resistors during circuit data input. There

are two light-buttons (No.1 and No.2 in Fig. 3.4a) under the

heading '*THERMAL NOISE'. The second of these two light-

46

buttons is the 'TEMPERATURE' light-button. Using this light-

button any temperature value in °C can be assigned to a

resistor. When this button is selected a 'box' appears

below it, indicating that a value for the temperature is

needed. When this value is typed-in (via the teletype) it

is stored (in the computer memory) and displayed within the

'box'. The value is assigned to a resistor and displayed

beside it, when a light-pen hit on the resistor is made.

Components having ohmic resistance and at a

temperature higher than °0 K will have thermal noise. And

usually there will be many such components (resistors) in a

circuit. Therefore, at the beginning (of noise data input

stage) thermal noise is assigned to all resistors automati-

cally. In this automatic thermal noise source simulation

room temperature value is used. Using the 'TEMPERATURE'

light-button this room.temperature value can be changed to

any temperature value. The first of the light-buttons under

the heading '*THERMAL NOISE' is the 'NOISELESS-RESISTOR'

button. Selection of this button and a subsequent light-pen

hit on any resistor will result in a label 'NLR'

(Noiseless resistor) being put beside the resistor and the

resistor will have no thermal noise contribution. This

facility is necessary in cases where dynamic resistances

are present in a circuit, because they will be represented

by resistors in a circuit diagram, and autom:.tic assignment

of thermal noise will be made to them.

When any one of the three light-buttons----

'NOISELESS-RESISTOR', 'TEMPERATURE' or 'NOISE CURRENT' is

selected the relevant labels on the circuit components

4?

are displayed at a higher intensity level for ease of

identification. As an example, in Fig. 3.4a in the photogr-

aph the 'NOISE CURRENT' light-button is selected and as a

result the noise current values displayed beside the compo-

nents in the circuit diagram are at a higher intensity

level.

3.4.3 Deleting and clearing the assignments

There is a light-button called 'DELETE' (No.5 in

Fig. 3.4a). Using this button any parameter assignments can

be cancelled. When the 'DELETE' button is selected a flash-

ing 'box' is displayed around this button as a warning to

the user. For example, to cancel any temperature assignment,

this button is selected alongwith the 'TEMPERATURE' button.

Then a light-pen hit on a resistor having temperature

assignment will result in temperature being restored -to

room temperature. In this way any number of assignments can

be cancelled. But cancelling many or all the assignments

in this way will be a tedious job. Therefore, another option

has been created: There is a light-button called 'CLEAR'

(No.6 in Fig. 3.4a) and using this button all assignments

can be cancelled simultaneously. There is a lock to

prevent any accidental cancellation. A first light-pen hit

on this light-button causes a warning message ("CLEAR ALL

ASSIGNMENTS ? PLEASE CONFIRM.) to be displayed. At this

stage, a light-pen hit on any other light-button will

cause the first hit on the 'CLEAR' button to be ignored,

the warning message to be removed and appropriate action

depending on the light-button hit to be taken. On the other

48

hand, if a second hit is made on the 'CLEAR' button then

all the assignments will be cancelled.

3.4.4 Simulation of noise sources for the bi.olar

transistor

Three noise sources --- one thermal and two shot

noise sources are simulated for a bipolar transistor (sub.-

sec. 2.3.3). The base spreading resistance and the quiescent

operating condition need to be known. The base spreading

resistance value is obtained from the transistor data

library (sec. 5.1).

With a circuit which has bipolar transistor as

a circuit component, as soon as the 'circuit definition'

(circuit drawing) stage is cancelled,the nonlinear

dc-analysis (chapter 4) is automatically selected. At the

end of the dc-analysis, the quiescent collector and base

currents are stored for later use. The stored quiescent

current values are used for shot noise source simulation.

For the simulation of these three noise

sources the user does not need to do anything.

3.4.5 The noise parameter assi•nment rogram

The flow-chart for the noise parameter assignment

program is broken down into four parts and shown in

Fig. 3.4b, Fig. 3.4c, Fig. 3.4d and Fig. 3.4e. This program

is selected by pointing the light-pen at the 'ASSIGN NOISE'

light-button (Fig. 5.3 ). As the execution of this program

starts (see flow-chart of Fig. 3,4b), the light-buttons and

49

the circuit diagram are displayed as in Fig. 3,4a.

Thermal noise is assigned to all the resistors

(at room temperature) and then a waiting point is reached.

The computer waits here until a light-pen hit occurs.

If a light-pen hit occurs a test is made to determine

whether the hit was in the main area or the offset area of

the CRT screen.

If the hit is in the offset area of the screen,

the control goes to the part of the program whose flow-chart

appears in Fig. 3.4c. The hit light-button is sorted out

first. If the 'NOISE ANALYSIS' light-button is hit the

control returns from this program (i.e. the noise parameter

assignment program) and goes to 'circuit definition'

program which is for circuit data input. If the 'ASSIGN

NOISE' light-button is hit the control returns from this

program and goes to the program from where either this

program or other analysis programs as shown in Fig. 5.3

can be selected (see Appendix B). For a light-pen hit on

any other light-button, appropriate action is taken and the

control goes to in Fig. 3.4b where it waits for a further

light-pen hit.

Of the three light-buttons, namely, 'NOISELECS-

RESISTOR', 'TEMPERATURE', and 'NOISE CURRENT' (Fig. 3.4a)

only one can be selected at any time. For example, if the

'TEMPERATURE' light-button is selected and then a light-pen

hit is made on the 'NOISELESS-RESISTOR' light-button; the

former will be cancelled and the later will be selected.

Of course, most of the light-buttons can be cancelled by

50

hitting it a second time with the light-pen.

Now, if a light-pen hit occurs on the circuit diagram, a test is made to see if the 'DELETE' light-button

is already selected. This 'DELETE' button can be selected

in conjunction with any one of the three light-buttons

already mentioned (NOISELESS-RESISTOR', 'TEMPERATURE' and

'NOISE CURRENT'). If this light-button is not selected the,

the control goes to the section of the program whose

flow-chart is shown in Fig. 3.4d. This section of the

program is used to make noise parameter assignments, and

some error checks are also made here. For example, the

temperature assignment to any component other than a

resistor is not permitted. At the completion of a parameter

assignment to a component the control goes back to in in

Fig. 3.4b.

If the 'DELETE' light-button is selected and a

light-pen hit is made on the circuit diagram, the control

goes to the part of the program whose flow-chart appears

in Fig. 3,4e. This section of the program is for the

cancellation of any noise parameter assignment. When the

user cancells an assignment, the program restores the state

of the circuit element that existed before that particular

assignment was made. For example, if the user cancells the

'no thermal noise' assignment to a resistor, the program

will assign to the resistor thermal noise at room

temperature.

0 comes from of Figs. 3.4c, 3.4d and 3.4e.

Assign thermal noise at room temperature to all resistors.

Yes

51

{

Display the light-buttons and the circuit diagram (as in Fig. 3.4a)

On the circuit On the light-button

No

Yes

O2 goes to O2 of Fig. 3.4c.

3 goes to O3 of Fig. 3.4d.

O goes to O of Fig. 3.4e.

Fig. 3.4b Part of flow-chart illustrating noise data input.

52

Yes 'NOISE ANALYSIS'

button hit 9

Go to 'CIRCUIT DEFINITION' stage.

No

'ASSIGN NOISE' button hit

9

Yes

Go to the stage from where either 'ASSIGN NOISE' or any other noise analysis program can be selected.

No

Yes •'NOISELESS-RESISTOR'

button hit 9

Select this button and cancel any other button if selected.

Yes Select this button and cancel any other button if selected.

'TEMPERATURE' button hit

9

Yes Select this button and cancel any other button if selected.

'NOISE CURRENT' button hit

9

'DELETE' button hit

9

Yes Select this button, draw a blinking 'box' around it cancel 'CLEAR' button if selected and remove the warning message if on.

'CLEAR' button hit

9

Yes, 1st hit Display the warning message "CLEAR ALL ASSIGNMENTS ? PLEASE CONFIRM" .

Yes, 2nd hit

Clear all assignments, remove the warning message and cancel all the light-buttons..

of Fig. 3.4b

jr of Fig. 3.4b

O goes to (2 comes from

Fig. 3.4c Part of the flow-chart, illustrating noise data input.

Assign noise temperature. Make

'Noiseless-resistor' assignment.

~1 goes to

(3 comes from

in Fig. 3.4b

in Fig. 3.4b

53

'Noiseless-resistor' button selected

9

Yes

Is 'Temperature'

button selected 7

Is hit component a resistor

Yes

No

'Ignore.

Ignore.

No

Yes

Is 'Noise current' button selected

9

Ignore.

v Yes

Assign noise current.

Is hit component 'a resistor

Fig. 3.4d Part of the flow-chart illustrating noise data input.

54

Cancel 'shot noise' assign-ment only.

1O goes to

comes from

of Fig. 3.4b

of Fig. 3.4b

Is 'NOISE CURRENT' button selected

Yes Is it

a resistor with 'shot noise' and 'no thermal noise'

assignment

Ignore No

Restore to a resistor with 'thermal noise at room temp.' assignment.

Is it a resistor with

'no thermal noise' assignment

Yes

N

Ignore

Is 'TEMPERATURE' button selected

Yes

s it a resistor

with 'temperature' assignment

Yes

Ignore

N

Is it a circuit element with 'shot noise'

assignment only ?

Yes • ICancel 'shot noise' assignment.

Is 'NOISELESS-RESISTOR'

button selected

Yes

Fig. 3.4e Part of flow-chart iliustraLing noise data input.

55

3.4.6 The display .file for displaying assignments

A display file is formed to display the three

types of assignments— 'NLR' (for noiseless-resistor),

'temperature' and 'noise current'. From now on they will

also be referred to as type 1 (for 'NLR'), type 2 (for

'temperature') and type 3 (for 'noise current'). A group

of five consecutive words of memory is used to display

the assignment of one type to one branch. The groups

belonging to the same type are linked up. The relative

positions of the groups in the linked-up structure are

dependent upon the order in which the branches (to which

they correspond) were selected, when the assignments of

a particular type were being made. Whereas, the relative

positions of the groups in the memory locations are

dependent upon the branch numbers to which they correspond.

To explain the construction of a group, the

group 2 of type 1 (Fig. 3.4.6a) is discussed. All the groups

excepting the first and the last (to be discussed later)

are similar to this group. The second and the third words

contain instructions to position the electron beam near the

relevant branch position on the CRT screen. The instruction

in the fourth word writes the label 'NLR'. The fifth worn

has the instru ion to cause a jump to the second word of

the group 3 and this is how the link among the groups of a

type are maintained. The first-word of this group holds the

address of the first word of the group 1 (of type 1). And

this address is used, if the 'DELETE' light-button is used

to cancel the `NLR' assignment to branch no.3. Because then.,

Address of pointer group which points at 2nd word of this group

Move the beam along the x-axis

Move the beam along the y-axis

Display the 'NLR' label

Jump to 2nd word of group 2 of type 1

J

1 -4

-1

J 1

Address of 1st word of previous group of type 1

Move the beam along the x-axis

Move the beam along the y-axis

Display the 'NLR' label

Jump to 2nd word of group 3 of type 1

—1

1

56

Branch no 1 : Group 1 : Type 1

Branch no 2 : Group 1 : Type 2

Branch no 3 : Group 2 : Type 1

Branch no 4

Branch no 5 : Group 3 : Type 1

Branch no 6 : Group 2 : Type 2

Fig. 3.4.6a The linked-up groups of the type 1 and the type 2.

5?

group 2 is excluded from the linked-up groups of type 1 and

a new link is formed from group 1 to group 3.

The linked-up structure of the groups of type 2

is similar to that of the type 1.

Because a resistor cannot have the 'NLR' and the

'temperature' assignments at the same time, the same area

of the core memory can be shared by the linked-up structures

of the type 1 and • the type 2. A group can be removed from

the linked-up structure of type 1 and added to the linked-

up structure of type 2 and vice versa. This is done if the

'NLR' assignment of a resistor is changed to a 'temperature'

assignment and vice versa.

The linked-up structure for type 3 is similar

to that of the other two types . But as a circuit component

can have the 'NLR' and the 'noise current' assignments at

the same time, this linked-up structure is kept in another

part of the core memory.

Fig. 3,4.6b illustrates the way in which the

three linked-up structures of type 1, type 2 and type 3 are

interlinked. In the figure the groups of any one type have

been drawn as if they are adjacent and sequential, for

ease of illustration but in the real case they are unlikely

to be so.

There are three pointer groups---one for each of

the three types. The pointer group consists of two words;

the first word contains the intensity level instruction.

When a particular type is selected, the first word content

i

1st group

2nd group

Last group

Pointer group

Intensity level

Jump to 2nd word of group 1

Address of pointer group of type 1

Jump to pointer group of type 2

Pointer group

Intensity level

Jump to 2nd word of group 2

Address of pointer group of type 2

Jump to pointer group of type 3

1st group

2nd group

Last group

Pointer group

Intensity level

Jump to 2nd word of group 3

Address of pointer group of type 3

Go to another display file

Type 1 Type 2• Type 3

Fig. 3.4.6b The interlinking of the linked-up groups.

59

of the pointer group corresponding to that type is modified.

For example, if the light-button 'TEMPERATURE' is selected

with the light-pen, then the instruction contained in the

pointer group of type 2 is modified to increase the

intensity level. As a result, any assignment displays)

caused by the group(s) of type 2 will become brighter. The

first word of the first group of any particular type holds

the address of the respective pointer group.

The last word of the last group of type 1 and

type 2 contain jump instructions to the pointer group of

the type 2 and type 3 respectively. Whereas the last word

of the last group of type 3 contain a jump instruction to

the start of the another display file (for example, the

circuit diagram display file or the light-button display

file).

3.5 ANALYSIS RESULTS OUTPUT

All circuit analysis results are outputted on

the CRT screen, in the form of numbers, graphs and symbols.

Analysis results that are calculated as a

function of a single variable (for example, output noise

voltage as a function of frequency) are well represented

by graphs (Fig. 5.3.1b).

The nonlinear dc-analysis results-- the quies-

cent node voltages and the nonlinear device currents are

shown by numbers. It is very useful for the user to be able

to 'see' the voltages and currents beside the nodes and the

devices concerned (Fig. 4.4d ).

60

In some cases, it is not necessary to know the exact values

of some quantities, rather a knowledge of their relative

importance is more useful. In such cases, the various

quantities can be represented by symbols, the sizes of the

symbols being dependent upon the quantities they represent.

One such case is that of the relative importance of the

noise contributions of the various circuit components

(Fig. 5.3.2a).

3.6 SUMMARY

For the noise analysis of a circuit, information

about the circuit and the noise mechanisms are needed by

the computer. A Graphic-15 display system (consisting of a

graphic processor, a display console and a light-pen) and

a PDP-15 computer are used.

Circuit data is inputted by 'drawing' the circuit

diagram on the CRT screen of the graphic display console by

using the light-pen. The graphic processor executes its

program (called 'display file') and produces analog signals

for the x- and y-deflection circuits of the display console

which in turn controls the electron beam of the CRT.

When the light-pen, which is a passive device,

is pointed at the CRT screen a signal is sent to the compu-

ter if the writing electron beam passes through its field

of view. The position of the electron beam on the CRT screen

when the signal (to the PDP-15) was sent gives the point

at which the light-pen was pointed at. A graphic pattern

is generated in a systematic way on the blank screen, so

61

that the user can select a starting point with the light-pen

for circuit diagram drawing. At the selected starting point

a 'tracking cross' is displayed, which serves two purposes

-----the first is to let the user know the latest position on

the screen the light-pen was moved to and the second is to

calculate the new position of the light-pen on the screen,

when the light-pen is moved. During the 'drawing' process,

circuit components are selected from the 'menu' displayed

on the screen. Value to the circuit components are given

either by using the light-buttons (with values on them) or

the teletype. Then there are such facilities as circuit

diagram deletion, enlargement, reduction etc.

The noise data are inputted by making noise

parameter assignments. Some assignments are automatically

made (by the computer). While other assignments are left

for the user to make. Any assignment can be changed to a

different type. Assignments can be cancelled one at a time

or all at the same time.

At the completion of the circuit analysis, the

results are displayed on the CRT screen by graph plots,

numbers and symbols.

62

CHAPTER FOUR

NONLINEAR DC-ANALYSIS

If any nonlinear device like a semiconductor

diode or a transistor is present in an electronic circuit,

then it is necessary to know the quiescent operating point

by carrying out the nonlinear dc-analysis before any noise

or small-signal gain-phase analysis can be done. Also, the

values of the shot noise sources are directly dependent on

the quiescent currents of the diodes and the transistors.

The nonlinear dc-analysis requires the solution

of a set of simultaneous nonlinear equations. But due to

the highly nonlinear nature of the diode and the transistor

p-n junction characteristic, the solution of the equations

cannot be found by direct algebraic manipulation [16] .

The solution can be obtained by using the method of succe-

ssive approximations. Almost all of the presently available

nonlinear dc-analysis programs use algorithms based on the

Newton-Raphson iteration technique.

Two efficient analysis programs BIAS-3 [17J and

CANCER [15] capable of nonlinear dc-analysis have been

reported. The program BIAS-3 is reported, to have been

tested quite extensively with different types of circuits

for more than a year and found reliable. Also, algorithms

similar to that of BIAS-3 have been used in several other

circuit analysis programs [19] , [20] , [21] and found fast

and reliable. For our nonlinear dc-analysis an algorithm

63

similar to that of BIAS-3 has been used.

4.1 NEWTON-RAPHSON ITERATION TECHNIQUE

The standard Newton-Raphson iteration technique

can be explained with a simple diode-resistor circuit.

(Fig. 4.1a). At first, a trial operating point is selected

Fig. 4.1a The diode-resistor circuit.

at some point (vd0'Ido)

on the nonlinear diode characteristic

(Fig. 4.1b). The nonlinear characteristic is then replaced by

a straight line which is tangent (to the nonlinear character-

istic) at the operating point. This is equivalent to approxi-

mating the diode by an independent current source in parallel

with a linear conductance. The value of the conductance is gi-

ven by the slope of the tangent and the value of the current

source is given by the intercept on the diode current axis.

The solution of the circuit with the approximated

diode gives the new diode voltage Vd1 (at the point P1) . When

this point is projected vertically up, the second trial ope-

rating point (v, , idi ),is obtained. Now, the nonlinear cha-

V/R

t

Id

64

racteristi.c is linearized at the second trial operating poi-

nt and the circuit is solved which leads to the third trial

operating point (Vd2, Id2). A linearized characteristic and

circuit solution at the third trial operating point leads to

the fourth and finally the real operating point P4 is found.

Vd V

Fig. 4.1b Illustrating the standard Newton-Raphson iteration.

The standard Newton-Raphson iteration is not

suitable for the solution of problems where rapidly varying

functions such as exponentials have to be evaluated. • As

with the diode-resistor case, a small increase in the

junction voltage causes a much greater increase in the

V/R

Id

V Vd

Fig. 4.1c Modified NewLon-Raphson iteration technique.

65

diode current and may even result in computer word-overflow

as illustrated in Fig. 4.1c.

4.2 MODIFICATIONS TO THE NEWTON-RAPHSON ITERATION

TECHNIQUE

One way of getting round the possible numerical

ill-conditioning (word-overflow) is to use a method [17] ,

which will now be described. At first, a trial operating

point is guessed at Pb (Fig. 4.1c).

66

After linearizing the circuit at the first trial

operating point P0 , the circuit is solved and the point P1

is obtained. Now instead of projecting the point P1

vertically up, it is projected horizontally on the nonlinear

characteristic and the second trial operating point ( v d1 Idl ) is obtained. Mathematically, this is done by taking

the logarithm of the currentIdlcorresponding to the point

Pl , which yields voltage vd1.

This method of updating with current, not only

avoids the possiblity of computer word-overflow, but also

reaches the actual operating point in less number of

iterations by damping the magnitude of the increasing

junction voltages. When the junction voltage decreases and

also when the junction voltage is negative, updating of the

operating point is done with voltage as in the standard

Newton-Raphson iteration.

The magnitude of the decreasing junction voltage

can be reduced by introducing a damping factor.

Another problem is the numerical ill-conditioning

(computer word-underflow) due to very small value of the

slope of the linearized characteristic when the value of

the junction voltage is very sm211 or negative. This-

problem has been taken care of in BIAS-3 by drawing a

straight line between the trial operating point and the

origin instead of the tangent.

Whereas in the computer program CANCER, for

junction voltages less than 10VT (where, VT =kT/q) instead

of making the value of the linear conductance equal to the

67

slope of the tangent, it is given the value of 10.0E-12

Siemens but the value of the independent current source is

calculated in the usual way.

4.3 TRANSISTOR MODELLING FOR THE DC-ANALYSIS

The well-known Ebers-Moll bipolar transistor

model [22] , [23] is shown in Fig. 4.3a.

o Collector

VBC

Base

VBE IF

Emitter -I E

Fig. 4.3a Ebers-Moll bipolar transistor model.

The currents through the diodes are

I = I exp VBE !- 1 F ES VT j- and IR _ ICS eXp VT

which are also the reference currents for this model. IES

and ICS are the emitter-base and collector-base saturation

68

currents respectively. aF and aR are the large-signal

forward and reverse current gains of a common-base

transistor. The diodes represent the two junctions of the

transistor and the two current-controlled current sources

represent the couplings between the two junctions.

The transistor model of Fig. 4.3a can be slightly

modified and the mathematically equivalent model of

Fig. 4.3b is obtained.

• Collector

VBC O ICC

I Base •

VBE ICC /aF IEC

Emitter

IE

Fig. 4.3b Slightly modified Ebers-Moll bipolar transistor model.

For the model of Fig. 4.3b the reference currents are the

currents of the controlled sources;

ICC __ (*F

IES 7.3

vBEI - 1 and ~ ! T j

I

Base

VBC

69.,

VBC

IEC __ aR ICS exp V

1 T

The transistor model of Fig. 4.3b can be simpli-

fied and the following nonlinear hybrid-Tr model of Fig. 4.3c

is obtained.

Collector

IEC /RR

Q ICC (DIEC

VBE 0

• Emitter IE

/RF

SF = aF/(1-(F) and = aR/(1-aR)

Fig. 4.3c Nonlinear hybrid-Tr transistor model.

This nonlinear hybrid-Tr transistor model has been used in

the dc-analysis program.

4.4 IMPLEMENTATION OF THE EC-ANALYSIS PROGRAM

At the beginning, the light-buttons (as in

Fig. 4.4a) are displayed on the CRT screen_ At this stage

Fig. 4. 4a Photograph illustrating the application of supply voltage to a circuit.

it is necessary to assign supply voltage to the circuit.

70

If the light-button 'SUPPLY VOLTAGE' is hit with the light-

pen a 'box' appears just below this light-button. Any value

typed-in on the teletype appears within this 'box'. Then

if any node (of the circuit) is hit with the light-pen,

the supply voltage is assigned to that particu~ar node and

is displayed beside the hit point on the node.

A light-button called 'DELETE' (Fig. 4.4a) has

been provided to enable the user to remove a supply voltage

which might have been applied by mistake.

Now, the circuit is ready for analysis and a

light-pen hit on the button 'START ANALYSIS' (above Figure)

71

starts the process.

At the start of the iteration, transistor

junction voltages are initialized. The base-emitter junction

is forward biased with 0.4 volt and the base-collector

junction is given 0.0 volt. Then if any inductor is present

in the circuit, the nodes between which it is connected are

short-circuited and the nodes are re-numbered (after the

dc-analysis the circuit is returned to its original configu-

ration }. Then the transistors are linearized at the trial

operating point and the nodal admittance matrix of the

circuit is formed. The node voltages of the nodes to which

grounded supply voltages are connected, are known and the

nodal admittance matrix is reduced in the following way.

If the supply voltage is connected to node 'm'

then the mth column of the nodal admittance matrix is

multiplied by the supply voltage value and subtracted from

the node current source vector. The mth row and the mth

column of the nodal admittance matrix are deleted. Then

Gaussian elimination method is used to evaluate the node

voltages.

At this stage the 'error voltage' defined as

Error voltage =(Vnew-Vold)IVold

is calculated for each node. The subscripts 'new' and 'old'

refer to the present and the previous iterations respective-

ly. At the end of an iteration, there are always two sets of

node voltages--- the 'new' set is the result of the present

iteration and the 'old' set is the result of the previous

72

iteration; excepting the first iteration when the 'old' set

contains only zeros.

If each one of the 'error voltage's is less than

or equal to 1.0E-6 the iterative process is stopped.

Otherwise, the new trial operating point is selected and

the next iteration is carried out.

During the dc-analysis, the progress can be

monitored on the CRT screen. Both the error voltage and the

iteration number are displayed (in the offset area of the

screen) as shown in Fig. 4.4b..

Fig. 4.4b Monitoring the progress of the dc-analysis.

The photograph of Fig. 4.4b shows the error

voltage after the dc-analysis has completed the third

73

iteration. In the photograph of Fig. 4.4c, it can be seen

that the error voltage has gone down after the completion

of the fifth iteration.

Fig. 4.4c Monitoring the progress of the dc-analysis.

As the error voltage can have a very wide range

of values wi th a minimum of 1 .. OE-6, the logari thm of the

error voltage is taken and displayed with a shifted scale

to make the minimum value zero.

(Error voltage)" = loglq(Error voltage) +6 .0

The scale is divided into eight divisions. Any value greater

than eight is taken as eight.

74

At the end of the iterations, when the dc-

analysis results are obtained, the iteration number and

the error voltage displays are removed. In their place two

new light-buttons-- 'NODE VOLTAGE' and 'COLLECTOR CURRENT'

are displayed as shown in Fig. 4.4d. The process up to here

is flow-charted in Fig. 4.4e.

Fig. 4.4d Photograph showing dc-analysis results display.

To know the quiescent collector current (or the

node'voltage), the light-button 'COLLECTOR CURRENT' (or

'NODE VOLTAGE') is selected. After selecting the light-

button 'COLLECTOR CURRENT', if a transistor is hit with

the light-pen the collector current of the transistor is

displayed beside the transistor as shown in above Figure.

Similarly, the node voltages can be displayed.

f

1

Display circuit diagram and' dc-analysis light-buttons.

Has the supply-voltage been

applied

Yes

Is 'START ANALYSIS' button

hit 9

Yes

Initialize transistor junction voltages.

Short-circuit inductors (if any), and re-number nodes.

Linearize the transistors and form the nodal admittance matrix.

Solve the matrix to get the new set of node voltages.

Yes

Stop iteration.

Display error voltage and iteration number.

Select the new trial operating point.

Stop displaying error voltage and iteration number.

Display two new light-buttons.

75

Fig. 4.4e Flow-chart illustrating ān ūray ;z is... .

76

4.5 SUMMARY

Nonlinear dc-analysis is essential for circuits

having nonlinear components (like diodes and transistors)

before noise analysis and small-signal gain-phase analysis.

Iterative methods based on Newton-Raphson iteration

technique are almost always used for the nonlinear do--

analysis. Modifications to the standard Newton-Raphson

iteration technique are necessary to avoid possible numeri-

cal ill-conditioning (computer word- overflow and underflow)

and also to speed up the iterative process. Nonlinear

hybrid-Tr model based on the well known Ebbers-Moll bipolar

transistor model has been used in our analysis program.

Supply voltages to the circuit are applied using the

teletype and the light-pen. During the dc-analysis the

'progress' is monitored on the CRT screen. The result of

the analysis can be seen as node voltages' and transistor

currents' values on the screen.

77

CHAPTER FIVE

NOISE AND GAIN-PHASE ANALYSES

While designing a low-noise amplifier, the

circuit designer needs to know the noise analysis results

(such as, output noise, equivalent input noise, etc.) and

also the gain and the bandwidth of the synthesized

amplifier. So one of the available analyses is the small-

signal gain and phase analysis. But to carry out this

analysis (and also the noise analysis), the small-signal

linearized circuit description (the nodal admittance matrix)

is needed. Nonlinear dc-analysis is required for a circuit

which contains nonlinear component(s) to know the quiescent

operating point. Then the small-signal model(s) of the

nonlinear device(s) are formed at the dc-operating point

and used to form the linearized circuit description.

5.1

'SMALL-SIGNAL MODELLING OF THE BIPOLAR TRANSISTOR

A hybrid-Tr model is formed for each bipolar

transistor as shown in Fig. 5.1. For each transistor a new

node (B') is created. Following is a description of how the

hybrid-Tr model element values are determined.

The transconductance gm is given by the following

relationship

gm = (q/kT)lIcl

where, q = electronic charge,

k = Boltzmann's constant,

T = temperature in °K and

IC = quiescent collector current.

78

Cb

I I

rbbi

B C

.Cb'e eigmv

i E

Fig. 5.1 The hybrid-7r model for the bipolar transistor.

The element rb l e is determined using the relationship

rb'e = hfe /gm

The hybrid parameter h is a function of collector current. fe

The information about the variation of hfe with collector

current is stored in the form of an equation in a data-

library. The data-library was formed with the manufacturer's

supplied data for the transistor 2N3904. Also, in the data-

library are information about the variations of iire with

V r ce

rbc 'VNM,

79

collector current, the gain-bandwidth product fT with

collector current and the output capacitance of the

transistor in the common-base configuration Cob with

reverse base-collector voltage. The value of rbc is obtained

from the following relationship

rbc rbe ihre

For the value of Cbl the value of Cob is used. For accurate

value of Cbē it is necessary to know the value of the

overlap-diode capacitance and the header capacitance from

high frequency y-parameter measurement [24]. To find the

value of Cbe the following relationship is used

Cbe [g

m '(27fT )] - Cb%

The base spreading resistance rbb can be measured

using different techniques. But as the main purpose of

transistor modelling here is to predict noise p