Inter-Integrated Circuit Module (I2C)

2301SPRUHM8I–December 2013–Revised September 2019Submit Documentation Feedback

Copyright © 2013–2019, Texas Instruments Incorporated

Inter-Integrated Circuit Module (I2C)

Chapter 20SPRUHM8I–December 2013–Revised September 2019


This chapter describes the features and operation of the inter-integrated circuit (I2C) module. The I2Cmodule provides an interface between one of these devices and devices compliant with the NXPSemiconductors Inter-IC bus (I2C bus) specification version 2.1, and connected by way of an I2C bus.External components attached to this 2-wire serial bus can transmit/receive 1 to 8-bit data to/from thedevice through the I2C module. This guide assumes the reader is familiar with the I2C bus specification.

NOTE: A unit of data transmitted or received by the I2C module can have fewer than 8 bits;however, for convenience, a unit of data is called a data byte throughout this document. Thenumber of bits in a data byte is selectable via the BC bits of the mode register, I2CMDR.

Topic ........................................................................................................................... Page

20.1 Introduction ................................................................................................... 230220.2 Configuring Device Pins .................................................................................. 230520.3 I2C Module Operational Details......................................................................... 230620.4 Interrupt Requests Generated by the I2C Module................................................ 231320.5 Resetting or Disabling the I2C Module............................................................... 231620.6 I2C Registers.................................................................................................. 2317

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28x

I2C

I2C

EPROM

I2C

I2C

28x

VDD

Pullupresistors

Serial data (SDA)

Serial clock (SCL)

controller

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20.1 IntroductionThe I2C module supports any slave or master I2C-compatible device. Figure 20-1 shows an example ofmultiple I2C modules connected for a two-way transfer from one device to other devices.

Figure 20-1. Multiple I2C Modules Connected

20.1.1 FeaturesThe I2C module has the following features:• Compliance with the NXP Semiconductors I2C bus specification (version 2.1):

– Support for 8-bit format transfers– 7-bit and 10-bit addressing modes– General call– START byte mode– Support for multiple master-transmitters and slave-receivers– Support for multiple slave-transmitters and master-receivers– Combined master transmit/receive and receive/transmit mode– Data transfer rate from 10 kbps up to 400 kbps (Fast-mode)

• Receive FIFO and Transmitter FIFO (16-deep x 8-bit FIFO)• Supports two ePIE interrupts:

– I2Cx Interrupt – Any of the below events can be configured to generate an I2Cx interrupt:• Transmit-data ready• Receive-data ready• Register-access ready• No-acknowledgment received• Arbitration lost• Stop condition detected• Addressed as slave

– I2Cx_FIFO interrupts:• Transmit FIFO interrupt• Receive FIFO interrupt

• Module enable/disable capability• Free data format mode

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20.1.2 Features Not SupportedThe I2C module does not support:• High-speed mode (Hs-mode)• CBUS-compatibility mode

20.1.3 Functional OverviewEach device connected to an I2C bus is recognized by a unique address. Each device can operate aseither a transmitter or a receiver, depending on the function of the device. A device connected to the I2Cbus can also be considered as the master or the slave when performing data transfers. A master device isthe device that initiates a data transfer on the bus and generates the clock signals to permit that transfer.During this transfer, any device addressed by this master is considered a slave. The I2C module supportsthe multi-master mode, in which one or more devices capable of controlling an I2C bus can be connectedto the same I2C bus.

For data communication, the I2C module has a serial data pin (SDA) and a serial clock pin (SCL), asshown in Section 20.6. These two pins carry information between the 28x device and other devicesconnected to the I2C bus. The SDA and SCL pins both are bidirectional. They each must be connected toa positive supply voltage using a pull-up resistor. When the bus is free, both pins are high. The driver ofthese two pins has an open-drain configuration to perform the required wired-AND function.

There are two major transfer techniques: .• Standard Mode: Send exactly n data values, where n is a value you program in an I2C module

register. See Section 20.6 for more information.• Repeat Mode: Keep sending data values until you use software to initiate a STOP condition or a new

START condition. See Registers for RM bit information.

The I2C module consists of the following primary blocks:• A serial interface: one data pin (SDA) and one clock pin (SCL)• Data registers and FIFOs to temporarily hold receive data and transmit data traveling between the

SDA pin and the CPU• Control and status registers• A peripheral bus interface to enable the CPU to access the I2C module registers and FIFOs.• A clock synchronizer to synchronize the I2C input clock (from the device clock generator) and the clock

on the SCL pin, and to synchronize data transfers with masters of different clock speeds• A prescaler to divide down the input clock that is driven to the I2C module• A noise filter on each of the two pins, SDA and SCL• An arbitrator to handle arbitration between the I2C module (when it is a master) and another master• Interrupt generation logic, so that an interrupt can be sent to the CPU• FIFO interrupt generation logic, so that FIFO access can be synchronized to data reception and data

transmission in the I2C module

Figure 20-2 shows the four registers used for transmission and reception in non-FIFO mode. The CPUwrites data for transmission to I2CDXR and reads received data from I2CDRR. When the I2C module isconfigured as a transmitter, data written to I2CDXR is copied to I2CXSR and shifted out on the SDA pinone bit at a time. When the I2C module is configured as a receiver, received data is shifted into I2CRSRand then copied to I2CDRR.

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I2CPSC + 1

SYSCLKI2C Module Clock

(ICCL + d) + (ICCH + d)

Master Clock on SCL pin

I2CXSR I2CDXR

I2CRSR I2CDRR

Clocksynchronizer

Prescaler

Noise filters

Arbitrator

I2C INT

Peripheral bus

Interrupt to

CPU/PIE

SDA

SCL

Control/statusregisters CPU

I2C module

TX FIFO

RX FIFO

FIFO Interrupt

to CPU/PIE

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Figure 20-2. I2C Module Conceptual Block Diagram

20.1.4 Clock GenerationThe I2C module clock determines the frequency at which the I2C module operates. A programmableprescaler in the I2C module divides down the SYSCLK to produce the I2C module clock and this I2Cmodule clock is divided further to produce the I2C master clock on the SCL pin. Figure 20-3 shows theclock generation diagram for I2C module.

Figure 20-3. Clocking Diagram for the I2C Module

To specify the divide-down value, initialize the IPSC field of the prescaler register, I2CPSC. The resultingfrequency is:

NOTE: To meet all of the I2C protocol timing specifications, the I2C module clock must be between7 - 12 MHz.

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Master Clock period (Tmst) =I2C Module Clock (Fmod)

[ (ICCH + d) + (ICCL + d) ]

SCL

High-time duration:Tmod × (ICCH + d)

High-time duration:Tmod × (ICCH + d)

Low-time duration:Tmod × (ICCL + d)

Low-time duration:Tmod × (ICCL + d)

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The prescaler must be initialized only while the I2C module is in the reset state (IRS = 0 in I2CMDR). Theprescaled frequency takes effect only when IRS is changed to 1. Changing the IPSC value while IRS = 1has no effect.

The master clock appears on the SCL pin when the I2C module is configured to be a master on the I2Cbus. This clock controls the timing of communication between the I2C module and a slave. As shown inFigure 20-3, a second clock divider in the I2C module divides down the module clock to produce themaster clock. The clock divider uses the ICCL value of I2CCLKL to divide down the low portion of themodule clock signal and uses the ICCH value of I2CCLKH to divide down the high portion of the moduleclock signal. See Section 20.1.5 for the master clock frequency equation.

20.1.5 I2C Clock Divider Registers (I2CCLKL and I2CCLKH)As explained in Section 20.1.4, when the I2C module is a master, the I2C module clock is divided downfurther to use as the master clock on the SCL pin. As shown in Figure 20-4, the shape of the master clockdepends on two divide-down values:• ICCL in I2CCLKL. For each master clock cycle, ICCL determines the amount of time the signal is low.• ICCH in I2CCKLH. For each master clock cycle, ICCH determines the amount of time the signal is

high.

Figure 20-4. The Roles of the Clock Divide-Down Values (ICCL and ICCH)

20.1.5.1 Formula for the Master Clock PeriodThe master clock period (Tmst) is a multiple of the period of the I2C Module Clock (Tmod):

where d depends on the divide-down value IPSC, as shown in Table 20-1. IPSC is described in theI2CPSC register.

Table 20-1. Dependency of Delay d on the Divide-DownValue IPSC

IPSC d0 71 6

Greater than 1 5

20.2 Configuring Device PinsThe GPIO mux registers must be configured to connect this peripheral to the device pins. To avoidglitches on the pins, the GPyGMUX bits must be configured first (while keeping the correspondingGPyMUX bits at the default of zero), followed by writing the GPyMUX register to the desired value.

Some IO functionality is defined by GPIO register settings independent of this peripheral. For inputsignals, the GPIO input qualification should be set to asynchronous mode by setting the appropriateGPxQSELn register bits to 11b. The internal pullups can be configured in the GPyPUD register.

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Data linestable data

Change of dataallowed

SDA

SCL

I2C Module Operational Details www.ti.com




See the GPIO chapter for more details on GPIO mux and settings.

20.3 I2C Module Operational DetailsThis section provides an overview of the I2C bus protocol and how it is implemented.

20.3.1 Input and Output Voltage LevelsOne clock pulse is generated by the master device for each data bit transferred. Due to a variety ofdifferent technology devices that can be connected to the I2C bus, the levels of logic 0 (low) and logic 1(high) are not fixed and depend on the associated level of VDD. For details, see the data manual for yourparticular device.

20.3.2 Data ValidityThe data on SDA must be stable during the high period of the clock (see Figure 20-5). The high or lowstate of the data line, SDA, should change only when the clock signal on SCL is low.

Figure 20-5. Bit Transfer on the I2C bus

20.3.3 Operating ModesThe I2C module has four basic operating modes to support data transfers as a master and as a slave.See Table 20-2 for the names and descriptions of the modes.

If the I2C module is a master, it begins as a master-transmitter and typically transmits an address for aparticular slave. When giving data to the slave, the I2C module must remain a master-transmitter. Toreceive data from a slave, the I2C module must be changed to the master-receiver mode.

If the I2C module is a slave, it begins as a slave-receiver and typically sends acknowledgment when itrecognizes its slave address from a master. If the master will be sending data to the I2C module, themodule must remain a slave-receiver. If the master has requested data from the I2C module, the modulemust be changed to the slave-transmitter mode.

Table 20-2. Operating Modes of the I2C Module

Operating Mode DescriptionSlave-receiver modes The I2C module is a slave and receives data from a master.

All slaves begin in this mode. In this mode, serial data bits received on SDA are shifted in withthe clock pulses that are generated by the master. As a slave, the I2C module does notgenerate the clock signal, but it can hold SCL low while the intervention of the device isrequired (RSFULL = 1 in I2CSTR) after a byte has been received. See section Section 20.3.7for more details.

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www.ti.com I2C Module Operational Details




Table 20-2. Operating Modes of the I2C Module (continued)Operating Mode DescriptionSlave-transmitter mode The I2C module is a slave and transmits data to a master.

This mode can be entered only from the slave-receiver mode; the I2C module must first receivea command from the master. When you are using any of the 7-bit/10-bit addressing formats,the I2C module enters its slave-transmitter mode if the slave address byte is the same as itsown address (in I2COAR) and the master has transmitted R/W = 1. As a slave-transmitter, theI2C module then shifts the serial data out on SDA with the clock pulses that are generated bythe master. While a slave, the I2C module does not generate the clock signal, but it can holdSCL low while the intervention of the device is required (XSMT = 0 in I2CSTR) after a byte hasbeen transmitted. See section Section 20.3.7 for more details.

Master-receiver mode The I2C module is a master and receives data from a slave.This mode can be entered only from the master-transmitter mode; the I2C module must firsttransmit a command to the slave. When you are using any of the 7-bit/10-bit addressingformats, the I2C module enters its master-receiver mode after transmitting the slave addressbyte and R/W = 1. Serial data bits on SDA are shifted into the I2C module with the clock pulsesgenerated by the I2C module on SCL. The clock pulses are inhibited and SCL is held low whenthe intervention of the device is required (RSFULL = 1 in I2CSTR) after a byte has beenreceived.

Master-transmitter modes The I2C module is a master and transmits control information and data to a slave.All masters begin in this mode. In this mode, data assembled in any of the 7-bit/10-bitaddressing formats is shifted out on SDA. The bit shifting is synchronized with the clock pulsesgenerated by the I2C module on SCL. The clock pulses are inhibited and SCL is held low whenthe intervention of the device is required (XSMT = 0 in I2CSTR) after a byte has beentransmitted.

To summarize, SCL will be held low in the following conditions:• When an overrun condition is detected (RSFULL = 1), in Slave-receiver mode.• When an underflow condition is detected (XSMT = 0), in Slave-transmitter mode.

I2C slave nodes have to accept and provide data when the I2C master node requests it.• To release SCL in slave-receiver mode, read data from I2CDRR.• To release SCL in slave-transmitter mode, write data to I2CDXR.• To force a release without handling the data, reset the module using the I2CMDR.IRS bit.

(1) S = START condition; A = Address; D = Data byte; P = STOP condition;

Table 20-3. Master-Transmitter/Receiver Bus Activity Defined by the RM, STT, and STP Bits ofI2CMDR

RM STT STP Bus Activity (1) Description0 0 0 None No activity0 0 1 P STOP condition0 1 0 S-A-D..(n)..D. START condition, slave address, n data bytes (n = value in

I2CCNT)0 1 1 S-A-D..(n)..D-P START condition, slave address, n data bytes, STOP condition (n =

value in I2CCNT)1 0 0 None No activity1 0 1 P STOP condition1 1 0 S-A-D-D-D. Repeat mode transfer: START condition, slave address, continuous

data transfers until STOP condition or next START condition1 1 1 None Reserved bit combination (No activity)

20.3.4 I2C Module START and STOP ConditionsSTART and STOP conditions can be generated by the I2C module when the module is configured to be amaster on the I2C bus. As shown in Figure 20-6:• The START condition is defined as a high-to-low transition on the SDA line while SCL is high. A

master drives this condition to indicate the start of a data transfer.

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SDA

SCL

STARTcondition (S) condition (P)

STOP





• The STOP condition is defined as a low-to-high transition on the SDA line while SCL is high. A masterdrives this condition to indicate the end of a data transfer.

Figure 20-6. I2C Module START and STOP Conditions

After a START condition and before a subsequent STOP condition, the I2C bus is considered busy, andthe bus busy (BB) bit of I2CSTR is 1. Between a STOP condition and the next START condition, the busis considered free, and BB is 0.

For the I2C module to start a data transfer with a START condition, the master mode bit (MST) and theSTART condition bit (STT) in I2CMDR must both be 1. For the I2C module to end a data transfer with aSTOP condition, the STOP condition bit (STP) must be set to 1. When the BB bit is set to 1 and the STTbit is set to 1, a repeated START condition is generated. For a description of I2CMDR and its bits(including MST, STT, and STP), see Registers Section 20.6.

The I2C peripheral cannot detect a START or STOP condition while it is in reset (IRS = 0). The BB bit willremain in the cleared state (BB = 0) while the I2C peripheral is in reset (IRS = 0). When the I2C peripheralis taken out of reset (IRS set to 1) the BB bit will not correctly reflect the I2C bus status until a START orSTOP condition is detected.

Follow these steps before initiating the first data transfer with I2C:1. After taking the I2C peripheral out of reset by setting the IRS bit to 1, wait a period larger than the total

time taken for the longest data transfer in the application. By waiting for a period of time after I2Ccomes out of reset, users can ensure that at least one START or STOP condition will have occurredon the I2C bus and been captured by the BB bit. After this period, the BB bit will correctly reflect thestate of the I2C bus.

2. Check the BB bit and verify that BB = 0 (bus not busy) before proceeding.3. Begin data transfers.

Not resetting the I2C peripheral in between transfers ensures that the BB bit reflects the actual bus status.If users must reset the I2C peripheral in between transfers, repeat steps 1 through 3 every time the I2Cperipheral is taken out of reset.

20.3.5 Serial Data FormatsFigure 20-7 shows an example of a data transfer on the I2C bus. The I2C module supports 1 to 8-bit datavalues. In Figure 20-7, 8-bit data is transferred. Each bit put on the SDA line equates to 1 pulse on theSCL line, and the values are always transferred with the most significant bit (MSB) first. The number ofdata values that can be transmitted or received is unrestricted. The serial data format used in Figure 20-7is the 7-bit addressing format. The I2C module supports the formats shown in Figure 20-8 throughFigure 20-10 and described in the paragraphs that follow the figures.

NOTE: In Figure 20-7 through Figure 20-10, n = the number of data bits (from 1 to 8) specified bythe bit count (BC) field of I2CMDR.

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S

1

1 1 1 1 0 x x

7

x x x x x x x xACK

11 8

ACK

1

Data

n

ACK

1

P

1

x x = 2 MSBs

R/W

8 LSBs of slave address

S

7 bits of slave address

R/W ACK Data ACK Data ACK P

7 n n1 1 1 1 1 1

x x x x x x x

SDA

SCL

MSB

Acknowledgementbit from slave

(No-)Acknowledgementbit from receiver

1 2 7 8 9 1 2 8 9Slave address ACK

STARTcondition (S)

STOPcondition (P)R/W ACK Data

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Figure 20-7. I2C Module Data Transfer (7-Bit Addressing with 8-bit Data Configuration Shown)

20.3.5.1 7-Bit Addressing FormatThe 7-bit addressing format is the default format after reset. Disabling expanded address (I2CMDR.XA =0) and free data format (I2CMDR.FDF = 0) enables 7-bit addressing format.

In this format (see Figure 20-8), the first byte after a START condition (S) consists of a 7-bit slave addressfollowed by a R/W bit. R/W determines the direction of the data:• R/W = 0: The I2C master writes (transmits) data to the addressed slave. This can be achieved by

setting I2CMDR.TRX = 1 (Transmitter mode)• R/W = 1: The I2C master reads (receives) data from the slave. This can be achieved by setting

I2CMDR.TRX = 0 (Receiver mode)

Figure 20-8. I2C Module 7-Bit Addressing Format (FDF = 0, XA = 0 in I2CMDR)

An extra clock cycle dedicated for acknowledgment (ACK) is inserted after each byte. If the ACK bit isinserted by the slave after the first byte from the master, it is followed by n bits of data from the transmitter(master or slave, depending on the R/W bit). n is a number from 1 to 8 determined by the bit count (BC)field of I2CMDR. After the data bits have been transferred, the receiver inserts an ACK bit.

20.3.5.2 10-Bit Addressing FormatThe 10-bit addressing format can be enabled by setting expanded address (I2CMDR.XA = 1) anddisabling free data format (I2CMDR.FDF = 0).

The 10-bit addressing format (see Figure 20-9) is similar to the 7-bit addressing format, but the mastersends the slave address in two separate byte transfers. The first byte consists of 11110b, the two MSBs ofthe 10-bit slave address, and R/W. The second byte is the remaining 8 bits of the 10-bit slave address.The slave must send acknowledgment after each of the two byte transfers. Once the master has writtenthe second byte to the slave, the master can either write data or use a repeated START condition tochange the data direction. For more details about using 10-bit addressing, see the NXP SemiconductorsI2C bus specification.

Figure 20-9. I2C Module 10-Bit Addressing Format (FDF = 0, XA = 1 in I2CMDR)

20.3.5.3 Free Data FormatThe free data format can be enabled by setting I2CMDR. FDF = 1.

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1 7 n 7 n1 1 1 1 1 1 1 1

S Slave address R/W ACK Data ACK S Slave address R/W ACK Data ACK P

1Any

number

1Any number

DataDataS

1

DataACK ACK ACK P

1n n n 111





In this format (see Figure 20-10), the first byte after a START condition (S) is a data byte. An ACK bit isinserted after each data byte, which can be from 1 to 8 bits, depending on the BC field of I2CMDR. Noaddress or data-direction bit is sent. Therefore, the transmitter and the receiver must both support the freedata format, and the direction of the data must be constant throughout the transfer.

Figure 20-10. I2C Module Free Data Format (FDF = 1 in I2CMDR)

NOTE: The free data format is not supported in the digital loopback mode (I2CMDR.DLB = 1).

Table 20-4. How the MST and FDF Bits of I2CMDR Affect the Role of the TRX Bit of I2CMDR

MST FDF I2C Module State Function of TRX0 0 In slave mode but not free data

format modeTRX is a don’t care. Depending on the command from the master, the I2Cmodule responds as a receiver or a transmitter.

0 1 In slave mode and free dataformat mode

The free data format mode requires that the I2C module remains thetransmitter or the receiver throughout the transfer. TRX identifies the roleof the I2C module:TRX = 1: The I2C module is a transmitter.TRX = 0: The I2C module is a receiver.

1 0 In master mode but not free dataformat mode

TRX = 1: The I2C module is a transmitter.TRX = 0: The I2C module is a receiver.

1 1 In master mode and free dataformat mode

TRX = 0: The I2C module is a receiver.TRX = 1: The I2C module is a transmitter.

20.3.5.4 Using a Repeated START ConditionI2C master can communicate with multiple slave addresses without having to give up control of the I2Cbus by driving a STOP condition. This can be achieved by driving another START condition at the end ofeach data type. The repeated START condition can be used with the 7-bit addressing, 10-bit addressing,and free data formats. Figure 20-11 shows a repeated START condition in the 7-bit addressing format.

Figure 20-11. Repeated START Condition (in This Case, 7-Bit Addressing Format)

NOTE: In Figure 20-11, n = the number of data bits (from 1 to 8) specified by the bit count (BC) fieldof I2CMDR.

20.3.6 NACK Bit GenerationWhen the I2C module is a receiver (master or slave), it can acknowledge or ignore bits sent by thetransmitter. To ignore any new bits, the I2C module must send a no-acknowledge (NACK) bit during theacknowledge cycle on the bus. Table 20-5 summarizes the various ways you can tell the I2C module tosend a NACK bit.

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I2CDRR I2CRSR0

1

I2CSAR

I2COAR

0

1

I2CDXR

I2CXSR

0

1 0

0

DLB

SCL_IN

SCL_OUT

Address/data

To internal I2C logic

From internal I2C logic

To internal I2C logic

To CPU

From CPU

From CPU

From CPU

SCL

SDA

I2C module

DLB

DLB

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Figure 20-14. Pin Diagram Showing the Effects of the Digital Loopback Mode (DLB) Bit

NOTE: The free data format (I2CMDR.FDF = 1) is not supported in digital loopback mode.

20.4 Interrupt Requests Generated by the I2C ModuleEach I2C module can generate two CPU interrupts.

1. Basic I2C interrupt: Possible basic I2C interrupt sources which can trigger this interrupt are describedin Section 20.4.1.

2. I2C FIFO interrupt: Possible I2C FIFO interrupt sources which can trigger this interrupt are described inSection 20.4.2

20.4.1 Basic I2C Interrupt RequestsThe I2C module generates the interrupt requests described in Table 20-6. As shown in Figure 20-15, allrequests are multiplexed through an arbiter to a single I2C interrupt request to the CPU. Each interruptrequest has a flag bit in the status register (I2CSTR) and an enable bit in the interrupt enable register(I2CIER). When one of the specified events occurs, its flag bit is set. If the corresponding enable bit is 0,the interrupt request is blocked. If the enable bit is 1, the request is forwarded to the CPU as an I2Cinterrupt.

The I2C interrupt is one of the maskable interrupts of the CPU. As with any maskable interrupt request, ifit is properly enabled in the CPU, the CPU executes the corresponding interrupt service routine(I2CINT1A_ISR). The I2CINT1A_ISR for the I2C interrupt can determine the interrupt source by readingthe interrupt source register, I2CISRC. Then the I2CINT1A_ISR can branch to the appropriate subroutine.

After the CPU reads I2CISRC, the following events occur:1. The flag for the source interrupt is cleared in I2CSTR. Exception: The ARDY, RRDY, and XRDY bits in

I2CSTR are not cleared when I2CISRC is read. To clear one of these bits, write a 1 to it.2. The arbiter determines which of the remaining interrupt requests has the highest priority, writes the

code for that interrupt to I2CISRC, and forwards the interrupt request to the CPU.

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Interrupt Requests Generated by the I2C Module www.ti.com




Table 20-6. Descriptions of the Basic I2C Interrupt Requests

I2C Interrupt Request Interrupt SourceXRDYINT Transmit ready condition: The data transmit register (I2CDXR) is ready to accept new data because the

previous data has been copied from I2CDXR to the transmit shift register (I2CXSR).As an alternative to using XRDYINT, the CPU can poll the XRDY bit of the status register, I2CSTR.XRDYINT should not be used when in FIFO mode. Use the FIFO interrupts instead.

RRDYINT Receive ready condition: The data receive register (I2CDRR) is ready to be read because data has beencopied from the receive shift register (I2CRSR) to I2CDRR.As an alternative to using RRDYINT, the CPU can poll the RRDY bit of I2CSTR. RRDYINT should notbe used when in FIFO mode. Use the FIFO interrupts instead.

ARDYINT Register-access ready condition: The I2C module registers are ready to be accessed because thepreviously programmed address, data, and command values have been used.The specific events that generate ARDYINT are the same events that set the ARDY bit of I2CSTR.As an alternative to using ARDYINT, the CPU can poll the ARDY bit.

NACKINT No-acknowledgment condition: The I2C module is configured as a master-transmitter and did notreceived acknowledgment from the slave-receiver.As an alternative to using NACKINT, the CPU can poll the NACK bit of I2CSTR.

ARBLINT Arbitration-lost condition: The I2C module has lost an arbitration contest with another master-transmitter.As an alternative to using ARBLINT, the CPU can poll the ARBL bit of I2CSTR.

SCDINT Stop condition detected: A STOP condition was detected on the I2C bus.As an alternative to using SCDINT, the CPU can poll the SCD bit of the status register, I2CSTR.

AASINT Addressed as slave condition: The I2C has been addressed as a slave device by another master on theI2C bus.As an alternative to using AASINT, the CPU can poll the AAS bit of the status register, I2CSTR.

Figure 20-15. Enable Paths of the I2C Interrupt Requests

The I2C module has a backwards compatibility bit (BC) in the I2CEMDR register. The timing diagram inFigure 20-16 demonstrates the effect the backwards compatibility bit has on I2C module registers andinterrupts when configured as a slave-transmitter.

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Empty Data 2 Data 3 Data 4




SSlave

AddressR A Data 1 A Data 2 A Data 2 nA P

SSlave

AddressR A Data 1 A Data 2 A Data 3 nA P

Left in I2CDXR

Interrupt

XRDY

XSMT

I2CDXR

I2CXSR

b) BC = 0

Interrupt

XRDY

XSMT

I2CDXR

I2CXSR

b) BC = 1

Slave-Transmitter

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Figure 20-16. Backwards Compatibility Mode Bit, Slave Transmitter

20.4.2 I2C FIFO InterruptsIn addition to the seven basic I2C interrupts, the transmit and receive FIFOs each contain the ability togenerate an interrupt (I2CINT2A). The transmit FIFO can be configured to generate an interrupt aftertransmitting a defined number of bytes, up to 16. The receive FIFO can be configured to generate aninterrupt after receiving a defined number of bytes, up to 16. These two interrupt sources are ORedtogether into a single maskable CPU interrupt. Figure 20-17 shows the structure of I2C FIFO interrupt.The interrupt service routine can then read the FIFO interrupt status flags to determine from which sourcethe interrupt came. See the I2C transmit FIFO register (I2CFFTX) and the I2C receive FIFO register(I2CFFRX) descriptions.

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Resetting or Disabling the I2C Module www.ti.com




Figure 20-17. I2C_FIFO_interrupt

20.5 Resetting or Disabling the I2C ModuleYou can reset or disable the I2C module in two ways:• Write 0 to the I2C reset bit (IRS) in the I2C mode register (I2CMDR). All status bits (in I2CSTR) are

forced to their default values, and the I2C module remains disabled until IRS is changed to 1. The SDAand SCL pins are in the high-impedance state.

• Initiate a device reset by driving the XRS pin low. The entire device is reset and is held in the resetstate until you drive the pin high. When the XRS pin is released, all I2C module registers are reset totheir default values. The IRS bit is forced to 0, which resets the I2C module. The I2C module stays inthe reset state until you write 1 to IRS.

The IRS must be 0 while you configure or reconfigure the I2C module. Forcing IRS to 0 can be used tosave power and to clear error conditions.

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I2C Registers www.ti.com




20.6.2 I2C_REGS RegistersTable 20-8 lists the I2C_REGS registers. All register offset addresses not listed in Table 20-8 should beconsidered as reserved locations and the register contents should not be modified.

Table 20-8. I2C_REGS Registers

Offset Acronym Register Name Write Protection Section0h I2COAR I2C Own address Go1h I2CIER I2C Interrupt Enable Go2h I2CSTR I2C Status Go3h I2CCLKL I2C Clock low-time divider Go4h I2CCLKH I2C Clock high-time divider Go5h I2CCNT I2C Data count Go6h I2CDRR I2C Data receive Go7h I2CSAR I2C Slave address Go8h I2CDXR I2C Data Transmit Go9h I2CMDR I2C Mode GoAh I2CISRC I2C Interrupt Source GoBh I2CEMDR I2C Extended Mode GoCh I2CPSC I2C Prescaler Go20h I2CFFTX I2C FIFO Transmit Go21h I2CFFRX I2C FIFO Receive Go

Complex bit access types are encoded to fit into small table cells. Table 20-9 shows the codes that areused for access types in this section.

Table 20-9. I2C_REGS Access Type Codes

Access Type Code DescriptionRead TypeR R ReadR-0 R

-0ReadReturns 0s

Write TypeW W WriteW1C W

1CWrite1 to clear

W1S W1S

Write1 to set

Reset or Default Value-n Value after reset or the default

valueRegister Array Variablesi,j,k,l,m,n When these variables are used in

a register name, an offset, or anaddress, they refer to the value ofa register array where the registeris part of a group of repeatingregisters. The register groups forma hierarchical structure and thearray is represented with aformula.

y When this variable is used in aregister name, an offset, or anaddress it refers to the value of aregister array.

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www.ti.com I2C Registers




20.6.2.1 I2COAR Register (Offset = 0h) [reset = 0h]I2COAR is shown in Figure 20-18 and described in Table 20-10.

Return to the Summary Table.

The I2C own address register (I2COAR) is a 16-bit register. The I2C module uses this register to specifyits own slave address, which distinguishes it from other slaves connected to the I2C-bus. If the 7-bitaddressing mode is selected (XA = 0 in I2CMDR), only bits 6-0 are usedwrite 0s to bits 9-7.

Figure 20-18. I2COAR Register15 14 13 12 11 10 9 8

RESERVED OARR-0h R/W-0h

7 6 5 4 3 2 1 0OAR

R/W-0h

Table 20-10. I2COAR Register Field Descriptions

Bit Field Type Reset Description15-10 RESERVED R 0h Reserved

9-0 OAR R/W 0h In 7-bit addressing mode (XA = 0 in I2CMDR):00h-7Fh Bits 6-0 provide the 7-bit slave address of the I2C module.Write 0s to bits 9-7.

In 10-bit addressing mode (XA = 1 in I2CMDR):000h-3FFh Bits 9-0 provide the 10-bit slave address of the I2Cmodule.

Reset type: SYSRSn

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20.6.2.2 I2CIER Register (Offset = 1h) [reset = 0h]I2CIER is shown in Figure 20-19 and described in Table 20-11.


I2CIER is used by the CPU to individually enable or disable I2C interrupt requests.

Figure 20-19. I2CIER Register15 14 13 12 11 10 9 8

RESERVEDR-0h

7 6 5 4 3 2 1 0RESERVED AAS SCD XRDY RRDY ARDY NACK ARBL

R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 20-11. I2CIER Register Field Descriptions


6 AAS R/W 0h Addressed as slave interrupt enableReset type: SYSRSn0h (R/W) = Interrupt request disabled1h (R/W) = Interrupt request enabled

5 SCD R/W 0h Stop condition detected interrupt enableReset type: SYSRSn0h (R/W) = Interrupt request disabled1h (R/W) = Interrupt request enabled

4 XRDY R/W 0h Transmit-data-ready interrupt enable bit.This bit should not be set when using FIFO mode.

Reset type: SYSRSn0h (R/W) = Interrupt request disabled1h (R/W) = Interrupt request enabled

3 RRDY R/W 0h Receive-data-ready interrupt enable bit.This bit should not be set when using FIFO mode.

Reset type: SYSRSn0h (R/W) = Interrupt request disabled1h (R/W) = Interrupt request enabled

2 ARDY R/W 0h Register-access-ready interrupt enableReset type: SYSRSn0h (R/W) = Interrupt request disabled1h (R/W) = Interrupt request enabled

1 NACK R/W 0h No-acknowledgment interrupt enableReset type: SYSRSn0h (R/W) = Interrupt request disabled1h (R/W) = Interrupt request enabled

0 ARBL R/W 0h Arbitration-lost interrupt enableReset type: SYSRSn0h (R/W) = Interrupt request disabled1h (R/W) = Interrupt request enabled

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20.6.2.3 I2CSTR Register (Offset = 2h) [reset = 410h]I2CSTR is shown in Figure 20-20 and described in Table 20-12.


The I2C status register (I2CSTR) is a 16-bit register used to determine which interrupt has occurred and toread status information.

Figure 20-20. I2CSTR Register15 14 13 12 11 10 9 8

RESERVED SDIR NACKSNT BB RSFULL XSMT AAS AD0R-0h R/W1C-0h R/W1C-0h R-0h R-0h R-1h R-0h R-0h

7 6 5 4 3 2 1 0RESERVED SCD XRDY RRDY ARDY NACK ARBL

R/W-0h R/W1C-0h R-1h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h

Table 20-12. I2CSTR Register Field Descriptions

Bit Field Type Reset Description15 RESERVED R 0h Reserved14 SDIR R/W1C 0h Slave direction bit

Reset type: SYSRSn0h (R/W) = I2C is not addressed as a slave transmitter. SDIR iscleared by one of the following events:- It is manually cleared. To clear this bit, write a 1 to it.- Digital loopback mode is enabled.- A START or STOP condition occurs on the I2C bus.1h (R/W) = I2C is addressed as a slave transmitter.

13 NACKSNT R/W1C 0h NACK sent bit.This bit is used when the I2C module is in the receiver mode. Oneinstance in which NACKSNT is affected is when the NACK mode isused (see the description for NACKMOD in

Reset type: SYSRSn0h (R/W) = NACK not sent. NACKSNT bit is cleared by any one ofthe following events:- It is manually cleared. To clear this bit, write a 1 to it.- The I2C module is reset (either when 0 is written to the IRS bit ofI2CMDR or when the whole device is reset).1h (R/W) = NACK sent: A no-acknowledge bit was sent during theacknowledge cycle on the I2C-bus.

12 BB R 0h Bus busy bit.BB indicates whether the I2C-bus is busy or is free for another datatransfer. See the paragraph following the table for more information

Reset type: SYSRSn0h (R/W) = Bus free. BB is cleared by any one of the followingevents:- The I2C module receives or transmits a STOP bit (bus free).- The I2C module is reset.1h (R/W) = Bus busy: The I2C module has received or transmitteda START bit on the bus.

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Table 20-12. I2CSTR Register Field Descriptions (continued)Bit Field Type Reset Description11 RSFULL R 0h Receive shift register full bit.

RSFULL indicates an overrun condition during reception. Overrunoccurs when new data is received into the shift register (I2CRSR)and the old data has not been read from the receive register(I2CDRR). As new bits arrive from the SDA pin, they overwrite thebits in I2CRSR. The new data will not be copied to ICDRR until theprevious data is read.

Reset type: SYSRSn0h (R/W) = No overrun detected. RSFULL is cleared by any one ofthe following events:- I2CDRR is read is read by the CPU. Emulator reads of theI2CDRR do not affect this bit.- The I2C module is reset.1h (R/W) = Overrun detected

10 XSMT R 1h Transmit shift register empty bit.XSMT = 0 indicates that the transmitter has experienced underflow.Underflow occurs when the transmit shift register (I2CXSR) is emptybut the data transmit register (I2CDXR) has not been loaded sincethe last I2CDXR-to-I2CXSR transfer. The next I2CDXR-to-I2CXSRtransfer will not occur until new data is in I2CDXR. If new data is nottransferred in time, the previous data may be re-transmitted on theSDA pin.

Reset type: SYSRSn0h (R/W) = Underflow detected (empty)1h (R/W) = No underflow detected (not empty). XSMT is set by oneof the following events:- Data is written to I2CDXR.- The I2C module is reset

9 AAS R 0h Addressed-as-slave bitReset type: SYSRSn0h (R/W) = In the 7-bit addressing mode, the AAS bit is clearedwhen receiving a NACK, a STOP condition, or a repeated STARTcondition. In the 10-bit addressing mode, the AAS bit is clearedwhen receiving a NACK, a STOP condition, or by a slave addressdifferent from the I2C peripheral's own slave address.1h (R/W) = The I2C module has recognized its own slave addressor an address of all zeros (general call).

8 AD0 R 0h Address 0 bitsReset type: SYSRSn0h (R/W) = AD0 has been cleared by a START or STOP condition.1h (R/W) = An address of all zeros (general call) is detected.

7-6 RESERVED R/W 0h Reserved5 SCD R/W1C 0h Stop condition detected bit.

SCD is set when the I2C sends or receives a STOP condition. TheI2C module delays clearing of the I2CMDR[STP] bit until the SCD bitis set.

Reset type: SYSRSn0h (R/W) = STOP condition not detected since SCD was lastcleared. SCD is cleared by any one of the following events:- I2CISRC is read by the CPU when it contains the value 110b(stop condition detected). Emulator reads of the I2CISRC do notaffect this bit.- SCD is manually cleared. To clear this bit, write a 1 to it.- The I2C module is reset.1h (R/W) = A STOP condition has been detected on the I2C bus.

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Table 20-12. I2CSTR Register Field Descriptions (continued)Bit Field Type Reset Description4 XRDY R 1h Transmit-data-ready interrupt flag bit.

When not in FIFO mode, XRDY indicates that the data transmitregister (I2CDXR) is ready to accept new data because the previousdata has been copied from I2CDXR to the transmit shift register(I2CXSR). The CPU can poll XRDY or use the XRDY interruptrequest When in FIFO mode, use TXFFINT instead.

Reset type: SYSRSn0h (R/W) = I2CDXR not ready. XRDY is cleared when data iswritten to I2CDXR.1h (R/W) = I2CDXR ready: Data has been copied from I2CDXR toI2CXSR.XRDY is also forced to 1 when the I2C module is reset.

3 RRDY R/W1C 0h Receive-data-ready interrupt flag bit.When not in FIFO mode, RRDY indicates that the data receiveregister (I2CDRR) is ready to be read because data has been copiedfrom the receive shift register (I2CRSR) to I2CDRR. The CPU canpoll RRDY or use the RRDY interrupt request When in FIFO mode,use RXFFINT instead.

Reset type: SYSRSn0h (R/W) = I2CDRR not ready. RRDY is cleared by any one of thefollowing events:- I2CDRR is read by the CPU. Emulator reads of the I2CDRR donot affect this bit.- RRDY is manually cleared. To clear this bit, write a 1 to it.- The I2C module is reset.1h (R/W) = I2CDRR ready: Data has been copied from I2CRSR toI2CDRR.

2 ARDY R/W1C 0h Register-access-ready interrupt flag bit (only applicable when the I2Cmodule is in the mastermode).ARDY indicates that the I2C module registers are ready to beaccessed because the previously programmed address, data, andcommand values have been used. The CPU can poll ARDY or usethe ARDY interrupt request.

Reset type: SYSRSn0h (R/W) = The registers are not ready to be accessed. ARDY iscleared by any one of the following events:- The I2C module starts using the current register contents.- ARDY is manually cleared. To clear this bit, write a 1 to it.- The I2C module is reset.1h (R/W) = The registers are ready to be accessed.In the nonrepeat mode (RM = 0 in I2CMDR): If STP = 0 inI2CMDR, the ARDY bit is set when the internal data counter countsdown to 0. If STP = 1, ARDY is not affected (instead, the I2Cmodule generates a STOP condition when the counter reaches 0).In the repeat mode (RM = 1): ARDY is set at the end of each bytetransmitted from I2CDXR.

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Table 20-12. I2CSTR Register Field Descriptions (continued)Bit Field Type Reset Description1 NACK R/W1C 0h No-acknowledgment interrupt flag bit.

NACK applies when the I2C module is a transmitter (master orslave). NACK indicates whether the I2C module has detected anacknowledge bit (ACK) or a noacknowledge bit (NACK) from thereceiver. The CPU can poll NACK or use the NACK interruptrequest.

Reset type: SYSRSn0h (R/W) = ACK received/NACK not received. This bit is cleared byany one of the following events:- An acknowledge bit (ACK) has been sent by the receiver.- NACK is manually cleared. To clear this bit, write a 1 to it.- The CPU reads the interrupt source register (I2CISRC) and theregister contains the code for a NACK interrupt. Emulator reads ofthe I2CISRC do not affect this bit.- The I2C module is reset.1h (R/W) = NACK bit received. The hardware detects that a no-acknowledge (NACK) bit has been received.Note: While the I2C module performs a general call transfer, NACKis 1, even if one or more slaves send acknowledgment.

0 ARBL R/W1C 0h Arbitration-lost interrupt flag bit (only applicable when the I2Cmodule is a master-transmitter).ARBL primarily indicates when the I2C module has lost an arbitrationcontest with another mastertransmitter. The CPU can poll ARBL oruse the ARBL interrupt request.

Reset type: SYSRSn0h (R/W) = Arbitration not lost. AL is cleared by any one of thefollowing events:- AL is manually cleared. To clear this bit, write a 1 to it.- The CPU reads the interrupt source register (I2CISRC) and theregister contains the code for anAL interrupt. Emulator reads of the I2CISRC do not affect this bit.- The I2C module is reset.1h (R/W) = Arbitration lost. AL is set by any one of the followingevents:- The I2C module senses that it has lost an arbitration with two ormore competing transmitters that started a transmission almostsimultaneously.- The I2C module attempts to start a transfer while the BB (busbusy) bit is set to 1.When AL becomes 1, the MST and STP bits of I2CMDR arecleared, and the I2C module becomes a slave-receiver.

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20.6.2.4 I2CCLKL Register (Offset = 3h) [reset = 0h]I2CCLKL is shown in Figure 20-21 and described in Table 20-13.


I2C Clock low-time divider

Figure 20-21. I2CCLKL Register15 14 13 12 11 10 9 8

I2CCLKLR/W-0h

7 6 5 4 3 2 1 0I2CCLKLR/W-0h

Table 20-13. I2CCLKL Register Field Descriptions

Bit Field Type Reset Description15-0 I2CCLKL R/W 0h Clock low-time divide-down value.

To produce the low time duration of the master clock, the period ofthe module clock is multiplied by (ICCL + d). d is an adjustmentfactor based on the prescaler. See the Clock Divider Registerssection of the Introduction for details.

Note: These bits must be set to a non-zero value for proper I2Cclock generation.

Reset type: SYSRSn

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20.6.2.5 I2CCLKH Register (Offset = 4h) [reset = 0h]I2CCLKH is shown in Figure 20-22 and described in Table 20-14.


I2C Clock high-time divider

Figure 20-22. I2CCLKH Register15 14 13 12 11 10 9 8

I2CCLKHR/W-0h

7 6 5 4 3 2 1 0I2CCLKHR/W-0h

Table 20-14. I2CCLKH Register Field Descriptions

Bit Field Type Reset Description15-0 I2CCLKH R/W 0h Clock high-time divide-down value.

To produce the high time duration of the master clock, the period ofthe module clock is multiplied by (ICCL + d). d is an adjustmentfactor based on the prescaler. See the Clock Divider Registerssection of the Introduction for details.

Note: These bits must be set to a non-zero value for proper I2Cclock generation.

Reset type: SYSRSn

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20.6.2.6 I2CCNT Register (Offset = 5h) [reset = 0h]I2CCNT is shown in Figure 20-23 and described in Table 20-15.


I2CCNT is a 16-bit register used to indicate how many data bytes to transfer when the I2C module isconfigured as a transmitter, or to receive when configured as a master receiver. In the repeat mode (RM =1), I2CCNT is not used.The value written to I2CCNT is copied to an internal data counter. The internal data counter isdecremented by 1 for each byte transferred (I2CCNT remains unchanged). If a STOP condition isrequested in the master mode (STP = 1 in I2CMDR), the I2C module terminates the transfer with a STOPcondition when the countdown is complete (that is, when the last byte has been transferred).

Figure 20-23. I2CCNT Register15 14 13 12 11 10 9 8

I2CCNTR/W-0h

7 6 5 4 3 2 1 0I2CCNTR/W-0h

Table 20-15. I2CCNT Register Field Descriptions

Bit Field Type Reset Description15-0 I2CCNT R/W 0h Data count value. I2CCNT indicates the number of data bytes to

transfer or receive. The value in I2CCNT is a don't care when theRM bit in I2CMDR is set to 1.The start value loaded to the internal data counter is 65536.The start value loaded to internal data counter is 1-65535.

Reset type: SYSRSn

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20.6.2.7 I2CDRR Register (Offset = 6h) [reset = 0h]I2CDRR is shown in Figure 20-24 and described in Table 20-16.


I2CDRR is a 16-bit register used by the CPU to read received data. The I2C module can receive a databyte with 1 to 8 bits. The number of bits is selected with the bit count (BC) bits in I2CMDR. One bit at atime is shifted in from the SDA pin to the receive shift register (I2CRSR). When a complete data byte hasbeen received, the I2C module copies the data byte from I2CRSR to I2CDRR. The CPU cannot accessI2CRSR directly.If a data byte with fewer than 8 bits is in I2CDRR, the data value is right-justified, and the other bits ofI2CDRR(7-0) are undefined. For example, if BC = 011 (3-bit data size), the receive data is in I2CDRR(2-0), and the content of I2CDRR(7-3) is undefined.When in the receive FIFO mode, the I2CDRR register acts as the receive FIFO buffer.

Figure 20-24. I2CDRR Register15 14 13 12 11 10 9 8

RESERVEDR-0h

7 6 5 4 3 2 1 0DATAR-0h

Table 20-16. I2CDRR Register Field Descriptions

Bit Field Type Reset Description15-8 RESERVED R 0h Reserved7-0 DATA R 0h Receive data

Reset type: SYSRSn

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20.6.2.8 I2CSAR Register (Offset = 7h) [reset = 3FFh]I2CSAR is shown in Figure 20-25 and described in Table 20-17.


The I2C slave address register (I2CSAR) is a 16-bit register for storing the next slave address that will betransmitted by the I2C module when it is a master. The SAR field of I2CSAR contains a 7-bit or 10-bitslave address. When the I2C module is not using the free data format (FDF = 0 in I2CMDR), it uses thisaddress to initiate data transfers with a slave, or slaves. When the address is nonzero, the address is for aparticular slave. When the address is 0, the address is a general call to all slaves. If the 7-bit addressingmode is selected (XA = 0 in I2CMDR), only bits 6-0 of I2CSAR are usedwrite 0s to bits 9-7.

Figure 20-25. I2CSAR Register15 14 13 12 11 10 9 8

RESERVED SARR-0h R/W-3FFh

7 6 5 4 3 2 1 0SAR

R/W-3FFh

Table 20-17. I2CSAR Register Field Descriptions


9-0 SAR R/W 3FFh In 7-bit addressing mode (XA = 0 in I2CMDR):00h-7Fh Bits 6-0 provide the 7-bit slave address that the I2C moduletransmits when it is in the master-transmittermode. Write 0s to bits 9-7.

In 10-bit addressing mode (XA = 1 in I2CMDR):000h-3FFh Bits 9-0 provide the 10-bit slave address that the I2Cmodule transmits when it is in the master transmitter mode.

Reset type: SYSRSn

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20.6.2.9 I2CDXR Register (Offset = 8h) [reset = 0h]I2CDXR is shown in Figure 20-26 and described in Table 20-18.


The CPU writes transmit data to I2CDXR. This 16-bit register accepts a data byte with 1 to 8 bits. Beforewriting to I2CDXR, specify how many bits are in a data byte by loading the appropriate value into the bitcount (BC) bits of I2CMDR. When writing a data byte with fewer than 8 bits, make sure the value is right-aligned in I2CDXR.After a data byte is written to I2CDXR, the I2C module copies the data byte to the transmit shift register(I2CXSR). The CPU cannot access I2CXSR directly. From I2CXSR, the I2C module shifts the data byteout on the SDA pin, one bit at a time.When in the transmit FIFO mode, the I2CDXR register acts as the transmit FIFO buffer.

Figure 20-26. I2CDXR Register15 14 13 12 11 10 9 8

RESERVEDR-0h

7 6 5 4 3 2 1 0DATA

R/W-0h

Table 20-18. I2CDXR Register Field Descriptions

Bit Field Type Reset Description15-8 RESERVED R 0h Reserved7-0 DATA R/W 0h Transmit data

Reset type: SYSRSn

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20.6.2.10 I2CMDR Register (Offset = 9h) [reset = 0h]I2CMDR is shown in Figure 20-27 and described in Table 20-19.


The I2C mode register (I2CMDR) is a 16-bit register that contains the control bits of the I2C module.

Figure 20-27. I2CMDR Register15 14 13 12 11 10 9 8

NACKMOD FREE STT RESERVED STP MST TRX XAR/W-0h R/W-0h R/W-0h R-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0RM DLB IRS STB FDF BC

R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 20-19. I2CMDR Register Field Descriptions

Bit Field Type Reset Description15 NACKMOD R/W 0h NACK mode bit. This bit is only applicable when the I2C module is

acting as a receiver.Reset type: SYSRSn0h (R/W) = In the slave-receiver mode: The I2C module sends anacknowledge (ACK) bit to the transmitter during each acknowledgecycle on the bus. The I2C module only sends a no-acknowledge(NACK) bit if you set the NACKMOD bit.In the master-receiver mode: The I2C module sends an ACK bitduring each acknowledge cycle until the internal data countercounts down to 0. At that point, the I2C module sends a NACK bitto the transmitter. To have a NACK bit sent earlier, you must setthe NACKMOD bit1h (R/W) = In either slave-receiver or master-receiver mode: TheI2C module sends a NACK bit to the transmitter during the nextacknowledge cycle on the bus. Once the NACK bit has been sent,NACKMOD is cleared.Important: To send a NACK bit in the next acknowledge cycle, youmust set NACKMOD before the rising edge of the last data bit.

14 FREE R/W 0h This bit controls the action taken by the I2C module when adebugger breakpoint is encountered.

Reset type: SYSRSn0h (R/W) = When I2C module is master:If SCL is low when the breakpoint occurs, the I2C module stopsimmediately and keeps driving SCL low, whether the I2C module isthe transmitter or the receiver. If SCL is high, the I2C module waitsuntil SCL becomes low and then stops.When I2C module is slave:A breakpoint forces the I2C module to stop when the currenttransmission/reception is complete.1h (R/W) = The I2C module runs freethat is, it continues to operate when a breakpoint occurs.

13 STT R/W 0h START condition bit (only applicable when the I2C module is amaster). The RM, STT, and STP bits determine when the I2Cmodule starts and stops data transmissions (see Table 9-6). Notethat the STT and STP bits can be used to terminate the repeatmode, and that this bit is not writable when IRS = 0.

Reset type: SYSRSn0h (R/W) = In the master mode, STT is automatically cleared afterthe START condition has been generated.1h (R/W) = In the master mode, setting STT to 1 causes the I2Cmodule to generate a START condition on the I2C-bus

12 RESERVED R 0h Reserved

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Table 20-19. I2CMDR Register Field Descriptions (continued)Bit Field Type Reset Description11 STP R/W 0h STOP condition bit (only applicable when the I2C module is a

master).In the master mode, the RM,STT, and STP bits determine when theI2C module starts and stops data transmissions.Note that the STT and STP bits can be used to terminate the repeatmode, and that this bit is not writable when IRS=0. When in non-repeat mode, at least one byte must be transferred before a stopcondition can be generated. The I2C module delays clearing of thisbit until after the I2CSTR[SCD] bit is set. To avoid disrupting the I2Cstate machine, the user must wait until this bit is clear beforeinitiating a new message.

Reset type: SYSRSn0h (R/W) = STP is automatically cleared after the STOP conditionhas been generated1h (R/W) = STP has been set by the device to generate a STOPcondition when the internal data counter of the I2C module countsdown to 0.

10 MST R/W 0h Master mode bit.MST determines whether the I2C module is in the slave mode or themaster mode. MST is automatically changed from 1 to 0 when theI2C master generates a STOP condition

Reset type: SYSRSn0h (R/W) = Slave mode. The I2C module is a slave and receivesthe serial clock from the master.1h (R/W) = Master mode. The I2C module is a master andgenerates the serial clock on the SCL pin.

9 TRX R/W 0h Transmitter mode bit.When relevant, TRX selects whether the I2C module is in thetransmitter mode or the receiver mode.

Reset type: SYSRSn0h (R/W) = Receiver mode. The I2C module is a receiver andreceives data on the SDA pin.1h (R/W) = Transmitter mode. The I2C module is a transmitter andtransmits data on the SDA pin.

8 XA R/W 0h Expanded address enable bit.Reset type: SYSRSn0h (R/W) = 7-bit addressing mode (normal address mode). The I2Cmodule transmits 7-bit slave addresses (from bits 6-0 of I2CSAR),and its own slave address has 7 bits (bits 6-0 of I2COAR).1h (R/W) = 10-bit addressing mode (expanded address mode).The I2C module transmits 10-bit slave addresses (from bits 9-0 ofI2CSAR), and its own slave address has 10 bits (bits 9-0 ofI2COAR).

7 RM R/W 0h Repeat mode bit (only applicable when the I2C module is a master-transmitter).The RM, STT, and STP bits determine when the I2C module startsand stops data transmissions

Reset type: SYSRSn0h (R/W) = Nonrepeat mode. The value in the data count register(I2CCNT) determines how many bytes arereceived/transmitted by the I2C module.1h (R/W) = Repeat mode. A data byte is transmitted each time theI2CDXR register is written to (or until the transmit FIFO is emptywhen in FIFO mode) until the STP bit is manually set. The value ofI2CCNT is ignored. The ARDY bit/interrupt can be used todetermine when the I2CDXR (or FIFO) is ready for more data, orwhen the data has all been sent and the CPU is allowed to write tothe STP bit.

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Table 20-19. I2CMDR Register Field Descriptions (continued)Bit Field Type Reset Description6 DLB R/W 0h Digital loopback mode bit.

Reset type: SYSRSn0h (R/W) = Digital loopback mode is disabled.1h (R/W) = Digital loopback mode is enabled. For proper operationin this mode, the MST bit must be 1.In the digital loopback mode, data transmitted out of I2CDXR isreceived in I2CDRR after n device cycles by an internal path,where:n = ((I2C input clock frequency/module clock frequency) x 8)The transmit clock is also the receive clock. The addresstransmitted on the SDA pin is the address in I2COAR.Note: The free data format (FDF = 1) is not supported in the digitalloopback mode.

5 IRS R/W 0h I2C module reset bit.Reset type: SYSRSn0h (R/W) = The I2C module is in reset/disabled. When this bit iscleared to 0, all status bits (in I2CSTR) are set to their defaultvalues.1h (R/W) = The I2C module is enabled. This has the effect ofreleasing the I2C bus if the I2C peripheral is holding it.

4 STB R/W 0h START byte mode bit. This bit is only applicable when the I2Cmodule is a master. As described in version 2.1 of the PhilipsSemiconductors I2C-bus specification, the START byte can be usedto help a slave that needs extra time to detect a START condition.When the I2C module is a slave, it ignores a START byte from amaster, regardless of the value of the STB bit.

Reset type: SYSRSn0h (R/W) = The I2C module is not in the START byte mode.1h (R/W) = The I2C module is in the START byte mode. When youset the START condition bit (STT), the I2C module begins thetransfer with more than just a START condition. Specifically, itgenerates:1. A START condition2. A START byte (0000 0001b)3. A dummy acknowledge clock pulse4. A repeated START conditionThen, as normal, the I2C module sends the slave address that is inI2CSAR.

3 FDF R/W 0h Free data format mode bit.Reset type: SYSRSn0h (R/W) = Free data format mode is disabled. Transfers use the7-/10-bit addressing format selected by the XA bit.1h (R/W) = Free data format mode is enabled. Transfers have thefree data (no address) format described in Section 9.2.5.The free data format is not supported in the digital loopback mode(DLB=1).

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Table 20-19. I2CMDR Register Field Descriptions (continued)Bit Field Type Reset Description2-0 BC R/W 0h Bit count bits.

BC defines the number of bits (1 to 8) in the next data byte that is tobe received or transmitted by the I2C module. The number of bitsselected with BC must match the data size of the other device.Notice that when BC = 000b, a data byte has 8 bits. BC does notaffect address bytes, which always have 8 bits.Note: If the bit count is less than 8, receive data is right-justified inI2CDRR(7-0), and the other bits of I2CDRR(7-0) are undefined. Also,transmit data written to I2CDXR must be right-justified

Reset type: SYSRSn0h (R/W) = 8 bits per data byte1h (R/W) = 1 bit per data byte2h (R/W) = 2 bits per data byte3h (R/W) = 3 bits per data byte4h (R/W) = 4 bits per data byte5h (R/W) = 5 bits per data byte6h (R/W) = 6 bits per data byte7h (R/W) = 7 bits per data byte

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20.6.2.11 I2CISRC Register (Offset = Ah) [reset = 0h]I2CISRC is shown in Figure 20-28 and described in Table 20-20.


The I2C interrupt source register (I2CISRC) is a 16-bit register used by the CPU to determine which eventgenerated the I2C interrupt.

Figure 20-28. I2CISRC Register15 14 13 12 11 10 9 8

RESERVED WRITE_ZEROSR-0h R/W-0h

7 6 5 4 3 2 1 0RESERVED INTCODE

R-0h R-0h

Table 20-20. I2CISRC Register Field Descriptions

Bit Field Type Reset Description15-12 RESERVED R 0h Reserved11-8 WRITE_ZEROS R/W 0h TI internal testing bits

These reserved bit locations should always be written as zeros.Reset type: SYSRSn

7-3 RESERVED R 0h Reserved2-0 INTCODE R 0h Interrupt code bits.

The binary code in INTCODE indicates the event that generated anI2C interrupt.

A CPU read will clear this field. If another lower priority interrupt ispending and enabled, the value corresponding to that interrupt willthen be loaded. Otherwise, the value will stay cleared.In the case of an arbitration lost, a no-acknowledgment conditiondetected, or a stop condition detected, a CPU read will also clear theassociated interrupt flag bit in the I2CSTR register.Emulator reads will not affect the state of this field or of the statusbits in the I2CSTR register.

Reset type: SYSRSn0h (R/W) = None1h (R/W) = Arbitration lost2h (R/W) = No-acknowledgment condition detected3h (R/W) = Registers ready to be accessed4h (R/W) = Receive data ready5h (R/W) = Transmit data ready6h (R/W) = Stop condition detected7h (R/W) = Addressed as slave

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20.6.2.12 I2CEMDR Register (Offset = Bh) [reset = 1h]I2CEMDR is shown in Figure 20-29 and described in Table 20-21.


I2C Extended Mode

Figure 20-29. I2CEMDR Register15 14 13 12 11 10 9 8

RESERVEDR-0h

7 6 5 4 3 2 1 0RESERVED BC

R-0h R/W-1h

Table 20-21. I2CEMDR Register Field Descriptions


0 BC R/W 1h Backwards compatibility mode.This bit affects the timing of the transmit status bits (XRDY andXSMT) in the I2CSTR register when in slave transmitter mode.Check Backwards Compatibility Mode Bit, Slave Transmitter diagramfor more details.

Reset type: SYSRSn0h (R/W) = See the "Backwards Compatibility Mode Bit, SlaveTransmitter" Figure for details.1h (R/W) = See the "Backwards Compatibility Mode Bit, SlaveTransmitter" Figure for details.

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20.6.2.13 I2CPSC Register (Offset = Ch) [reset = 0h]I2CPSC is shown in Figure 20-30 and described in Table 20-22.


The I2C prescaler register (I2CPSC) is a 16-bit register (see Figure 14-21) used for dividing down the I2Cinput clock to obtain the desired module clock for the operation of the I2C module. See the device-specificdata manual for the supported range of values for the module clock frequency.IPSC must be initialized while the I2C module is in reset (IRS = 0 in I2CMDR). The prescaled frequencytakes effect only when IRS is changed to 1. Changing the IPSC value while IRS = 1 has no effect.

Figure 20-30. I2CPSC Register15 14 13 12 11 10 9 8

RESERVEDR-0h

7 6 5 4 3 2 1 0IPSC

R/W-0h

Table 20-22. I2CPSC Register Field Descriptions

Bit Field Type Reset Description15-8 RESERVED R 0h Reserved7-0 IPSC R/W 0h I2C prescaler divide-down value.

IPSC determines how much the CPU clock is divided to create themodule clock of the I2C module:module clock frequency = I2C input clock frequency/(IPSC + 1)Note: IPSC must be initialized while the I2C module is in reset (IRS= 0 in I2CMDR).

Reset type: SYSRSn

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20.6.2.14 I2CFFTX Register (Offset = 20h) [reset = 0h]I2CFFTX is shown in Figure 20-31 and described in Table 20-23.


The I2C transmit FIFO register (I2CFFTX) is a 16-bit register that contains the I2C FIFO mode enable bitas well as the control and status bits for the transmit FIFO mode of operation on the I2C peripheral.

Figure 20-31. I2CFFTX Register15 14 13 12 11 10 9 8

RESERVED I2CFFEN TXFFRST TXFFSTR-0h R/W-0h R/W-0h R-0h

7 6 5 4 3 2 1 0TXFFINT TXFFINTCLR TXFFIENA TXFFIL

R-0h R-0/W1S-0h R/W-0h R/W-0h

Table 20-23. I2CFFTX Register Field Descriptions

Bit Field Type Reset Description15 RESERVED R 0h Reserved14 I2CFFEN R/W 0h I2C FIFO mode enable bit.

This bit must be enabled for either the transmit or the receive FIFOto operate correctly.

Reset type: SYSRSn0h (R/W) = Disable the I2C FIFO mode.1h (R/W) = Enable the I2C FIFO mode.

13 TXFFRST R/W 0h Transmit FIFO ResetReset type: SYSRSn0h (R/W) = Reset the transmit FIFO pointer to 0000 and hold thetransmit FIFO in the reset state.1h (R/W) = Enable the transmit FIFO operation.

12-8 TXFFST R 0h Contains the status of the transmit FIFO:xxxxx Transmit FIFO contains xxxxx bytes.00000 Transmit FIFO is empty.

Note: Since these bits are reset to zero, the transmit FIFO interruptflag will be set when the transmit FIFO operation is enabled and theI2C is taken out of reset. This will generate a transmit FIFO interruptif enabled. To avoid any detrimental effects from this, write a one tothe TXFFINTCLR once the transmit FIFO operation is enabled andthe I2C is taken out of reset.

Reset type: SYSRSn7 TXFFINT R 0h Transmit FIFO interrupt flag.

This bit cleared by a CPU write of a 1 to the TXFFINTCLR bit. If theTXFFIENA bit is set, this bit will generate an interrupt when it is set.

Reset type: SYSRSn0h (R/W) = Transmit FIFO interrupt condition has not occurred.1h (R/W) = Transmit FIFO interrupt condition has occurred.

6 TXFFINTCLR R-0/W1S 0h Transmit FIFO Interrupt Flag ClearReset type: SYSRSn0h (R/W) = Writes of zeros have no effect. Reads return a 0.1h (R/W) = Writing a 1 to this bit clears the TXFFINT flag.

5 TXFFIENA R/W 0h Transmit FIFO Interrupt EnableReset type: SYSRSn0h (R/W) = Disabled. TXFFINT flag does not generate an interruptwhen set.1h (R/W) = Enabled. TXFFINT flag does generate an interruptwhen set.

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Table 20-23. I2CFFTX Register Field Descriptions (continued)Bit Field Type Reset Description4-0 TXFFIL R/W 0h Transmit FIFO interrupt level.

These bits set the status level that will set the transmit interrupt flag.When the TXFFST4-0 bits reach a value equal to or less than thesebits, the TXFFINT flag will be set. This will generate an interrupt ifthe TXFFIENA bit is set. Because the I2C on this device has a 16-level transmit FIFO, these bits cannot be configured for an interruptof more than 16 FIFO levels.

Reset type: SYSRSn

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20.6.2.15 I2CFFRX Register (Offset = 21h) [reset = 0h]I2CFFRX is shown in Figure 20-32 and described in Table 20-24.


The I2C receive FIFO register (I2CFFRX) is a 16-bit register that contains the control and status bits forthe receive FIFO mode of operation on the I2C peripheral.

Figure 20-32. I2CFFRX Register15 14 13 12 11 10 9 8

RESERVED RXFFRST RXFFSTR-0h R/W-0h R-0h

7 6 5 4 3 2 1 0RXFFINT RXFFINTCLR RXFFIENA RXFFIL

R-0h R-0/W1S-0h R/W-0h R/W-0h

Table 20-24. I2CFFRX Register Field Descriptions


13 RXFFRST R/W 0h I2C receive FIFO reset bitReset type: SYSRSn0h (R/W) = Reset the receive FIFO pointer to 0000 and hold thereceive FIFO in the reset state.1h (R/W) = Enable the receive FIFO operation.

12-8 RXFFST R 0h Contains the status of the receive FIFO:

xxxxx Receive FIFO contains xxxxx bytes00000 Receive FIFO is empty.

Reset type: SYSRSn7 RXFFINT R 0h Receive FIFO interrupt flag.

This bit cleared by a CPU write of a 1 to the RXFFINTCLR bit. If theRXFFIENA bit is set, this bit will generate an interrupt when it is set

Reset type: SYSRSn0h (R/W) = Receive FIFO interrupt condition has not occurred.1h (R/W) = Receive FIFO interrupt condition has occurred.

6 RXFFINTCLR R-0/W1S 0h Receive FIFO interrupt flag clear bit.Reset type: SYSRSn0h (R/W) = Writes of zeros have no effect. Reads return a zero.1h (R/W) = Writing a 1 to this bit clears the RXFFINT flag.

5 RXFFIENA R/W 0h Receive FIFO interrupt enable bit.Reset type: SYSRSn0h (R/W) = Disabled. RXFFINT flag does not generate an interruptwhen set.1h (R/W) = Enabled. RXFFINT flag does generate an interruptwhen set.

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Table 20-24. I2CFFRX Register Field Descriptions (continued)Bit Field Type Reset Description4-0 RXFFIL R/W 0h Receive FIFO interrupt level.

These bits set the status level that will set the receive interrupt flag.When the RXFFST4-0 bits reach a value equal to or greater thanthese bits, the RXFFINT flag is set. This will generate an interrupt ifthe RXFFIENA bit is set.

Note: Since these bits are reset to zero, the receive FIFO interruptflag will be set if the receive FIFO operation is enabled and the I2Cis taken out of reset. This will generate a receive FIFO interrupt ifenabled. To avoid this, modify these bits on the same instruction asor prior to setting the RXFFRST bit. Because the I2C on this devicehas a 16-level receive FIFO, these bits cannot be configured for aninterrupt of more than 16 FIFO levels.

Reset type: SYSRSn

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