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Document Number: 329676-001US

Intel Quark SoC X1000Datasheet

October 2013

Intel Quark SoC X1000DS October 20132 Document Number: 329676-001US

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Intel Quark SoC X1000October 2013 DSDocument Number: 329676-001US 3

Intel Quark SoC X1000

Contents

1.0 Introduction ............................................................................................................ 371.1 About This Manual ............................................................................................. 371.2 Component Overview......................................................................................... 37

1.2.1 SoC CPU Core Features ........................................................................... 381.2.2 System Memory Controller Features ......................................................... 391.2.3 Embedded SRAM Features ....................................................................... 391.2.4 Power Management Features ................................................................... 391.2.5 Security Features ................................................................................... 391.2.6 PCI Express* Features ............................................................................ 391.2.7 Ethernet Features................................................................................... 401.2.8 USB2 Host Controller Features ................................................................. 401.2.9 USB2 Device Controller Features .............................................................. 401.2.10 SD/SDIO/eMMC Controller Features .......................................................... 401.2.11 I2C* Master Controller ............................................................................ 401.2.12 GPIO Features ....................................................................................... 411.2.13 SPI Master Controller.............................................................................. 411.2.14 High Speed UART Controller with DMA ...................................................... 411.2.15 Legacy Bridge........................................................................................ 411.2.16 Package ................................................................................................ 41

1.3 Component Identification ................................................................................... 41

2.0 Physical Interfaces .................................................................................................. 452.1 Pin States Through Reset ................................................................................... 472.2 System Memory Signals ..................................................................................... 472.3 PCI Express* 2.0 Signals.................................................................................... 482.4 Ethernet Interface Signals .................................................................................. 492.5 USB 2.0 Interface Signals................................................................................... 492.6 Integrated Clock Interface Signals ....................................................................... 502.7 SDIO/SD/MMC Signals ....................................................................................... 502.8 High Speed UART Interface Signals...................................................................... 512.9 I2C* Interface Signals........................................................................................ 512.10 Legacy Serial Peripheral Interface (SPI) Signals..................................................... 522.11 Serial Peripheral Interface (SPI) .......................................................................... 522.12 Real Time Clock (RTC) Interface Signals ............................................................... 532.13 Power Management Signals ................................................................................ 532.14 JTAG and Debug Interface Signals ....................................................................... 532.15 Legacy Interface Signals .................................................................................... 542.16 General Purpose I/O Interface Signals.................................................................. 542.17 Power And Ground Pins ...................................................................................... 552.18 Hardware Straps ............................................................................................... 56

3.0 Ballout and Package Information............................................................................. 59

4.0 Electrical Characteristics ......................................................................................... 694.1 Absolute Maximum Ratings................................................................................. 694.2 Recommended Power Supply Ranges ................................................................... 704.3 Maximum Supply Current ................................................................................... 714.4 Configurable IO Characteristics ........................................................................... 724.5 RTC DC Characteristics ...................................................................................... 724.6 PCI Express* 2.0 DC/AC Characteristics ............................................................... 734.7 USB 2.0 DC/AC Characteristics............................................................................ 75



4.8 General Interface Timing ....................................................................................784.8.1 Legacy SPI Interface Timing.....................................................................784.8.2 SPI0/1 Interface Timing...........................................................................784.8.3 SDIO Interface Timing.............................................................................79

4.9 Clock AC Timing ................................................................................................804.9.1 Reference Clock AC Characteristics............................................................80

5.0 Register Access Methods.........................................................................................835.1 Fixed I/O Register Access ...................................................................................835.2 Fixed Memory Mapped Register Access .................................................................835.3 I/O Referenced Register Access ...........................................................................835.4 Memory Referenced Register Access.....................................................................845.5 PCI Configuration Register Access ........................................................................84

5.5.1 PCI Configuration Access - CAM: I/O Indexed Scheme .................................845.5.2 PCI Configuration Access - ECAM: Memory Mapped Scheme .........................85

5.6 Message Bus Register Access ..............................................................................865.7 Register Field Access Types.................................................................................87

6.0 Mapping Address Spaces..........................................................................................896.1 Physical Address Space Mappings.........................................................................89

6.1.1 Bridge Memory Map ................................................................................896.1.1.1 MMIO ......................................................................................916.1.1.2 DOS DRAM...............................................................................926.1.1.3 Additional Mappings...................................................................92

6.1.2 MMIO Map .............................................................................................936.2 I/O Address Space .............................................................................................93

6.2.1 Host Bridge I/O Map ...............................................................................946.2.2 I/O Fabric I/O Map..................................................................................94

6.2.2.1 Legacy Bridge Fixed I/O Address Ranges ......................................946.2.2.2 Variable I/O Address Ranges.......................................................94

6.3 PCI Configuration Space .....................................................................................956.4 Message Bus Space............................................................................................97

7.0 Clocking ...................................................................................................................997.1 Clocking Features ..............................................................................................997.2 Platform/System Clock Domains ........................................................................100

8.0 Power Management ...............................................................................................1038.1 Power Management Features.............................................................................1038.2 ACPI Supported States .....................................................................................103

8.2.1 S-State Definition .................................................................................1038.2.1.1 S0 - Full On............................................................................1038.2.1.2 S3 - Suspend to RAM (Standby) ................................................1038.2.1.3 S4 - Suspend to Disk (Hibernate) ..............................................1038.2.1.4 S5 - Soft Off ...........................................................................104

8.2.2 System States......................................................................................1048.2.3 Processor Idle States.............................................................................1058.2.4 Integrated Memory Controller States.......................................................1058.2.5 PCIe* States ........................................................................................1058.2.6 Interface State Combinations .................................................................106

8.3 Processor Core Power Management ....................................................................1068.3.1 Low-Power Idle States...........................................................................106

8.3.1.1 Clock Control and Low-Power States ..........................................1068.3.2 Processor Core C-States Description........................................................106

8.3.2.1 Core C0 State .........................................................................1068.3.2.2 Core C1 State .........................................................................1078.3.2.3 Core C2 State .........................................................................107



8.4 Memory Controller Power Management............................................................... 1078.4.1 Disabling Unused System Memory Outputs .............................................. 1078.4.2 DRAM Power Management and Initialization ............................................. 107

8.4.2.1 Initialization Role of CKE.......................................................... 1078.4.2.2 Dynamic Self-Refresh .............................................................. 1078.4.2.3 Dynamic Power Down Operation ............................................... 1088.4.2.4 Functional Clock Gating ........................................................... 108

9.0 Power Up and Reset Sequence............................................................................... 1099.1 Intel Quark SoC X1000 System States ............................................................. 109

9.1.1 System Sleeping States Control (S-States) .............................................. 1099.2 Power Up and Down Sequences......................................................................... 109

9.2.1 Power Up, Wake and Reset Overview ...................................................... 1099.2.2 RTC Power Well Transition: G5 to G3 State Transition ............................... 1109.2.3 Power-Up Sequence without G2/G3: No Coin-Cell Battery .......................... 1119.2.4 AC Power Applied: G3 to S4/S5 State Transition....................................... 1129.2.5 Using PWR_BTN: Transition from S4/S5 to S0 .......................................... 1129.2.6 Going to Sleep: Transitions from S0 to S3 or S4/S5 .................................. 1169.2.7 Wake Events: Transition from S3 to S0 ................................................... 1169.2.8 System Reset Sequences....................................................................... 116

9.2.8.1 Cold Boot Sequence ............................................................... 1179.2.8.2 Cold Reset Sequence............................................................... 1179.2.8.3 Warm Reset Sequence (Internal) .............................................. 1179.2.8.4 Externally Initiated Warm Reset Sequence ................................. 117

9.2.9 Handling Power Failures ........................................................................ 117

10.0 Thermal Management ............................................................................................ 11910.1 Overview ....................................................................................................... 11910.2 Thermal Sensor............................................................................................... 119

11.0 Processor Core ...................................................................................................... 121

12.0 Host Bridge ........................................................................................................... 12312.1 Embedded SRAM (eSRAM)................................................................................ 123

12.1.1 Initialization ........................................................................................ 12312.1.2 Configuration....................................................................................... 123

12.1.2.1 4KB Page Mode ...................................................................... 12312.1.2.2 512KB Block Page Mode........................................................... 124

12.1.3 Configuration Locking ........................................................................... 12512.1.4 ECC Protection ..................................................................................... 12612.1.5 Flush to DRAM ..................................................................................... 126

12.2 Isolated Memory Regions (IMR)......................................................................... 12612.2.1 IMR Violation ....................................................................................... 12712.2.2 IMR Locking......................................................................................... 127

12.3 Remote Management Unit DMA ......................................................................... 12712.3.1 ECC Scrubbing .................................................................................... 128

12.4 Register Map .................................................................................................. 12812.5 PCI Configuration Registers .............................................................................. 129

12.5.1 PCI Device ID and Vendor ID Fields (PCI_DEVICE_VENDOR)Offset 0h....... 12912.5.2 PCI Status and Command Fields (PCI_STATUS_COMMAND)Offset 4h ........ 12912.5.3 PCI Class Code and Revision ID Fields (PCI_CLASS_REVISION)Offset 8h... 13012.5.4 PCI Miscellaneous Fields (PCI_MISC)Offset Ch ....................................... 13012.5.5 PCI Subsystem ID and Subsystem Vendor ID Fields

(PCI_SUBSYSTEM)Offset 2Ch .............................................................. 13112.5.6 Message Bus Control Register (MCR) (SB_PACKET_REG)Offset D0h.......... 13212.5.7 Message Data Register (MDR) (SB_DATA_REG)Offset D4h ...................... 132



12.5.8 Message Control Register eXtension (MCRX) (SB_ADDR_EXTN_REG)OffsetD8h ....................................................................................................132

12.5.9 Manufacturer ID (PCI_MANUFACTURER)Offset F8h .................................13312.6 IO Mapped Register .........................................................................................134

12.6.1 ACPI Processor Block.............................................................................13412.6.1.1 Processor Control (P_CNT)Offset 0h ........................................13412.6.1.2 Level 2 Register (P_LVL2)Offset 4h .........................................13512.6.1.3 C6 Control Register (P_C6C)Offset Ch .....................................135

12.6.2 SPI DMA Block .....................................................................................13612.6.2.1 SPI DMA Count Register (SPI_DMA_CNT_IOSF)Offset 0h ...........13612.6.2.2 SPI DMA Destination Register (SPI_DMA_DST_IOSF)Offset 4h....13612.6.2.3 SPI DMA Source Register (SPI_DMA_SRC_IOSF)Offset 8h..........137

12.7 Message Bus Register.......................................................................................13812.7.1 Host Bridge Arbiter (Port 0x00) ..............................................................138

12.7.1.1 Enhanced Configuration Space (AEC_CTRL)Offset 0h.................13812.7.1.2 STATUSOffset 21h ................................................................13812.7.1.3 Requester ID Match Control (ASUBCHAN_CTRL)Offset 50h .........13912.7.1.4 Requester ID Match Sub-Channel 1 (ASUBCHAN1_MATCH)Offset

51h .......................................................................................14012.7.1.5 Requester ID Match Sub-Channel 2 (ASUBCHAN2_MATCH)Offset

52h .......................................................................................14112.7.1.6 Requester ID Match Sub-Channel 3 (ASUBCHAN3_MATCH)Offset

53h .......................................................................................14112.7.2 Host Bridge (Port 0x03).........................................................................142

12.7.2.1 Host Miscellaneous Controls 2 (HMISC2)Offset 3h .....................14312.7.2.2 Host System Management Mode Controls (HSMMCTL)Offset 4h...14412.7.2.3 Host Memory I/O Boundary (HMBOUND)Offset 8h.....................14512.7.2.4 Extended Configuration Space (HECREG)Offset 9h ....................14612.7.2.5 Host Bridge Write Flush Control (HWFLUSH)Offset Ch................14712.7.2.6 MTRR Capabilities (MTRR_CAP)Offset 40h ................................14712.7.2.7 MTRR Default Type (MTRR_DEF_TYPE)Offset 41h......................14812.7.2.8 MTRR Fixed 64KB Range 0x00000 (MTRR_FIX64K_00000)Offset

42h .......................................................................................14812.7.2.9 MTRR Fixed 64KB Range 0x40000 (MTRR_FIX64K_40000)Offset

43h .......................................................................................14912.7.2.10MTRR Fixed 16KB Range 0x80000 (MTRR_FIX16K_80000)Offset

44h .......................................................................................14912.7.2.11MTRR Fixed 16KB Range 0x90000 (MTRR_FIX16K_90000)Offset

45h .......................................................................................15012.7.2.12MTRR Fixed 16KB Range 0xA0000 (MTRR_FIX16K_A0000)Offset

46h .......................................................................................15112.7.2.13MTRR Fixed 16KB Range 0xB0000 (MTRR_FIX16K_B0000)Offset

47h .......................................................................................15112.7.2.14MTRR Fixed 4KB Range 0xC0000 (MTRR_FIX4K_C0000)Offset



4Ah .......................................................................................15312.7.2.17MTRR Fixed 4KB Range 0xCC000 (MTRR_FIX4K_CC000)Offset

4Bh .......................................................................................15312.7.2.18MTRR Fixed 4KB Range 0xD0000 (MTRR_FIX4K_D0000)Offset

4Ch.......................................................................................15412.7.2.19MTRR Fixed 4KB Range 0xD40000 (MTRR_FIX4K_D4000)Offset

4Dh.......................................................................................15512.7.2.20MTRR Fixed 4KB Range 0xD8000 (MTRR_FIX4K_D8000)Offset

4Eh .......................................................................................15512.7.2.21MTRR Fixed 4KB Range 0xDC000 (MTRR_FIX4K_DC000)Offset

4Fh .......................................................................................156



12.7.2.22MTRR Fixed 4KB Range 0xE0000 (MTRR_FIX4K_E0000)Offset50h....................................................................................... 156



12.7.2.25MTRR Fixed 4KB Range 0xEC000 (MTRR_FIX4K_EC000)Offset53h....................................................................................... 158

12.7.2.26MTRR Fixed 4KB Range 0xF0000 (MTRR_FIX4K_F0000)Offset54h....................................................................................... 158



12.7.2.29MTRR Fixed 4KB Range 0xFC000 (MTRR_FIX4K_FC000)Offset57h....................................................................................... 160

12.7.2.30System Management Range Physical Base(MTRR_SMRR_PHYSBASE)Offset 58h ...................................... 161

12.7.2.31System Management Range Physical Mask(MTRR_SMRR_PHYSMASK)Offset 59h...................................... 161

12.7.2.32MTRR Variable Range Physical Base 0(MTRR_VAR_PHYSBASE0)Offset 5Ah....................................... 162

12.7.2.33MTRR Variable Range Physical Mask 0 (MTRR_VAR_PHYSMASK0)Offset 5Bh ............................................................................. 162

12.7.2.34MTRR Variable Range Physical Base 1(MTRR_VAR_PHYSBASE1)Offset 5Ch....................................... 163

12.7.2.35MTRR Variable Range Physical Mask 1 (MTRR_VAR_PHYSMASK1)Offset 5Dh ............................................................................. 164

12.7.2.36MTRR Variable Range Physical Base 2(MTRR_VAR_PHYSBASE2)Offset 5Eh....................................... 164

12.7.2.37MTRR Variable Range Physical Mask 2 (MTRR_VAR_PHYSMASK2)Offset 5Fh.............................................................................. 165

12.7.2.38MTRR Variable Range Physical Base 3(MTRR_VAR_PHYSBASE3)Offset 60h....................................... 165

12.7.2.39MTRR Variable Range Physical Mask 3 (MTRR_VAR_PHYSMASK3)Offset 61h ............................................................................. 166









12.7.3 Remote Management Unit (Port 0x04) .................................................... 17112.7.3.1 ECC Scrubber Configuration Register (P_CFG_50)Offset 50h ...... 17112.7.3.2 SPI DMA Count Register (P_CFG_60)Offset 60h........................ 17212.7.3.3 SPI DMA Destination Register (P_CFG_61)Offset 61h ................ 17312.7.3.4 SPI DMA Source Register (P_CFG_62)Offset 62h ...................... 17312.7.3.5 Processor Register Block (P_BLK) Base Address

(P_CFG_70)Offset 70h .......................................................... 17412.7.3.6 Control Register (P_CFG_71)Offset 71h................................... 174



12.7.3.7 Watchdog Control Register (P_CFG_74)Offset 74h ....................17512.7.3.8 ECC Scrubber Start Address Register (P_CFG_76)Offset 76h ......17612.7.3.9 ECC Scrubber End Address Register (P_CFG_77)Offset 77h ........17612.7.3.10ECC Scrubber Next Address Register (P_CFG_7C)Offset 7Ch ......17712.7.3.11Thermal Sensor Mode Register (P_CFG_B0)Offset B0h...............17812.7.3.12Thermal Sensor Temperature Register (P_CFG_B1)Offset B1h ....17812.7.3.13Thermal Sensor Programmable Trip Point Register

(P_CFG_B2)Offset B2h ..........................................................17912.7.4 Memory Manager (Port 0x05) .................................................................180

12.7.4.1 Control (BCTRL)Offset 1h ......................................................18112.7.4.2 Write Flush Policy (BWFLUSH)Offset 2h ...................................18212.7.4.3 Isolated Memory Region Violation Control (BIMRVCTL)Offset 19h 18312.7.4.4 Debug 1 (DEBUG1)Offset 31h ................................................18412.7.4.5 Isolated Memory Region 0 Low Address (IMR0L)Offset 40h ........18512.7.4.6 Isolated Memory Region 0 High Address (IMR0H)Offset 41h .......18612.7.4.7 Isolated Memory Region 0 Read Mask (IMR0RM)Offset 42h ........18612.7.4.8 Isolated Memory Region 0 Write Mask (IMR0WM)Offset 43h .......18812.7.4.9 Isolated Memory Region 1 Low Address (IMR1L)Offset 44h ........19012.7.4.10Isolated Memory Region 1 High Address (IMR1H)Offset 45h .......19112.7.4.11Isolated Memory Region 1 Read Mask (IMR1RM)Offset 46h ........19112.7.4.12Isolated Memory Region 1 Write Mask (IMR1WM)Offset 47h.......19312.7.4.13Isolated Memory Region 2 Low Address (IMR2L)Offset 48h ........19512.7.4.14Isolated Memory Region 2 High Address (IMR2H)Offset 49h .......19512.7.4.15Isolated Memory Region 2 Read Mask (IMR2RM)Offset 4Ah ........19612.7.4.16Isolated Memory Region 2 Write Mask (IMR2WM)Offset 4Bh.......19812.7.4.17Isolated Memory Region 3 Low Address (IMR3L)Offset 4Ch ........19912.7.4.18Isolated Memory Region 3 High Address (IMR3H)Offset 4Dh.......20012.7.4.19Isolated Memory Region 3 Read Mask (IMR3RM)Offset 4Eh ........20012.7.4.20Isolated Memory Region 3 Write Mask (IMR3WM)Offset 4Fh .......20212.7.4.21Isolated Memory Region 4 Low Address (IMR4L)Offset 50h ........20412.7.4.22Isolated Memory Region 4 High Address (IMR4H)Offset 51h .......20512.7.4.23Isolated Memory Region 4 Read Mask (IMR4RM)Offset 52h ........20512.7.4.24Isolated Memory Region 4 Write Mask (IMR4WM)Offset 53h.......20712.7.4.25Isolated Memory Region 5 Low Address (IMR5L)Offset 54h ........20912.7.4.26Isolated Memory Region 5 High Address (IMR5H)Offset 55h .......20912.7.4.27Isolated Memory Region 5 Read Mask (IMR5RM)Offset 56h ........21012.7.4.28Isolated Memory Region 5 Write Mask (IMR5WM)Offset 57h.......21212.7.4.29Isolated Memory Region 6 Low Address (IMR6L)Offset 58h ........21312.7.4.30Isolated Memory Region 6 High Address (IMR6H)Offset 59h .......21412.7.4.31Isolated Memory Region 6 Read Mask (IMR6RM)Offset 5Ah ........21412.7.4.32Isolated Memory Region 6 Write Mask (IMR6WM)Offset 5Bh.......21612.7.4.33Isolated Memory Region 7 Low Address (IMR7L)Offset 5Ch ........21812.7.4.34Isolated Memory Region 7 High Address (IMR7H)Offset 5Dh.......21912.7.4.35Isolated Memory Region 7 Read Mask (IMR7RM)Offset 5Eh ........21912.7.4.36Isolated Memory Region 7 Write Mask (IMR7WM)Offset 5Fh .......22112.7.4.37eSRAM Control (ESRAMCTRL)Offset 81h ..................................22312.7.4.38eSRAM Block Page Control (ESRAMPGCTRL_BLOCK)Offset 82h ...22412.7.4.39eSRAM Correctable Error (ESRAMCERR)Offset 83h ....................22512.7.4.40eSRAM Uncorrectable Error (ESRAMUERR)Offset 84h.................22612.7.4.41eSRAM ECC Error Syndrome (ESRAMSDROME)Offset 88h...........227

12.7.5 Memory Manager eSRAM (Port 0x05) ......................................................22812.7.5.1 eSRAM Page Control Register[0-127]

(ESRAMPGCTRL[0-127])Offset 0h, Count 128, Stride 4h ............22812.7.6 SoC Unit (Port 0x31).............................................................................229

12.7.6.1 Thermal Sensor Configuration 4 (SCU_TSCFG4_Config)Offset34h .......................................................................................229

12.7.6.2 Sticky Write Once (CFGSTICKY_W1)Offset 50h .........................23012.7.6.3 Sticky Read/Write (CFGSTICKY_RW)Offset 51h.........................23012.7.6.4 Non-Sticky Read/Write Once (CFGNONSTICKY_W1)Offset 52h....231



13.0 System Memory Controller .................................................................................... 23313.1 Signal Descriptions .......................................................................................... 23313.2 Features ........................................................................................................ 234

13.2.1 System Memory Technology Supported ................................................... 23413.2.2 Rules for Populating Memory Down Ranks................................................ 23513.2.3 DRAM Error Detection & Correction (EDC)................................................ 23513.2.4 DRAM Data Scrambling ......................................................................... 23513.2.5 Power Management .............................................................................. 235

13.3 Register Map .................................................................................................. 23513.4 Message Bus Registers..................................................................................... 236

13.4.1 DRAM Rank Population (DRP)Offset 0h ................................................. 23713.4.2 DRAM Timing Register 0 (DTR0)Offset 1h ............................................. 23813.4.3 DRAM Timing Register 1 (DTR1)Offset 2h ............................................. 24013.4.4 DRAM Timing Register 2 (DTR2)Offset 3h ............................................. 24213.4.5 DRAM Timing Register 3 (DTR3)Offset 4h ............................................. 24313.4.6 DRAM Timing Register 4 (DTR4)Offset 5h ............................................. 24413.4.7 DRAM Power Management Control 0 (DPMC0)Offset 6h........................... 24513.4.8 DRAM Refresh Control (DRFC)Offset 8h ................................................ 24713.4.9 DRAM Scheduler Control (DSCH)Offset 9h............................................. 24813.4.10DRAM Calibration Control (DCAL)Offset Ah............................................ 24913.4.11DRAM Reset Management Control (DRMC)Offset Bh ............................... 25013.4.12Power Management Status (PMSTS)Offset Ch........................................ 25113.4.13DRAM Control Operation (DCO)Offset Fh............................................... 25213.4.14Sticky Scratchpad 0 (SSKPD0)Offset 4Ah.............................................. 25213.4.15Sticky Scratchpad 1 (SSKPD1)Offset 4Bh.............................................. 25313.4.16DRAM ECC Control Register (DECCCTRL)Offset 60h................................ 25313.4.17DRAM ECC Status (DECCSTAT)Offset 61h ............................................. 25413.4.18DRAM ECC Single Bit Error Count (DECCSBECNT)Offset 62h .................... 25413.4.19DRAM Single Bit ECC Error Captured Address (DECCSBECA)Offset 68h ..... 25513.4.20DRAM Single Bit ECC Error Captured Syndrome (DECCSBECS)Offset 69h .. 25613.4.21DRAM Double Bit ECC Error Captured Address (DECCDBECA)Offset 6Ah.... 25613.4.22DRAM Double Bit ECC Error Captured Syndrome (DECCDBECS)Offset 6Bh. 25713.4.23Memory Controller Fuse Status (DFUSESTAT)Offset 70h ......................... 25713.4.24Scrambler Seed (DSCRMSEED)Offset 80h ............................................. 258

14.0 PCI Express* 2.0 ................................................................................................... 25914.1 Signal Descriptions .......................................................................................... 25914.2 Features ........................................................................................................ 259

14.2.1 Interrupts and Events ........................................................................... 26014.2.1.1 Express Card Hot Plug Events ................................................... 26014.2.1.2 System Error (SERR)............................................................... 261

14.2.2 Power Management .............................................................................. 26114.3 References ..................................................................................................... 26114.4 Register Map .................................................................................................. 26114.5 PCI Configuration Registers .............................................................................. 262

14.5.1 Identifiers (ID)Offset 0h ..................................................................... 26414.5.2 Primary Status (CMD_PSTS)Offset 4h................................................... 26414.5.3 Class Code (RID_CC)Offset 8h............................................................. 26614.5.4 Header Type (CLS_PLT_HTYPE)Offset Ch .............................................. 26614.5.5 Secondary Latency Timer (BNUM_SLT)Offset 18h .................................. 26714.5.6 Secondary Status (IOBL_SSTS)Offset 1Ch ............................................ 26714.5.7 Memory Base and Limit (MBL)Offset 20h .............................................. 26814.5.8 Prefetchable Memory Base and Limit (PMBL)Offset 24h........................... 26914.5.9 Prefetchable Memory Base Upper 32 Bits (PMBU32)Offset 28h................. 26914.5.10Prefetchable Memory Limit Upper 32 Bits (PMLU32)Offset 2Ch................. 270



14.5.11Capabilities List Pointer (CAPP)Offset 34h..............................................27014.5.12Bridge Control (INTR_BCTRL)Offset 3Ch................................................27114.5.13PCI Express Capabilities (CLIST_XCAP)Offset 40h...................................27214.5.14Device Capabilities (DCAP)Offset 44h....................................................27314.5.15Device Status (DCTL_DSTS)Offset 48h .................................................27414.5.16Link Capabilities (LCAP)Offset 4Ch........................................................27514.5.17Link Status (LCTL_LSTS)Offset 50h ......................................................27714.5.18Slot Capabilities (SLCAP)Offset 54h ......................................................27814.5.19Slot Status (SLCTL_SLSTS)Offset 58h...................................................27914.5.20Root Control (RCTL)Offset 5Ch.............................................................28114.5.21Root Status (RSTS)Offset 60h..............................................................28114.5.22Device Capabilities 2 (DCAP2)Offset 64h ...............................................28214.5.23Device Status 2 (DCTL2_DSTS2)Offset 68h ...........................................28314.5.24Link Capability 2 (LCAP2)Offset 6Ch .....................................................28414.5.25Link Status 2 (LCTL2_LSTS2)Offset 70h ................................................28414.5.26Slot Capabilities 2 (SLCAP2)Offset 74h..................................................28614.5.27Slot Status 2 (SLCTL2_SLSTS2)Offset 78h.............................................28614.5.28Message Signaled Interrupt Message Control (MID_MC)Offset 80h............28714.5.29Message Signaled Interrupt Message Address (MA)Offset 84h ..................28714.5.30Message Signaled Interrupt Message Data (MD)Offset 88h ......................28814.5.31Subsystem Vendor Capability (SVCAP)Offset 90h ...................................28814.5.32Subsystem Vendor IDs (SVID)Offset 94h ..............................................28914.5.33PCI Power Management Capabilities (PMCAP_PMC)Offset A0h ..................28914.5.34PCI Power Management Control And Status (PMCS)Offset A4h .................29014.5.35Channel Configuration (CCFG)Offset D0h ..............................................29114.5.36Miscellaneous Port Configuration 2 (MPC2)Offset D4h .............................29214.5.37Miscellaneous Port Configuration (MPC)Offset D8h..................................29314.5.38SMI / SCI Status (SMSCS)Offset DCh ...................................................29414.5.39Message Bus Control (PHYCTL_PHYCTL2_IOSFSBCTL)Offset F4h ..............29514.5.40Advanced Error Reporting Capability Header (AECH)Offset 100h...............29614.5.41Uncorrectable Error Status (UES)Offset 104h.........................................29714.5.42Uncorrectable Error Mask (UEM)Offset 108h ..........................................29814.5.43Uncorrectable Error Severity (UEV)Offset 10Ch ......................................29914.5.44Correctable Error Status (CES)Offset 110h ............................................30014.5.45Correctable Error Mask (CEM)Offset 114h..............................................30114.5.46Advanced Error Capabilities and Control (AECC)Offset 118h.....................30214.5.47Header Log (HL_DW1)Offset 11Ch........................................................30214.5.48Header Log (HL_DW2)Offset 120h........................................................30314.5.49Header Log (HL_DW3)Offset 124h........................................................30314.5.50Header Log (HL_DW4)Offset 128h........................................................30314.5.51Root Error Command (REC)Offset 12Ch ................................................30414.5.52Root Error Status (RES)Offset 130h......................................................30414.5.53Error Source Identification (ESID)Offset 134h ........................................305

15.0 10/100 Mbps Ethernet ...........................................................................................30715.1 Signal Descriptions ..........................................................................................30715.2 Features:........................................................................................................30715.3 References......................................................................................................30815.4 Register Map...................................................................................................30915.5 PCI Configuration Registers...............................................................................309

15.5.1 Vendor ID (VENDOR_ID)Offset 0h ........................................................31015.5.2 Device ID (DEVICE_ID)Offset 2h..........................................................31115.5.3 Command Register (COMMAND_REGISTER)Offset 4h..............................31115.5.4 Status Register (STATUS)Offset 6h.......................................................31215.5.5 Revision ID and Class Code (REV_ID_CLASS_CODE)Offset 8h ..................313



15.5.6 Cache Line Size (CACHE_LINE_SIZE)Offset Ch ...................................... 31315.5.7 Latency Timer (LATENCY_TIMER)Offset Dh ........................................... 31315.5.8 Header Type (HEADER_TYPE)Offset Eh ................................................. 31415.5.9 BIST (BIST)Offset Fh ......................................................................... 31415.5.10Base Address Register (BAR0)Offset 10h .............................................. 31515.5.11Cardbus CIS Pointer (CARDBUS_CIS_POINTER)Offset 28h ...................... 31515.5.12Subsystem Vendor ID (SUB_SYS_VENDOR_ID)Offset 2Ch....................... 31615.5.13Subsystem ID (SUB_SYS_ID)Offset 2Eh ............................................... 31615.5.14Expansion ROM Base Address (EXP_ROM_BASE_ADR)Offset 30h.............. 31615.5.15Capabilities Pointer (CAP_POINTER)Offset 34h....................................... 31715.5.16Interrupt Line Register (INTR_LINE)Offset 3Ch ...................................... 31715.5.17Interrupt Pin Register (INTR_PIN)Offset 3Dh ......................................... 31815.5.18MIN_GNT (MIN_GNT)Offset 3Eh .......................................................... 31815.5.19MAX_LAT (MAX_LAT)Offset 3Fh ........................................................... 31815.5.20Capability ID (PM_CAP_ID)Offset 80h................................................... 31915.5.21Next Capability Pointer (PM_NXT_CAP_PTR)Offset 81h ........................... 31915.5.22Power Management Capabilities (PMC)Offset 82h................................... 31915.5.23Power Management Control/Status Register (PMCSR)Offset 84h .............. 32015.5.24PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)Offset 86h ..... 32115.5.25Power Management Data Register (DATA_REGISTER)Offset 87h .............. 32115.5.26Capability ID (MSI_CAP_ID)Offset A0h ................................................. 32215.5.27Next Capability Pointer (MSI_NXT_CAP_PTR)Offset A1h .......................... 32215.5.28Message Control (MESSAGE_CTRL)Offset A2h ....................................... 32215.5.29Message Address (MESSAGE_ADDR)Offset A4h ..................................... 32315.5.30Message Data (MESSAGE_DATA)Offset A8h .......................................... 32315.5.31Mask Bits for MSI (PER_VEC_MASK)Offset ACh...................................... 32415.5.32Pending Bits for MSI (PER_VEC_PEND)Offset B0h .................................. 324

15.6 Memory Mapped Registers................................................................................ 32515.6.1 MAC Configuration Register (Register 0) (GMAC_REG_0)Offset 0h............ 32915.6.2 MAC Frame Filter (Register 1) (GMAC_REG_1)Offset 4h .......................... 33215.6.3 Hash Table High Register (Register 2) (GMAC_REG_2)Offset 8h............... 33415.6.4 Hash Table Low Register (Register 3) (GMAC_REG_3)Offset Ch ............... 33415.6.5 GMII Address Register (Register 4) (GMAC_REG_4)Offset 10h................. 33515.6.6 GMII Data Register (Register 5) (GMAC_REG_5)Offset 14h ..................... 33615.6.7 Flow Control Register (Register 6) (GMAC_REG_6)Offset 18h .................. 33715.6.8 VLAN Tag Register (Register 7) (GMAC_REG_7)Offset 1Ch ...................... 33815.6.9 Version Register (Register 8) (GMAC_REG_8)Offset 20h ......................... 33915.6.10Debug Register (Register 9) (GMAC_REG_9)Offset 24h........................... 34015.6.11Interrupt Register (Register 14) (GMAC_REG_14)Offset 38h.................... 34115.6.12Interrupt Mask Register (Register 15) (GMAC_REG_15)Offset 3Ch ........... 34215.6.13MAC Address0 High Register (Register 16) (GMAC_REG_16)Offset 40h ..... 34315.6.14MAC Address0 Low Register (Register 17) (GMAC_REG_17)Offset 44h...... 34315.6.15MMC Control Register (Register 64) (GMAC_REG_64)Offset 100h............. 34415.6.16MMC Receive Interrupt Register (MMC_INTR_RX)Offset 104h .................. 34515.6.17MMC Transmit Interrupt Register (MMC_INTR_TX)Offset 108h ................. 34715.6.18MMC Receive Interrupt Mask Register (MMC_INTR_MASK_RX)Offset 10Ch 34915.6.19MMC Transmit Interrupt Mask Register (MMC_INTR_MASK_TX)Offset 110h 35115.6.20MMC Transmit Good Bad Octet Counter Register

(TXOCTETCOUNT_GB)Offset 114h........................................................ 35315.6.21MMC Transmit Good Bad Frame Counter Register

(TXFRAMECOUNT_GB)Offset 118h ....................................................... 35315.6.22MMC Transmit Broadcast Good Frame Counter Register

(TXBROADCASTFRAMES_G)Offset 11Ch................................................ 35415.6.23MMC Transmit Multicast Good Frame Counter Register

(TXMULTICASTFRAMES_G)Offset 120h ................................................. 354



15.6.24MMC Transmit 64 Octet Good Bad Frame Counter Register(TX64OCTETS_GB)Offset 124h ............................................................355

15.6.25MMC Transmit 65 to 127 Octet Good Bad Frame Counter Register (TX65TO127OCTETS_GB)Offset 128h ...................................................355

15.6.26MMC Transmit 128 to 255 Octet Good Bad Frame Counter Register (TX128TO255OCTETS_GB)Offset 12Ch .................................................356

15.6.27MMC Transmit 256 to 511 Octet Good Bad Frame Counter Register (TX256TO511OCTETS_GB)Offset 130h..................................................356

15.6.28MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Register (TX512TO1023OCTETS_GB)Offset 134h................................................356

15.6.29MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Register (TX1024TOMAXOCTETS_GB)Offset 138h ...............................................357

15.6.30MMC Transmit Unicast Good Bad Frame Counter Register (TXUNICASTFRAMES_GB)Offset 13Ch ...................................................357

15.6.31MMC Transmit Multicast Good Bad Frame Counter Register (TXMULTICASTFRAMES_GB)Offset 140h................................................358

15.6.32MMC Transmit Broadcast Good Bad Frame Counter Register (TXBROADCASTFRAMES_GB)Offset 144h ..............................................358

15.6.33MMC Transmit Underflow Error Frame Counter Register (TXUNDERFLOWERROR)Offset 148h .....................................................359

15.6.34MMC Transmit Single Collision Good Frame Counter Register(TXSINGLECOL_G)Offset 14Ch.............................................................359

15.6.35MMC Transmit Multiple Collision Good Frame Counter Register (TXMULTICOL_G)Offset 150h...............................................................360

15.6.36MMC Transmit Deferred Frame Counter Register (TXDEFERRED)Offset154h...................................................................................................360

15.6.37MMC Transmit Late Collision Frame Counter Register (TXLATECOL)Offset158h...................................................................................................360

15.6.38MMC Transmit Excessive Collision Frame Counter Register(TXEXESSCOL)Offset 15Ch..................................................................361

15.6.39MMC Transmit Carrier Error Frame Counter Register(TXCARRIERERROR)Offset 160h...........................................................361

15.6.40MMC Transmit Good Octet Counter Register (TXOCTETCOUNT_G)Offset164h...................................................................................................362

15.6.41MMC Transmit Good Frame Counter Register (TXFRAMECOUNT_G)Offset168h...................................................................................................362

15.6.42MMC Transmit Excessive Deferral Frame Counter Register (TXEXCESSDEF)Offset 16Ch .........................................................................................363

15.6.43MMC Transmit Pause Frame Counter Register (TXPAUSEFRAMES)Offset170h...................................................................................................363

15.6.44MMC Transmit VLAN Good Frame Counter Register(TXVLANFRAMES_G)Offset 174h ..........................................................364

15.6.45MMC Transmit Oversize Good Frame Counter Register(TXOVERSIZE_G)Offset 178h...............................................................364

15.6.46MMC Receive Good Bad Frame Counter Register(RXFRAMECOUNT_GB)Offset 180h........................................................364

15.6.47MMC Receive Good Bad Octet Counter Register(RXOCTETCOUNT_GB)Offset 184h........................................................365

15.6.48MMC Receive Good Octet Counter Register (RXOCTETCOUNT_G)Offset188h...................................................................................................365

15.6.49MMC Receive Broadcast Good Frame Counter Register (RXBROADCASTFRAMES_G)Offset 18Ch................................................366

15.6.50MMC Receive Multicast Good Frame Counter Register (RXMULTICASTFRAMES_G)Offset 190h .................................................366

15.6.51MMC Receive CRC Error Frame Counter Register (RXCRCERROR)Offset194h...................................................................................................367



15.6.52MMC Receive Alignment Error Frame Counter Register(RXALIGNMENTERROR)Offset 198h...................................................... 367

15.6.53MMC Receive Runt Frame Counter Register (RXRUNTERROR)Offset 19Ch .. 36815.6.54MMC Receive Jabber Error Frame Counter Register

(RXJABBERERROR)Offset 1A0h............................................................ 36815.6.55MMC Receive Undersize Good Frame Counter Register

(RXUNDERSIZE_G)Offset 1A4h............................................................ 36815.6.56MMC Receive Oversize Good Frame Counter Register

(RXOVERSIZE_G)Offset 1A8h.............................................................. 36915.6.57MMC Receive 64 Octet Good Bad Frame Counter Register

(RX64OCTETS_GB)Offset 1ACh ........................................................... 36915.6.58MMC Receive 65 to 127 Octet Good Bad Frame Counter Register

(RX65TO127OCTETS_GB)Offset 1B0h................................................... 37015.6.59MMC Receive 128 to 255 Octet Good Bad Frame Counter Register

(RX128TO255OCTETS_GB)Offset 1B4h................................................. 37015.6.60MMC Receive 256 to 511 Octet Good Bad Frame Counter Register

(RX256TO511OCTETS_GB)Offset 1B8h................................................. 37115.6.61MMC Receive 512 to 1023 Octet Good Bad Frame Counter Register

(RX512TO1023OCTETS_GB)Offset 1BCh............................................... 37115.6.62MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Register

(RX1024TOMAXOCTETS_GB)Offset 1C0h .............................................. 37215.6.63MMC Receive Unicast Good Frame Counter Register (RXUNICASTFRAMES_G)

Offset 1C4h ......................................................................................... 37215.6.64MMC Receive Length Error Frame Counter Register

(RXLENGTHERROR)Offset 1C8h ........................................................... 37215.6.65MMC Receive Out Of Range Error Frame Counter Register

(RXOUTOFRANGETYPE)Offset 1CCh...................................................... 37315.6.66MMC Receive Pause Frame Counter Register (RXPAUSEFRAMES)Offset

1D0h .................................................................................................. 37315.6.67MMC Receive FIFO Overflow Frame Counter Register

(RXFIFOOVERFLOW)Offset 1D4h.......................................................... 37415.6.68MMC Receive VLAN Good Bad Frame Counter Register (RXVLANFRAMES_GB)

Offset 1D8h......................................................................................... 37415.6.69MMC Receive Watchdog Error Frame Counter Register

(RXWATCHDOGERROR)Offset 1DCh ..................................................... 37515.6.70MMC Receive Error Frame Counter Register (RXRCVERROR)Offset 1E0h.... 37515.6.71MMC Receive Control Frame Counter Register (RXCTRLFRAMES_G)Offset

1E4h .................................................................................................. 37615.6.72MMC IPC Receive Checksum Offload Interrupt Mask Register

(MMC_IPC_INTR_MASK_RX)Offset 200h ............................................... 37615.6.73MMC Receive Checksum Offload Interrupt Register

(MMC_IPC_INTR_RX)Offset 208h......................................................... 37815.6.74MMC Receive IPV4 Good Frame Counter Register

(RXIPV4_GD_FRMS)Offset 210h .......................................................... 38015.6.75MMC Receive IPV4 Header Error Frame Counter Register

(RXIPV4_HDRERR_FRMS)Offset 214h................................................... 38115.6.76MMC Receive IPV4 No Payload Frame Counter Register

(RXIPV4_NOPAY_FRMS)Offset 218h ..................................................... 38115.6.77MMC Receive IPV4 Fragmented Frame Counter Register

(RXIPV4_FRAG_FRMS)Offset 21Ch....................................................... 38215.6.78MMC Receive IPV4 UDP Checksum Disabled Frame Counter Register

(RXIPV4_UDSBL_FRMS)Offset 220h ..................................................... 38215.6.79MMC Receive IPV6 Good Frame Counter Register

(RXIPV6_GD_FRMS)Offset 224h .......................................................... 38215.6.80MMC Receive IPV6 Header Error Frame Counter Register

(RXIPV6_HDRERR_FRMS)Offset 228h................................................... 383



15.6.81MMC Receive IPV6 No Payload Frame Counter Register(RXIPV6_NOPAY_FRMS)Offset 22Ch .....................................................383

15.6.82MMC Receive UDP Good Frame Counter Register (RXUDP_GD_FRMS)Offset 230h...................................................................................................384

15.6.83MMC Receive UDP Error Frame Counter Register(RXUDP_ERR_FRMS)Offset 234h ..........................................................384

15.6.84MMC Receive TCP Good Frame Counter Register (RXTCP_GD_FRMS)Offset238h...................................................................................................385

15.6.85MMC Receive TCP Error Frame Counter Register (RXTCP_ERR_FRMS)Offset 23Ch...................................................................................................385

15.6.86MMC Receive ICMP Good Frame Counter Register(RXICMP_GD_FRMS)Offset 240h ..........................................................386

15.6.87MMC Receive ICMP Error Frame Counter Register(RXICMP_ERR_FRMS)Offset 244h.........................................................386

15.6.88MMC Receive IPV4 Good Octet Counter Register(RXIPV4_GD_OCTETS)Offset 250h .......................................................386

15.6.89MMC Receive IPV4 Header Error Octet Counter Register (RXIPV4_HDRERR_OCTETS)Offset 254h................................................387

15.6.90MMC Receive IPV4 No Payload Octet Counter Register (RXIPV4_NOPAY_OCTETS)Offset 258h ..................................................387

15.6.91MMC Receive IPV4 Fragmented Octet Counter Register (RXIPV4_FRAG_OCTETS)Offset 25Ch....................................................388

15.6.92MMC Receive IPV4 UDP Checksum Disabled Octet Counter Register (RXIPV4_UDSBL_OCTETS)Offset 260h ..................................................388

15.6.93MMC Receive IPV6 Good Octet Counter Register(RXIPV6_GD_OCTETS)Offset 264h .......................................................389

15.6.94MMC Receive IPV6 Good Octet Counter Register (RXIPV6_HDRERR_OCTETS)Offset 268h..........................................................................................389

15.6.95MMC Receive IPV6 Header Error Octet Counter Register (RXIPV6_NOPAY_OCTETS)Offset 26Ch..................................................390

15.6.96MMC Receive IPV6 No Payload Octet Counter Register (RXUDP_GD_OCTETS)Offset 270h..........................................................................................390

15.6.97MMC Receive UDP Good Octet Counter Register(RXUDP_ERR_OCTETS)Offset 274h.......................................................390

15.6.98MMC Receive TCP Good Octet Counter Register(RXTCP_GD_OCTETS)Offset 278h ........................................................391

15.6.99MMC Receive TCP Error Octet Counter Register(RXTCP_ERR_OCTETS)Offset 27Ch .......................................................391

15.6.100MMC Receive ICMP Good Octet Counter Register(RXICMP_GD_OCTETS)Offset 280h.......................................................392

15.6.101MMC Receive ICMP Error Octet Counter Register(RXICMP_ERR_OCTETS)Offset 284h .....................................................392

15.6.102VLAN Tag Inclusion or Replacement Register (Register 353)(GMAC_REG_353)Offset 584h..............................................................393

15.6.103VLAN Hash Table Register (Register 354) (GMAC_REG_354)Offset 588h ..39415.6.104Timestamp Control Register (Register 448) (GMAC_REG_448)Offset 700h39415.6.105Sub-Second Increment Register (Register 449) (GMAC_REG_449)Offset

704h...................................................................................................39615.6.106System Time - Seconds Register (Register 450) (GMAC_REG_450)Offset

708h...................................................................................................39615.6.107System Time - Nanoseconds Register (Register 451)

(GMAC_REG_451)Offset 70Ch .............................................................39715.6.108System Time - Seconds Update Register (Register 452) (GMAC_REG_452)

Offset 710h..........................................................................................39715.6.109System Time - Nanoseconds Update Register (Register 453)

(GMAC_REG_453)Offset 714h..............................................................39815.6.110Timestamp Addend Register (Register 454) (GMAC_REG_454)Offset 718h398



15.6.111Target Time Seconds Register (Register 455) (GMAC_REG_455)Offset71Ch .................................................................................................. 399

15.6.112Target Time Nanoseconds Register (Register 456)(GMAC_REG_456)Offset 720h ............................................................. 399

15.6.113System Time - Higher Word Seconds Register (Register 457) (GMAC_REG_457)Offset 724h ............................................................. 400

15.6.114Timestamp Status Register (Register 458) (GMAC_REG_458)Offset 728h 40115.6.115Bus Mode Register (Register 0) (DMA_REG_0)Offset 1000h ................... 40215.6.116Transmit Poll Demand Register (Register 1) (DMA_REG_1)Offset 1004h .. 40415.6.117Receive Poll Demand Register (Register 2) (DMA_REG_2)Offset 1008h.... 40415.6.118Receive Descriptor List Address Register (Register 3) (DMA_REG_3)Offset

100Ch ................................................................................................ 40515.6.119Transmit Descriptor List Address Register (Register 4)

(DMA_REG_4)Offset 1010h................................................................. 40515.6.120Status Register (Register 5) (DMA_REG_5)Offset 1014h........................ 40615.6.121Operation Mode Register (Register 6) (DMA_REG_6)Offset 1018h........... 40915.6.122Interrupt Enable Register (Register 7) (DMA_REG_7)Offset 101Ch.......... 41215.6.123Missed Frame and Buffer Overflow Counter Register (Register 8)

(DMA_REG_8)Offset 1020h................................................................. 41315.6.124Receive Interrupt Watchdog Timer Register (Register 9)

(DMA_REG_9)Offset 1024h................................................................. 41415.6.125AHB Status Register (Register 11) (DMA_REG_11)Offset 102Ch ............. 41415.6.126Current Host Transmit Descriptor Register (Register 18)

(DMA_REG_18)Offset 1048h ............................................................... 41515.6.127Current Host Receive Descriptor Register (Register 19)

(DMA_REG_19)Offset 104Ch............................................................... 41515.6.128Current Host Transmit Buffer Address Register (Register 20)

(DMA_REG_20)Offset 1050h ............................................................... 41615.6.129Current Host Receive Buffer Address Register (Register 21) (DMA_REG_21)

Offset 1054h ....................................................................................... 41615.6.130HW Feature Register (Register 22) (DMA_REG_22)Offset 1058h............. 417

16.0 USB 2.0 ................................................................................................................. 42116.1 Signal Descriptions .......................................................................................... 42116.2 Features ........................................................................................................ 421

16.2.1 USB2.0 Host Controller Features ............................................................ 42116.2.2 USB2.0 Device Features ........................................................................ 422

16.3 References ..................................................................................................... 42216.4 Register Map .................................................................................................. 42316.5 PCI Configuration Registers .............................................................................. 423

16.5.1 USB Device ......................................................................................... 42316.5.1.1 Vendor ID (VENDOR_ID)Offset 0h .......................................... 42416.5.1.2 Device ID (DEVICE_ID)Offset 2h ............................................ 42516.5.1.3 Command Register (COMMAND_REGISTER)Offset 4h ................ 42516.5.1.4 Status Register (STATUS)Offset 6h......................................... 42616.5.1.5 Revision ID and Class Code (REV_ID_CLASS_CODE)Offset 8h .... 42616.5.1.6 Cache Line Size (CACHE_LINE_SIZE)Offset Ch ......................... 42716.5.1.7 Latency Timer (LATENCY_TIMER)Offset Dh .............................. 42716.5.1.8 Header Type (HEADER_TYPE)Offset Eh ................................... 42816.5.1.9 BIST (BIST)Offset Fh ............................................................ 42816.5.1.10Base Address Register (BAR0)Offset 10h ................................. 42916.5.1.11Cardbus CIS Pointer (CARDBUS_CIS_POINTER)Offset 28h......... 42916.5.1.12Subsystem Vendor ID (SUB_SYS_VENDOR_ID)Offset 2Ch ......... 43016.5.1.13Subsystem ID (SUB_SYS_ID)Offset 2Eh.................................. 43016.5.1.14Expansion ROM Base Address (EXP_ROM_BASE_ADR)Offset 30h 43016.5.1.15Capabilities Pointer (CAP_POINTER)Offset 34h ......................... 43116.5.1.16Interrupt Line Register (INTR_LINE)Offset 3Ch......................... 43116.5.1.17Interrupt Pin Register (INTR_PIN)Offset 3Dh ........................... 432



16.5.1.18MIN_GNT (MIN_GNT)Offset 3Eh .............................................43216.5.1.19MAX_LAT (MAX_LAT)Offset 3Fh ..............................................43216.5.1.20Capability ID (PM_CAP_ID)Offset 80h......................................43316.5.1.21Next Capability Pointer (PM_NXT_CAP_PTR)Offset 81h ..............43316.5.1.22Power Management Capabilities (PMC)Offset 82h......................43316.5.1.23Power Management Control/Status Register (PMCSR)Offset 84h .43416.5.1.24PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)Offset

86h .......................................................................................43516.5.1.25Power Management Data Register (DATA_REGISTER)Offset 87h .43516.5.1.26Capability ID (MSI_CAP_ID)Offset A0h ....................................43616.5.1.27Next Capability Pointer (MSI_NXT_CAP_PTR)Offset A1h .............43616.5.1.28Message Control (MESSAGE_CTRL)Offset A2h ..........................43616.5.1.29Message Address (MESSAGE_ADDR)Offset A4h ........................43716.5.1.30Message Data (MESSAGE_DATA)Offset A8h .............................43716.5.1.31Mask Bits for MSI (PER_VEC_MASK)Offset ACh.........................43816.5.1.32Pending Bits for MSI (PER_VEC_PEND)Offset B0h .....................438

16.5.2 USB EHCI ............................................................................................43916.5.2.1 Vendor ID (VENDOR_ID)Offset 0h ..........................................44016.5.2.2 Device ID (DEVICE_ID)Offset 2h ............................................44016.5.2.3 Command Register (COMMAND_REGISTER)Offset 4h ................44016.5.2.4 Status Register (STATUS)Offset 6h .........................................44116.5.2.5 Revision ID and Class Code (REV_ID_CLASS_CODE)Offset 8h ....44216.5.2.6 Cache Line Size (CACHE_LINE_SIZE)Offset Ch .........................44216.5.2.7 Latency Timer (LATENCY_TIMER)Offset Dh ..............................44316.5.2.8 Header Type (HEADER_TYPE)Offset Eh ....................................44316.5.2.9 BIST (BIST)Offset Fh ............................................................44316.5.2.10Base Address Register (BAR0)Offset 10h .................................44416.5.2.11Cardbus CIS Pointer (CARDBUS_CIS_POINTER)Offset 28h .........44516.5.2.12Subsystem Vendor ID (SUB_SYS_VENDOR_ID)Offset 2Ch..........44516.5.2.13Subsystem ID (SUB_SYS_ID)Offset 2Eh ..................................44516.5.2.14Expansion ROM Base Address (EXP_ROM_BASE_ADR)Offset 30h.44616.5.2.15Capabilities Pointer (CAP_POINTER)Offset 34h..........................44616.5.2.16Interrupt Line Register (INTR_LINE)Offset 3Ch .........................44616.5.2.17Interrupt Pin Register (INTR_PIN)Offset 3Dh............................44716.5.2.18MIN_GNT (MIN_GNT)Offset 3Eh .............................................44716.5.2.19MAX_LAT (MAX_LAT)Offset 3Fh ..............................................44816.5.2.20Serial Bus Release Number Register (SBRN)Offset 60h ..............44816.5.2.21Frame Length Adjustment Register (FLADJ)Offset 61h ...............44816.5.2.22Capability ID (PM_CAP_ID)Offset 80h......................................44916.5.2.23Next Capability Pointer (PM_NXT_CAP_PTR)Offset 81h ..............44916.5.2.24Power Management Capabilities (PMC)Offset 82h......................44916.5.2.25Power Management Control/Status Register (PMCSR)Offset 84h .45016.5.2.26PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)Offset

86h .......................................................................................45116.5.2.27Power Management Data Register (DATA_REGISTER)Offset 87h .45116.5.2.28Capability ID (MSI_CAP_ID)Offset A0h ....................................45116.5.2.29Next Capability Pointer (MSI_NXT_CAP_PTR)Offset A1h .............45216.5.2.30Message Control (MESSAGE_CTRL)Offset A2h ..........................45216.5.2.31Message Address (MESSAGE_ADDR)Offset A4h ........................45316.5.2.32Message Data (MESSAGE_DATA)Offset A8h .............................45316.5.2.33Mask Bits for MSI (PER_VEC_MASK)Offset ACh.........................45416.5.2.34Pending Bits for MSI (PER_VEC_PEND)Offset B0h .....................45416.5.2.35USB Legacy Support Extended Capability (USBLEGSUP)Offset

C0h.......................................................................................45416.5.2.36USB Legacy Support Control/Status (USBLEGCTLSTS)Offset C4h 455

16.5.3 USB OHCI............................................................................................45716.5.3.1 Vendor ID (VENDOR_ID)Offset 0h ..........................................45816.5.3.2 Device ID (DEVICE_ID)Offset 2h ............................................45816.5.3.3 Command Register (COMMAND_REGISTER)Offset 4h ................45916.5.3.4 Status Register (STATUS)Offset 6h .........................................459



16.5.3.5 Revision ID and Class Code (REV_ID_CLASS_CODE)Offset 8h .... 46016.5.3.6 Cache Line Size (CACHE_LINE_SIZE)Offset Ch ......................... 46116.5.3.7 Latency Timer (LATENCY_TIMER)Offset Dh .............................. 46116.5.3.8 Header Type (HEADER_TYPE)Offset Eh ................................... 46116.5.3.9 BIST (BIST)Offset Fh ............................................................ 46216.5.3.10Base Address Register (BAR0)Offset 10h ................................. 46216.5.3.11Cardbus CIS Pointer (CARDBUS_CIS_POINTER)Offset 28h......... 46316.5.3.12Subsystem Vendor ID (SUB_SYS_VENDOR_ID)Offset 2Ch ......... 46316.5.3.13Subsystem ID (SUB_SYS_ID)Offset 2Eh.................................. 46416.5.3.14Expansion ROM Base Address (EXP_ROM_BASE_ADR)Offset 30h 46416.5.3.15Capabilities Pointer (CAP_POINTER)Offset 34h ......................... 46516.5.3.16Interrupt Line Register (INTR_LINE)Offset 3Ch......................... 46516.5.3.17Interrupt Pin Register (INTR_PIN)Offset 3Dh ........................... 46516.5.3.18MIN_GNT (MIN_GNT)Offset 3Eh............................................. 46616.5.3.19MAX_LAT (MAX_LAT)Offset 3Fh ............................................. 46616.5.3.20Capability ID (PM_CAP_ID)Offset 80h ..................................... 46616.5.3.21Next Capability Pointer (PM_NXT_CAP_PTR)Offset 81h .............. 46716.5.3.22Power Management Capabilities (PMC)Offset 82h ..................... 46716.5.3.23Power Management Control/Status Register (PMCSR)Offset 84h . 46816.5.3.24PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)Offset

86h....................................................................................... 46916.5.3.25Power Management Data Register (DATA_REGISTER)Offset 87h. 46916.5.3.26Capability ID (MSI_CAP_ID)Offset A0h.................................... 46916.5.3.27Next Capability Pointer (MSI_NXT_CAP_PTR)Offset A1h ............ 47016.5.3.28Message Control (MESSAGE_CTRL)Offset A2h .......................... 47016.5.3.29Message Address (MESSAGE_ADDR)Offset A4h ........................ 47016.5.3.30Message Data (MESSAGE_DATA)Offset A8h............................. 47116.5.3.31Mask Bits for MSI (PER_VEC_MASK)Offset ACh ........................ 47116.5.3.32Pending Bits for MSI (PER_VEC_PEND)Offset B0h ..................... 472

16.6 Memory Mapped Registers................................................................................ 47216.6.1 USB Device ......................................................................................... 472

16.6.1.1 IN Endpoint 0 Control Register (ep0_in_ctrl_udc_reg)Offset 0h .. 47516.6.1.2 IN Endpoint 0 Status Register (ep0_in_sts_udc_reg)Offset 4h.... 47616.6.1.3 IN Endpoint 0 Buffer Size Register

(ep0_in_bufsize_udc_reg)Offset 8h ........................................ 47816.6.1.4 IN Endpoint 0 Maximum Packet Size Register

(ep0_in_mpkt_sz_reg)Offset Ch............................................. 47916.6.1.5 IN Endpoint 0 Data Descriptor Pointer Register

(ep0_in_desptr_udc_reg)Offset 14h ....................................... 47916.6.1.6 IN Endpoint 0 Write Confirmation register (for Slave-Only mode)

(ep0_wr_cfrm_udc_reg)Offset 1Ch......................................... 48016.6.1.7 IN Endpoint 1 Control Register (ep1_in_ctrl_udc_reg)Offset 20h 48016.6.1.8 IN Endpoint 1 Status Register (ep1_in_sts_udc_reg)Offset 24h .. 48116.6.1.9 IN Endpoint 1 Buffer Size Register

(ep1_in_bufsize_udc_reg)Offset 28h....................................... 48316.6.1.10IN Endpoint 1 Maximum Packet Size Register

(ep1_in_mpkt_sz_reg)Offset 2Ch ........................................... 48416.6.1.11IN Endpoint 1 Data Descriptor Pointer Register

(ep1_in_desptr_udc_reg)Offset 34h ....................................... 48416.6.1.12IN Endpoint 1 Write Confirmation register (for Slave-Only mode)

(ep1_wr_cfrm_udc_reg)Offset 3Ch......................................... 48516.6.1.13IN Endpoint 2 Control Register (ep2_in_ctrl_udc_reg)Offset 40h 48516.6.1.14IN Endpoint 2 Status Register (ep2_in_sts_udc_reg)Offset 44h .. 48616.6.1.15IN Endpoint 2 Buffer Size Register

(ep2_in_bufsize_udc_reg)Offset 48h....................................... 48816.6.1.16IN Endpoint 2 Maximum Packet Size Register

(ep2_in_mpkt_sz_reg)Offset 4Ch ........................................... 48916.6.1.17IN Endpoint 2 Data Descriptor Pointer Register

(ep2_in_desptr_udc_reg)Offset 54h ....................................... 489



16.6.1.18IN Endpoint 2 Write Confirmation register (for Slave-Only mode) (ep2_wr_cfrm_udc_reg)Offset 5Ch .........................................490

16.6.1.19IN Endpoint 3 Control Register (ep3_in_ctrl_udc_reg)Offset 60h .49016.6.1.20IN Endpoint 3 Status Register (ep3_in_sts_udc_reg)Offset 64h...49116.6.1.21IN Endpoint 3 Buffer Size Register

(ep3_in_bufsize_udc_reg)Offset 68h .......................................49316.6.1.22IN Endpoint 3 Maximum Packet Size Register

(ep3_in_mpkt_sz_reg)Offset 6Ch ...........................................49416.6.1.23IN Endpoint 3 Data Descriptor Pointer Register

(ep3_in_desptr_udc_reg)Offset 74h........................................49416.6.1.24IN Endpoint 3 Write Confirmation register (for Slave-Only mode)

(ep3_wr_cfrm_udc_reg)Offset 7Ch .........................................49516.6.1.25OUT Endpoint 0 Control Register (ep0_out_ctrl_udc_reg)Offset

200h .....................................................................................49516.6.1.26OUT Endpoint 0 Status Register (ep0_out_sts_udc_reg)Offset

204h .....................................................................................49616.6.1.27OUT Endpoint 0 Receive Packet Frame Number Register

(ep0_out_rpf_udc_reg)Offset 208h .........................................49816.6.1.28OUT Endpoint 0 Buffer Size Register (ep0_out_bufsize_udc_reg)

Offset 20Ch ............................................................................49916.6.1.29OUT Endpoint 0 SETUP Buffer Pointer Register

(ep0_subptr_udc_reg)Offset 210h ..........................................49916.6.1.30OUT Endpoint 0 Data Descriptor Pointer Register

(ep0_out_desptr_udc_reg)Offset 214h ....................................50016.6.1.31OUT Endpoint 0 Read Confirmation Register for zero-length OUT

data (for Slave-Only mode) (ep0_rd_cfrm_udc_reg)Offset 21Ch .50016.6.1.32OUT Endpoint 1 Control Register (ep1_out_ctrl_udc_reg)Offset

















(ep3_out_rpf_udc_reg)Offset 268h .........................................516



16.6.1.49OUT Endpoint 3 Buffer Size Register (ep3_out_bufsize_udc_reg)Offset 26Ch ........................................................................... 517

16.6.1.50OUT Endpoint 3 SETUP Buffer Pointer Register(ep3_subptr_udc_reg)Offset 270h.......................................... 517

16.6.1.51OUT Endpoint 3 Data Descriptor Pointer Register (ep3_out_desptr_udc_reg)Offset 274h.................................... 518

16.6.1.52OUT Endpoint 3 Read Confirmation Register for zero-length OUTdata (for Slave-Only mode) (ep3_rd_cfrm_udc_reg)Offset 27Ch. 518

16.6.1.53Device Configuration Register (d_cfg_udc_reg)Offset 400h ........ 51916.6.1.54Device Control Register (d_ctrl_udc_reg)Offset 404h ................ 52016.6.1.55Device Status Register (d_sts_udc_reg)Offset 408h.................. 52216.6.1.56Device Interrupt Register (d_intr_udc_reg)Offset 40Ch ............. 52316.6.1.57Device Interrupt Mask Register (d_intr_msk_udc_reg)Offset

410h..................................................................................... 52416.6.1.58Endpoints Interrupt Register (ep_intr_udc_reg)Offset 414h ....... 52516.6.1.59Endpoints Interrupt Mask Register (ep_intr_msk_udc_reg)Offset

418h..................................................................................... 52516.6.1.60Test Mode Register (test_mode_udc_reg)Offset 41Ch ............... 52616.6.1.61Product Release Number Register (revision_udc_reg)Offset 420h 52716.6.1.62SETUP command address pointer register

(udc_desc_addr_udc_reg)Offset 500h..................................... 52716.6.1.63Physical Endpoint 0 Register (udc_ep_ne_udc_reg_0)Offset 504h52816.6.1.64Physical Endpoint 1 Register (udc_ep_ne_udc_reg_1)Offset 508h52816.6.1.65Physical Endpoint 2 Register (udc_ep_ne_udc_reg_2)Offset

50Ch..................................................................................... 52916.6.1.66Physical Endpoint 3 Register (udc_ep_ne_udc_reg_3)Offset 510h53016.6.1.67Physical Endpoint 4 Register (udc_ep_ne_udc_reg_4)Offset 514h53116.6.1.68Physical Endpoint 5 Register (udc_ep_ne_udc_reg_5)Offset 518h53216.6.1.69Physical Endpoint 6 Register (udc_ep_ne_udc_reg_6)Offset

51Ch..................................................................................... 53216.6.1.70RxFIFO Array[0-511] (udc_rx_fifo_reg_array[0-511])Offset

800h, Count 512, Stride 4h ...................................................... 53316.6.1.71TxFIFO 0 Array[0-255] (udc_tx_fifo_reg_0_array[0-255])Offset

1000h, Count 256, Stride 4h .................................................... 53416.6.1.72TxFIFO 1 Array[0-255] (udc_tx_fifo_reg_1_array[0-255])Offset



1C00h, Count 256, Stride 4h .................................................... 53516.6.2 USB EHCI............................................................................................ 535

16.6.2.1 Host Controller Interface Version Number and Capability Registers Length (HCCAPBASE)Offset 0h............................................... 536

16.6.2.2 Host Controller Structural Parameters (HCSPARAMS)Offset 4h ... 53616.6.2.3 Host Controller Capability Parameters (HCCPARAMS)Offset 8h ... 53816.6.2.4 USB Command (USBCMD)Offset 10h ...................................... 53916.6.2.5 USB Status (USBSTS)Offset 14h ............................................ 54116.6.2.6 USB Interrupt Enable (USBINTR)Offset 18h ............................. 54316.6.2.7 USB Frame Index (FRINDEX)Offset 1Ch .................................. 54416.6.2.8 4 Gigabyte Memory Segment Selector (CTRLDSSEGMENT)Offset

20h....................................................................................... 54516.6.2.9 Periodic Frame List Base Address (PERIODICLISTBASE)Offset

24h....................................................................................... 54516.6.2.10Asynchronous List Address (ASYNCLISTADDR)Offset 28h .......... 54616.6.2.11Configure Flag (CONFIGFLAG)Offset 50h ................................. 54616.6.2.12Port Status/Control[0-1] (PORTSC[0-1])Offset 54h, Count 2,

Stride 4h ............................................................................... 54716.6.2.13Programmable Microframe Base Value (INSNREG00)Offset 90h .. 55016.6.2.14Programmable Packet Buffer OUT/IN Thresholds

(INSNREG01)Offset 94h........................................................ 551



16.6.2.15Programmable Packet Buffer Depth (INSNREG02)Offset 98h ......55116.6.2.16Programmable Controller Settings (INSNREG03)Offset 9Ch ........55216.6.2.17Programmable Controller Settings (INSNREG04)Offset A0h ........55316.6.2.18UTMI Configuration (INSNREG05)Offset A4h ............................554

16.6.3 USB OHCI............................................................................................55516.6.3.1 OHCI Revision (HCREVISION)Offset 0h....................................55616.6.3.2 Host Controller Control (HCCONTROL)Offset 4h ........................55616.6.3.3 Host Controller Command Status (HCCMDSTATUS)Offset 8h ......55716.6.3.4 Host Controller Interrupt Status (HCINTRSTATUS)Offset Ch .......55916.6.3.5 Host Controller Interrupt Enable (HCINTRENABLE)Offset 10h......56016.6.3.6 Host Controller Interrupt Disable (HCINTRDISABLE)Offset 14h ...56116.6.3.7 Host Controller Communication Area (HCHCCA)Offset 18h .........56216.6.3.8 Host Controller Current Isochronous or Interrupt Endpoint

(HCPRDCURED)Offset 1Ch .....................................................56316.6.3.9 Host Controller Current First Control Endpoint (HCCTRLHEADED)

Offset 20h..............................................................................56316.6.3.10Host Controller Current Control Endpoint (HCCTRLCURED)Offset

24h .........

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