Intel Pentium III Processor Low Power/440BX AGPsetapplication-notes.digchip.com/027/27-46183.pdf ·...

Intel® Pentium® III Processor – Low Power/440BX AGPsetDesign Guide

December 2002

Order Number: 273532-002

2 Design Guide

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Copyright © Intel Corporation, 2002

Design Guide 3

Contents

Contents1.0 Introduction .............................................................................................................................11

1.1 Key Terms ..........................................................................................................................111.2 Overview.............................................................................................................................111.3 Related Documents ............................................................................................................13

2.0 Design Features .....................................................................................................................15

2.1 Intel® Pentium® III Processor – Low Power .......................................................................152.2 Intel® 440BX AGPset..........................................................................................................15

2.2.1 System Bus Interface.............................................................................................162.2.2 DRAM Interface .....................................................................................................162.2.3 Accelerated Graphics Port Interface......................................................................162.2.4 PCI Interface..........................................................................................................162.2.5 System Clocking ....................................................................................................16

2.3 PCI ISA IDE Xcelerator (PIIX4E) ........................................................................................17

3.0 System Bus Guidelines.......................................................................................................19

3.1 Definitions ...........................................................................................................................193.2 Recommended Low Power GTL+ Design Guideline ..........................................................22

3.2.1 Components ..........................................................................................................223.2.2 Initial Timing Analysis ............................................................................................223.2.3 Determine General Layout, Routing and Topology................................................243.2.4 Estimate Component to Component Spacing

for Low Power GTL+ Signals .................................................................................253.3 Simulation ...........................................................................................................................26

3.3.1 Overview................................................................................................................263.3.2 Extract Interconnect Information ............................................................................263.3.3 Run Simulations.....................................................................................................26

3.4 Summary of System Design Guidelines .............................................................................273.5 Timing Diagram for Processor Side Bus.............................................................................28

4.0 Memory Guidelines...............................................................................................................29

4.1 100 MHz SDRAM Interface Overview ................................................................................294.1.1 SDRAM Signal Description....................................................................................304.1.2 SDRAM Signal Connectivity ..................................................................................314.1.3 Pin Groups.............................................................................................................314.1.4 Single Set DRAM Interface....................................................................................32

4.2 General SDRAM Layout Guidelines ...................................................................................324.2.1 SO-DIMM Connection to SDRAM..........................................................................32

4.3 Trace Lengths for Three or Two SO-DIMM Designs ..........................................................344.3.1 MD[63:0] Signals ...................................................................................................344.3.2 DQMA[7:0] Signals ................................................................................................354.3.3 Chip Select Signals - CSA[5:0] ..............................................................................364.3.4 Clock Enable Signals - CKE[5:0] ...........................................................................364.3.5 Command Signals - MAB[13:0]x, WEA#, SRASA#, and SCASA ..........................37

4.4 SODIMM DRAM Organization ............................................................................................384.4.1 SDRAM System Examples ....................................................................................39

4.5 SO-DIMM Placement Options ............................................................................................40

4 Design Guide

Contents

5.0 Clocking Guidelines ............................................................................................................. 43

5.1 Clocking System Overview ................................................................................................. 435.2 Clock Synthesizer Pinout and Specifications...................................................................... 445.3 Timing Guidelines ............................................................................................................... 455.4 Host Clock Layout Guidelines............................................................................................. 465.5 SDRAM Clock Layout Guidelines ....................................................................................... 47

5.5.1 General Clocking Guidelines ................................................................................. 475.5.2 SDRAM Clock Layout Guidelines .......................................................................... 485.5.3 DCLKWR Layout Guidelines ................................................................................. 50

5.6 PCI/AGP Clock Layout Guidelines ..................................................................................... 515.7 Clock Vendors .................................................................................................................... 52

6.0 82443BX AGP Interface Guidelines ...............................................................................53

6.1 Layout and Routing Guidelines........................................................................................... 536.1.1 On-board AGP Compliant Device Layout Guidelines ............................................ 54

6.2 ACPI Compliance Requirements ........................................................................................ 556.3 AGP IDSEL Routing ........................................................................................................... 56

7.0 Design Guideline Checklists ............................................................................................57

7.1 Resistor Values................................................................................................................... 577.2 Pentium III Processor – Low Power Design Checklist........................................................ 58

7.2.1 GTL+ Signals .........................................................................................................587.2.2 CMOS Signals ....................................................................................................... 597.2.3 TAP Signals .......................................................................................................... 607.2.4 Clock Signals .........................................................................................................617.2.5 Miscellaneous Signals ........................................................................................... 617.2.6 Power Pins............................................................................................................. 627.2.7 NO CONNECT Pins............................................................................................... 627.2.8 Processor Decoupling Requirements .................................................................... 63

7.3 82443BX Design Checklist ................................................................................................. 637.3.1 Host Interface Signals............................................................................................637.3.2 DRAM (SO-DIMM) Interface Signals ..................................................................... 647.3.3 PCI Interface Signals ............................................................................................. 657.3.4 PCI Sideband Signals............................................................................................657.3.5 AGP Interface Signals ........................................................................................... 667.3.6 Clocks, Resets, and Miscellaneous Signals .......................................................... 677.3.7 Power Management Interface................................................................................ 677.3.8 Reference Pins ...................................................................................................... 687.3.9 82443BX Decoupling Guidelines ........................................................................... 687.3.10 82443BX Strapping Options .................................................................................. 69

7.4 82371EB (PIIX4E) Design Checklist................................................................................... 707.4.1 PCI Interface Signals ............................................................................................. 707.4.2 ISA/EIO Bus Interface Signals...............................................................................717.4.3 X-Bus Interface Signals ......................................................................................... 727.4.4 DMA Signals .......................................................................................................... 727.4.5 Interrupt Controller/APIC Signals........................................................................... 737.4.6 CPU Interface Signals ........................................................................................... 737.4.7 Clocking Signals .................................................................................................... 747.4.8 IDE Signals ............................................................................................................ 757.4.9 USB Signals........................................................................................................... 76

Design Guide 5

Contents

7.4.10 Power Management Signals ..................................................................................777.4.11 Other System and Test Signals .............................................................................787.4.12 Power and Ground Pins.........................................................................................787.4.13 PIIX4E Decoupling Guidelines...............................................................................78

8.0 Power Sequencing ................................................................................................................79

8.1 PIIX4E Power Sequencing .................................................................................................798.1.1 Power Sequencing Requirements .........................................................................798.1.2 Suspend/Resume and Power Plane Control .........................................................798.1.3 System Resume ....................................................................................................828.1.4 System Suspend and Resume Control Signaling ..................................................848.1.5 Power Management State Transition Timings.......................................................91

8.2 82443BX Host Bridge/Controller Power Sequencing .......................................................1048.2.1 Power Sequencing Requirements .......................................................................1048.2.2 Intel® 440BX AGPset Power Management..........................................................104

A Bill of Materials.....................................................................................................................117

B Schematics.............................................................................................................................125

C PLD Code Listing.................................................................................................................155

6 Design Guide

Contents

Figures

1 Intel® Pentium® III Processor – Low Power/440BX AGPset System Block Diagram ............................................................................................................... 12

2 Definition of the Flight Time Criteria - Falling Edge .................................................................... 203 Definition of the Flight Time Criteria - Rising Edge..................................................................... 214 Pentium® III Processor – Low Power General GTL+ Interconnect

and Topology Guidelines............................................................................................................ 245 Processor Routing Example ....................................................................................................... 246 Pentium® III Processor- Low Power Component Placement Example....................................... 257 Processor Side Bus Timing Concepts ........................................................................................ 288 SDRAM Connections.................................................................................................................. 339 MD[63:0] Topology, Three SO-DIMM Sockets ........................................................................... 3410 MD[63:0] Topology, Two SO-DIMM Sockets.............................................................................. 3411 DQMA [7:0] Topology, Three SO-DIMM Sockets....................................................................... 3512 DQMA [7:0] Topology, Two SO-DIMM Sockets .........................................................................3513 CSA [5:0] Topology .................................................................................................................... 3614 CKE[5:0] Topology ..................................................................................................................... 3615 Command Signals Topology, Three SO-DIMM .......................................................................... 3716 Command Signals Topology, Two SO-DIMM............................................................................. 3717 Three SO-DIMM Slots on One Side (First Two Back-to-Back)................................................... 4018 Two SO-DIMM Slots Back-to-Back, Third Slot on the Other Side.............................................. 4019 Two SO-DIMM Slots on One Side, Third Slot on the Other Side ...............................................4120 Two SO-DIMM Slots on One Side, Third Slot on the Other Side

(Alternate Method)......................................................................................................................4121 Clock Connections to the Intel® Pentium® III Processor — Low Power

and 440BX Chipset..................................................................................................................... 4322 Pinout for CK100-M Compatible Clock Synthesizer ................................................................... 4423 Pinout for CKBF-M Compatible Clock Buffer.............................................................................. 4424 Timing Specifications Layout...................................................................................................... 4525 Host Clock Topology .................................................................................................................. 4626 Clocking Layout Diagram ........................................................................................................... 4827 DCLKWR (Figure 16, Variable B2) Guidelines........................................................................... 5028 PCI and AGP Clocking Layout ...................................................................................................5129 On-board AGP Compliant Device Layout Guidelines................................................................. 5430 Signal Layout Recommendations............................................................................................... 5431 Pull-up Resistor Example ........................................................................................................... 5732 External Glue Logic .................................................................................................................... 5933 82443BX Decoupling.................................................................................................................. 6834 VREF Supply Schematic ............................................................................................................ 7935 PIIX4E Power Well Timings........................................................................................................ 8536 RSMRST# and PWROK Timings ............................................................................................... 8537 Suspend Well Power and RSMRST# Activated Signals ............................................................8638 PCI Clock Stop Timing ............................................................................................................... 8739 PCI Clock Start Timing ............................................................................................................... 8740 Core Well Power and PWROK Activated Signals

(RSMRST# Inactive before Core Well Power Applied) .............................................................. 8841 Core Well Power and PWROK Activated Signals

(Core Well Power Applied before RSMRST# Inactive) .............................................................. 8942 Mechanical Off to On.................................................................................................................. 91

Design Guide 7

Contents

43 On to POS ..................................................................................................................................9244 POS to On (with Processor and PCI Reset) ...............................................................................9345 POS to On (with Processor Reset) .............................................................................................9446 POS to On (No Reset) ................................................................................................................9547 On to STR...................................................................................................................................9648 STR to On...................................................................................................................................9849 On to STD/SOff.........................................................................................................................10050 STD/SOff to On.........................................................................................................................10251 REFVCC5 Supply Circuit Schematic ........................................................................................10452 System Power-up Sequencing .................................................................................................10753 Suspend/Resume with PCIRST# Active...................................................................................11354 Suspend/Resume with CPURST#, PCIRST# Inactive .............................................................11455 Suspend/Resume with CPURST# Active, PCIRST# Inactive...................................................11556 Suspend/Resume from STD.....................................................................................................116

8 Design Guide

Contents

Tables

1 Related Intel Documents ............................................................................................................ 132 Related Specifications ................................................................................................................133 Summary of Board Design Guidelines ....................................................................................... 274 SDRAM Signal Descriptions....................................................................................................... 305 SDRAM Signals and Corresponding SO-DIMM Pins ................................................................. 316 82443BX SDRAM Signals and Corresponding Onboard SDRAM Signals................................. 317 MD[63:0] Topology, Three SO-DIMM Sockets - Section Tolerances .........................................348 MD[63:0] Topology, Two SO-DIMM Sockets - Section Tolerances............................................ 359 DQMA [7:0] Topology, Three SO-DIMM Sockets, Section Tolerances ...................................... 3510 DQMA [7:0] Topology, Two SO-DIMM Sockets - Section Tolerances ....................................... 3511 CSA[5:0] Topology - Section Tolerances ................................................................................... 3612 CKE[5:0] Topology - Section Tolerances ................................................................................... 3613 Command Signals Topology, Three SO-DIMM - Section Tolerances ........................................ 3714 Command Signals Topology, Two SO-DIMM - Section Tolerances........................................... 3715 SODIMM DRAM Organization.................................................................................................... 3816 SDRAM System Examples.........................................................................................................3917 Timing Specifications for Maximum and Minimum Clock Skews................................................ 4518 Host Clock Trace Length Guidelines .......................................................................................... 4619 SDRAM Clocks and DCLK Trace Lengths ................................................................................. 4920 DCLKWR Guidelines - Section Tolerances ................................................................................ 5021 PCI and AGP Clock Trace Length.............................................................................................. 5122 Clock Vendors ............................................................................................................................ 5223 Data and Associated Strobe....................................................................................................... 5324 Motherboard Recommendations ................................................................................................ 5425 Control Signal Line Length Recommendations .......................................................................... 5526 GTL+ Signals.............................................................................................................................. 5827 CMOS Signals ............................................................................................................................ 6028 Clock Signals.............................................................................................................................. 6129 Miscellaneous Signals ................................................................................................................6130 Power Pins ................................................................................................................................. 6231 NO CONNECT Pins ................................................................................................................... 6232 Host Interface Signals ................................................................................................................6333 DRAM (SO-DIMM) Interface Signals.......................................................................................... 6434 PCI Interface Signals.................................................................................................................. 6535 PCI Sideband Signals................................................................................................................. 6536 AGP Interface Signals ................................................................................................................6637 Clocks, Resets, and Miscellaneous Signals ...............................................................................6738 Power Management Interface .................................................................................................... 6739 Reference Pins ........................................................................................................................... 6840 82443BX Strapping Options ....................................................................................................... 6941 PCI Interface Signals.................................................................................................................. 7042 ISA/EIO Bus Interface Signals.................................................................................................... 7143 X-Bus Interface Signals .............................................................................................................. 7244 DMA Signals............................................................................................................................... 7245 Interrupt Controller/APIC Signals ............................................................................................... 7346 CPU Interface Signals ................................................................................................................7347 Clocking Signals ......................................................................................................................... 7448 IDE Signals................................................................................................................................. 75

Design Guide 9

Contents

49 USB Signals................................................................................................................................7650 Power Management Signals.......................................................................................................7751 Other System and Test Signals ..................................................................................................7852 Power and Ground Pins..............................................................................................................7853 Power State Decode...................................................................................................................8154 Resume Events Supported In Different Power States................................................................8255 Resume Event Programming Model...........................................................................................8356 Power Plane Control...................................................................................................................8457 Power Plane Control Using SUS[C:A]# Signals .........................................................................8458 PIIX4E Power Well Timing Tolerances.......................................................................................8559 RSMRST# and PWROK Timing Tolerance ................................................................................8560 Suspend Well Power and RSMRST# Timing Tolerances...........................................................8661 Core Well Power and PWROK Timing Tolerances.....................................................................8862 Core Well Power and PWROK Timing .......................................................................................9063 Mechanical Off to On Timing Tolerances ...................................................................................9164 On to POS Timing Tolerances....................................................................................................9265 POS to On Timing Tolerances....................................................................................................9366 POS to On (with Processor Reset) Timing Tolerances ..............................................................9467 POS to On (No Reset) Timing ....................................................................................................9568 On to STR Timing Tolerances ....................................................................................................9769 STR to On Timing Tolerances ....................................................................................................9970 On to STD/SOff Timing Tolerances ..........................................................................................10171 STD/SOff to On Timing Tolerances ..........................................................................................10372 System-wide Low-power Modes...............................................................................................10573 System Power-up Sequencing Tolerances...............................................................................10874 Suspend Resume Events And Activities...................................................................................10975 Intel® 440BX AGPset Signal States During POS and STR Modes ..........................................11076 Suspend/Resume Timing Tolerances.......................................................................................11277 Bill of Materials .........................................................................................................................117

10 Design Guide

Contents

Revision History

Date Revision Description

December 2002 002

Section 7.3.3, PLOCK# - In Pin Connection description, removed reference to PIIX4E in the second sentence.

Section 7.3.5, Introductory bullet - Revised to state “To disable AGP, tie MAB9# high using a 10 K ohm pull-up to 3.3 V, connect GCLKO to GCLKIN through an 18 W resistor, and ground AGPREF.

Section 7.3.6, DCLKWR - Revised Pin Connection description to state “22 Ω series termination at CKBFM. ‘T’ at the 22 Ω resistor with 15 pF cap to Vss.”

Section 7.3.6, GCLKIN, Revised Pin Connection description to state “Connect to GCLKO through 18 Ω series resistor.”

Section 7.4.5, IRQ [3:7, 9:11, and 14:15] - In Pin Connection description, added comma between 3:7 and 9:11.

Section 7.4.5, PIRQ[A:D]# - In Pin Connection description, removed reference to 82443BX.

Section 7.4.7, CLK48 - In Pin Connection description, added second sentence to state “When not using USB, the may be connected to GND.”

Section 7.4.10, PCIREQ[A:D] - In Pin Connection description, added second sentence to state “Connect to 82443BX and PCI slots.”

Section 7.4.10, RSMRST# - Added sentence to Pin Connection description to state “When not using power management (suspend modes), this may be connected to PIIX4E PWROK.

Section 7.4.10, Vss (USB) - Removed reference as it is duplicated.

Section 7.4.11, PWROK - Revised second sentence in Pin Connection description to state “When not using power management (suspend modes), also connect to PIIX4E RSMRST#.”

Section 7.4.11, SPKR - Added sentence to Pin Connection description to state “NO CONNECT if not used.”

Section 4.1.1 - Changed note for MAB[13] from Note #1 to Note #2.

August 2001 001 Initial release of this document.

Intel® Pentium® III Processor – Low Power/440BX AGPset

Design Guide 11

1.0 Introduction

This document provides design guidelines for developing systems based on the Intel® Pentium® III processor – Low Power in a BGA2 package and the Intel® 440BX AGPset. System board and memory subsystem design guidelines are included. Special design recommendations and concerns are presented. Likely design errors have been listed here in a checklist format. These are recommendations only. It is recommended that you perform your own simulations to meet design-specific requirements.

Note: These guidelines also apply to the Intel® Celeron® processor – Low Power in a BGA2 package.

1.1 Key Terms

The Pentium® III processor – Low Power is specific to the applied computing market segment. A complete description of the processor is located in the Intel® Pentium® III Processor – Low Power Datasheet (order number 273500).

Intel 440BX AGPset refers to both the 82443BX Host Bridge/Controller and the 82371EB PCI ISA IDE Xcelerator.

82443BX refers to the Intel 82443BX Host Bridge/Controller.

PIIX4E refers to the Intel 82371EB PCI ISA IDE Xcelerator.

Design Features are items that allow the designer to fully use the capabilities of the Pentium III processor and the Intel 440BX AGPset.

Design Checklists are items which provide recommendations for designing an Pentium III processor – Low Power-based platform.

Design Considerations are items that should be considered but may not be applicable to your design.

1.2 Overview

A Pentium III processor – Low Power/440BX AGPset system contains the features summarized below. Figure 1 is a block diagram of a typical Pentium III processor – Low Power/440BX AGPset system design.

• Full support for the Pentium® III processor – Low Power with system bus frequency of 100 MHz

• Intel 440BX AGPset

— 82443BX Host Bridge/Controller (443BX)

— 82371EB PCI ISA IDE Accelerator (PIIX4E)

• 100 MHz memory interface: A wide range of DRAM support including:

— 64-bit memory data interface plus eight ECC bits and hardware scrubbing

— 100 MHz SDRAM Support

— 64-Mbit and 128-Mbit DRAM technologies


12 Design Guide

• Five PCI masters

— PCI Specification Rev 2.1 Compliant

• Accelerated Graphics Port (AGP) Slot:

— AGP Interface Specification Revision 1.0 compliant

— AGP - 66/133 MHz, 3.3 V device support

• Integrated IDE controller with Ultra DMA/33 support

— PIO Mode 4 transfers

— PCI IDE bus master support

• Integrated Universal Serial Bus (USB) controller with two USB ports

• Integrated System Power Management support

Figure 1. Intel® Pentium® III Processor – Low Power/440BX AGPset System Block Diagram

A8984-01

USBUSB

Keyb

oard

BIO

S

Au

dio

Serial P

ort

Parallel P

ort

Flo

pp

y Disc

Infrared

Micro

Co

ntro

ller

AGPEnabledDevice

AGP

3.3 V PCI-0

3.3 V ISA (5 V Tolerant)

3.3 V

100 MHz SDRAM Bus

PCISlots

Bus Master IDEGPIO (30+)

SMBus

Ultra DMA/33 IDE

(33 MHz, 5 V Tolerant)

®

100 MHzGTL+ Processor

Interface

Interface

82443BXHost Bridge/

Controller

492 mBGA

82371EBPIIX4E

324 mBGA

Pentium® III ProcessorLow Power495-BGA2


Design Guide 13

1.3 Related Documents

Table 1. Related Intel Documents

Document Order Number

Intel® Pentium® III Processor – Low Power Datasheet 273500

Mobile Pentium® III Processor Specification Update 245306

Intel® 440BX AGPset: 82443BX Host Bridge/Controller Datasheet 290633

Intel® 440BX AGPset 82443BX Host Bridge/Controller Specification Update 290639

Intel® 82371AB PCI-to-ISA/IDE Xcelerator (PIIX4) Datasheet 290562

Intel® 82371AB PIIX4E, Intel 82371EB PIIX4E and Intel 82371MB PIIX4M Specification Update 297738

Intel® Architecture Software Developer’s Manual, Volume 1; Basic Architecture 243190

Intel® Architecture Software Developer’s Manual, Volume 2; Instruction Set Reference 243191

Intel® Architecture Software Developer’s Manual, Volume 3; System Programming Guide 243192

Intel® Architecture MMX™ Technology Developer’s Guide 243006

Low Power Module SDRAM DIMM Routing Guidelines 273317

CK97 Clock Synthesizer Design Guidelines Application Note 243867

AP-485 Intel Processor Identification and the CPUID Instruction Application Note 241618

Pentium® III Processor Active Thermal Management Technology Application Note 273405

Intel® Pentium® III Processor - Low Power Thermal Design Guide 273285

PIIX4 Universal Serial Bus Design Guide and Checklist NDA†

† NDA documents are only available through an Intel Field Sales Representative.

Table 2. Related Specifications

Document URL/Contact

PCI Local Bus Specification, Revision 2.1 http://www.pcisig.com/specs.html

Universal Serial Bus Specification, Revision 1.1 http://www.usb.org/developers/docs.html

AGP Interface Specification, Revision 1.0 http://www.agpforum.org/index.htm

AGP Platform Design Guide, Revision 1.1A http://www.agpforum.org/index.htm

System Management Bus Specification http://www.sbs-forum.org/

66-MHz Unbuffered SDRAM 64-bit (Non-ECC/Parity)144-pin SO-DIMM Specification, Revision 1.0

http://developer.intel.com/technology/memory/sodm1_0.htm

Universal Host Controller Interface (UHCI) Design Guide http://developer.intel.com/design/USB/UHCI11D.htm

http://www.pcisig.com/specs.html

http://www.usb.org/developers/docs.html

http://www.agpforum.org/index.htm

http://www.agpforum.org/index.htm

http://www.sbs-forum.org/

http://developer.intel.com/technology/memory/sodm1_0.htm

http://developer.intel.com/design/USB/UHCI11D.htm


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Design Guide 15

2.0 Design Features

2.1 Intel® Pentium® III Processor – Low Power

The Intel® Pentium® III processor – Low Power is the first of the Pentium III processor family to be offered for the applied computing platform. It is offered in a 495 ball BGA2 package at 400 MHz, 500 MHz and 700 MHz with a processor system bus speed of 100 MHz. It consists of a Pentium III processor core with an integrated 256-Kbyte second-level cache and a 64-bit high-performance host bus. The second-level cache bus complements the host bus by providing critical data faster, improving performance, and reducing total system power consumption. The Pentium III processor – Low Power’s 64-bit wide low power GTL+ host bus is compatible with the Intel® 440BX AGPset and provides a glueless, point-to-point interface for an I/O bridge and memory controller.

2.2 Intel® 440BX AGPset

The Intel® 440BX AGPset is based on the Pentium III processor architecture. It interfaces with the Pentium III processor’s system bus at 100 MHz. Along with its Host-to-PCI bridge interface, the 82443BX Host Bridge/Controller has been optimized with a 100 MHz SDRAM memory controller and data path unit. The 82443BX also features the Accelerated Graphics Port (AGP) interface. The 82443BX component includes the following functions and capabilities:

• 64-bit Low Power GTL+ based system data bus interface

• 32-bit system address bus support

• 64-bit main memory interface with optimized support for SDRAM

• 32-bit PCI bus interface with integrated PCI arbiter

• AGP interface with up to 133 MHz data transfer capability

• Extensive data buffering between all interfaces for high throughput and concurrent operations

Figure 1 shows a block diagram of a typical platform based on the 440BX AGPset. The 82443BX system bus interface supports a Pentium III processor at a bus frequency of 100 MHz. The physical interface design is based on the Low Power GTL+ specification and is compatible with the Intel 440BX AGPset. The 440BX provides an optimized 72-bit DRAM interface (64-bit Data plus ECC). This interface supports 3.3 V DRAM technologies.

The 82443BX is designed to support the PIIX4E PCI-to-ISA bridge. The PIIX4E is a highly-integrated multifunctional component that supports the following functions and capabilities:

• PCI Revision 2.1 compliant PCI-to-ISA bridge with support for 33 MHz PCI operations

• ACPI Power Management support

• Enhanced DMA controller, interrupt controller and timer functions

• Integrated IDE controller with Ultra DMA/33 support

• USB host interface with support for two USB ports

• System Management Bus (SMB) with support for DIMM Serial Presence Detect


16 Design Guide

2.2.1 System Bus Interface

The 82443BX supports a maximum of 4 Gbytes of memory address space from the processor perspective. The largest address size is 32 bits. The 82443BX provides bus control signals and address paths for transfers between the processor bus, PCI bus, Accelerated Graphics Port and main memory. The 82443BX supports a 4-deep-in-order queue, which provides support for pipelining of up to four outstanding transaction requests on the system bus. The Pentium III processor supports a second-level cache. All cache-control logic is provided on the processor.

For system bus-to-PCI transfers, the addresses are either translated or directly forwarded on the PCI bus, depending on the PCI address space being accessed. When the access is to a PCI configuration space, the processor I/O cycle is mapped to a PCI configuration space cycle. When the access is to a PCI I/O or memory space, the processor address is passed without modification to the PCI bus. Certain memory address ranges are dedicated for a graphics memory address space. When this space or a portion of it is mapped to main DRAM, the address is translated by the AGP address remapping mechanism and the request is forwarded to the DRAM subsystem. A portion of the graphics aperture may be mapped on the AGP, and the corresponding system bus cycles accessing that range are forwarded to the AGP without any translation. The AGP address map defines other system bus cycles that are forwarded to the AGP.

2.2.2 DRAM Interface

The 82443BX integrates a main memory controller that supports a 64-bit DRAM interface which operates at 100 MHz. The integrated DRAM controller features include:

• 3.3 V interface

• Support for up to three double-sided SODIMMs

— 384 Mbytes using 128-Mbit technology



• Support for ECC with hardware scrubbing

2.2.3 Accelerated Graphics Port Interface

The 82443BX supports an AGP interface. The AGP interface has a maximum theoretical transfer rate of ~532 Mbytes/s.

2.2.4 PCI Interface

The 82443BX PCI interface operates at 3.3 V (5 V tolerant), 33 MHz, is Revision 2.1 compliant, and supports up to five external PCI bus masters in addition to the PIIX4E I/O bridge.

2.2.5 System Clocking

Used with the Pentium® III processor, the 82443BX operates the system bus interface at 100 MHz, the PCI bus at 33 MHz and the AGP at a transfer rate of 66/133 MHz. The 82443BX clocking scheme uses an external clock synthesizer that produces reference clocks for the system bus and PCI interfaces. The 82443BX generates the AGP and DRAM clock signals. Please refer to the CK97 Clock Synthesizer/Design Guidelines Application Note (order number 243867).


Design Guide 17

2.3 PCI ISA IDE Xcelerator (PIIX4E)

The PCI ISA IDE Xcelerator (PIIX4E) is a multi-function PCI device that implements a PCI-to-ISA bridge function, a PCI IDE function, a Universal Serial Bus host/hub function, and an Enhanced Power Management function. Because it is a PCI-to-ISA bridge, the PIIX4E integrates many common I/O functions found in ISA-based PC systems; a seven channel DMA Controller, two 82C59 Interrupt Controllers, an 8254 Timer/Counter, and a Real Time Clock. In addition to DMA Compatible transfers, each DMA channel also supports Type F transfers.

The PIIX4E contains full support for PC/PCI and Distributed DMA protocols that implement PCI-based DMA. The Interrupt Controller has edge or level sensitive programmable inputs. Chip select decoding is provided for a BIOS, Real Time Clock, Keyboard Controller, second external microcontroller, and two Programmable Chip Selects. The PIIX4E provides full Plug-and-Play compatibility. The PIIX4E may be configured as a subtractive decode bridge or as a positive decode bridge.

The PIIX4E supports two IDE connectors. This provides an interface for IDE/EIDE hard disks and CD-ROMs. Up to four IDE devices may be supported in Bus Master mode. The PIIX4E contains support for Ultra DMA/33 compatible synchronous DMA devices.

The PIIX4E contains a Universal Serial Bus (USB) host controller that is Universal Host Controller Interface (UHCI) compatible. The host controller’s root hub has two programmable USB ports.

The PIIX4E supports Enhanced Power Management, including full clock control, device management for up to 14 devices, and suspend and resume logic with Power On Suspend, Suspend to RAM, or Suspend to Disk. The PIIX4E fully supports operating-system-directed power management according to the Advanced Configuration and Power Interface (ACPI) specification. The PIIX4E integrates both a System Management bus (SMBus) host and slave interface for serial communication with other devices.

For more information on the PIIX4E, please refer to the Intel® 82371AB PCI-to-ISA/IDE Xcelerator (PIIX4) Datasheet (order number 290562) and the Intel® 82371AB PIIX4, Intel® 82371EB PIIX4E and Intel® 82371MB PIIX4M Specification Update (order number 297738).


18 Design Guide



Design Guide 19

3.0 System Bus Guidelines

This section provides the guidelines required for the Pentium® III processor – Low Power and 82443BX bus portion of the PCB layout. The guidelines and methodologies do not provide absolute rules. They include recommendations on Processor System Bus (PSB) routing topologies and system board impedance. Even when the guidelines are followed, it is strongly recommended that you run analog simulations using the available I/O buffer models together with layout information extracted from your specific design.

3.1 Definitions

Frequently used abbreviations are defined below:

Aggressor - A network that transmits a coupled signal to another network is called the aggressor network.

Bus Agent - A component or group of components that, when combined, represent a single load on the GTL+ bus.

Corner - Describes how a component performs when all parameters that could impact performance are adjusted to have the same impact on performance. Examples of these parameters include variations in the manufacturing process, the operating temperature, and the operating voltage. The results in performance of an electronic component that may change as a result of this in-clude but are not limited to: clock to output time, output driver edge rate, output drive current, and input drive current. Discussion of the ‘slow’ corner means having a component operating at its slowest, weakest performance. Similar discussion of the ‘fast’ corner means having a component operating at its fastest, strongest performance. Operation or simulation of a com-ponent at its slow corner and fast corner is expected to bind the extremes between slowest, weakest performance and fastest, strongest performance. The component packages, printed circuit boards and electrical connectors also have corner characteristics that effect Pentium III processor-Low Power based system designs.

Crosstalk - The reception on a victim network of a signal imposed by aggressor network(s) through inductive and capacitive coupling between the networks.

Backward Crosstalk - Coupling that creates a signal in a victim network that travels in the opposite direction as the aggressor’s signal.

Even Mode Crosstalk - Coupling from one or more aggressors when all the aggressors switch in the same direction that the victim is switching.

Forward Crosstalk - Coupling that creates a signal in a victim network that travels in the same direction as the aggressor’s signal.

Odd Mode Crosstalk - Coupling from one or more aggressors when all the aggressors switch in the opposite direction that the victim is switching.

Flight Time - The additional delay between the driver and receiver introduced by the printed circuit board interconnects and the component loading effects as compared to the data sheet specifi-cation load. Although the name implies that this is the time required for a signal to travel from one end of the interconnect to the other, a better definition of this term is simply that it is the total delay the layout (interconnects plus loads) adds to the component timings. (This is similar to the usage of the term ‘derating’, but that term fails to acknowledge that transmission line effects are being included in the analysis.) Flight time is therefore defined as the difference between when a signal at the input pin of a receiving agent crosses VREF and the time that the output pin of the driving agent crosses the VREF were it driving the test load used


20 Design Guide

to specify that driver’s AC timings. VREF for the Pentium III processor- Low Power is 2/3 of VCCT. (VCCT = VTT)

Flight time is defined as:

TFLIGHT = TRECEIVER - TREF

where TREF is the reference delay discussed above, and TRECEIVER is the time at which the waveform has a valid VREF crossing.

Figure 2 and Figure 3 show the definition of flight time. Notice that determining flight time requires a minimum of two simulations, one in which the driver is driving the test load, and one in which it is driving the actual system load. Also note that this method introduces the concept of negative flight time, as seen in Figure 3.

Figure 2. Definition of the Flight Time Criteria - Falling Edge


Design Guide 21

Maximum and Minimum Flight Time - Flight time variations may be caused by many different parameters. The more obvious causes include variation of the board dielectric constant, changes in load condition, variation in termination resistance and differences in I/O buffer performance as a function of temperature, voltage and manufacturing process. Some less obvious causes include effects of multiple signals switching and additional packaging affects. Table 4 includes recommended adjustment factors.

Maximum Flight Time – This is the largest flight time a network will experience under all variations of conditions.

Minimum Flight Time - This is the smallest flight time a network will experience under all variations of conditions.

FSB - Front Side Bus, a reference to the GTL+ bus on the front of the Pentium III processor – Low Power, as opposed to the cache or backside bus. This nomenclature is not used in this document. Please see PSB.

GTL+ - The bus technology used by the Pentium III processor – Low Power. This is an incident wave switching, open drain bus with internal pullups at the processor that provide both the high logic level and termination at each processor end of the bus. It is an enhancement to the GTL+(Gunning Transceiver Logic) technology. Refer to the Pentium® II Processor Developer’s Manual for more information.

Low Power GTL+ - A modification of the GTL+ bus technology for use in low power applied computing applications.

Network - The trace of a Printed Circuit Board (PCB) that completes an electrical connection be tween two or more components.

Network Length - The distance between extreme bus agents on the network and does not include the distance connecting the end bus agents to the termination resistors.

Figure 3. Definition of the Flight Time Criteria - Rising Edge


22 Design Guide

Northbridge - The system logic component that interfaces directly to the processor’s PSB.

OEM - Original Equipment Manufacturer.

Overdrive Region - The voltage range, at a receiver, from VREF to VREF + 200 mV for a low to high going signal and VREF to VREF - 200 mV for a high to low going signal.

Overshoot - A voltage amplitude that exceeds the maximum voltage, VIH, level as specified in the component specification.

PSB - Processor System Bus, a reference to the Low Power GTL+ bus on the Pentium III processor – Low Power.

Ringback - The re-crossing of a high or low input logic threshold after it has initially crossed that logic threshold.

Settling Limit - The maximum allowed peak to peak oscillation after a signal has transitioned to the correct logic level as specified in the component specification.

Setup Window - The time between the beginning of Setup to Clock (TSU_MIN) and the clock input.

Undershoot - A voltage amplitude that negatively exceeds the minimum low voltage, VIL level as specified in the component specification.

Victim - A network that receives a coupled crosstalk signal from another network is called the victim network.

3.2 Recommended Low Power GTL+ Design Guideline

The following step-by-step guideline was developed for systems based on one Pentium III processor – Low Power and one 82443BX load. The methodology recommended in this section is based on experience developed at Intel while developing many different Pentium III processor-based systems for validation and feasibility studies. This methodology relies on spreadsheet type calculations for initial timing analysis and performing signal integrity/noise analysis. The analog simulations should be validated after actual systems become available.

3.2.1 Components

The GTL+ PSB is restricted to two agents: the Pentium III processor – Low Power and the 82443BX.

3.2.2 Initial Timing Analysis

An initial timing analysis of the system is required. To complete the timing analysis, values for the clock skew and clock jitter are needed with the component specifications. These values should be sufficient for determining the bounds for system flight times. Equation 1 and Equation 2 are the basis for the timing analysis.

Equation 1. Maximum Frequency

Clock Period ≥ TFLIGHT_MAX + TCO_MAX + TSU_MIN + CLKSKEW + CLKJITTER + TADJ_SU

Equation 2. Hold Time

TCO_MIN + TFLT_MIN ≥ THOLD + CLKSKEW + TADJ_Hold


Design Guide 23

Symbols used in Equation 1 and Equation 2:

TCO_MAX - the maximum clock to output specification.1

TCO_MIN - the minimum clock to output specification.1

TSU_MIN - the minimum required time specified to setup before the clock.1

THOLD - the minimum specified input hold time.

TADJ - an empirical timing adjustment factor that accounts for timing ‘push out’ or ‘pull in’ seen when multiple bits change state at the same time. The factors that contribute to the adjustment factor include crosstalk on the PCB, substrate, and packages, simultaneous switching noise, and edge rate degradation caused by inductance in the ground return path.2 This number is also sometimes called Tsso. The SSO stands for Simultaneous Switching Output. This adjustment is for board SSO, not chip SSO, as chip SSO numbers are included in the Tco specification of the device.

CLKJITTER - the maximum clock edge to edge variation.

CLKSKEW - the maximum variation between components receiving the same clock edge.

TFLT_MAX - the maximum flight time as defined in Section 3.1.

TFLT_MIN - the minimum flight time as defined in Section 3.1.

NOTES:1. The Clock to Output (TCO) and Setup to Clock (TSU) timings are both measured from the signals last crossing

of VREF, with the requirement that the signal does not violate the ringback or edge rate limits. See the Pentium® II Processor Developer’s Manual for more details.

2. TADJ should be calculated for each individual system. A value of 0.5 ns is used throughout this document and may be used as a generic TADJ value during flight time calculations if an actual crosstalk flight time delay may not be calculated.

Solving these equations for flight time results in the following equations:

Equation 3. Maximum Flight Time

TFLIGHT_MAX = Clock Period - TCO_MAX - TSU_MIN - CLKSKEW - CLKJITTER - TADJ_SU

Equation 4. Minimum Flight Time

TFLIGHT_MIN = THOLD + CLKSKEW + TADJ_Hold - TCO_MIN

There are two cases to consider. Note that while the same trace connects two components (e.g., A and B), the minimum and maximum flight time requirements for A driving B as well as B driving A must be met. The cases discussed in this document are:

Pentium III processor – Low Power driving the 82443BX

82443BX driving the Pentium III processor – Low Power

GTL+ trace lengths required to meet these timings may be calculated using the maximum and minimum flight time calculations and the effective board propagation constant (SEFF). SEFF is a function of:


24 Design Guide

Dielectric constant (εr) of the PCB material

The type of trace connecting the components (stripline or microstrip)

The length of the trace and the load of the components on the trace. (Note that the board propagation constant multiplied by the trace length is a component of the flight time but not necessarily equal to the flight time.)

3.2.3 Determine General Layout, Routing and Topology

Once the processor bus components have been selected and the timing budget calculated, then determine their approximate location on the printed circuit board. Estimate the printed circuit board parameters from the placement and other information including the following general layout and routing given below:

General recommendations for Low Power GTL+ bus topology, layout, and routing are given in the following list. Also refer to Figure 4 and Figure 5.

• The net must not exceed 6.0 inches and must exceed 1.5 inches.

• Closely control the characteristic line impedance, Z0 = 55Ω +/- 10%.

• PSB Traces should all be internal traces except for the breakout from the processor or chipset, which should not exceed 75 mils.

• Successive dual-stripline trace layers should be routed orthogonally.

• Trace width and spacing should be at least 4/6. (Trace width and spacing of 4/8 is even better. Do not route 5/5 except as necessary within the area of the processor or chipset.)

• Triple and Quad-stripline stackups are discouraged. When these types of stackups are used, Intel recommends a rigorous post-layout validation of the design including crosstalk analysis.

Figure 4. Pentium® III Processor – Low Power General GTL+ Interconnectand Topology Guidelines

Figure 5. Processor Routing Example

Pentium® III Processor – Low Power

Processor Core 82443BX

1.5 – 6.0 inches

82443BX Pentium® III Processor – Low Power 82443BX Host Bridge/

Controller Pentium® III Processor — Low Power


Design Guide 25

• Route the same type of Low Power GTL+ I/O signals in isolated signal groups. That is, route the data signals in one group, the address signals in another group. Keep at least 12 mils between each group of signals.

• Minimize use of vias.

• Maximum parallel- trace routing length is 3.5 inches (at 4/6).

• Always be sure to validate signal quality after making any changes in agent locations or changes to inter-agent spacing.

• This document addresses Low Power GTL+ layout. Other chassis requirements including cooling, mechanical stability, and memory location may constrain the system topology and component placement location; therefore constraining the board routing. These issues are not directly addressed in this document.

3.2.4 Estimate Component to Component Spacingfor Low Power GTL+ Signals

After determining the general layout, do a more specific preliminary component placement. Estimate the number of layers that will be required. Then determine the expected interconnect distances between the components on the Low Power GTL+ bus. Using the estimated interconnect distances, verify that the placement may support the system timing requirements.

Figure 6 shows one example of a Pentium III processor – Low Power based system component placement.

The maximum network length between the bus agents is determined by the bus frequency and the maximum flight time propagation delay on the PCB. The minimum network length is independent of the required bus frequency. The equations DO NOT allow for any change in the propagation of the signal due to ringback, crosstalk on the network/package, or for any difference in buffer

Figure 6. Pentium® III Processor- Low Power Component Placement Example

PCI Bus

Pentium® III Pocessor–Low Power

GTL+ Bus

Memory Bus

DRAMs

82443BX Host Bridge/ Controller

AGP Bus


26 Design Guide

performance caused by driving actual loaded transmission lines instead of test loads that are used in the component specification. Intel suggests running analog simulations to ensure that each design has adequate noise and timing margin.

After the board layout is complete, extract real trace lengths and run analog simulations to verify the actual layout meets the timing and noise requirements.

3.3 Simulation

3.3.1 Overview

Intel strongly suggests running analog simulations for Pentium III processor – Low Power designs. Intel provides the Pentium III processor – Low Power I/O Buffer Models and the 82443BX I/O Buffer Models in IBIS 2.1 format. These models are available from your local Intel Field Sales Representative. Accurate simulations require that the actual range of parameters be used in the simulations.

Positioning drivers with faster edges closer to the middle of the network results in more noise than positioning them towards the ends. Intel has seen that the worst-case noise margin may be generated by drivers located in all positions (given appropriate variations in the other network parameters). Therefore, stimulating the networks from all driver locations and analyzing each receiver for each possible driver is recommended. Simulate using both values of RTT in the Pentium III processor – Low Power IBIS model.

Faster edge rates cause increased ringback, which reduces the noise margin on the rising edge (Low to High); therefore, only the fast corner (voltage, temperature, and process) I/O buffer model needs to be simulated for the Low to High transitions to evaluate signal quality. Analysis has also shown that both fast and slow models must be run to verify signal quality on the falling edge (High to Low). The fast corner is needed because the fast edge rate creates the most noise. The slow corner is needed because the buffer’s drive capability will be a minimum causing the VOL to shift up, which may cause the noise from the slower edge to exceed the available budget. The slow corner I/O buffer model is used to check the maximum flight time.

The transmission line package models must be inserted between the output of the buffer and the net it is driving. Likewise, the package model must also be placed between a net and the input of a receiver model. This is generally done by editing your simulator's net description or topology file.

3.3.2 Extract Interconnect Information

Extract the actual interconnect information for the board from the CAD layout tools.

3.3.3 Run Simulations

For timing and signal integrity analysis at the Pentium III processor – Low Power connector pins, simulations need to be performed using the fast/slow buffer models, board impedance and the dielectric extreme values, and VTT and RTT extremes. As shown in Equation 3 and Equation 4, both the minimum and maximum lengths need to be simulated.


Design Guide 27

For timing simulations use a VREF voltage of 2/3 VCCT ± 2% for both the Pentium III processor – Low Power and 82443BX. RTT for the Pentium III processor – Low Power is an idealized 50-65Ω internal resistor pulled up to VCCT. Flight times measured from the Pentium III processor- Low Power connector pins to other system components use the standard method of subtracting the reference delay with this load from the delay to the destination component at 2/3 VCCT.

3.4 Summary of System Design Guidelines

A quick summary of the board design guidelines presented in Section 3.0 is shown in Table 3.

• The Pentium III processor – Low Power has on-die RTT. The RESET# signal needs an off-die 56.2Ω ± 1% resistor pulled-up to VCCT.

• The 82443BX GTL+ buffers are programmed for Low Power GTL+ setting (vs. desktop GTL+ choice) by strapping MAB6# high. See the Design Checklist in Section 7.0 for 82443BX strapping options.

Table 3. Summary of Board Design Guidelines

Parameter Value Units

Pentium III processor- Low Power to 82443BX Trace length 1.5 – 6.0 inches

Trace line impedance 55 +/-10% ohms

Trace line width 4 mils

Trace line spacing >= 6 mils

Breakout from Package 75 mils

FR4 dielectric constant 3.9-4.5 n/a

Maximum Parallel Routing 3.5 inches

Traces Internally Routed (Stripline or Dual-Stripline)


28 Design Guide

3.5 Timing Diagram for Processor Side Bus

Figure 7 illustrates the timing concepts for the processor side bus.

Figure 7. Processor Side Bus Timing Concepts

CLK at Driver(Generate)

Tperiod

Signal at Driver Pininto Tester load

Signal at Driver Pininto Actual board trace

Signal atReceiver Pin

Gen N Gen N+1

Bit N

CLK at Receiver(Sample)

Bit N+1

Bit N Bit N+1

Vt

Vt

Vt

TCO_minTCO_max

Tflt_maxTclk_offset

Tsetup

Sampling Bit N

Bit N+1

Tflt_min

Setup/Hold Window

Thold

Tsetup_margin

Thold_margin

Vt


Design Guide 29

4.0 Memory Guidelines

This section lists guidelines to be followed when routing the signal traces for the board design. The order in which signals are routed first and last will vary from designer to designer. Some designers prefer routing the clock signals first, while others prefer routing the high-speed bus signals first. Either order may be used, as long as the guidelines listed here are followed. When the guidelines listed here are not followed, it is very important to simulate the design. Even when the guidelines are followed, it is recommended that you simulate these signals for proper signal integrity, flight time and cross talk.

4.1 100 MHz SDRAM Interface Overview

The 82443BX integrates a main memory DRAM controller that supports a 64-bit or 72-bit (64 bit memory data plus 8 bit ECC) DRAM array for 100 MHz embedded environments. A Pentium® III processor – Low Power/440BX system supports Synchronous DRAM (SDRAM); it does not support EDO memory. The 82443BX DRAM interface runs at 100 MHz. The DRAM controller interface is fully configured through a set of control registers. Complete descriptions of these registers are given in the Intel® 440BX AGPset: 82443BX Host Bridge/Controller Datasheet (order number 290633).

The 443BX supports industry standard 64-bit wide 144-pin SODIMM modules with SDRAM devices. Both symmetric and asymmetric addressing is supported. For write operations of less than a Qword in size, the 443BX will either perform a byte-wide write cycle (non-ECC protected configuration) or a read-modify-write cycle by merging the write data on a byte basis with the previously read data (ECC or error correction configurations). The 82443BX requires SDRAM with CAS latency of 2 (CL2), and supports 1-and 2-row SODIMMs. The 82443BX provides refresh functionality with programmable rates (normal DRAM rate is 1 refresh/15.6 µs). The 82443BX may be configured through the paging policy register to keep multiple pages open within the memory array. Pages may be kept open in all rows of memory. When using two bank SDRAM devices in a particular row, up to two pages may be kept open within that row.

The DRAM interface of the 82443BX is configured by the DRAM control registers, DRAM timing register, SDRAM control register, bits in the NBXCFG register and the eight DRAM row boundary (DRB) registers. The DRAM configuration registers control the DRAM interface to select EDO or SDRAM, RAS timing, and CAS rates. The eight DRB registers define the size of each row in the memory array, enabling the 82443BX to assert the proper CSA[7:0]#, CSB[7:0]# pair for accesses to the array.


30 Design Guide

4.1.1 SDRAM Signal Description

The following sections explain which signals are used in applied computing platforms, and how they should be connected. Note that MAB[13,10] are not inverted because these address bits are used to define various SDRAM commands.

Table 4 identifies the SDRAM signals and the corresponding description.

Table 4. SDRAM Signal Descriptions

Name Type Voltage Description

MECC[7:0]1I/O

CMOSV_3 Memory ECC Data: These signals carry Memory ECC data

during access to DRAM.

CSA[5:0]#O

CMOSV_3 Chip Select (SDRAM): These pins activate SDRAM. SDRAM

accepts any command when its CS# pin is active low.

DQMA[7:0]O

CMOSV_3

Input/Output Data Mask (SDRAM): These pins act as synchronized output enables during a read cycle and as a byte mask during a write cycle.

MAB[9:0]#

MAB[10]2

MAB[12:11]#

MAB[13]2

O

CMOSV_3

Memory Address (SDRAM): This is the row and column address for DRAM. The 443BX Host Bridge system controller has two identical sets of address lines (MAA and MAB#). The recommendations in this design guide are based on the use of only one set of address lines. For additional addressing features, please refer to the Intel® 440BX AGPset: 82443BX Host Bridge/Controller Datasheet (order number 290633).

MWEA#O

CMOSV_3 Memory Write Enable (SDRAM): MWEA# should be used as the

write enable for the memory data bus.

SRASA#O

CMOSV_3

SDRAM Row Address Strobe (SDRAM): When active low, this signal latches Row Address on the positive edge of the clock. This signal also allows Row access and pre-charge.

SCASA#O

CMOSV_3

SDRAM Column Address Strobe (SDRAM): When active low, this signal latches Column Address on the positive edge of the clock. This signal also allows Column access.

CKE[5:0]O

CMOSV_3

SDRAM Clock Enable (SDRAM): The SDRAM clock enable pin. When these signals are deasserted, SDRAM enters power-down mode. Each row is individually controlled by its own clock enable.

MD[63:0]I/O

CMOSV_3 Memory Data: These signals are connected to the DRAM data

bus.

NOTES:1. MECC[7:0] signals on the 82443BX may be left unconnected if the design does not support ECC. For

information regarding DIMM memory designs using ECC, refer to the Intel 440BX AGPset design guide.2. MAB[13,10] signals are not inverted because these address bits are used to define various SDRAM

commands.


Design Guide 31

4.1.2 SDRAM Signal Connectivity

The DRAM expansion socket is a 144-pin SO-DIMM. Table 5 identifies the SDRAM signals and the corresponding SO-DIMM pins. Table 6 identifies the 82443BX SDRAM signals and the corresponding onboard SDRAM signals.

4.1.3 Pin Groups

The 82443BX has multiple copies of many of the signals interfacing to memory. However, the recommendations in this design guide are based on only a single copy of the memory signals. See “Single Set DRAM Interface” on page 32 for more information. The interface consists of the following pins:

Multiple copies:

MAA[13:0], MAB[12:11,9:0]# and MAB[13, 10]CSA[7:0]#, CSB[7:0]#SRASA#, SRASB#SCASA#, SCASB#WEA#, WEB#DQMA[7:0], DQMB[5:1]

Single copies:

CKE[5:0] (for three SODIMM configuration)MD[63:0]MECC[7:0]GCKE (for four DIMM configuration)FENA (FET switch control for four DIMM configuration)

Two CS# lines are provided per row. These are functionally equivalent. The extra copy is provided for loading reasons. The two SRAS#, SCAS# and WE# pins are also functionally equivalent and each copy drives two rows of DRAM. Most pins use programmable strength output buffers. When a row contains 16-Mbit SDRAMs, MAA11 and MAB11# function as Bank Select lines. When a row contains 64-Mbit SDRAMs, MAA[12:11], MAB[12:11] function as Bank Addresses

Table 5. SDRAM Signals and Corresponding SO-DIMM Pins

Signal Name SO-DIMM Pin

MAB[11]# 106

MAB[12]# 70, 110

MAB[13] 72, 112

Table 6. 82443BX SDRAM Signals and Corresponding Onboard SDRAM Signals

Signal Name SDRAM Component Pin

MAB[11]# A13/BA0

MAB[12]# A12/BA1

MAB[13] A11


32 Design Guide

(BA[1:0], or Bank Selects). When the design does not support ECC, you may leave MECC[7:0] unconnected. When the design supports ECC, perform simulations to determine which buffer strength is needed for loading requirements. This may require a BIOS change.

4.1.4 Single Set DRAM Interface

The following two sections explain which signals are used in embedded platforms. Note that MAB[13,10] are not active low because these address bits are used to define various SDRAM commands.

4.1.4.1 SDRAM

Single copies used:

MAB[12:11,9:0]# and MAB[13,10]MD[63:0]MECC[7:0]CSA[5:0]#DQMA[7:0]CKE[5:0]SRASA#SCASA#WEA#

4.2 General SDRAM Layout Guidelines

The following list identifies the SDRAM layout guidelines:

1. To obtain the most advantageous system electronics board layout, byte lanes may be swapped. Bits within a byte lane may also be swapped. However, bits between byte lanes may not be swapped.

2. A system electronics board nominal trace width should have an impedance of 55 Ω ± 10%. Impedance of a nominal trace width is a key parameter specified to board fabricators. Typically, nominal trace width is constrained by design density, the substrate material, and the board fabrication process. Common trace widths are 4 mils, 5 mils, and 6 mils.

3. All resistors should have a maximum ± 5% tolerance.

4. Populate the furthest SO-DIMM first to avoid stub reflections.

5. Any onboard memory should replace the furthest SO-DIMM socket.

6. Place onboard DRAM and SO-DIMM connectors as near as possible to each other.

7. CKBF-M should be powered by V_3 (the 3.3 V rail power supply which remains on during Suspend).

4.2.1 SO-DIMM Connection to SDRAM

Guidelines for the following memory configurations are provided: three SO-DIMM sockets, two SO-DIMM sockets, or two SO-DIMM sockets with onboard memory. For memory configurations with onboard memory, the onboard memory routing may be treated as a third SO-DIMM. For


Design Guide 33

example, the onboard memory is routed to a place on the board where a third SO-DIMM connector would otherwise be placed. In this document, the space is identified as a ‘virtual’ SO-DIMM connector. See Figure 8 for more detail.

The ‘virtual’ SO-DIMM connector is not a physical component but a design reference point (placeholder).

Figure 8. SDRAM Connections

SO-DIMM2 SO-DIMM1 SO-DIMM0

Intel 82443BX Host Bridge/ Controller

CSA[1:0]# CSA[3:2]# CSA[5:4]#

SRASA#

SCASA#

WEA# DQMA[7:0]

MAB[12:11, 9:0]#, MAB[13, 10] MD[63:0]

CKE[5:4] CKE[3:2] CKE[1:0]

PC-100 SDRAMs

10 Ω

Follow the 66/100 MHz SO-DIMM specification to route the signals

Replace the last slot by onboard memory

Follow the 100-MHz layout and routing guidelines

Virtual Connector


34 Design Guide

4.3 Trace Lengths for Three or Two SO-DIMM Designs

The figures and tables below show the topology, and provide the minimum and maximum trace lengths to the SODIMM connector pads for each signal group in a three or two SO-DIMM design.

4.3.1 MD[63:0] Signals

Figure 9 and Table 7 list the three SO-DIMM socket trace lengths and illustrates the corresponding topology.

Figure 10 and Table 8 list the two SO-DIMM socket trace lengths and illustrates the corresponding topology.

Figure 9. MD[63:0] Topology, Three SO-DIMM Sockets

Table 7. MD[63:0] Topology, Three SO-DIMM Sockets - Section Tolerances

Section Minimum(inches)

Maximum(inches)

L0 0.0 in 1.00 in

L0+L1 1.1 in N/A

L2+L3 0.0 in 2.75 in

L0+L1+L2+L3 1.1 in 4.25 in

L0 L1 L2 L3


SO-DIMM PAD

Figure 10. MD[63:0] Topology, Two SO-DIMM Sockets

L0 L1 L2

82443BX Host Bridge/ Controller SO-DIMM

PAD


Design Guide 35

4.3.2 DQMA[7:0] Signals

Figure 11 and Table 9 list the three SO-DIMM trace lengths and illustrates the corresponding topology.

Figure 12 and Table 10 list the two SO-DIMM trace lengths and illustrates the corresponding topology.

Table 8. MD[63:0] Topology, Two SO-DIMM Sockets - Section Tolerances


Maximum(inches)

L0 0.0 in 1.0 in

L0+L1 1.1 in N/A

L0+L1+L2 1.1 in 6.0 in

Figure 11. DQMA [7:0] Topology, Three SO-DIMM Sockets

Table 9. DQMA [7:0] Topology, Three SO-DIMM Sockets, Section Tolerances


Maximum(inches)

L0 1.0 N/A

L0+L1+L2 1.0 4.0

L0 L1 L2 L3


PAD

Figure 12. DQMA [7:0] Topology, Two SO-DIMM Sockets

Table 10. DQMA [7:0] Topology, Two SO-DIMM Sockets - Section Tolerances


Maximum(inches)

L0 1.0 N/A

L0+L1 1.0 6.0

L0 L1

82443BX Host Bridge/

Controller SO-DIMM PAD


36 Design Guide

4.3.3 Chip Select Signals - CSA[5:0]

Figure 13 and Table 11 list the Chip Select signals and illustrates the corresponding topology.

4.3.4 Clock Enable Signals - CKE[5:0]

Figure 14 and Table 12 list the Clock Enable signals and illustrates the corresponding topology.

Figure 13. CSA [5:0] Topology

Table 11. CSA[5:0] Topology - Section Tolerances


Maximum(inches)

L0 1.0 6.0

L0 82443BX

Host Bridge/ Controller

SO-DIMM PAD

Figure 14. CKE[5:0] Topology

Table 12. CKE[5:0] Topology - Section Tolerances


Maximum(inches)

L0 1.0 6.0

L0 82443BX

Host Bridge/ Controller

SO-DIMM PAD


Design Guide 37

4.3.5 Command Signals - MAB[13:0]x, WEA#, SRASA#, and SCASA

Figure 15 and Table 13 list the three SO-DIMM trace lengths for the command signals and illustrate the corresponding topology.

Figure 16 and Table 14 list the two SO-DIMM trace lengths for the command signals and illustrates the corresponding topology.

Figure 15. Command Signals Topology, Three SO-DIMM

Table 13. Command Signals Topology, Three SO-DIMM - Section Tolerances


Maximum(inches)

L0 1.0 N/A

L0+L1+L2 1.0 6.0

L0 L1 L2


PAD

Figure 16. Command Signals Topology, Two SO-DIMM

Table 14. Command Signals Topology, Two SO-DIMM - Section Tolerances


Maximum(inches)

L0 1.0 N/A

L0+L1 1.0 6.0

L0 L1


PAD


38 Design Guide

4.4 SODIMM DRAM Organization

The 144-pin SODIMM (one inch height) has a maximum capacity of eight devices and provides the following configuration possibilities (see Table 15) for SDRAM.

Table 15. SODIMM DRAM Organization

Technology SODIMMOrganization

Component Organization

Devicesper Row

Mbyte per SODIMM

16 Mbit 1 M x 64 / S 1 M x 16 4 8 Mbyte

2 M x 64 / D 1 M x 16 4 16 Mbyte

2 M x 64 / S 2 M x 8 8 16 Mbyte

64 Mbit 2 M x 64 / S 2 M x 32 2 16 Mbyte

4 M x 64 / D 2 M x 32 2 32 Mbyte

4 M x 64 / S 4 M x 16 4 32 Mbyte

8 M x 64 / D 4 M x 16 4 64 Mbyte

8 M x 64 / S 8 M x 8 8 64 Mbyte

128 Mbit 16 M x 64 /S 8 M x 16 4 128 Mbyte

NOTE: ‘S’ denotes single-sided SODIMMs; ‘D’ denotes double-sided SODIMMs.


Design Guide 39

4.4.1 SDRAM System Examples

Table 16 lists five system examples. Each example is based on using three SODIMM sockets or one on-board DRAM and two SODIMM sockets. The terms used in Table 16 are defined below:

144 SODIMM: Number of SODIMM sockets plus on-board DRAMRow: RAS[5:0]# or CS[5:0]# connection. Technology: DRAM technology 16 Mbit, 64 Mbit, 128 MbitDensity/Width: DRAM configuration 16 Mbit: 2 M x 8, or 1 M x 16

64 Mbit: 8 M x 8, 4 M x16, or 2 M x 32128 Mbit: 8 M x 16, or 16 M x 8

# Devices/Row: Number of DRAM components per row.

Table 16. SDRAM System Examples

144SODIMM Row Technology Density x Width # Devices/Row Mbytes per

SODIMM

Example #1

#1 or on-board 0 16 Mbit 2 M x 8 8 16 Mbytes

#21

2

16 Mbit

16 Mbit

1 M x 16

1 M x 16

4

4

8 Mbytes

8 Mbytes

#3 3 16 Mbit 2 M x 8 8 16 Mbytes

Total 4 24 48 Mbytes

Example #2


#2 1 16 Mbit 2 M x 8 8 16 Mbytes

#3 2 16 Mbit 2 M x 8 8 16 Mbytes


Example #3


#2 1 64 Mbit 8 M x 8 8 64 Mbytes

#3 2 64 Mbit 4 M x 16 4 32 Mbytes


Example #4


#2 1 64 Mbit 8 M x 8 8 64 Mbytes

#3 2 64 Mbit 8 M x 8 8 64 Mbytes


Example #5

#1 or on-board 01

128 Mbit128 Mbit

8 M x 168 M x 16

44

64 Mbytes64 Mbytes

#2 23

128 Mbit128 Mbit

8 M x 168 M x 16

44

64 Mbytes64 Mbytes

#3 45

128 Mbit128 Mbit

8 M x 168 M x 16

44

64 Mbytes64 Mbytes



40 Design Guide

4.5 SO-DIMM Placement Options

There are many ways to place the SO-DIMMs on the system electronics. The following diagrams illustrate a few of the possibilities. The dotted outline indicates the SO-DIMM socket is on the other side of the board. In all the configurations, the last SO-DIMM (SODIMM0) slot may be replaced by on-board memory.

Figure 17. Three SO-DIMM Slots on One Side (First Two Back-to-Back)

Figure 18. Two SO-DIMM Slots Back-to-Back, Third Slot on the Other Side

82443BX

Host Bridge

Controller

SODIMM2 SODIMM1 SODIMM0

82443BX

Host Bridge/

Controller

SODIMM2 SODIMM1

SODIMM0


Design Guide 41

Figure 19. Two SO-DIMM Slots on One Side, Third Slot on the Other Side

Figure 20. Two SO-DIMM Slots on One Side, Third Slot on the Other Side (Alternate Method)

Controller

Host Bridge/

82443BX

SODIMM2

SODIMM1

SODIMM0

82443BX

Host Bridge/

Controller

SODIMM2 SODIMM1

SODIMM0


42 Design Guide



Design Guide 43

5.0 Clocking Guidelines

This section lists guidelines to be followed when routing the signal traces for the board design. The order in which signals are routed will vary from designer to designer. Some designers prefer routing all of the clock signals first, while others prefer routing the high-speed bus signals first. Either order may be used, as long as the guidelines listed here are followed. When the guidelines listed here are not followed, it is very important to simulate the design. Even when the guidelines are followed, it is recommended that you simulate signals for proper signal integrity, flight time and cross talk.

5.1 Clocking System Overview

This section provides guidelines and application information for clock layout in a Pentium® III processor – Low Power/440BX AGPset system. These guidelines are based on the HCLK, PCICLK and SDRAMCLK requirements and should be implemented along with the application instructions supplied by your clock chip vendor. Figure 21 shows the clock synthesizer connection to the processor, 82443BX, PIIX4E, and SDRAM.

S

Figure 21. Clock Connections to the Intel® Pentium® III Processor — Low Powerand 440BX Chipset

82443BX

Clock Synthesizer

2.5V 100MHz

3.3V 33MHz

PIIX4E

Free running PCI clock

SDRAM

SDRAM CLOCK

BUFFER

BCLK

HCLKIN DCLK DCLKWR

PCLK

PCLK

BCLK

PCLK

Intel ® Pentium ® III processor -

Low Power


44 Design Guide

5.2 Clock Synthesizer Pinout and Specifications

A clock synthesizer that meets the CK97 Clock Synthesizer Design Guidelines (order number 243867) will meet the requirement for a Pentium III processor – Low Power/440BX AGPset-based system. Table 22 lists clock vendors that provide clock synthesizers which meet the CK97 Clock Synthesizer Design Guidelines.

Note: The CK100-M compatible clock synthesizer operates in multi-voltage mode. The processor clocks operate at 100 MHz at 2.5 V, and the PCI clocks operate at 33 MHz at 3.3 V. The CKBF-M compatible clock buffer provides clocks for SDRAM operating at 100 MHz at 3.3 V. See Figure 22 and Figure 23 for more details.

Figure 22. Pinout for CK100-M Compatible Clock Synthesizer

Figure 23. Pinout for CKBF-M Compatible Clock Buffer

VssrefXTAL_INXTAL_OUT

Vsspci0PCICLK_F

PCICLK1Vddpci0

PCICLK2PCICLK3

Vsspci1

PCICLK4PCICLK5

Vddpci1

Vsscore0Vddcore0

VddrefREF

Vsscpu

CPUCLK0CPUCLK1

Vddcpu

Vddcore1Vsscore1PCISTOP#CPUSTOP#PWRDWN#SELSEL100/66#

1234567891011121314

2827262524232221201918171615

CK100-M

Vdd0Sdram0Sdram1

Vss0

Sdram3Sdram2

Vss1buf in

Vdd1Sdram13Sdram12

Vss4

Vdd4

Sdram14Sdram15

Vss5VddiicSdata

Vdd9

Vss9Vdd8

Vss8OEVdd5

VssiicSclock

1234567891011121314

2827262524232221201918171615

CKBF-M

Sdram16 Sdram17


Design Guide 45

5.3 Timing Guidelines

Figure 24 shows a simplified clocking layout for the timing specifications. See Table 17 for the clock skews.

Figure 24. Timing Specifications Layout

Table 17. Timing Specifications for Maximum and Minimum Clock Skews

Symbol Description CK100-M pin to pin Boards Total

A CPU (BCLK) to82443BX (HCLKIN) skew

0 ps (max) 10 ps (min) 1

250 ps (max) 3-250 ps (min) 3

250 ps (max) 3-250 ps (min) 3

C AGP device (GCLK) to82443BX (HCLKIN) skew N/A 100 ps (max)

-100 ps (min)100 ps (max)- 100 ps (min)

D 82443BX (HCLKIN) toPCI (PCLK) skew

4.0 ns (max.) 21.5 ns (min.)

1.0 ns (max.)0 ns (min.)

5.0 ns (max.)1.5 ns (min.)

E PCI (PCLK) toPCI (PCLK) skew

500 ps (max)-500 ps (min)

1.5 ns (max)-1.5 ns (min)

2.0 ns (max)- 2.0 ns (min)

F DCLKWR toSDRAM (SCLK) skew

250 ps (max)-250 ps (min)

380 ps (max) 4-380 ps (min) 4

630 ps (max)- 630 ps (min)

NOTES:1. In a Pentium® III processor – Low Power based design, use the same clock output pin for both the

82443BX HCLK input and the processor clock input in a ‘T’ signal trace configuration. 2. The 82443BX PCICLK input should lag its HCLK input by a minimum of 1.5 ns to a maximum of 4.0 ns at

the pins of the CK100-M device. An integrated buffer will offer the best control over these output to output drive skews.

3. The total allowable CPU(BCLK) to 82443BX(HCLKIN) skew for the Pentium III processor – Low Poweris ±250 ps.

4. This skew allowance includes ±280 ps for I/O capacitance and SODIMM routing variation. Motherboards should be designed to allow for no more than ±100 ps contribution to the total skew.

82443BX Host Bridge Controller

HCLKIN

Intel ® Pentium ® III processor - Low

Power AGP Device

GCLKO

GCLKIN A C

DCLKO

DCLKWR

Clock Buffer

SDRAM Component

SODIMM

F

Clock Synthesizer

PCLKIN D

PCI Device

PCI Device

E

E


46 Design Guide

Note: .Clock period, jitter, offset and skew are measured on the rising edge of the clock signals at 1.25 V for the 2.5 V clocks and at 1.5 V for the 3.3 V clocks.

5.4 Host Clock Layout Guidelines

The following list provides Host Clock guidelines for a Pentium III processor – Low Power design:

1. The trunk trace length (from clock driver output pin to T-split) may range from 2.0 inches to 4.5 inches, with the entire length at an 8-mil trace width. (8-mil trace width on a layer where a 4-mil trace is nominally 55 Ω.)

2. Clocks must be routed on the same layer internally to contain EMI. Space all other signals at least 2 W from clock traces.

3. A series resistor at the clock driver is 22Ω ±5% tolerance, placed as near to the driver pin as possible (up to 0.5 inches). Intel recommends that the clock series resistors not be placed in the R-packs to allow individual tunability if necessary.

4. Minimize the vias on all clock traces.

5. Do not allow the clock traces to cross a plane split.

NOTE: Table 18 refers to a board where characteristic impedance is nominally 55 Ω ± 10% at 4 mils.

The Host Clock should be routed in an unbalanced ‘T’ topology. Route the branches of the ‘T’ in 4-mil wide traces and route the trunk of the ‘T’ in an 8-mil wide trace. Place the trunk of the ‘T’ such that the Pentium III processor – Low Power branch is equal to the BX branch + 0.877.

Table 18. Host Clock Trace Length Guidelines

Variable Trace Width Minimum Trace Length (inches)

Maximum Trace Length (inches) Resistor

A 8 mil 2.0 in 4.5 in 22 Ω ± 5%

J 4 mil 1.25 in 1.35 in N/A

K 4 mil J + 0.876 in J + 0.878 in N/A

Figure 25. Host Clock Topology

A8986-01

8 mil

A

4 mil

K

4 mil

J

ClockGenerator 82443BX

Host Bridge/Controller

Intel® Pentium® IIIProcessor –Low Power

BCLK

HCLKIN


Design Guide 47

5.5 SDRAM Clock Layout Guidelines

This section defines the clock lengths and series termination for 100-MHz SDRAM clocks.

5.5.1 General Clocking Guidelines

The goal of the SDRAM clock guidelines is to route all SDRAM clock signals as near to the same length as possible, not deviating more than 0.2 inches from maximum to minimum.

The following list provides design considerations for the SDRAM clocks.

1. Series termination resistors are required. Place them as close to the driver pin as possible (within 1 inch).

2. Route all SDRAM clocks and DCLKWR on the same internal layer to provide better trace delay consistency as well as EMI containment.

3. A system electronics board nominal trace width should have an impedance of 55 Ω ± 10%. Impedance of a nominal trace width is a key parameter specified to board fabricators. Typically, nominal trace width is constrained by design density, the substrate material, and the board fabrication process. Common trace widths are 4 mils, 5 mils, and 6 mils.

4. Minimize the use of vias in clock signals.

5. All clocks should have 1:2 width-to-spacing ratio.

6. A zero delay buffer should not be used in place of the CKBF-M.


48 Design Guide

5.5.2 SDRAM Clock Layout Guidelines

Figure 26 shows the SDRAM clock layout guidelines and Table 19 provides the measurement values.

Intel recommends the following guidelines for SDRAM clock trace length design. The terms used in Figure 26 are mathematically defined as follows:

1. SDRAM clock trace lengths should not differ in length from maximum to minimum by more than 0.2 inches. This means that the longest SDRAM clock trace length (B1max) minus the shortest SDRAM clock trace length (B1min) should be within 0.2 inches of each other; B1max - B1min ≤ 0.2 inches.

2. B1nom is an imaginary target nominal SDRAM clock trace length that is centered in length between the maximum and the minimum SDRAM clock lengths.This is defined as:

3. B1= B1nom ± 0.1 inches (maximum = B1nom + 0.1 in, minimum = B1nom - 0.1 in).

4. B2 = DCLKWR = B1nom + 2.5 inches ± 0.1 inches (maximum = B1nom + 2.6 in, minimum = B1nom + 2.4 in).

Figure 26. Clocking Layout Diagram

NOTES:1. B1 represents memory SDRAM clock signals.2. B1max represents the “Maximum” SDRAM clock trace length.3. B1nom represents an imaginary “Nominal” SDRAM clock trace length.4. B1min represents the “Minimum” SDRAM clock trace length.

DCLK0

DCLKWR

B2

82443BX Host

Bridge/ Controller

CKBF-M

D buf_in

“Virtual” Pad

Follow the SO-DIMM Specification

B1

B1

B1

B1min

B1max SO-DIMM 0

SO-DIMM 1

Onboard SDRAM

Onboard SDRAM

Onboard SDRAM

Onboard SDRAM

C1

B1nom

B1nom = B1min +B1max - B1min

2


Design Guide 49

Table 19. SDRAM Clocks and DCLK Trace Lengths

Variable Trace Zo Trace Length (min) Trace Length (max) Resistor

B1nom N/A 0.0 in 0.0 mm 4.0 in 101.6 mm N/A

B1 55 Ω ± 10% B1nom - 0.1 in

B1nom - 2.5 mm B1nom + 0.1 in B1nom + 2.5 mm 10 Ω ± 5%

B2 55 Ω ± 10% B1nom + 2.4 in

B1nom + 61 mm B1nom + 2.6 in B1nom + 66.0 mm 22 Ω ± 5%

D 55 Ω ± 10% 0.0 in 0.0 mm 4.0 in 101.6 mm 18 Ω ± 5%

C1 15 pF ± 5%Use a 0603 package size with an NPO or C0G dielectric and place it within 0.2 inches of the resistor. Route from the resistor pad through the capacitor pad and then into the via going into the system electronics board.


50 Design Guide

5.5.3 DCLKWR Layout Guidelines

Intel recommends that a capacitor be added to the system electronics on the DCLKWR signal. Notebook designers should use a capacitor value that will minimize the skew between the SDRAM clocks and the Intel 82443BX component. The capacitor should be placed no more than 0.2 inches from the 22-Ω series dampening resistor. Intel recommends using the topology shown in Figure 27. This allows the capacitor to be removed from a design without creating an open-ended stub on DCLKWR. See Table 20 for section tolerances.

1. Series matching resistors are required. Placement: As near to the driver pin as possible (within 1 inch).

2. Route all clocks on internal layers to provide better trace delay consistency as well as EMI containment.

3. Board impedance should be 55 Ω ± 10%.

4. Minimize the use of vias in clock signals.

5. All clocks should have 1:2 width to spacing ratio.

Figure 27. DCLKWR (Figure 16, Variable B2) Guidelines

Table 20. DCLKWR Guidelines - Section Tolerances


Maximum(inches)

L1 0.0 1.0

L2 0.0 0.2

L3 N/A N/A

L1+L2+L3 B1nom +2.4 in B1nom +2.6 in

A8985-01

L1

NewCapacitor

Pads

22 ΩCKBF-M

82443BXHost Bridge/

Controller

L2

L3


Design Guide 51

5.6 PCI/AGP Clock Layout Guidelines

Note: Figure 28 assumes AGP and PCI devices are ‘down’ on the motherboard and not on a connector. When designing a board that will use connectors to add AGP or PCI devices, be sure to take into account the trace length already routed on the AGP or PCI card. PCI cards have a PCI CLK trace length of 2.5 inches. AGP cards have an AGP CLK trace length of approximately 3.3 inches.

Figure 28. PCI and AGP Clocking Layout

Table 21. PCI and AGP Clock Trace Length

Variable Trace Width

Minimum Trace Length

Maximum Trace Length Tolerance Resistor

Value

C1 5 mil A+J A+J+4 inch(A+J+101.6 mm) 33 Ω ± 5%

C2 5 mil C1 C1± 4.5 inch

(± 114.3mm) 33 Ω ± 5%

E 10 mil 0 inch(0 mm)

1 inch(25.4 mm) None

F 5 mil 0 inch(0 mm)

8.5 inch(215.9 mm) 18 Ω ± 5%

NOTE: Tolerance refers to the allowed difference in length between multiple traces sharing the same variable name.


CK100-M

3.3V

33M Hz

AGP Device

82371EB PIIX4E

PC

LK

PCICLK_F OTHER PCI DEVICES

C1

C2

E

F

F GCLKO

GCLKIN


52 Design Guide

5.7 Clock Vendors

This vendor list is provided as a service to our customers for reference only. The inclusion of this list should not be considered a recommendation or product endorsement by Intel Corporation.

Table 22. Clock Vendors

Vendor Name Address

International Microcircuits, Inc.

525 Los Coches StreetMilpitas, CA 95035(408) 263-6300http://www.imicorp.com

Integrated Circuit Systems, Inc.

1271 Parkmoor AvenueSan Jose, CA 95126-3448(408) 925-9493http://www.icst.com

Cypress Semiconductor

12020 113th Ave. NortheastKirkland, WA 98034(425) 398-3400http://www.cypress.com

http://www.imicorp.com

http://www.icst.com

http://www.cypress.com


Design Guide 53

6.0 82443BX AGP Interface Guidelines

This section lists guidelines to be followed when routing the signal traces for the board design. Even when the guidelines are followed, it is recommended that you simulate as many signals as possible for proper signal integrity and cross talk. See Section 7.3.5 for AGP pull-up requirements. See Section 5.0, “Clocking Guidelines” on page 43 for AGP clocking information.

6.1 Layout and Routing Guidelines

For the definition of AGP interface functionality (protocols, rules and signaling mechanisms, and the platform level aspects of AGP functionality), refer to the latest AGP Interface Specification and AGP Platform design guide. This document focuses only on specific 440BX platform recommendations for the AGP interface.

Throughout this section the term ‘data’ refers to G_AD[31:0], G_C/BE[3:0]# and SBA[7:0]. The term ‘strobe’ refers to AD_STB[B:A] and SB_STB. When the term ‘data’ is used, it is referring to one of three groups of data as indicated in Table 23. When the term ‘strobe’ is used it is referring to one of the three strobes as it relates to the data in its associated group.

Table 23. Data and Associated Strobe

Data Associated Strobe

G_AD[15:0] and G_C/BE[1:0]# AD_STBA

G_AD[31:16] and G_C/BE[3:2]# AD_STBB

SBA[7:0] SB_STB


54 Design Guide

6.1.1 On-board AGP Compliant Device Layout Guidelines

Longer trace lengths require a greater amount of spacing between traces in order to reduce crosstalk. When using 1:2 spacing, maximum trace length of data lines is 9.5 inches. The line length mismatch is 0.5 inches. The strobe is the longest trace of the group. This restricts the maximum trace length of data lines to less than 4.5 inches for a 1:1 trace spacing. The strobe requires a 1:2 trace spacing. Trace length guidelines given in this section do not reflect signal integrity and EMI. It is recommended that you simulate the routes to ensure that signal quality requirements are met. See Figure 29 for the AGP compliant device layout guidelines and Figure 30 for signal layout recommendations.

6.1.1.1 Data and Strobe Signal Routing Recommendations

The line length mismatch must be less than 0.5 inches and the strobe must be the longest signal of the group. For example, if the strobe is at 4.0 inches, the data line may be from 3.5 to 4.0 inches in length. It is best to reduce the line length mismatch wherever possible to ensure added margin. The strobe is always required to have 1:2 trace spacing. It is also best to separate the traces by as much as possible in order to reduce the amount of trace-to-trace coupling.

Figure 29. On-board AGP Compliant Device Layout Guidelines

Figure 30. Signal Layout Recommendations

Table 24. Motherboard Recommendations

Width:Space Trace Line Length Line Length Matching

1:1(Data)/1:2(Strobe) Data /Strobe 1.0 in < line length < 4.5 in 0.5 in, strobe longest trace

1:2 Data/Strobe 1.0 in < line length < 9.5 in 0.5 in, strobe longest trace


Compliant AGP

Graphics Device

1.0”-4.5” 1:1 Data Routing

Always 1:2 Strobe Routing

1.0”-9.5” 1:2 Data Routing

Always 1:2 Strobe Routing

A D S ig n a ls

A D S ig n a ls

1 :2 A D S t r o b e

1 :1 A D S ig n a ls

1 :1 A D S ig n a ls


Design Guide 55

Note: Under certain layouts, crosstalk and ground bounce may be observed on the AD_STB signals of the AGP interface. Although Intel has not observed system failures due to this issue, noise margin has been improved by enhancing the AGP buffers on the 82443BX. For new designs, additional margin may be obtained by following AGP layout guidelines.

6.1.1.2 Control Signal Routing Recommendations

Some of the control signals require pull-up resistors to be installed on the motherboard. Pull-up resistors should be discrete resistors, since resistor packs will need longer stub lengths and may violate timing requirements. The stub length to these pull-up resistors must be controlled. The maximum stub length on a strobe trace is < 0.1 inch. The maximum stub trace length on all other traces is < 0.5 inch. See Table 25 for control signal line length recommendations. For pull-up recommendations, see “AGP Interface Signals” on page 66.

6.2 ACPI Compliance Requirements

Based on the Advanced Configuration and Power Interface (ACPI) specification, the AGP graphics device must be ACPI compliant and must implement its self power management circuitry, such as self clock-gating and an idle bus detection mechanism to reduce power. However, in a Pentium® III processor-based platform the AGP device clock is a derivative of the host clock.

When the host clock stops (C3 state - Deep Sleep), the AGP clock also stops. An AGP_BUSY# protocol solves this instantaneous AGP stop clock problem. The AGP graphics device must signal the operating system or the south bridge that it is currently busy and the AGP clock should not be stopped.

The AGP device internally protects its core logic to ensure that an illegal clock will not corrupt the AGP device state. This protection gates the internal clock nets used for the device’s logic from the time STP_AGP# is asserted until it is deasserted. The STP_AGP# signal is an indication that the AGP clock will not be valid for much longer and should be gated off for protection. STP_AGP# should be connected to the PIIX4E’s SUS_STAT1# signal.

The AGP_BUSY# signal indicates that the graphics controller requires the GCLK to be running. This signal should be connected to one of the PIIX4E’s PCIREQ# pins. When the PCIREQ# pin must be shared, it may be logically ORed with one of the PIIX4E’s PCIREQ# inputs. AGP_BUSY# is an open-drain signal from the graphics device and requires a 10 KΩ pull-up resistor.

AGP_SUSPEND# is for AGP devices that support Suspend mode. The AGP_SUSPEND# signal may be connected to the PIIX4E’s SUSB# signal.

Table 25. Control Signal Line Length Recommendations

Width:Space Board Trace Line Length Pull-up Stub Length

1:1 Motherboard Control Signals 1.0 in < line length < 8.5 in < 0.5 in (Strobes < 0.1 in)

1:2 Motherboard Control Signals 1.0 in < line length < 10.0 in < 0.5 in (Strobes < 0.1 in)


56 Design Guide

6.3 AGP IDSEL Routing

An AGP compliant master is composed of a PCI compliant target interface and an AGP compliant master interface. (Optionally the device may also include a PCI compliant master interface when required.) When used in a PCI mode of operation, the AGP device must provide an external IDSEL that is connected to AD16. When the AGP device is designed for exclusive operation on the AGP interface the device does not have an external IDSEL pin, therefore IDSEL does not need to be routed.


Design Guide 57

7.0 Design Guideline Checklists

Design checklists provided in this section are intended to be used for schematic reviews of the Pentium® III processor – Low Power/440BX AGPset platform designs. The checklists do not represent the only way to design a system, but do provide recommendations. The system designer should examine the checklist items for correctness. Additional design considerations are also provided.

7.1 Resistor Values

Pull-up and pull-down resister values are system dependent. The appropriate value for your system may be determined from an AC/DC analysis of the pull-up voltage used, the current drive capability of the output driver, input leakage currents of all devices on the signal net, the pull-up voltage tolerance, the pull-up/pull-down resistor tolerance, the input high/low voltage specifications, the input timing specifications (RC rise time), etc. Analysis should be done to determine the minimum and maximum values that may be used on an individual signal. Engineering judgment should be used to determine the optimal value. This determination may include cost concerns, commonality considerations, manufacturing issues, specification and other considerations. See Figure 31 for an example for a pull-up resistor configuration.

A simplistic DC calculation for a pull-up value is:

R MAX = (Vcc PU MIN - V IH MIN) / I Leakage MAX

R MIN = (Vcc PU MAX - V IL MAX) / I OL MAX

Figure 31. Pull-up Resistor Example

VIH MIN

VccPU MIN

RMAX

VIL MAX

VccPU MAX

RMIN

ILeakage MAX

IOLMAX


58 Design Guide

7.2 Pentium III Processor – Low Power Design Checklist

7.2.1 GTL+ Signals

Table 26. GTL+ Signals

CPU Pin Pin Connection

A[35:3]# A[31:3]#: Connect to 82443BX. A[35:32]#: NO CONNECT

ADS# Connect to 82443BX

AERR# NO CONNECT

AP[1:0]# NO CONNECT

BERR# NO CONNECT

BINIT# NO CONNECT

BNR# Connect to 82443BX

BP[3:2]# NO CONNECT

BPM[1:0]# NO CONNECT

BPRI# Connect to 82443BX

BREQ0# Connect to 82443BX pin BREQ0#. Optional 10 Ω pull-down to Vss.

D[63:0]# Connect to 82443BX

DBSY# Connect to 82443BX

DEFER# Connect to 82443BX

DEP[7:0] NO CONNECT

DRDY# Connect to 82443BX

HIT# Connect to 82443BX

HITM# Connect to 82443BX

LOCK# Connect to 82443BX

REQ[4:0]# Connect to 82443BX

RESET# Terminate to VCCT with 56.2 Ω 1% resistor / Connect to 82443BX

RP# NO CONNECT

RS[2:0]# Connect to 82443BX

RSP# NO CONNECT

TRDY# Connect to 82443BX


Design Guide 59

7.2.2 CMOS Signals

• FERR# is an open-drain signal from the Pentium III processor – Low Power and must be pulled-up to VCCT with a 1.5 KΩ resistor. In addition to this pull-up, external glue logic is needed to convert the 1.5 V signal to 2.5 V or 3.3 V. Figure 32 illustrates the implementation of the glue logic.

• CMOS open-drain signals should have maximum trace length of five inches. When CMOS undershoot specifications are not met with the recommended pull-ups, stronger pull-ups may be required. Please see the Intel® Pentium® III Processor — Low Power Datasheet (order number 273500) for details on CMOS signal specifications.

• Intel recommends that the PWRGOOD signal from the power supply not be connected directly to logic on the board, without first going through a Schmitt trigger type circuitry to square-off and maintain the signal integrity.

• To enable Quick Start state: Pull-up SLP# pin on the processor to VCCT with a 1.5 KΩ resistor, pull-up MAB10 on 443BX to 3 V with a 10 KΩ resistor, leave SLP# on PIIX4 unconnected.

Figure 32. External Glue Logic

A8987-01

1.5 V

1.5 KΩ

3904

82371EBPIIX4E

Intel®Pentium® IIIProcessor –Low Power

1.5 V

1KΩ

2.5 Vor 3.3 V

10 KΩ

FERR#

FERR#


60 Design Guide

7.2.3 TAP Signals

Table 27. CMOS Signals


A20M# 1.5 KΩ pull-up to VCCT. Connect to PIIX4E.

FERR#1.5 KΩ pull-up to VCCT. Connect to PIIX4E.

For an example of level conversion logic see Figure 32, “External Glue Logic” on page 59

FLUSH# 1.5 KΩ pull-up to VCCT if not used.

IERR# 1.5 KΩ pull-up to VCCT. Connect to error logic. No connect if not used.

IGNNE# 1.5 KΩ pull-up to VCCT. Connect to PIIX4E.

INIT# 1 KΩ pull-up to VCCT. Connect to PIIX4E.

LINT[1]/NMI 1.5 KΩ pull-up to VCCT. Connect to PIIX4E.

LINT[0]/INTR 1.5 KΩ pull-up to VCCT. Connect to PIIX4E.

PICD[1:0] 1 KΩ pull-down to Vss.

PREQ# 1.5 KΩ pull-up to VCCT. Connect to ITP.

PWRGOOD 1.5 KΩ pull-up to 2.5 V. Connect to power sense logic

SLP# 1.5 KΩ pull-up to VCCT. Connect to PIIX4E.

SMI# 270 Ω pull-up to VCCT. Connect to PIIX4E.

STPCLK# 680 Ω pull-up to VCCT. Connect to PIIX4E.


PRDY# 56.2 Ω 1% pull up to VCCT, 240 Ω series resistor to ITP connector

TCK 1 KΩ pull-up to VCCT. 47 Ω series resistor to ITP connector; 1 KΩ pull-down if not used.

TDO 150 Ω pull-up to VCCT. Connect to ITP. No connect if not used

TDI 150 Ω pull-up to VCCT. Connect to ITP; 1 KΩ pull-down if not used.

TMS 1 KΩ pull-up to VCCT. 47 Ω series resistor to ITP connector; 1 KΩ pull-down if not used.

TRST# 1 KΩ pull-down to Vss. Connect to ITP


Design Guide 61

7.2.4 Clock Signals

• Ensure that the clock generation logic is at a 2.5-V level (BCLK and PICCLK) and at a 1.5 V level (TCK) into the Pentium III processor – Low Power.

• Use discrete resistors for the BCLK signals from the CK100M. Do not mix HCLK, and PCLK signals coming from the CK100M device in resistor packs.

7.2.5 Miscellaneous Signals

Table 28. Clock Signals


BCLK Connect to 82443BX HCLKIN and CK100M with 22 Ω series resistor at the CK100M device. See Section 5.0 for clock routing guidelines.

PICCLK 1 KΩ pull-down to Vss.

Table 29. Miscellaneous Signals


BSEL0 1 KΩ pull-up to VCCT.

BSEL1 1 KΩ pull-down to Vss.

EDGCTRLP 110 Ω 1% Pull-down to Vss.

GHI# NO CONNECT

RTTIMPEDP 56.2 Ω 1% pull-down to Vss

TESTHI 1 KΩ pull-up to VCCT.

TESTLO[2:1] 1 KΩ pull-down to Vss.

THERMDC NO CONNECT if not used. Otherwise connect to thermal sensor.

THERMDA NO CONNECT if not used. Otherwise connect to thermal sensor.

VID[4:0] For Voltage Regulator’s (VR) that do not contain internal pull-ups use a 10 KΩ pull-up to 5 V; Connect to VR.


62 Design Guide

7.2.6 Power Pins

7.2.7 NO CONNECT Pins

Table 30. Power Pins


CLKREFBoard divider on V CC2.5 or V CC3.3 to create 1.25 V reference with a 0.1 µF decoupling capacitor. Resistor divider must be created from 1% tolerance resistors. Do not use VCCT as source voltage for this reference.

CMOSREFBoard divider on V CC2.5 or V CC3.3 to create 1.0 V reference with a 0.1 uF decoupling capacitor. Resistor divider must be created from 1% tolerance resistors. Do not use VCCT as source voltage for this reference.

PLL[2:1]Typically a 4.7 µH inductor in series with VCCT is connected to PLL1 then through a series 33µF capacitor to PLL2. Refer to the Intel® Pentium® III Processor – Low Power Datasheet (order number 273500) for more information.

VCC Connect to Voltage Regulator output. For decoupling guidelines see Section 7.2.8

VCCT Connect to Voltage Regulator output. For decoupling guidelines see Section 7.2.8

VREF

V REF = 2/3 VCCT. Create with voltage divider made up of 1 KΩ ± 1% and 2 KΩ ± 1% resistors connected to VCCT. Decouple with 3 (min) 0.1 µF high freq. caps close to processor.

Vss Tie to GND

Table 31. NO CONNECT Pins


NCThe following pins must be left as NO CONNECTS: A15, A16, A17, C14, D8, D14, D16, E15, G2, G4, G5, G18, H3, H4, H5, J5, M4, M5, P3, P4, R2, AA5, AA17, AA19, AC3, AC17, AC20, AD15, AD20

RSVD The following pins must be left as NO CONNECTS: AB19


Design Guide 63

7.2.8 Processor Decoupling Requirements

For a processor operating at 700 MHz and above, the following decoupling is recommended. The processor core power plane (VCc) should have 15 0.68 µF 0603 ceramic capacitors (using X7R dielectric for thermal reasons) placed directly under the package using two vias for power and two vias for ground to reduce the trace inductance. Also to minimize inductance, traces to those vias should be 22mils (in width) from the capacitor pads to match the via-pad size (assuming 22-mil pad size). Twenty-four 2.2 µF 0805, X5R mid frequency decoupling capacitors should be placed around the die as close to the die as flex solution allows.

The system bus buffer power plane (VCCT) should have twenty (20) 0.1-µF high frequency decoupling capacitors around the die.

For a processor operating at 650 MHz and below, the following decoupling is recommended. The processor core power plan (VCc) should have twelve (12) 0.1 µF high frequency decoupling capacitors placed underneath the die and twenty seven (27) 0.1 µF mid frequency decoupling capacitors placed around the die as close to the die (< 0.8 inch away) as flex solution allows. The system bus buffer power plane (VCCT) should have 15 0.1-µF high frequency decoupling capacitors no further than 0.25 inch away from the VCCT vias (balls).

7.3 82443BX Design Checklist

7.3.1 Host Interface Signals

Table 32. Host Interface Signals

82443BX Pin Pin Connection

CPURST# Connect to CPU and ITP (240 Ω series resistor)

HA[31:3]# Connect to CPU

HD[63:0]# Connect to CPU

ADS# Connect to CPU

BNR# Connect to CPU

BPRI# Connect to CPU

BREQ0# Connect to CPU. Optional, leave as No Connect if CPU BREQ0# pin is pulled to Vss with a 10 Ω resistor

DBSY# Connect to CPU

DEFER# Connect to CPU

DRDY# Connect to CPU

HIT# Connect to CPU

HITM# Connect to CPU

HLOCK# Connect to CPU

HREQ[4:0] Connect to CPU

HTRDY# Connect to CPU

RS[2:0]# Connect to CPU


64 Design Guide

7.3.2 DRAM (SO-DIMM) Interface Signals

• For standard DIMM SDRAM interface signal guidelines refer to the Intel® 440BX AGPset Design Guide.

• MD[63:0] should have 10 Ω series termination resistors for SO-DIMM designs.

• Clock signals from the CKBF-M to each SO-DIMM should have 10 Ω series termination resistors.

• A zero delay buffer should not be used in place of the CKBF-M.

Table 33. DRAM (SO-DIMM) Interface Signals


RASA[5:0]#

/CSA[5:0]#Connect two CSA[5:0]# signals to each SO-DIMM.

CASA[7:0]#

/DQMA[7:0]#Connect DQMA[7:0]# to each SO-DIMM.

CKE[5:0] Connect two CKE signals to each SO-DIMM

SRASA# Connect SRASA# to each SO-DIMM

SCASA# Connect SCASA# to each SO-DIMM

MAB[0:9]# Connect to associated address pin of SO-DIMM

MAB10 Connect to A10 pin of SO-DIMM

MAB11# Connect to SO-DIMM pin #106

MAB12# Connect to SO-DIMM pin #70, #110

MAB13 Connect to SO-DIMM pin #72, #112

WEA# Connect WEA# to each SO-DIMM

MD[63:0] 10 Ω series resistor. Connect MD[63:0] to each SO-DIMM

MECC[7:0] 10 Ω series resistor. Connect MECC[7:0] to each SODIMM. Leave as No Connect if not used.


Design Guide 65

7.3.3 PCI Interface Signals

• The 82443BX supports up to five PCI masters with its REQ[4:0]#/GNT[4:0]# pairs. The PCI bus supports up to ten PCI loads. The 82443BX and the PIIX4E each represent one load; other PCI components soldered on the motherboard add one load each; and each PCI connector adds approximately two loads. A design with four PCI slots and no motherboard devices uses all available PCI loads. When all five REQ[4:0]#/GNT[4:0]# pairs are used, simulation is required to ensure that the PCI Bus Specification, Rev. 2.1, timings are met.

7.3.4 PCI Sideband Signals

Table 34. PCI Interface Signals


AD[31:0] Connect to PCI Slots and PIIX4E.

DEVSEL# 2.7 K Ω pull-up to 5 V or 10 KΩ pull-up to 3.3 V. Connect to PCI Slots and PIIX4E.

FRAME# 2.7 KΩ pull-up to 5 V or 10 KΩ pull-up to 3.3 V. Connect to PCI Slots and PIIX4E.

IRDY# 2.7 ΚΩ pull-up to 5 V or 10 KΩ pull-up to 3.3 V. Connect to PCI Slots and PIIX4E.

C/BE[3:0]# Connect to PCI Slots and PIIX4E.

PAR Connect to PCI Slots and PIIX4E.

PLOCK# 2.7 KΩ pull-up to 5 V or 10 KΩ pull-up to 3.3 V. Connect to PCI Slots.

TRDY# 2.7 KΩ pull-up to 5 V or 10 KΩ pull-up to 3.3 V. Connect to PCI Slots and PIIX4E.

SERR# 2.7 KΩ pull-up to 5 V or 10 KΩ pull-up to 3.3 V. Connect to PCI Slots and PIIX4E.

STOP# 2.7 KΩ pull-up to 5 V or 10 KΩ pull-up to 3.3 V. Connect to PCI Slots and PIIX4E.

Table 35. PCI Sideband Signals


PHOLD# 10 KΩ pull-up to 3.3 V. Connect to PIIX4E.

PHLDA# 10 KΩ pull-up to 3.3 V. Connect to PIIX4E.

WSC# NO CONNECT

PREQ[4:0] 10 KΩ pull-up to 3.3 V. Connect to PCI Slots.

PGNT[4:0] 10 KΩ pull-up to 3.3 V. Connect to PCI Slots.


66 Design Guide

7.3.5 AGP Interface Signals

• To disable AGP, tie MAB9# high using a 10 KΩ pull-up to 3.3 V, connect GCLKO to GCLKIN through an 18 Ω resistor, and ground AGPREF. When AGP is properly disabled, all AGP signals are tri-stated and isolated; no termination is needed.

Table 36. AGP Interface Signals


PIPE# 8.2 KΩ pull-up to 3.3 V. Connect to AGP connector.

SBA[7:0] Connect to AGP connector.

RBF# 8.2 KΩ pull-up to 3.3 V. Connect to AGP connector.

ST[2:0] Connect to AGP connector.

ADSTB_A 8.2 KΩ pull-up to 3.3 V. Connect to AGP connector.

ADSTB_B 8.2 KΩ pull-up to 3.3 V. Connect to AGP connector.

SBSTB 8.2 KΩ pull-up to 3.3 V. Connect to AGP connector.

GFRAME# 8.2 KΩ pull-up to 3.3 V. Connect to AGP connector.

GIRDY# 8.2 KΩ pull-up to 3.3 V. Connect to AGP connector.

GTRDY# 8.2 KΩ pull-up to 3.3 V. Connect to AGP connector.

GSTOP# 8.2 KΩ pull-up to 3.3 V. Connect to AGP connector.

GDEVSEL# 8.2 KΩ pull-up to 3.3 V. Connect to AGP connector.

GREQ# 8.2 KΩ pull-up to 3.3 V. Connect to AGP connector.

GGNT# 8.2 KΩ pull-up to 3.3 V. Connect to AGP connector.

GAD[31:0] Connect to AGP connector.

GC/BE[3:0]# Connect to AGP connector.

GPAR 100 KΩ pull-down to Vss. Pull-down not required if the AGP device uses GFRAME# only.


Design Guide 67

7.3.6 Clocks, Resets, and Miscellaneous Signals

• See Section 5.0 for clock routing guidelines.

7.3.7 Power Management Interface

Table 37. Clocks, Resets, and Miscellaneous Signals


HCLKIN Connect to CPU BCLK and CK100M through 22 Ω series resistor at CK100M device

PCLKIN Connect to CK100M through 33 Ω series resistor.

DCLKO Connect to CKBFM through 18 Ω series resistor placed next to 82443BX.

DCLKWR 22 Ω series termination at CKBFM. ‘T’ at the 22 Ω resistor with 15 pF cap to Vss.

PCIRST# Connect to AGP, PCI, and PIIX4E. 33 Ω series resistor next to PIIX4E.

GCLKIN Connect to GCLKO through 18 Ω series resistor.

GCLKO Connect to AGP device through 18 Ω series resistor.

CRESET# NO CONNECT. Optional connect to bus ratio logic for qualification processors.

TESTIN# 8.2 KΩ pull-up to 3.3 V. May be removed if validation permits.

Table 38. Power Management Interface


CLKRUN#When not connected to PIIX4E, pull-down with a 100 Ω resistor at both the 82443BX and PIIX4E. Otherwise, pull-up to 3.3 V with a 10 KΩ and connect to PIIX4E.

SUSTAT# 10 KΩ pull-up to 3.3 V. Connect to PIIX4E SUS_STAT1# pin for POS implementation.

BXPWROK Connect to processor PWRGOOD pin through voltage conversion logic. Connect to PIIX4E PWROK pin.


68 Design Guide

7.3.8 Reference Pins

7.3.9 82443BX Decoupling Guidelines

Decoupling caps should be placed at the corners of the 82443BX (BGA Package). A minimum of four 0.1 µF and four 0.01 µF are recommended. The system bus, AGP, PCI, and DRAM interface may break out from the BGA package on all four sides. Additional caps will also help reduce EMI and cross-talk. Refer to Figure 33 for decoupling topology.

Table 39. Reference Pins


GTLREF[B:A] GTLREF = 2/3 VCCT. Use voltage divider with R1 = 1.0 KΩ 1%, and R2 = 2.0 KΩ 1%. Place two 0.1uF caps next to 82443BX

VTT[B:A] Tie to VCCT voltage plane.

VCC Power pin at 3.3 V.

VSS Tie to GND.

REF5VFor a 5 V tolerant PCI bus connect to 5 V through a 1 KΩ resistor. See Section 8.2.1 for voltage sequencing requirements. For non-5 V tolerant PCI connect directly to 3.3 V.

AGPREFAGPREF = (2/5)3.3 V. Use a voltage divider with R1 = 3.48 KΩ 1% and R2 = 2.32 KΩ 1%. Place 0.1uF cap next to 82443BX. When disabling AGP, tie to ground.

Figure 33. 82443BX Decoupling

82443BX

Host Bridge/

Controller 492 BGA

0.1uF 0.01uF

0.1uF 0.01uF

0.1uF 0.01uF

0.1uF 0.01uF


Design Guide 69

7.3.10 82443BX Strapping Options

• Highlighted strapping options shown below are required for this platform.

• Internal resistors are 50 KΩ pull-up or pull-down.

• Use external resistors of 10 KΩ to configure modes.

• Strapping option pull-ups should be to 3.3 V.

Table 40. 82443BX Strapping Options

Pin Name Function Low High Internal Resistor

Status Register

MAB12# Host Frequency Select 66 MHz 100 MHz Pull-down NBXCFG[13]

MAB11# In-Order Queue Depth Enable 1 (no pipelining) 4 (max) Pull-up NBXCFG[2]

MAB10 Quick Start Select Stop Clock Mode Quick Start Mode Pull-down PMCR[3]

MAB9# AGP Disable AGP Enabled AGP Disabled Pull-down PMCR[1]

MAB7# MM Configuration Normal Operation Tri-states certain Memory signals Pull-down DRAMC[5]

MAB6# Host Bus Buffer Mode Select Desktop GTL+ Low Power

GTL+ Pull-down None


70 Design Guide

7.4 82371EB (PIIX4E) Design Checklist

7.4.1 PCI Interface Signals

• For systems in which the PCIRST# signal is lightly loaded (< 50pF), place a 47 pF capacitor to Vss on this signal. The capacitor should be placed as close as possible to the PIIX4E.

Table 41. PCI Interface Signals

PIIX4E Pin Pin Connection

AD[31:0] Connect to PCI slots and 82443BX.

C/BE#[3:0] Connect to PCI slots and 82443BX.

CLKRUN# 10 KΩ pull-up to 3.3 V. Connect to 82443BX. When not used, tie a 100 Ω pull-down at both the 82443BX and PIIX4E.

DEVSEL#2.7 KΩ pull-up to 5 V or 10 KΩ pull-up to 3.3 V. Connect between 82443BX,

PCI slots, and PIIX4E.

FRAME#2.7 KΩ pull-up to 5 V or 10 KΩ pull-up to 3.3 V. Connect between 82443BX,


IDSEL 100 Ω series resistor to AD18.

IRDY#2.7 KΩ pull-up to 5 V or 10 KΩ pull-up to 3.3 V. Connect between 82443BX,


PAR Connect to PCI slots and 82443BX.

PCIRST# 33 Ω series resistor next to PIIX4E. Connect to AGP, PCI, and 82443BX.

PHOLD# Connect to 82443BX. 10 KΩ pull-up to 3.3V.

PHLDA# Connect to 82443BX. 10 KΩ pull-up to 3.3V.

SERR#2.7 KΩ pull-up to 5 V or 10 KΩ pull-up to 3.3 V. Connect between 82443BX,


STOP#2.7 KΩ pull-up to 5 V or 10 KΩ pull-up to 3.3 V. Connect between 82443BX,


TRDY#2.7 KΩ pull-up to 5 V or 10 KΩ pull-up to 3.3 V. Connect between 82443BX,



Design Guide 71

7.4.2 ISA/EIO Bus Interface Signals

• Recommendations below are for ISA implementation.

• When implementing Power On Suspend (POS) mode, ISA signals should be pulled up to 3.3 V. Otherwise use 5 V.

Note: This pull-up voltage is referred to VCCISA in this checklist.

Table 42. ISA/EIO Bus Interface Signals


AEN Connect to SIO and ISA slots.

BALE/GPO0 10K Ω pull-up to VCCISA. Connect to ISA slots.

IOCHK# /GPI0 1K Ω pull-up to VCCISA. Connect to ISA slots.

IOCHRDY 1K Ω pull-up to VCCISA. Connect to ISA slots and Ultra I/O.

IOCS16# 1K Ω pull-up to VCCISA. Connect to ISA slots.

IOR# 10K Ω pull-up to VCCISA. Connect to ISA slots, Ultra I/O, LM79.

IOW# 10K Ω pull-up to VCCISA. Connect to ISA slots, Ultra I/O, LM79.

LA[23:17]

/GPO[7:1]10K Ω pull-up to VCCISA. Connect to ISA slots.

MEMCS16# 1K Ω pull-up to VCCISA. Connect to ISA slots.

MEMR# 10K Ω pull-up to VCCISA. Connect to ISA slots and Flash.

MEMW# 10K Ω pull-up to VCCISA. Connect to ISA slots and Flash.

REFRESH# 1K Ω pull-up to VCCISA. Connect to ISA slots.

RSTDRV Connect to Ultra I/O, ISA slots, and IDE (IDE through a Schmitt trigger).

SA[19:0] 10K Ω pull-up to VCCISA. Connect to ISA slots, Ultra I/O, Flash, LM79.

SBHE# 10K Ω pull-up to VCCISA. Connect to ISA slots.

SD[15:0] 10K Ω pull-up to VCCISA. Connect to ISA slots, Ultra I/O, LM79.

SMEMR# 10K Ω pull-up to VCCISA. Connect to ISA slots.

SMEMW# 10K Ω pull-up to VCCISA. Connect to ISA slots.

ZEROWS# 1K Ω pull-up to VCCISA. Connect to ISA slots.


72 Design Guide

7.4.3 X-Bus Interface Signals

Value of pull-up on A20GATE# and RCIN# could vary depending on SIO output type.

7.4.4 DMA Signals

Table 43. X-Bus Interface Signals


A20GATE# 10 KΩ pull-up to 3.3 V. Connect to SIO.

BIOSCS# Connect to Flash.

KBCCS#

/GPO26NO CONNECT. When the KBCCS# signal is not used, this signal may be programmed to be a general-purpose output.

MCCS# NO CONNECT

PCS[0:1]# 10 KΩ pull-up to 3.3 V. Connect to LM79. NO CONNECT if not used.

RCIN# 10 KΩ pull-up to 3.3 V. Connect to SIO.

RTCALE

/GPO25NO CONNECT. When the internal Real Time Clock is used, this signal may be programmed as a general-purpose output.

RTCCS#

/GPO24NO CONNECT. When the internal Real Time Clock is used, this signal may be programmed as a general-purpose output.

XDIR#

/GPO22Connect to SIO. NO CONNCET if not used. When the X-Bus not used, this signal may be programmed to be a general-purpose output.

XOE#

/GPO23Connect to SIO. NO CONNECT if not used. When the X-Bus not used, this signal may be programmed to be a general-purpose output.

Table 44. DMA Signals


DACK[0,1,2,3]#

DACK[5,6,7]#Connect to ISA slots. DACK#[3:0] also connect to SIO.

DREQ[0,1,2,3]

DREQ[5,6,7]Connect to ISA slots. 5.6 KΩ pull-down.

REQ[A:C]#

/GPI[2:4]10 K Ω pull-up to 3.3 V. When the PC/PCI DMA request is not needed, these pins may be used as general-purpose inputs.

GNT[A:C]#

/GPO[9:11]NO CONNECT. When the PC/PCI DMA acknowledge is not needed, these pins may be used as general-purpose outputs.

TC Connect to SIO and ISA slots.


Design Guide 73

7.4.5 Interrupt Controller/APIC Signals

7.4.6 CPU Interface Signals

Table 45. Interrupt Controller/APIC Signals


APICACK#/GPO12

Connect to IOAPIC. When the external APIC is not used, this pin is ageneral-purpose output.

APICCS#/GPO13

2.7 KΩ pull-up to 3.3 V. Connect to IOAPIC. When the external APIC is not used, this pin is a general-purpose output.

APICREQ#/GPI5

10 KΩ pull-up to 3.3 V. Connect to IOAPIC. When the external APIC is not used, this pin is a general-purpose input.

IRQ0/GPO14 Connect to INTIN2 of IOAPIC. When the external APIC is not used, this pin is a general-purpose output.

IRQ1 10 KΩ pull-up to VCCISA. Connect to ISA slots and Ultra I/O. Connect to IOAPIC.

IRQ[3:7, 9:11]

IRQ[14:15]

IRQ[3:7, 9:11] - 10 KΩ pull-up to VCCISA. Connect to ISA slots and Ultra I/O. Connect to IOAPIC.

IRQ[14:15] - 10 KΩ pull-up to VCCISA. Connect to ISA slots, Ultra I/O and IDE.

Connect to IOAPIC.

IRQ8#/GPI6 10 KΩ pull-up to 3.3VSB. Connect to IOAPIC through tri-state buffer.

IRQ9OUT/GPO29

Connect to IOAPIC. When the external APIC is not used, this pin is a general-purpose output.

IRQ12/M 10 KΩ pull-up to VCCISA. Connect to ISA slots and Ultra I/O. Connect to IOAPIC.

PIRQ[A:D]# 2.7 KΩ pull-up to 5 V or 10 KΩ pull-up to 3.3 V. Connect between PCI slots and PIIX4E. PIRQ[A:B]# also go to AGP.

SERIRQ/GPI7

10 KΩ pull-up to 3.3 V. When not using serial interrupts, this pin may be used as a genera purpose input.

Table 46. CPU Interface Signals


A20M# 1.5 KΩ pull-up to VCCT.

CPURST NO CONNECT

FERR# Connect to voltage conversion logic as described in processor checklist.

IGNNE# 1.5 KΩ pull-up to VCCT.

INIT 1 KΩ pull-up to VCCT.

INTR 1.5 KΩ pull-up to VCCT. Connect to IOAPIC.

NMI 1.5 KΩ pull-up to VCCT.

SLP# 1.5 KΩ pull-up to VCCT.

SMI# 270 Ω pull-up to VCCT. Connect to IOAPIC.

STPCLK# 680 Ω pull-up to VCCT.


74 Design Guide

7.4.7 Clocking Signals

• USB Clock – A 48 MHz clock with a duty cycle of better than 40%/60% should be fed into the PIIX4E’s USB clock input, pin L3.

• The RTC capacitor value should be chosen to provide the manufacturer’s specified load capacitance of the trace, socket (if used), and package which may vary from 0 pF to 8 pF. When choosing the value the following equation may be used:

Specified Crystal Load = (Cap1*Cap2)/Cap1+Cap2) + parasitic capacitance

Table 47. Clocking Signals


CLK48 Connect to 48 MHz clock through a 33 Ω series resistor. When not using USB, this may be connected to GND.

PCICLK Connect to CK100M through a 33 Ω series resistor.

OSC Connect to CK100M through a 33 Ω series resistor.

RTCX1, RTCX2 Connect to 32.768 KHz crystal. Place capacitors on each side of crystal to Vss. For capacitor values see above.

SUSCLK NO CONNECT

SYSCLK Connect to LM79 and ISA slots. NO CONNECT if not using ISA.


Design Guide 75

7.4.8 IDE Signals

• Series termination resistors should be placed within one inch of the PIIX4E.

• When not using IDE the following primary and secondary IDE signals, they may be left as NO CONNECTS: xDA[2:0], xDCS1#, xDCS3#, xDD[15:8,6:0], xDDACK#, xDIOR#, xDIOW#.

Table 48. IDE Signals


PDA[2:0] Connect to IDE connector through 33 Ω series resistors.

PDCS1# Connect to IDE connector through 33 Ω series resistor.

PDCS3# Connect to IDE connector through 33 Ω series resistor.

PDD[15:0] Connect to IDE connector through 33 Ω series resistors. It is recommended that PDD[7] have a 10 KΩ pull-down resistor even if IDE is not used.

PDDACK# Connect to IDE connector through 33 Ωseries resistor.

PDDREQ Connect to IDE through 33 Ω series resistor. 5.6 KΩ pull-down on the PIIX4E side of the series resistor. When not used, a 5.6 KΩ pull-down is still required.

PDIOR# Connect to IDE connector through 33 Ω series resistor.

PDIOW# Connect to IDE connector through 33 Ω series resistor.

PIORDY Connect to IDE through 47 Ω series resistor. 1 KΩ pull-up to VCCISA on the PIIX4E side of the series resistor. When not used, a 1 KΩ pull-up is still required

SDA[2:0] Connect to IDE connector through 33 Ω series resistors.

SDCS1# Connect to IDE connector through 33 Ω series resistor.

SDCS3# Connect to IDE connector through 33 Ω series resistor.

SDD[15:0] Connect to IDE connector through 33 Ω series resistors. It is recommended that SDD[7] have a 10 KΩ pull-down resistor even if IDE is not used.

SDDACK# Connect to IDE connector through 33 Ω series resistor.

SDDREQ Connect to IDE through 33 Ωseries resistor. 5.6 KΩ pull-down on the PIIX4E side of the series resistor. When not used, a 5.6 KΩ pull-down is still required.

SDIOR# Connect to IDE connector through 33 Ω series resistor.

SDIOW# Connect to IDE connector through 33 Ω series resistor.

SIORDY Connect to IDE through 47 Ω series resistor. 1 KΩ pull-up to VCCISA on the PIIX4E side of the series resistor. When not used, a 1 KΩ pull-up is still required.


76 Design Guide

7.4.9 USB Signals

• When not using USB, a 10 KΩ pull-up to 3.3 V is required on OC[1:0]# and 15 KΩ pull-downs are required on all USBP signals.

• Refer to the PIIX4 Universal Serial Bus design guide and Checklist for USB layout guidelines, available from your Intel field sales representative.

Table 49. USB Signals


OC[1:0]# Driven by USB over-current detection voltage divider.

USBP0+

/USBP0-

47pF cap to Vss with 27 Ω series resistor to USB port. These should be

placed as close as possible to the PIIX4E.

USBP1+

/USBP1-

47pF cap to Vss with 27 Ω series resistor to USB port. These should be

placed as close as possible to the PIIX4E.


Design Guide 77

7.4.10 Power Management Signals

• SUSA# is primarily used to control the primary power plane. This signal is asserted during POS, STR, and STD suspend states.

• SUSB# is primarily used to control the secondary power plane. This signal is asserted during STR, and STD suspend states.

• SUSC# is primarily used to control the tertiary power plane. This signal is asserted during STD suspend state.

Table 50. Power Management Signals (Sheet 1 of 2)


BATLOW# /GPI19 10 KΩ pull-up to 3.3 VSB if BATLOW# is not used. When the Battery Low function is not needed, this pin may be used as a general-purpose input.

CPU_STP# /GPO17 NO CONNECT, or connect to CK100M with 10 KΩ pull-up to 3.3 VSB.

EXTSMI# Connect to LM79. 10 KΩ pull-up to 3.3 VSB.

LID/GPI10 10 KΩ pull-up to 3.3 VSB if LID is not used.

PCIREQ[A:D]# 10 KΩ pull-up to 3.3 V. Connect to 82443BX and PCI slots.

PCI_STP#/GPO18 No connect, or connect to CK100M with 10 KΩ pull-up to 3.3 VSB. When this function is not needed, this pin may be used as a general-purpose output.

PWRBTN# From power button circuitry. When not used, add a 10 KΩ pull-up to 3.3 VSB.

RI#/GPI1210 KΩ pull-up to 3.3 VSB. Connect to AGP connector AGP_PME# (pin A48). When this function is not needed, this signal may be individually used as a general-purpose input.

RSMRST# From ATX connector buffer/delay circuitry. When not using power management (suspend modes), this may be connected to PIIX4E PWROK.

SMBALERT#/GPI11 10 KΩ pull-up to 3.3 VSB. Connect to MAX1617. When this function is not needed, this pin may be used as a general-purpose input.

SMBCLK 2.7 KΩ pull-up to 3.3 V. Connect to all devices on SMBus. This value may need to be adjusted based on bus loading.

SMBDATA 2.7 KΩ pull-up to 3.3 V. Connect to all devices on SMBus. This value may need to be adjusted based on bus loading.

SUSA# No connect, or connect to CK100M power down control with 10 K Ω pull-up to 3.3 V.

SUSB# /GPO15Controls secondary power plane during STR and STD suspend state. When the power plane control is not needed, this pin may be used as a general-purpose output.

SUSC#/GPO16 Controls tertiary power plane during STD suspend state. When the power plane control is not needed, this pin may be used as a general-purpose output.

SUS_STAT1#/GPO20 No Connect or connect to 82443BX for POS implementation. When this function is not needed, this pin may be used as a general-purpose output.

SUS_STAT2#/GPO21 NO CONNECT. When this function is not needed, this pin may be used as a general-purpose output.

THRM#/GPI8 10 KΩ pull-up to 3.3 V. Connect to LM75. When this function is not needed, this pin may be used as a general-purpose input.

ZZ/GPO19 NO CONNECT. When this function is not needed, this pin may be used as a general-purpose output.

GPI[21:0] 10 KΩ pull-up to 3.3 V if these pins are not used.


78 Design Guide

7.4.11 Other System and Test Signals

7.4.12 Power and Ground Pins

7.4.13 PIIX4E Decoupling Guidelines

Use the same guidelines as shown in Section 7.3.9, “82443BX Decoupling Guidelines” on page 68.

GPO[30:0] NO CONNECT if these pins are not used.

Table 51. Other System and Test Signals


CONFIG1 10 KΩ pull-up to 3.3 VSB.

CONFIG2 10 KΩ pull-down to Vss

PWROK Connect to 82443BX and power up logic. When not using power management (suspend modes), also connect to PIIX4E RSMRST#.

SPKR Connect to speaker circuit. NO CONNECT if not used.

TEST# 10 KΩ pull-up to 3.3VSB.

Table 52. Power and Ground Pins


Vcc Tie to 3.3 V.

Vcc(RTC) Tie to 3.3 V. Connect to battery circuitry. Also referred to as VBAT

Vcc(SUS)Tie to 3.3 V Standby plane (Also referred to as 3.3 VSB). The 3.3 VSB should power off only when the system is mechanically off. When power management is not used, tie directly to 3.3 V.

Vcc(USB) Tie to 3.3 V.

VREF

For a 5 V tolerant PCI bus connect to 5 V. It must be powered up before or simultaneous to 3.3 V. It must power down after or simultaneous to 3.3 V. See Section 8.1.1 for example circuit. For non-5 V tolerant PCI (3.3 V only) connect directly to 3.3 V. There are no sequencing requirements.

Vss Tie to GND.

Vss (USB) Tie to GND.

Table 50. Power Management Signals (Sheet 2 of 2)



Design Guide 79

8.0 Power Sequencing

This section provides a summary of the power sequencing requirements and options of the 440BX AGPset. It provides a detailed description of the PIIX4E Suspend/Resume sequence, signaling protocols, and timings. The recommended usage model for power plane control in a 440BX platform using PIIX4E power management signals is described.

This section does not represent the only way to design a system, but it does provide recommendations for using the 440BX AGPset.

8.1 PIIX4E Power Sequencing

8.1.1 Power Sequencing Requirements

In systems requiring 5 V tolerance, the VREF signal must be tied to 5 V. This signal must power up before or simultaneous to VCC. It must power down after or simultaneous to VCC. In a non 5 V tolerant system (3.3 V only), this signal may be tied directly to VCC. There are then no sequencing requirements. Refer to Figure 34 for an example circuit schematic, which may be used to ensure the proper VREF sequencing.

The PIIX4E VCC and VCC(USB) supplies are separated internally in order to reduce noise on USB signals. They should not be powered up or down independently of one another. They should be connected to the same power plane on the motherboard. There are no other power sequencing requirements for the various VCC power supplies to the PIIX4E.

8.1.2 Suspend/Resume and Power Plane Control

The PIIX4E supports three different Suspend modes. The common system usage model for these modes is described here and includes Power On Suspend (POS), Suspend to RAM (STR), and Suspend to Disk (STD). This mode definition allows for other system usage models that use the PIIX4E suspend/resume control signals in other ways. The common system mode names are used throughout this document.

Figure 34. VREF Supply Schematic

VCC Supply(3.3V)

5V Supply

1k

1 uF

VREFTo System To System

SchottkyDiode


80 Design Guide

The PIIX4E power management architecture is designed to allow systems to support multiple suspend modes, and to switch between those modes as required. A suspended system may be resumed by a number of different events. The system returns to full operation, and may then continue processing or be placed into another suspend mode. The new mode may be at a lower power mode than the mode from which it resumed.

8.1.2.1 Power On Suspend (POS) System Model

All devices are powered up except for the clock synthesizer. The Host and PCI clocks are inactive, and the PIIX4E provides control signals and the 32 KHz Suspend Clock (SUSCLK) to allow for DRAM refresh and to turn off the clock synthesizer. The only power consumed in the system while it is in POS mode is due to DRAM refresh and leakage current of the powered devices.

When the system resumes from POS mode, the PIIX4E may resume without resetting the system, may reset the processor only, or may reset the entire system. When no reset is performed, the PIIX4E only needs to wait for the clock synthesizer and processor PLLs to lock before the system is resumed. This takes typically 20 ms.

8.1.2.2 Suspend to RAM (STR)

Power is removed from most of the system components during STR, except the DRAM. Power is supplied to the host bridge (for DRAM Suspend Refresh) and the PIIX4E’s RTC and Suspend Well logic. The PIIX4E provides control signals and a 32 KHz Suspend Clock (SUSCLK) to allow for DRAM refresh and to turn off the clock synthesizer and other power planes.

The PIIX4E resets the system on resume from STR.

8.1.2.3 Suspend to Disk (STD) and Soft Off (SOff)

Power is removed from most of the system components during STD. Power is maintained to the RTC and Suspend Well logic in the PIIX4E.

The PIIX4E resets the system on resume from STD.

The STD state is also called the Soft Off (SOff) state. The difference depends on whether the system state is restored by software to a pre-suspend condition or the system is rebooted.


Design Guide 81

8.1.2.4 Mechanical Off (MOff)

This is not a suspend state. This is a condition where all power except the RTC battery has been removed from the system. It is typically controlled by a mechanical switch that turns off AC power to a power supply. It could be used as a condition in which an embedded system’s main battery has been removed.

The PIIX4E controls the system entering the various suspend states through the suspend control signals listed in Table 53. Upon initiation of suspend, the PIIX4E asserts the SUS_STAT[1-2]#, SUSA#, SUSB#, and SUSC# signals in a well defined sequence to switch the system into the desired power state. The SUSA#, SUSB#, and SUSC# signals may be used to control various power planes in the system. The SUS_STAT1# signal is a status signal that indicates to the host bridge when to enter or exit a suspend state, or when to enter or exit a stop clock state (when the system is still running). This is typically used to place the DRAM controller into a Suspend Refresh mode of operation. The SUS_STAT2# signal is a status signal that may be used to indicate to other system devices when to enter or exit a suspend state (like the graphics and Cardbus controllers). See “System Suspend and Resume Control Signaling” on page 84 for sequencing details. Note that these signals are associated with a particular type of suspend mode and power plane for descriptive purposes here. The system designer is free to use these signals to control any type of function desired.

The system is placed into a suspend mode by programming the Power Management Control register. The Suspend Type is first programmed and then the Suspend Enable bit is set. This causes the PIIX4E to automatically sequence into the programmed suspend mode.

Table 53. Power State Decode

Power State RSMRST# SUS_STAT1# SUS_STAT2# SUSA# SUSB# SUSC#

On 1 x† 1 1 1 1

POS 1 0 0 0 1 1

STR 1 0 0 0 0 1

STD/SOFF 1 0 0 0 0 0

Mechanical Off 0 0 0 0 0 0

† SUS_STAT1# is also used when the system is running. It indicates to the Host-to-PCI bridge when to switch between the normal and suspend refresh mode for DRAM Stop Clock support. In the Stop Clock condition, HCLK is stopped and the Host-to-PCI bridge must run DRAM refresh from the internal oscillator.


82 Design Guide

8.1.3 System Resume

The PIIX4E may be resumed from either a Suspend or Soft Off state. Depending on the suspend state that the system is in, different features may be enabled to resume the system. There are two classes of resume events, those whose logic resides in the PIIX4E main power well and those whose logic resides in the PIIX4E suspend well. Those in the suspend well may resume the system from any Suspend or Soft Off state. Those in the main power well may only resume the system from a Power On Suspend state. Table 54 lists the suspend states for which a particular resume event may be enabled.

Upon detection of an enabled resume event, the PIIX4E sets appropriate status signals and automatically transitions its suspend control signals to bring the system into a ‘full on’ condition. The sequencing is shown in “System Suspend and Resume Control Signaling” on page 84.

Table 54. Resume Events Supported In Different Power States

Resume EventSuspend States

POS STR STD/SOff MOff

RTC Alarm (IRQ8) † x x x

SMBus Resume Event (Slave Port Match) x x x

Serial A Ring (RI) x x x

Power Button (PWRBTN#) x x x

EXTSMI (EXTSMI#) x x x

LID (LID) x x x

GPI 1 x x x

GSTBY Timer Expiration x x x

Interrupt (IRQ 1,3-15) x

USB x

† RTC Alarm only supports internal RTC. For external RTC implementations, the IRQ8 must be tied to one of the other resume input signals (GPI[1], LID, EXTSMI#,RI#) for the resume functionality.


Design Guide 83

8.1.3.1 System Resume Events

Table 55 indicates the various resume events and their corresponding programming models.

8.1.3.2 Global Standby Timer Resume

The Global Standby Timer is used to monitor system activity during normal operation and may be reloaded by system activity events. Upon expiration, it generates an SMI#. When the system is placed in a Suspend Mode, the Global Standby Timer may be used to generate a resume event. The Global Standby Timer may enable two different timer resolutions for wake-up times from approximately 30 seconds to 8.5 hours. This may allow the system to transition into a lower power suspend state.

See the System Management Section of the Intel® 82371AB PCI-to-ISA/IDE Xcelerator (PIIX4) Datasheet (order number 290562) for additional information about the Global Standby Timer.

Table 55. Resume Event Programming Model

System Resume Event Programming Model

PWRBTN# Asserted [PWRBTN_EN]

LID Asserted

- Polarity Select

[LID_EN]

[LID_POL]

GPI[1] Asserted [GPI_EN]

EXTSMI# Asserted [EXTSMI_EN]

SMBus Events:

[ALERT_EN][SLV_EN]

[SHDW1_EN][SHDW2_EN]

Global Standby Timer Expiration: [GSTBY_EN]

Ring Indicate Assertion (RI#) [RI_EN]

RTC Alarm (IRQ8)† [RTC_EN]

USB Resume Signaling: (POS Only) [USB_EN]

IRQ[1,3-7,9-15]: (POS Only) [IRQ_RSM_EN]

† RTC Alarm only supports internal RTC. For external RTC implementations, the IRQ8 must be tied to one of the other resume input signals (GPI[1], LID, EXTSMI#,RI#) for the resume functionality.


84 Design Guide

8.1.4 System Suspend and Resume Control Signaling

The PIIX4E automatically controls the signals required to transition the system between the various power states. It provides control for Host and PCI clocks, main memory and video memory refresh, system power plane control, and system reset. Table 56 and Table 57 indicate the common usage model for power plane control using the SUS[C:A]# signals. The PIIX4E Resume well should always be powered by a trickle supply (main battery or backup battery in an embedded system).

8.1.4.1 Power Well and Reset Signal Timings

Figure 35 shows the system timings for changing the power states of a system using the POS/STR/STD models.

Table 56. Power Plane Control

SUSA# (POS) SUSB# (STR) SUSC# (STD)

Clock synthesizer

Video display1

Processor (Low Power GTL+ supplies)

PIIX4E Core

Other system devices2

82443BX Host Bridge/Controller

DRAM

Graphics Controller

NOTES:1. The video display (flat panel or CRT) may optionally be powered off in POS. This could be accomplished

by using the PIIX4E’s SUSA# or SUS_STAT2# signals to assert the video controller’s STANDBY signal.2. Devices may include mass storage, audio, or other devices that will not generate system resume events.

Table 57. Power Plane Control Using SUS[C:A]# Signals

Power Plane

Suspend Mode(Suspend Mode Signals Asserted by the PIIX4E)

Full On(None)

POS(SUSA#,

SUS_STAT[2:1]#)

STR(SUS[B:A]#

SUS_STAT[2:1]#)

STD(SUS[C:A]#

SUS_STAT[2:1]#)

Clock Synthesizer On Off Off Off

Video Display On On/Off1 Off Off

CPU On On Off Off

PIIX4E Core On On Off Off

Other Devices2 On On Off Off

82443BX On On On Off

DRAM On On On Off

Graphics Controller On On On Off

PIIX4E Resume On On On On

PIIX4E RTC On On On On

NOTES:1. The video display (flat panel or CRT) may optionally be powered off in POS. This could be accomplished

by using the PIIX4E’s SUSA# or SUS_STAT2# signals to assert the video controller’s STANDBY signal.2. Devices may include mass storage, audio, or other devices that will not generate system resume events.


Design Guide 85

8.1.4.2 PIIX4E Power Well Timings

Figure 35 describes the relative transitions for PIIX4E power supplies. Table 58 indicates the PIIX4E power well timing tolerances.

8.1.4.3 RSMRST# and PWROK Timing

Figure 36 describes the required timings for PIIX4E power level active status signals. Table 59 indicates the RSMRST# and PWROK timing tolerances.

Figure 35. PIIX4E Power Well Timings

Table 58. PIIX4E Power Well Timing Tolerances

Sym Parameter Min Max Unit Notes

t1 RTC Well Power to Suspend Well Power 0 ns

t2 Suspend Well Power to Core Well Power 0 ns

t1

t2

RTC Well Power

Suspend Well Power

Core W ell Power

Figure 36. RSMRST# and PWROK Timings

Table 59. RSMRST# and PWROK Timing Tolerance


t3 Suspend Well Power to RSMRST# Inactive 1 ms

t4 Core Well Power to PWROK Active 1 ms

t5 RSMRST# Inactive to PWROK Active 0 ns

t3

t4

t5

Suspend Well Power

RSMRST#

Core Well Power

PWROK


86 Design Guide

8.1.4.4 Suspend Well Power and RSMRST# Activated Signals

Figure 37 shows the timing relationships for the PIIX4E power management signals that are powered from the Suspend Well Power signal. These timings hold independent of the condition of Core Well Power or the PWROK signal. Table 60 indicates the Suspend Well Power and RSMRST# timing tolerances.

Figure 37. Suspend Well Power and RSMRST# Activated Signals

Table 60. Suspend Well Power and RSMRST# Timing Tolerances


t6 Resume Well Power and RSMRST# Active to SUS_STAT[1:2]# Active 1 RTC †

t7 Resume Well Power and RSMRST# Active to SUS [A:C]# Active 1 RTC †

t8 Resume Well Power and RSMRST# Active to SUSCLK Low 1 RTC †

t9 RSMRST# Inactive to SUS[A:C]# Inactive 1 2 RTC †

† These signals are controlled off an internal RTC clock. One RTC unit is approximately 32 µs.

t6

t7 t9

t8

Suspend Well Power

RSMRST#

SUS_STAT[1-2]#

SUS[A-C]#

SUSCLK


Design Guide 87

8.1.4.5 PCI Clock Control Timings

This section describes the timing requirements for the control of the system PCICLK. The system PCICLK timing shown in Figure 38 must be followed exactly for proper operation of the PC/PCI DMA or Serial IRQ logic. When the PC/PCI DMA and Serial IRQs are not used in the system, the system PCICLK stop timings must meet the system developer’s requirements.

Figure 39 describes the timing requirements for the control of the system PCICLK. The system PCICLK timings shown in Figure 39 must be followed exactly for proper operation of PC/PCI DMA or Serial IRQ logic. When PC/PCI DMA and Serial IRQs are not used in the system, the system PCICLK stop timings must meet the system developer’s requirements.

Figure 38. PCI Clock Stop Timing

PCI_STP#

PIIX4 PCICLK

SYSTEM PCICLK

Figure 39. PCI Clock Start Timing

PCI_STP#

PIIX4 PCICLK

SYSTEM PCICLK


88 Design Guide

8.1.4.6 Core Well Power and PWROK Activated Signals (RSMRST#Inactive Before Core Well Power Applied)

Figure 40 shows the timing relations for Power Management signals powered from the PIIX4E Main Core well. The Suspend Well Power active status signals (RSMRST#) transitions before the application of core well power to the PIIX4E. This figure corresponds to the usage model for PIIX4E power management. Table 61 indicates the Core Well Power and PWROK timing tolerances.

Figure 40. Core Well Power and PWROK Activated Signals(RSMRST# Inactive before Core Well Power Applied)

Table 61. Core Well Power and PWROK Timing Tolerances


t20 Core Well Power and PWROK Inactive to CPU_STP# and PCI_STP# Float 1 RTC 1

t21 Core Well Power and PWROK Inactive to PCIRST# Active 1 RTC 1

t22 Core Well Power and PWROK Inactive to CPURST Active 1 RTC 1

t23 Core Well Power and PWROK Inactive to SLP# Active 1 RTC 1

t24 Core Well Power and PWROK Inactive to STPCLK# Active 1 RTC 1

t25 CPU_STP# and PCI_STP# Float to Clocks Running 2

t26 PWROK Active to CPU_STP# and PCI_STP# Active 1 RTC 1

t27 CPU_STP# and PCI_STP# Active to Clocks Stopped 2

NOTES:1. These signals are controlled off an internal RTC clock. One RTC unit is approximately 32 µs.2. There are no specific requirements for these timings related to the PIIX4E. The system manufacturer

should make sure that the clocks on power up meet any other system specifications. As a minimum, the clocks must be available and stable after time t29 shown in Figure 42.

RTC Well Power

Suspend Well Power

RSMRST#

SUS[C:A]#

PWROK

Core Well Power

Running Stopped

Float

Active

CPU_STP# / PCI_STP#

PCICLK / CPU

PCIRST#

CPURST

SLP#

STPCLK#

t20 t26

t25 t27

t21

t22

t23

t24


Design Guide 89

8.1.4.7 Core Well Power and PWROK Activated Signals (Core WellPower Applied Before RSMRST# Inactive)

Figure 41 shows the timing relations for Power Management signals powered from the PIIX4E Core well. Here the power active status signals (RSMRST# and PWROK) transition after the application of all power to the PIIX4E. This is an example of an implementation in which the Core Well power plane is not controlled by the SUSB# signal. It may be applied to situations where two or more of the PIIX4E power planes are connected together. It also shows timings when RSMRST# and PWROK are connected together.

Figure 41. Core Well Power and PWROK Activated Signals (Core Well Power Applied before RSMRST# Inactive)

t10 t16

t15 t17

t11

t12

t13 t18t19

t14 t18at19a

Active

Float

Stopped

RTC Well Power

Suspend Well Power

Core Well Power

RSMRST#

PWROK

CPU_STP# / PCI_STP#

PCICLK / CPU CLK

PCI_RST#

CPURST

SLP#

STPCLK#


90 Design Guide

Table 62. Core Well Power and PWROK Timing


t10 Core Well Power and PWROK Inactive to CPU_STP# and PCI_STP# Float 1 RTC 1

t11 Core Well Power and PWROK Inactive to PCIRST# Active 1 RTC 1

t12 Core Well Power and PWROK Inactive to CPURST Active 1 RTC 1

t13 Core Well Power and PWROK Inactive to SLP# Inactive 1 RTC 1

t14 Core Well Power and PWROK Inactive to STPCLK# Inactive 1 RTC 1

t15 CPU_STP# and PCI_STP# Float to Clocks Running 2

t16 PWROK Active to CPU_STP# and PCI_STP# Active 1 RTC 1

t17 CPU_STP# and PCI_STP# Active to Clocks Stopped 2

t18 PWROK Active to SLP# Active 0 ns 3

t18a PWROK Active to STPCLK# Active 0 ns 1

t19 PWROK Active to SLP# Inactive 1 2 RTC 1, 3

t19a PWROK Active to STPCLK# Inactive 1 2 RTC 1, 3

NOTES:1. These signals are controlled off an internal RTC clock. One RTC unit is approximately 32 µs.2. There are no specific requirements for these timings related to the PIIX4E. The system manufacturer

should make sure that the clocks on power up meet any other system specifications. As a minimum, the clocks must be available and stable after time t29 shown in Figure 42.

3. These timings depend on the relative timings between RSMRST# and PWROK. When RSMRST# goes inactive two RTC periods before PWROK active, SLP# and STPCLK# will remain inactive. When RSMRST# goes inactive less than two RTC periods before PWROK active, an active pulse will be seen on SLP# and STPCLK#.


Design Guide 91

8.1.5 Power Management State Transition Timings

8.1.5.1 Mechanical Off to On

Figure 42 shows the transition from a Mechanical Off condition to the On condition. Table 63 describes the mechanical Off to On timing tolerances.

Figure 42. Mechanical Off to On

Table 63. Mechanical Off to On Timing Tolerances


t28 SUS[A:C]# Inactive to CPU_STP# and PCI_STP# Inactive 16 ms 1

t29 CPU_STP# and PCI_STP# Inactive to Clocks Running 2 PCICLK 2

t30 CPU_STP# and PCI_STP# Inactive to SUS_STAT[1:2]# Inactive 1 ms

t31 SUS_STAT[1:2]# Inactive to SUSCLK Running 1 RTC 3

t32 SUS_STAT[1:2]# Inactive to PCI_RST# Inactive 1 RTC 3

t33 PCI_RST# Inactive to CPURST Inactive 1 RTC 3

NOTES:1. This transition requires a minimum of 16 ms wait for the clock synthesizer PLL to lock and PWROK to be

active. When PWROK goes active after 16 ms from SUS[A:C]# inactive, the transition occurs a minimum of one RTC period from PWROK active.

2. See Figure 38 and Figure 39 for exact PCICLK requirements for use with PC/PCI DMA and Serial IRQs.3. These signals are controlled from an internal RTC clock. One RTC unit is approximately 32 µs.

t30

t31

t28

t29

t32

t33

Running

Running

InactiveActive

Stopped

RSMRST#

PWROK

SUS[A-C]#

SUS_STAT[1-2]#

SUSCLK

CPU_STP# / PCI_STP#

PCICLK / CPU CLK

PCI_RST#

CPURST

SLP#

STPCLK#

Float


92 Design Guide

8.1.5.2 On to POS

Figure 43 describes the signal transitions from the On state to the Power On Suspend state. Table 64 indicates the On to POS timing tolerances.

Figure 43. On to POS

Table 64. On to POS Timing Tolerances


t34 CPU_STP# and PCI_STP# Inactive to STPCLK# Active 1 RTC 1, 2

t35 STPCLK# Active to SLP# Active 1 RTC 1, 3

t36 SLP# Active to SUS_STAT[1:2]# Active 1 RTC 1

t37 SUS_STAT[1:2]# Active to CPU_STP# and PCI_STP# Active 1 RTC 1

t38 CPU_STP# and PCI_STP# Active to SUS[A]# Active 1 RTC 1

t39 CPU_STP# and PCI_STP# Active to Clocks Stopped (if applicable) 2 PCICLK 4, 5

NOTES:1. These signals are controlled from an internal RTC clock. One RTC unit is approximately 32 µs.2. CPU_STP# and PCI_STP# will only be active when the system is under clock control. 3. This transition waits for the Stop Grant cycle to execute.4. It is up to the system vendor to determine whether CPU_STP# and PCI_STP# signals are used to control

system clocks.5. See Figure 38 and Figure 39 for exact PCICLK requirements for use with PC/PCI DMA and Serial IRQs.

t36

38

t37

t39

t35

t34

Clocks Running

Running

Clocks Stopped

Inactive

PWROK

SUS_STAT[1-2]#

SUS[A]#

SUS[B-C]#

SUSCLK

CPU_STP# / PCI_STP#

PCICLK / CPU CLK

PCI_RST#

CPURST

SLP#

STPCLK#


Design Guide 93

8.1.5.3 POS to On (with Processor and PCI Reset)

Figure 44 describes the system transition from Power On Suspend to On with a full system reset. Table 65 indicates the POS to On timing tolerances.

Figure 44. POS to On (with Processor and PCI Reset)

Table 65. POS to On Timing Tolerances


t40 Resume Event to SUS[A]# Inactive 1 RTC 1t41 Resume Event to PCI_RST# Active 1 RTC 1t42 Resume Event to CPURST Active 1 RTC 1t43 Resume Event to SLP# Inactive 1 RTC 1t44 Resume Event to STPCLK# Inactive 1 RTC 1

t45 SUS[A]# Inactive to PCI_STP# and CPU_STP# Inactive 16 ms 2

t46 PCI_STP# and CPU_STP# Inactive to Clocks Running 2 PCICLK 3

t47 PCI_STP# and CPU_STP# Inactive to SUS_STAT[1:2]# Inactive 1 ms


t49 PCI_RST# Inactive to PCI_STP# and CPU_STP# allowed to change 1 RTC 1

t50 PCI_RST# Inactive to CPURST Inactive 1 RTC 1NOTES:1. These signals are controlled from an internal RTC clock. One RTC unit is approximately 32 µs.2. This transition requires a minimum of 16 ms wait for the clock synthesizer PLL to lock and PWROK to be

active. When PWROK goes active after 16 ms from SUS[A:C]# inactive, the transition will occur a minimum of one RTC period from PWROK active. PWROK remains active throughout POS system usage.

3. See Figure 38 and Figure 39 for exact PCICLK requirements for use with PC/PCI DMA and Serial IRQs.

t47

t40

t45 t49

t46

t41 t48

t42 t50

t43

t44

Clocks Stopped Clocks Running

Running

Inactive Active Inactive

Resume Event

PWROK

SUS_STAT[1-2]#

SUS[A]#

SUS[B-C]#

SUSCLK

CPU_STP# / PCI_STP#

PCICLK / CPU CLK

PCI_RST#

CPURST

SLP#

STPCLK#


94 Design Guide

8.1.5.4 POS to On (with Processor Reset)

Figure 45 describes the system transition from Power On Suspend (POS) to On with only a processor reset. Table 66 indicates the POS to On (with processor reset) timing tolerances.

Figure 45. POS to On (with Processor Reset)

Table 66. POS to On (with Processor Reset) Timing Tolerances


t51 Resume Event to SUSA# Inactive 1 RTC 1

t52 Resume Event to CPURST Active 1 RTC 1

t53 Resume Event to SLP# Inactive 1 RTC 1

t54 Resume Event to STPCLK# Inactive 1 RTC 1




t58 SUS_STAT[1:2]# Inactive to PCI_STP# and CPU_STP# allowed to change 2 RTC 1

t59 SUS_STAT[1:2]# Inactive to CPURST Inactive 2 RTC 1

NOTES:1. These signals are controlled from an internal RTC clock. One RTC unit is approximately 32 µs.2. This transition requires both a minimum of 16 ms wait for the clock synthesizer PLL to lock and PWROK to

be active. When PWROK goes active after 16 ms from SUS[A:C]# inactive, the transition will occur a minimum of one RTC period from PWROK active. PWROK remains active throughout POS system usage.


t57

t51

t55 t58

t56

t52 t59

t53

t54


Running

Inactive Active Inactive

Resume Event

PWROK

SUS_STAT[1-2]#

SUS[A]#

SUS[B-C]#

SUSCLK

CPU_STP# / PCI_STP#

PCICLK / CPU CLK

PCI_RST#

CPURST

SLP#

STPCLK#


Design Guide 95

8.1.5.5 POS to On (No Reset)

Figure 46 describes the system transition from Power On Suspend to On with no resets performed. Table 67 indicates the POS to On (no reset) timing tolerances.

Figure 46. POS to On (No Reset)

Table 67. POS to On (No Reset) Timing


t60 Resume Event to SUS[A]# Inactive 1 RTC 1




t64 SUS_STAT[1:2]# Inactive to PCI_STP# and CPU_STP# allowed to change 2 RTC 1

t65 SUS_STAT[1:2]# Inactive to SLP# Inactive 1 RTC 1

t66 SLP# Inactive to STPCLK# Inactive 1 RTC 1

NOTES:1. These signals are controlled from the internal RTC clock. One RTC is approximately 32 µs.2. This transition requires both a minimum of 16 ms wait for the clock synthesizer PLL to lock and PWROK to

be active. When PWROK goes active after 16 ms from SUS[A:C]# inactive, the transition will occur a minimum of one RTC period from PWROK active. PWROK remains active throughout POS system usage.


t63

t60

t61 t64

t62

t65

t66


Running

Inactive

Resume Event

PWROK

SUS_STAT[1-2]#

SUS[A]#

SUS[B-C]#

SUSCLK

CPU_STP# / PCI_STP#

PCICLK / CPU CLK

PCI_RST#

CPURST

SLP#

STPCLK#


96 Design Guide

8.1.5.6 On to STR

Figure 47 describes the signal transitions from On state to Suspend to RAM state. Table 68 indicates the On to STR timing tolerances.

Figure 47. On to STR

t73

t80

t69

t72

t70 t74 t81

t71 t79

t75 t82

t76 t83

t68 t77 t84

t67 t78 t85

Running

Invalid

Running Stopped

Inactive Active

Invalid

Invalid

Invalid

Invalid

Invalid

Float

PWROK

Core Well Power

SUS STAT[1-2]#

SUS[A-B]#

SUS[C]#

SUSCLK

CPU STP# /PCI_STP#

PCICLK / CPU CLK

PCI_RST#

CPURST

SLP#

STPCLK#


Design Guide 97

Table 68. On to STR Timing Tolerances






t71 CPU_STP# and PCI_STP# Active to CLOCKS Stopped 2 PCICLK 4, 5

t72 CPU_STP# and PCI_STP# Inactive to SUS[A:B]# Active 1 RTC 1

t73 SUS[A:B]# Active to PWROK Inactive 0 ns 6

t74 PWROK Inactive to CPU_STP# and PCI_STP# Float 1 RTC 1

t75 PWROK Inactive to PCI_RST# Active 1 RTC 1

t76 PWROK Inactive to CPURST Active 1 RTC 1

t77 PWROK Inactive to SLP# Inactive 1 RTC 1

t78 PWROK Inactive to STPCLK# Inactive 1 RTC 1

t79 CPU_STP# and PCI_STP# Float to Clocks Invalid 0 ns 7

t80 PWROK Inactive to Core Well Power Removed 0 ns

t81 Core Well Power Removed to PCI_STP# and CPU_STP# Invalid 0 ns

t82 Core Well Power Removed to PCIRST# Invalid 0 ns

t83 Core Well Power Removed to CPURST Invalid 0 ns

t84 Core Well Power Removed to SLP# Invalid 0 ns

t85 Core Well Power Removed to STPCLK# Invalid 0 ns

NOTES:1. These signals are controlled from the internal RTC clock. One RTC is approximately 32 µs.2. CPU_STP# and PCI_STP# will only be active if the system is under clock control. 3. This transition will also wait for the Stop Grant cycle to execute.4. It is up to the system vendor to determine if CPU_STP# and PCI_STP# signals are used to control system

clocks.5. See Figure 38 and Figure 39 for exact PCICLK requirements for use with PC/PCI DMA and Serial IRQs.6. It is up to the system vendor to determine if SUS[A:B]# signals are used to control system power planes.

When power remains applied to system board and PWROK stays active during STR, the PIIX4E signals will remain in the states shown after t73.

7. Clocks may or may not be running depending on the condition of the Power Supply voltages.


98 Design Guide

8.1.5.7 STR to On

Figure 48 describes the system transition from Suspend To RAM to On with a full system reset. Table 56 indicates the STR to On timing tolerances.

Figure 48. STR to On

t94

t87

t100

t86

t88 t95t98

t97

t101

t93 t96 t99

t89 t101a

t90 t102

t91

t92

Invalid Float

Running

Invalid Running

Invalid Active Inactive

Invalid

Invalid

Invalid

Running Stopped

Resume Event

PWROK

Core Well Power

SUS_STAT[1-2]#

SUS[A-B]#

SUS[C]#

SUSCLK

CPU_STP# /PCI_STP#

PCICLK / CPU CLK

PCI_RST#

CPURST

SLP#

STPCLK#


Design Guide 99

Table 69. STR to On Timing Tolerances


t86 Resume Event to SUS[A:B]# Inactive 1 RTC 1

t87 SUS[A:B]# Inactive to Core Well Power Applied 0 ns

t88 Core Well Power Applied to PCI_STP# and CPU_STP# Float 0 ns

t89 Core Well Power Applied to PCI_RST# Active 0 ns

t90 Core Well Power Applied to CPURST Active 0 ns

t91 Core Well Power Applied to SLP# Inactive 0 ns

t92 Core Well Power Applied to STPCLK# Inactive 0 ns

t93 PCI_STP# and CPU_STP# Float to Clocks Running 2

t94 Core Well Power Applied to PWROK Active 1 ms

t95 PWROK Active to CPU_STP# and PCI_STP# Active 0 ns

t96 PCI_STP# and CPU_STP# Active to Clocks Stopped 2 PCICLK 3

t97 PWROK Active to CPU_STP# and PCI_STP# Inactive 1 RTC 1

t98 SUS[A-B]# Inactive to CPU_STP# and PCI_STP# Inactive 16 ms

t99 CPU_STP# and PCI_STP# Inactive to Clocks Running 2 PCICLK 3

t100 CPU_STP# and PCI_STP# Inactive to SUS_STAT[1-2]# Inactive 1 ms

t101 SUS_STAT[1-2]# Inactive to CPU_STP# and PCI_STP# allowed to change 2 RTC 1

t101a SUS_STAT[1-2]# Inactive to PCI_RST# Inactive 1 RTC 1


NOTES:1. These signals are controlled from the internal RTC clock. One RTC is approximately 32 µs. 2. There are no specific requirements for these timings related to the PIIX4E. The system manufacturer

should make sure that the clocks meet any other system specifications upon power up. At a minimum, the clocks must be available and stable after time t99.

3. See Figure 38 and Figure 39 for exact PCICLK requirements for use with the PC/PCI DMA and Serial IRQs.


100 Design Guide

8.1.5.8 On to STD/SOff

Figure 49 describes the signal transitions from the On state to the Suspend to Disk/Soft Off state. Table 70 indicates the On to STD/SOff timing tolerances.

Figure 49. On to STD/SOff

t110

t117

t105

t108

t109

t106 t111 t118

t107 t116

t112 t119

t113 t120

t104 t114 t121

t103 t115 t122

Running

Invalid

Running Stopped

Inactive Active

Invalid

Invalid

Invalid

Invalid

Invalid

Float

PWROK

Core Well Power

SUS_STAT[1-2]#

SUS[A-C]#

SUSCLK

CPU_STP# / PCI_STP#

PCICLK / CPU CLK

PCI_RST#

CPURST

SLP#

STPCLK#


Design Guide 101

Table 70. On to STD/SOff Timing Tolerances






t107 CPU_STP# and PCI_STP# Inactive to CLOCKS Stopped 2 PCICLK 1, 4, 5

t108 CPU_STP# and PCI_STP# Inactive to SUS[A:C]# Active 1 RTC 1

t109 SUS[A:C]# Active to SUSCLK Low 1 RTC 1

t110 SUS[A:C]# Active to PWROK Inactive 0 ns 6

t111 PWROK Inactive to CPU_STP# and PCI_STP# Float 1 RTC 1

t112 PWROK Inactive to PCI_RST# Active 1 RTC 1

t113 PWROK Inactive to CPURST Active 1 RTC 1

t114 PWROK Inactive to SLP# Inactive 1 RTC 1

t115 PWROK Inactive to STPCLK# Inactive 1 RTC 1

t116 CPU_STP# and PCI_STP# Float to Clocks Invalid 0 ns 1

t117 PWROK Inactive to Core Well Power Removed 0 ns

t118 Core Well Power Removed to PCI_STP# and CPU_STP# Invalid 0 ns

t119 Core Well Power Removed to PCIRST# Invalid 0 ns

t120 Core Well Power Removed to CPURST Invalid 0 ns

t121 Core Well Power Removed to SLP# Invalid 0 ns

t122 Core Well Power Removed to STPCLK# Invalid 0 ns

NOTES:1. These signals are controlled from the internal RTC clock. One RTC is approximately 32 µs.2. CPU_STP# and PCI_STP# will only be active if the system is under clock control. 3. This transition will also wait for the Stop Grant cycle to execute.4. It is up to the system vendor to determine if CPU_STP# and PCI_STP# signals are used to control system

clocks.5. See Figure 38 and Figure 39 for exact PCICLK requirements for use with the PC/PCI DMA and Serial

IRQs.6. It is up to the system vendor to determine if SUS[A:C]# signals are used to control system power planes.

When the power remains applied to the system board and the PWROK stays active during STD, the PIIX4E signals will remain in the states shown after t110.


102 Design Guide

8.1.5.9 STD/SOff to On

Figure 50 describes the system transition from Suspend To Disk/Soft Off to On with a full system reset. Table 71 indicates the STD/SOff to On timing tolerances.

Figure 50. STD/SOff to On

t131

t124

t137

t123

t138

t125 t132t135

t134

t140

t130 t133 t136

t126 t139

t127 t141

t128

t129

Invalid Float

Running

Invalid Running

Invalid Active Inactive

Invalid

Invalid

Invalid

Running Stopped

Resume Event

PWROK

Core Well Power

SUS_STAT[1-2]#

SUS[A-C]#

SUSCLK

CPU_STP# / PCI_STP#

PCICLK / CPU CLK

PCI_RST#

CPURST

SLP#

STPCLK#


Design Guide 103

Table 71. STD/SOff to On Timing Tolerances


t123 Resume Event to SUS[A:C]# Inactive 1 RTC 1

t124 SUS[A-C]# Inactive to Core Well Power Applied 0 ns

t125 Core Well Power Applied to PCI_STP# and CPU_STP# Float 0 ns

t126 Core Well Power Applied to PCI_RST# Active 0 ns

t127 Core Well Power Applied to CPURST Active 0 ns

t128 Core Well Power Applied to SLP# Inactive 0 ns

t129 Core Well Power Applied to STPCLK# Inactive 0 ns

t130 PCI_STP# and CPU_STP# Float to Clocks Running 2

t131 Core Well Power Applied to PWROK Active 1 ms

t132 PWROK Active to CPU_STP# and PCI_STP# Active 0 ns

t133 PCI_STP# and CPU_STP# Active to Clocks Stopped 2 PCICLK 3

t134 SUS[A-C]# Inactive to CPU_STP# and PCI_STP# Inactive 16 ms

t135 PWROK Active to CPU_STP# and PCI_STP# Inactive 1 RTC 1

t136 PCI_STP# and CPU_STP# Active to Clocks Running 1 2 PCICLK 3

t137 CPU_STP# and PCI_STP# Inactive to SUS_STAT[1:2]# Inactive 1 ms

t138 SUS_STAT[1:2]# Inactive to SUSCLK Running 1 RTC 1


t140 SUS_STAT[1:2]# Inactive to CPU_STP# and PCI_STP# allowed to change 2 RTC 1


1. These signals are controlled from the internal RTC clock. One RTC is approximately 32 µs.2. There are no specific requirements for these timings related to the PIIX4E. The system manufacturer

should make sure that the clocks on power up meet any other system specifications. At a minimum, the clocks must be available and stable after time t136.

3. See Figure 38 and Figure 39 for exact PCICLK requirements for use with the PC/PCI DMA and Serial IRQs.


104 Design Guide

8.2 82443BX Host Bridge/Controller Power Sequencing

8.2.1 Power Sequencing Requirements

In systems requiring 5 V tolerance, the REF5V signal must be tied to 5 V. This signal must power up before or simultaneous to VCC. It must power down after or simultaneous to VCC. In a non-5 V tolerant system (3.3 V only), this signal may be tied directly to VCC. There are then no sequencing requirements. Refer to Figure 51 for an example circuit schematic that may be used to ensure the proper REF5V sequencing. This is the same circuit that is recommended for the PIIX4E VREF supply. However, different power planes may supply the PIIX4E core and the 82443BX Host Bridge/Controller (the PIIX4E core may be powered down during STR). In this case a separate circuit must be used for each of the two devices.

VCC must power up before or simultaneous to the AGP supplies (VCC_AGP and AGP_REF) and Low Power GTL+ supplies (VTT and GTL_REF). VCC must power down after or simultaneous to the AGP and Low Power GTL+ supplies. The AGP and Low Power GTL+ supplies must not be powered up while VCC is powered down. There are no other power sequencing requirements for the 82443BX Host Bridge/Controller.

8.2.2 Intel® 440BX AGPset Power Management

The Intel® 440BX AGPset supports a variety of system-wide low-power modes using the following functions:

• Hardware interface with the PIIX4E that is used to indicate:

— Suspend mode entry— Resume from suspend— Whether to automatically switch from suspend to normal refresh

• Automatic transition from normal to suspend refresh

• Optional automatic transition from suspend to normal refresh

• Optional CPU reset during resume from Power On Suspend (POS)

• Variety of Suspend refresh types:

— Self Refresh for SDRAMs— Optional Self Refresh for EDO— Optional CAS Before RAS (CBR) refresh for EDO. An Integrated Ring oscillator is used

to provide the time base for the associated logic.

Figure 51. REFVCC5 Supply Circuit Schematic

VCC Supply(3.3V)

5V Supply

1k

1 uF

REFVCC5To System To System

SchottkyDiode


Design Guide 105

— Programmable slow refresh (relevant for CBR refresh only)

• Isolated I/O pins to significantly reduce power consumption while in POS and STR modes

Based on the above functions, the Intel® 440BX AGPset recognizes the following system-wide low power modes:

• STR and POS suspend entry and exit are generally handled in the same manner. The following exceptions are related to POS mode:— The POS resume sequence may or may not include a processor reset. STR, with PCIRST#

active always includes a processor reset.— The POS resume sequence requires a hardware transition from suspend to a normal

refresh. STR with PCIRST# active requires a software initiated transition.

• STD resume is handled in the same way as the power on sequence, including a complete reset of the Intel 440BX AGPset state.

8.2.2.1 System Power Modes

Table 72 provides an overview of how the above features map into system-wide low power modes.

Table 72. System-wide Low-power Modes (Sheet 1 of 2)

System Suspend State

82443BX State Description

POS Exit

PCIRST

External ClkHCLK PCLK

Power On ON

82443BX AGPset is fully on and operating normally.

Internal clock gating as well as PCI CLKRUN# may be enabled.

N/A Active Active

CPU STOP_GRANT or

QUICK_START (C2)

ON

This is transparent to the Intel 82443BX AGPset since the external HCLK and PCLK are unaffected. The Host Bus is Idle.

Internal clock gating and PCI CLKRUN# may be enabled.

N/A Active Active

CPU STOP CLOCK (C3)

(DEEP SLEEP)POS

System PLLs remain powered, but are disabled. HCLK clock is kept low. The only guaranteed running clock is SUSCLK.

The 82443BX maintains DRAM refresh using suspend refresh.

The Intel 82443BX’s internal PLLs are disabled.

The 82443BX PCI and AGP arbiters are disabled.

N Low Low or Active

NOTE: The processor will generally be powered off during STR (the processor voltage regulator will be controlled by the PIIX4E’s SUSB# signal). In this case, the 82443BX Low Power GTL+ supply (VTT and GTL_REF) should also be controlled by SUSB#, and hence be powered off during STR.


106 Design Guide

Power On Suspend (POS) POS

System PLLs are powered down. The only running clock is the RTC clock and SUSCLK. The 82443BX maintains DRAM refresh using suspend refresh.

The 82443BX’s PLLs are disabled.

The 82443BX PCI and AGP arbiters are disabled.

When resumed, the 82443BX may or may not generate a processor reset.

All 82443BX logic, with the exception of resume and refresh, are inactive.

Y Low Low

Suspend to RAM(STR) POS

The processor and other components (with the exception of the DRAM and PIIX4E resume logic) are assumed to be powered OFF.

The 82443BX VCC supply is on and all I/O buffers are isolated (with the exception of suspend and DRAM signals).

The 82443BX Low Power GTL+ supplies should be powered down with the processor.

The 82443BX maintains DRAM refresh using a suspend refresh.

All 82443BX logic, with the exception of resume and refresh, are inactive.

Y Low Low

Suspend -to-Disk (STD) or Powered-Off

OFFThe entire system is powered OFF except for the PIIX4E resume and RTC wells. Upon resume, the 82443BX resets its entire state.

N/A X X

Table 72. System-wide Low-power Modes (Sheet 2 of 2)

NOTE: The processor will generally be powered off during STR (the processor voltage regulator will be controlled by the PIIX4E’s SUSB# signal). In this case, the 82443BX Low Power GTL+ supply (VTT and GTL_REF) should also be controlled by SUSB#, and hence be powered off during STR.


Design Guide 107

8.2.2.2 System Power-up Sequencing

The waveforms in Figure 52 show the powerup sequence and timing information for the Intel® 440BX AGPset. Table 73 indicates the system power-up sequencing tolerances.

Figure 52. System Power-up Sequencing

PIIX4EVCC(SUS)

RSMRST#

SUS[C:A]#

PIIX4EVCC(CORE)

PIIX4EPWROK

SUS_STAT#

CPU_STP#PCI_STP#

FLOAT

PCIRST#

BX_VCC

BXPWROK

CPURST#

1

2

4

7

8

13

14

16

17

15

CLOCKS RUNNING

3

5

6

9

10

11

12

18


108 Design Guide

Table 73. System Power-up Sequencing Tolerances

Sym Parameter Min Max Units Notes

t1 PIIX4E VCC(SUS) nominal to SUS[C:A]# active 1 RTC 1

t2 PIIX4E VCC(SUS) nominal to SUS_STAT[2:1]# active 1 RTC 1

t3 PIIX4E VCC(SUS) nominal to RSMRST# active 1 ms

t4 RSMRST# inactive to SUS[C:A]# inactive 1 2 RTC 1

t5 SUS[B]# inactive to PIIX4E VCC(CORE) nominal 0 ms

t6 SUS[C]# inactive to BX_VCC nominal 0 ms

t7 PIIX4E VCC(CORE) nominal to CPU_STP#, PCI_STP# float 1 RTC 1

t8 PIIX4E VCC(CORE) nominal to PCIRST# active 1 RTC 1

t9 PIIX4E VCC(CORE) nominal to PIIX4E PWROK active 1 ms

t10 BX_VCC nominal to CPURST# active 10 ns

t11 BX_VCC nominal to BXPWROK active 1 ms

t12 BXPWROK active to PIIX4E PWROK active 0 ns 2

t13 PIIX4E PWROK active to CPU_STP#, PCI_STP# active 1 RTC 1

t14 SUS[C:A]# inactive to CPU_STP#, PCI_STP# inactive 16 ms 3

t15 CPU_STP#, PCI_STP# inactive to clocks running 2 PCICLK

t16 CPU_STP#, PCI_STP# inactive to SUS_STAT[2:1]# inactive 1 ms

t17 SUS_STAT[2:1]# inactive to PCIRST# inactive 1 RTC 1

t18 PCIRST# inactive to CPURST# inactive 1 ms

NOTES:1. One RTC unit is approximately 32 µs2. This parameter only applies if BXPWROK will not transition to an active state within 15 ms of SUS[C:A]#

de-assertion3. This transition requires both a minimum of 16 ms wait for the clock synthesizer PLL lock and PIIX4

PWROK to be active. When PWROK goes active after 16 ms from SUS[C:A]# inactive, the transition will occur a minimum of one RTC period from PWROK active.


Design Guide 109

8.2.2.3 Suspend Resume Protocols

The suspend resume sequences are indicated to the 82443BX by the PIIX4E, using SUS_STAT# and PCIRST#. In addition, the 82443BX contains NREF_EN and CRst_En configuration bits that participate in the suspend resume sequences.

As a result of suspend resume, the 82443BX performs the following activities:

• Changing its refresh mode

• Performing internal and processor reset

• Isolate or re-enable normal IO buffers

Table 74 indicates the suspend resume events and activities.

The requirements for suspending the 82443BX are:

• The system must be idle when SUS_STAT# is asserted. There must be no active processor or bus masters’ cycles and there must be no meaningful pending cycle’s information in a chipset or peripheral device’s buffers.

• After the assertion of SUS_STAT#, the PIIX4E provides the 82443BX 32 µs with stable power and clocks to perform the necessary suspend sequence.

• The PCICLK must not be stopped with CLKRUN# during the suspend sequence.

• The 82443BX isolates its IO buffers within less than 32 µs time allocated from SUS_STAT# assertion.

— The 82443BX does not isolate PCIRST# (being pulled up) or clock inputs. The clock inputs are driven low by the clock synthesizer, and 32 µs later the clock synthesizer device may be powered down.

The requirements for resuming the 82443BX are:

• Power and clocks must be stable for at least 1 ms before SUS_STAT# is deasserted.

• When resuming from POS, STPCLK# remains active for about 100 µs after SUS_STAT# deassertion, to allow an automatic switch to normal DRAM operation before processor pending cycles take place.

The 82443BX provides isolation of its I/O buffers during POS and STR. During the events that were specified in Table 74, the isolation takes effect. Table 75 provides information about the state of each of the 82443BX signals during POS and STR.

Table 74. Suspend Resume Events And Activities

SUSSTAT# PCIRST# CrstEn Reset Refresh I/O Buffers

Assert Inactive - - Switch to suspend refresh Isolate

Deassert Active -

Reset exclude

resume/ref logic

Suspend refresh

NREF_EN remains inactive

Enable

Deassert Inactive 0 No resetsAuto switch to normal ref

NREF_EN is setEnable

Deassert Inactive 1Reset

processor only

Auto switch to normal ref

NREF_EN is setEnable


110 Design Guide

Table 75. Intel® 440BX AGPset Signal States During POS and STR Modes (Sheet 1 of 2)

Signal Name State During POS/STR

CPURST# Three-state

A[31:3]# Three-state

HD[63:0]# Three-state

ADS# Three-state

BNR# Three-state

BPRI# Three-state

DBSY# Three-state

DEFER# Three-state

DRDY# Three-state

HIT# Three-state

HITM# Three-state

HLOCK#

HREQ[4:0]# Three-state

HTRDY# Three-state

RS[2:0]# Three-state

RASA[5:0]# / CSA[5:0]# High1

RASB[5:0]# / CSB[5:0]# High1

CKE[3:2] / CSA[7:6]# Low/High2

CKE[5:4] / CSB[7:6]# Low/High2

CASA[7:0]# / DQMA[7:0]# High1

CASB[5,1]# / DQMB[5,1]# High1

GCKE / CKE1 Low/High2

SRAS[B:A]# Low/High2

CKE0 / FENA Low/High2

SCAS[B:A]# High/Low2

MAA[13:0] Driven3

MAB[9:7]# / MAB[13,10] Driven3

MAB[12:11]# Driven3

MAB[6:0]# Driven3

WEA#, WEB# High

MD [63:0] Driven3

MECC[7:0] Driven3

AD[31:0] Low

DEVSEL# Three-state

FRAME# Three-state

IRDY# Three-state

C/BE[3:0]# Low

PAR Low

PLOCK# Three-state

NOTES:1. SDRAM Mode: After putting the SDRAMs into self-refresh mode, these signals are driven high. EDO

Mode: For self-refresh mode, RAS and CAS are driven low. Otherwise, the 82443BX continues to refresh during the POS/STR state.

2. SDRAM Mode: SRAS#, SCAS#, CKE[5:0] and GCKE are driven to the first value listed. EDO Mode: These signals are driven to the second value listed.

3. MA lines are always driven by the 82443BX, except for MAB[13:11,9:0]# and MAB10, which are three-stated during reset. MD/MECC are always driven by the 82443BX when there is no active cycle. The values driven on MA, MD and MECC are indeterminate during and after reset.


Design Guide 111

TRDY# Three-state

SERR# Three-state

STOP# Three-state

PHOLD# Three-state

PHLDA# Three-state

WSC# Three-state

PREQ[4:0]# Three-state

PGNT[4:0]# Three-state

PIPE# Three-state

SBA[7:0] Three-state

RBF# Three-state

ST[2:0] Low

AD_STBA Three-state

AD_STBB Three-state

SB_STB Three-state

G_FRAME# Three-state

G_IRDY# Three-state

G_TRDY# Three-state

G_STOP# Three-state

G_DEVSEL# Three-state

G_REQ# Three-state

G_GNT# Three-state

G_AD[31:0] Low

G_C/BE[3:0]# Low

G_PAR Low

HCLKIN

PCLKIN

DCLKO Low

DCLKRD

DCLKWR

CRESET# Three-state

PCIRST#

GCLKIN

GCLKO Low

TESTIN#

SMBCLK Three-state

SMBDATA Three-state

CLKRUN# Three-state

SUSTAT#

Table 75. Intel® 440BX AGPset Signal States During POS and STR Modes (Sheet 2 of 2)

Signal Name State During POS/STR

NOTES:1. SDRAM Mode: After putting the SDRAMs into self-refresh mode, these signals are driven high. EDO

Mode: For self-refresh mode, RAS and CAS are driven low. Otherwise, the 82443BX continues to refresh during the POS/STR state.

2. SDRAM Mode: SRAS#, SCAS#, CKE[5:0] and GCKE are driven to the first value listed. EDO Mode: These signals are driven to the second value listed.

3. MA lines are always driven by the 82443BX, except for MAB[13:11,9:0]# and MAB10, which are three-stated during reset. MD/MECC are always driven by the 82443BX when there is no active cycle. The values driven on MA, MD and MECC are indeterminate during and after reset.


112 Design Guide

8.2.2.4 82443BX Suspend/Resume Sequences and Timing

Table 76 indicates the suspend/resume timing tolerances for Figure 53 through Figure 56.

Table 76. Suspend/Resume Timing Tolerances

Sym Parameter Min Max Unit

t1 BX_VCC stable to BXPWROK asserted. † 1 ms

t2 BXPWROK asserted to SUS_STAT# inactive 1 ms

t3 Clocks running to SUS_STAT# inactive, ensure 1 ms

t4 BX_VCC active and BXPWROK inactive to CPURST# active 10 ns

t5 SUS_STAT# deasserted to PCIRST# de-asserted, ensure 32 µs

t6 PCIRST# deasserted to CPURST# deasserted 1 ms

t7 SUS_STAT# deasserted to buffers valid 2 HCLK

t8 SUS_STAT# asserted to clocks stopped, ensure 32 µs

t9 SUS_STAT# asserted to suspend refresh 32 µs

t10 SUS_STAT# asserted to buffers isolated 32 µs

t11 PCIRST# asserted to CPURST# asserted 10 ns

t12 PCIRST# asserted to SUS_STAT# de-asserted, ensure 1 ms

t13 SUS_STAT# de-asserted to normal refresh 32 µs

t14 SUS_STAT# de-asserted to CPURST# asserted 0 4 HCLK

t15 CPURST# pulse width 1 ms

† “BX_VCC stable” means BX_VCC is within the specified Functional Operating Range.


Design Guide 113

8.2.2.5 Suspend/Resume with PCIRST# Active

The following resume sequence is typically used when resuming from STR. It includes the following components:

• BXPWROK must transition from inactive (low) to active (high) a minimum of 1 ms after BX_VCC is within the specified Functional Operating Range.

• When 15 ms or more may elapse from the time that the PIIX4E deasserts SUS[C:A]# until BXPWROK is asserted, BXPWROK must be asserted before or simultaneous to PWROK being asserted to the PIIX4E.

• Upon resume, the 82443BX detects that the PCIRST# signal is active (low) and drives CPURST# to the processor. Note that CPURST# is driven active based on PCIRST# timing, independent of SUS_STAT# timing.

• Based on the assertion of SUS_STAT#, the 82443BX isolates its I/O buffer within 32 µs.

• Based on the deassertion of SUS_STAT#, the 82443BX enables its I/O buffer to normal operation within 32 µs. Clock inputs and PCIRST# are never gated by the 82443BX and thus affect it before the deassertion of SUS_STAT#.

• Software must release the memory controller from its suspend refresh state to its normal refresh state.

• The 82443BX clears its internal state, with the exception of resume/refresh logic, since it sampled PCIRST# asserted.

Figure 53 shows the suspend resume sequence with PCIRST# active.

Figure 53. Suspend/Resume with PCIRST# Active

SUS_STAT#

BX_VCC

BXPWROK

CLOCKS Running

PCIRST#

CPURST#

1

2

4 5 6

Running

Normal Refresh Suspend Refresh Normal Refresh

Buffers valid Buffers valid

Refresh

Buffers

7

8

9

10

11

3

12

6

5

7

13

OFF RESET ON ONSUSPEND

3

12


114 Design Guide

8.2.2.6 Suspend/Resume with CPURST#, PCIRST# Inactive

The following resume sequence is typically used when resuming from POS. It includes the following components:

• Since PCIRST# signal is inactive, per resume the 82443BX does not drive CPURST# to the processor, since CrstEn is ‘0’.


• Based on the deassertion of SUS_STAT#, the 82443BX enables its I/O buffer to normal operation within 32 µs.

• The 82443BX switches from suspend refresh to normal DRAM operation mode.

• The processor starts execution from the instruction just prior to the stop grant request being recognized. The 82443BX switches to normal DRAM operation before the deassertion of STPCLK#.

• The 82443BX state is not reset.

Figure 54 shows the suspend/resume sequence with CPURST#, PCIRST# inactive.

Figure 54. Suspend/Resume with CPURST#, PCIRST# Inactive

SUS_STAT#

BX_VCC

BXPWROK

CLOCKS Running

PCIRST#

CPURST#

1

2

5 6

Running



Refresh

Buffers

7

8

9

10

3

7

13

OFF RESET ON SUSPEND ON

4

3

12


Design Guide 115

8.2.2.7 Suspend/Resume with CPURST Active, PCIRST# Inactive

The following resume sequence is typically used when resuming from POS. It includes the following components:

• The PCIRST# signal is inactive, upon resume the 82443BX drives CPURST# to the processor since CrstEn is ‘1’. CPURST# is active for 1 ms.


• Based on the deassertion of SUS_STAT#, the 82443BX enables its I/O buffer to normal operation within 32 µs.

• The 82443BX automatically switches from suspend refresh to normal DRAM operation mode when SUS_STAT# deassertion is detected.

• The 82443BX state is not reset.

Figure 55 shows the suspend/resume sequence with CPURST# active, PCIRST# inactive.

Figure 55. Suspend/Resume with CPURST# Active, PCIRST# Inactive

SUS_STAT#

BX_VCC

BXPWROK

CLOCKS Running

PCIRST#

CPURST#

1

2

5 6

Running



Refresh

Buffers

7

8

9

10

3

7

13


14 154

3

12


116 Design Guide

8.2.2.8 Suspend/Resume from STD

The following resume sequence is typically used when resuming from STD. It includes the following components:

• When BXPWROK is sampled low ‘0’, the 82443BX undergoes a complete reset and asserts CPURST#.

• Based on the deassertion of SUS_STAT#, the 82443BX enables its buffer to normal operation within less than 32 µs. Clock inputs and PCIRST# are never gated by the 82443BX and thus affect it before the deassertion of SUS_STAT#.

• Software must release the memory controller from its suspend refresh state to its normal refresh state, and enable refresh with the appropriate refresh rate.

Figure 56 shows the suspend/resume sequence from STD.

Figure 56. Suspend/Resume from STD

SUS_STAT#

BX_VCC

BXPWROK

CLOCKS Running

PCIRST#

CPURST#

5 6

Running

Normal Refresh Norm

Buffers valid Valid

Refresh

Buffers

7

8

9

10


3

1 1

2 2

RESET

4

7

3

12

4

12


Design Guide 117

Appendix A Bill of Materials

Table 77 is the bill of materials for the Intel® Pentium® III processor — Low Power/440BX AGPset Reference Design.

Table 77. Bill of Materials (Sheet 1 of 8)

Rev. A0

Reference Designator Description Manufacturer Manufacturer

P/N Comments Alternate Manufacturing Info

J14, J15 Conn, Jumper2,1X2 25-mil sq/100-mil space, HDR2 3M 929647-09-02

J20-24 Conn, Jumper3,1X3 25-mil sq/100-mil space, HDR3 3M 929647-09-03

J12 Conn, Fan AMP 173981-3

XU9 PLCC, Socket 28 AMP 822271-1

U6 IC, Clock Generator, CK100, SSOP300-48(PIN) Cypress CY2280PVC-11S

U16 IC, Clock Buffer, 18 Output low skew, SSOP300-48(PIN) Cypress CY2318ANZPVC-1

Y2 Crystal, 32.768KHz,XTAL/MC-405 Epson MC-405

J4 Conn, Serial Stack, DB9MX2 FOXCONN DM10156-73

J3 Conn, DB25, DB25FM1 FOXCONN DT11323-R5T

J7, J8, J9 Conn, PCI Edge Recept., 145154-120 FOXCONN EH06001-PC-W

J5, J6 Conn, ISA Edge Recept., isa-98 FOXCONN EQ04901-S6

JP1 Conn, Floppy, 17X2 Header FOXCONN HL07173-P4

JP3, JP4 Conn, IDE, 20X2 Header FOXCONN HL07206-D2

J11 Conn, Power, 5566DP-20/ATX FOXCONN HM20100-P2

J1 Conn, PS2 Keyboard / Mouse Connector FOXCONN MH11067-D2

J13 Conn, AGP Edge Recept., 120 pins, AGP-124 FOXCONN PC1243K-10

J2 2 USB Stack Connectors FOXCONN UB1112C-D3

U11 BIOS FLASH Memory, TSOP12X20/40S INTEL E28F004B5T60

U8VLSI, PIIX4, PCI to IDE and ISA Bridge, 324 mBGA, BGA20x20-324

Intel FW82371EB

C99, C100, C132, C133,

Chip Capacitor, 10pF, 50 V, CC0603 Kemet C0603C100J5GAC


118 Design Guide

C22, C42-43, C48-49, C54, C59-65, C70-71, C73, C75-76, C85-87, C90-92, C96-97, C102, C106-108,C111-112, C114, C116-118,C126-127, C129-131, C142, C147, C157, C159-162, C174-176, C181-183, C187-200, C205-206, C208, C226-228

Chip Capacitor, 0.1 uF, 16 V, CC0603 Kemet C0603C104K4RAC

DO NOT POPULATE C143, C146, C203, C210, C215

C27-C41, C44-C47,C50-C53

Chip Capacitor, 470 pF, 50 V, CC0603 Kemet C0603C471K5RAC

C3-5, C8, C55-57, C94, C119-121, C134, C138, C145, C153

Cap, Tant, 10 uF, 15 V, C Case, 6032 Kemet T491C106K016AS

C93, C103-105, C128, C152, C154-156

Cap, Tant, 47 uF, 20 V, D Case, 7343 Kemet T491D476M020AS

C2, C6, C58, C72, C84, C88, C89, C95, C109

Cap, Tant, 100 uF, 10 V, D Case, 7343 Kemet T495D107M010AS

C1, C7, C23, C66-C68, C74, C77-C82, C101, C113, C115, C141, C158,C163-173, C177-180, C184-186, C201-202, C204,C207, C211-213, C216-217, C220-C225

Chip Capacitor, 0.01 uF 50 V, CC0603 Kemet C0603C103J5RAC

U9 IC, PLD, PLCC28, Socket28 LATTICE GAL22V10B-7LJ

U23 IC, Linear Voltage Regulator, SOT-223 Linear Tech. LT1117-3.3cst


Rev. A0




Design Guide 119

U5 IC, Linear Voltage Regulator, SOT-223 Linear Tech. LT1117CST

XU11 40TSOP BIOS Socket, TSOP12X20/40S Meritec 980020-40-01

XU12, XU13 TIL311 SOCKET, DIP14 MILLMAX 110-99-314-41-001

U25 IC, Logic, 74ACT05, SO14 Motorola MC74ACT05DR

FB1-FB-4, FB9 Ferrite Bead, SM1806, Z-Bead Murata BLM41P750S

FB5, FB6, FB7, FB8 Ferrite Bead, SM1806, Z-Bead Murata BLM41A800S

U22 IC, Logic, 74ALS00, SOIC14 National DM74ALS00M

U7IC, Transceiver, 8-Bit Bidirectional Buffer, SOIC20, SO20W

National DM74ALS245AWM

C69, C83, C98, C110

Cap, Electrolytic, 220 uF, 25 V, 6.3 mm x 11.2 mm, PCAPR200-300

Panasonic ECE-A1EU221

R48, R52, R98-R100, R106,R108-R116,R118-R122

Chip Resistor, 0 Ohm Shunt, 5%, CR0805 Panasonic ERJ6GEY0R00V

R25, R42, R45, R49, R63, R101, R102

Chip Resistor, 1 K, 5%, CR0805 Panasonic ERJ6GEYJ102V

R2, R4, R5, R11, R40, R41, R43, R53-R56, R105, R117, R123-124, R127


R1, R3, R88, R89, R90, R91


R9, R24 Chip Resistor, 22, 5%, CR0805 Panasonic ERJ6GEYJ220V

R10, R12, R13, R14, R39, R58, R70

Chip Resistor, 220, 5%, CR0805 Panasonic ERJ6GEYJ221V

R92-R95 Chip Resistor, 27, 5%, CR0805 Panasonic ERJ6GEYJ270V

R20, R44, R57, R71

Chip Resistor, 2.7 K, 5%, CR0805 Panasonic ERJ6GEYJ272V

R17-R19, R21, R23, R26, R28, R30, R32, R34, R36, R38


R103,R104 Chip Resistor, 470, 5%, CR0805 Panasonic ERJ6GEYJ471V

R7, R64-R69, R125, R126, R128


R72-R87, R96, R107



Rev. A0




120 Design Guide

S1, S2 Switch-Push Button, PBSW / PNASNC2 Panasonic EVQ-PHP03T

RP2, RP3, RP41-RP47, RP54-RP56, RP58, RP60, RP61

Res, Array, SMT, 33, 5%, EXB-V Panasonic EXB33V330JV

RP10, RP18, RP23

Res, Array, SMT, 1 K, 5%, EXB-V Panasonic EXB38V102JV

RP8-9, RP11, RP13-17, RP19-RP22, RP24, RP26-33, RP35-36, RP39, RP51-52, RP59

Res, Array, SMT, 10 K, 5%,EXB-V Panasonic EXB38V103JV

RP1, RP4 Res, Array, SMT, 22, 5%, EXB-V Panasonic EXB38V220JV

RP25, RP37, RP49, RP50, RP53

Res, Array, SMT, 2.7 K, 5%,EXB-V Panasonic EXB38V272JV

RP57 Res, Array, SMT, 47, 5%, EXB-V Panasonic EXB38V470JV

RP5, RP6, RP7, RP48

Res, Array, SMT, 4.7 K, 5%, EXB-V Panasonic EXB38V472JV

RP12, RP34 Res, Array, SMT, 5.6 K, 5%, EXB-V Panasonic

U24 IC, Logic, Inverter, Schmitt Trigger, SOIC14 Philips 74LVC14AD

U10 IC, Logic, 10 Bit Bus Switch, QSOP, SO24W Quality Semi QS3384SO

Y1 Crystal,14.318 MHz, XTAL,FOX-HC495D Raltron AS-14.31818-20

F1-F3 Fuse, Drawing, SM250 RayChem SMD250-2

XBT1 Battery Holder Socket Renata HU-2032-1

BT1 Battery Reneta CR2032

D1, D2, D5 Diode, LED, SOT23-A Siemens LGS260-DO

U1 VLSI, Super I/O, QFP128 SMSC FDC37B787

C122-C125 Chip Capacitor, 47 pF, CC0603 TDK C1608C0G1H470JT$

C9-C21, C24-C26 Chip Capacitor, 220 pF, CC0603 TDK C1608X7R1H221KT

009A

U15 IC, Logic, 3-state buffer, SOP-14 TI 74LVC125A

U21 IC, Logic, SOP-14 TI 74LVC14A

U3, U4 IC, RS232 Transceiver, SOIC20, SO20W TI GD75232DW

U2 IC, Logic, Open Drain Buffer, SOP-14 TI SN7407D

U12, U13 7 Segment LED display, DIP14 TI TIL311

D3-D4, D6-D7 Schottky Diode, SOT23-E ZETEX BAT54


Rev. A0




Design Guide 121

R8, R15, R16, R46, R47 Chip Resistor, 124, 1%, CR0805 Panasonic ERJ-6ENF1240V

RP38, RP40 Res, Array, SMT, 270, 5%, EXB-V Panasonic EXB38V271JV

R300-R307 Chip Resistor, 0, 5%, CR0805 Panasonic ERJ6GEY0R00V

R50 Chip Resistor, 680, 5%, CR0805 Panasonic ERJ6GEYJ681V


R309 Chip Resistor, 0 Ohm Shunt, 5%, CR0805 Panasonic ERJ6GEY0R00V

J25 Conn, ITP, Vertical Recept., 30 pins AMP 104078-4

XU28 SPDIP, Socket 28 AMP 345724-1

C331, C332, C333, C334, C335

Chip Capacitor, 10 uF,16 V, Y5V, CC1210 AVX Corp 1210YG106ZAT4A

D9, D11 Schottky Diode, SOD-323 Central Semiconductor CMDSH-3TR

L2

Inductor, 1uH, IRMS = 12.5 A, ISAT = 15.3 A, DCRmax = .0034 ohm, UNI-PAC 3B

Coiltronics UP3B-1R0

L3

Inductor, 2.2 uH, IRMS = 3.1 A, ISAT = 3.5 A, DCRmax = .0363 ohm, UNI-PAC 1B

Coiltronics UP1B-2R2

R402 Chip Resistor, 15 milliohms, 5%, CR2512 Dale/Vishay WSL-2512 0.015 5%

R329, R403 Chip Resistor, 3 milliohms, 5%, CR2512 Dale/Vishay WSL-2512 0.003 5%

Q2, Q3, Q4 N-Channel FET, 25 V, SOT-23 Fairchild FDV301N

U33 Dual N Channel MOSFET, SO8 Fairchild FDS6982

U27 82443BX Host Bridge/Controller, 492 BGA Intel FW82443BX

U26Pentium® III Processor – Low Power at 500 MHz with 256 Kbyte L2 cache, 495 BGA2

Intel KC80526LY500256

U34, U35 N Channel MOSFET, SO8 International Rectifier IRF7809A

U31 N Channel MOSFET, SO8 International Rectifier IRF7811A

C230 Cap, Tant., 33 uF, 16 V, 7343 Kemet T495D336M016AS

U32 Dual Regulator Controller, SSOP36 Linear Tech LT1708PG#TRSL25

026

U30 Remote/Local Temp Sensor, QSOP16 Maxim MAX1617MEE

U28 8-bit CMOS FLASH Microcontroller, SPDIP28 Microchip PIC16LF873-04I/SP

L1 Chip Inductor, 4.7 uH, 10%, 30 mA, .7ohm, CR0805 Murata LQG21N4R7K10


Rev. A0




122 Design Guide

Y3 Crystal, 4 MHz, +/-0.5% Murata CSA4.00MG

D12 Schottky Barrier Rectifier, 1 A, 40V, 457-04

On Semiconductor MBRM140T3

D10 Schottky Barrier Rectifier, 3 V, 40 V, 403-03

On Semiconductor MBRS340T3

C350 Cap, SP, 180 uF, 4 V, UE Panasonic EEFUE0G181R

C353, C354, C355, C356 Cap, SP, 270 uF, 2 V, UE Panasonic EEFUE0D271R

C343 Cap, Tant., 4.7 uF, 6.3 V, Y Panasonic ECST0JY475R

C232, C233, C234, C235, C236, C237, C238, C239, C240, C241, C242, C243, C244, C245, C246, C247, C248, C249, C277, C278, C279, C280, C281, C282, C283, C284, C285, C286, C287, C288, C289, C290, C291, C292, C293, C294, C295, C296, C305, C306, C307, C308, C309, C310, C312, C313, C314, C315, C316, C317, C318, C319, C323, C327, C328, C336, C338, C358, C359

Chip Capacitor, 0.1 uF, 16 V, X7R, CC0603 Panasonic ECJ1VB1C104K

For 700MHz processor, populate C238-C245, C297-C299 with .22 uF, X7R, CC 0603: Panasonic ECJ1VB1A224K

C250, C251, C252, C253, C254, C255, C256, C257, C258, C259, C260, C261, C262, C263, C264, C265, C266, C267, C268, C269, C270, C271, C272, C273, C274, C275, C276

Chip Capacitor, 0.1 uF, 16 V, X7R, CC0805 Panasonic ECJ2VB1C104K

For 700MHz processor, populate C250-C276 with 2.2 uF, X5R,CC 0805: Panasonic ECJ2YB0J225K

C329, C330 Chip Capacitor, 0.1 uF, 25 V, X7R, CC0603 Panasonic ECJ1VB1E104K


Rev. A0




Design Guide 123

C337 Chip Capacitor, 0.47 uF, 16 V, X7R, CC0805 Panasonic ECJ2YB1C474K

C339, C342, C345, C348

Chip Capacitor, 1000 pF, 50 V, X7R,CC0603 Panasonic ECJ1VB1H102K

C347 Chip Capacitor, 100 pF, 50 V, NPO, CC0603 Panasonic ECUV1H101JCV

C357 Chip Capacitor, 10 uF, 10 V, X5R, CC1210 Panasonic ECJ4YB1A106K

C325, C326 Chip Capacitor, 15 pF, 50 V NP0, CC0603 Panasonic ECUV1C150JCV


C344 Chip Capacitor, 1 uF, 10 V, X7R, CC0805 Panasonic ECJ2YB1A105K

C322 Chip Capacitor, 20 pF, 16 V, NP0, CC0603 Panasonic ECUV1C200JCV



R334, R391 Chip Resistor, 0, 5%, CR0805 Panasonic ERJ6GEY0R00V

R327, R333, R359, R360, R383

Chip Resistor, 1.5K, 5%, CR0805 Panasonic ERJ6GEYJ152V

R393, R396, R399 Chip Resistor, 10, 5%, CR0805 Panasonic ERJ6GEYJ100V

R332, R342 Chip Resistor, 100, 1%, CR0805 Panasonic ERJ6ENF1000V

R395 Chip Resistor, 100K, 5%, CR0805 Panasonic ERJ6GEYJ015V

R400, R407, R411

Chip Resistor, 10K, 1%, CR0805 Panasonic ERJ6ENF0014V

R323, R336, R350, R347, R361, R397, R398, R335, R345

Chip Resistor, 10k, 5%, CR0805 Panasonic ERJ6GEYJ103V

R315 Chip Resistor, 110, 1%, CR0805 Panasonic ERJ6ENF1100V

R325, R339, R338 Chip Resistor, 150, 1%, CR0805 Panasonic ERJ6ENF1500V

R381, R382, R388, R389, R390




R324, R326, R331 Chip Resistor, 1K, 1%, CR0805 Panasonic ERJ6ENF1001V


Rev. A0




124 Design Guide

R311, R312, R313, R341, R353, R372, R373, R376, R377, R379, R392, R316, R317, R318, R319

Chip Resistor, 1K, 5%, CR0805 Panasonic ERJ6GEYJ102V

R394, R409, R410 Chip Resistor, 1M, 5%, CR0805 Panasonic ERJ6GEYJ016V

R344, R340, R343 Chip Resistor, 22, 5%, CR0805 Panasonic ERJ6GEYJ220V



R330 Chip Resistor, 2K, 1%, CR0805 Panasonic ERJ6ENF2001V

R375, R378 Chip Resistor, 3.3K, 5%, CR0805 Panasonic ERJ6GEYJ332V




R314, R328, R384

Chip Resistor, 56.2, 1%, CR0805 Panasonic ERJ6ENF56R2V


R404 Chip Resistor, 7.5K, 1%, CR0805 Panasonic ERJ6ENF0752V

R337 Chip Resistor, 75, 1%, CR0805 Panasonic ERJ6ENF0750V

D8 Schottky Diode, SOT23-E Zetex BAT54


Rev. A0




Design Guide 125

Appendix B Schematics

Schematics are provided for the following items listed below. Schematics are available from the Intel Developer’s web site in OrCAD* (version 9.0 or later) and PDF format.

• Table of Contents

• Block Diagram

• Routing Requirements

• Pentium® III Processor – Low Power Part 1

— This design will support either the Pentium® III processor – Low Power or the Intel® Celeron™ processor – Low Power in a 495 BGA2 package.

• Pentium® III Processor – Low Power Part 2

— When using a processor running at 700 MHz or above, larger value capacitors for high and mid frequency decoupling will be required. A table is provided on this page with the proper stuffing.

• 82443BX Part 1 Host, PCI, and AGP

• 82443BX Part 2 Memory, Power, and GND

• ITP, Thermal Sensor, and Clock Throttling

— The ITP, thermal sensor chip, and microcontroller are optional. More information on using a microcontroller to throttle the processor may be found in the Pentium® III Processor Active Thermal Management Technology Application Note (order number 273405). This application note also contains sample microcontroller code.

• Processor Voltage Regulator

• Mini-PCI Connector (Not Populated)

• DIMM0

— This design uses DIMMs instead of SO-DIMMs. For DIMM design guidelines, please see the Intel® 440BX AGPset Design Guide (order number 290634). Note also that Suspend To RAM is not supported as the DIMMs are powered with 3.3 V and not 3.3 VSB.

• DIMM1

• DIMM2 (Not Populated)

• System Clocks

— This design uses a CK100 compatible clock synthesizer instead of a CK100-M or CK100-SM. Because this design uses DIMMs, a CKBF SDRAM buffer is used instead of a CKBF-M.

• PCI/ISA Pullups

• PCI Connectors 0 and 1

• PCI Connector 2

• AGP Connector

• PIIX4E Part 1

• PIIX4E Part 2


126 Design Guide

• IDE Connectors

• Super I/O

• USB Connectors

• ISA Connectors

• Serial / Parallel / Floppy

• Flash BIOS / Port 80

— The code for the PLD is in Appendix C.

• ATX Power Connector

• Unused Devices

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Intel® Pentium® III Processor - Low Power / 440BX AGPset

Revision A0

THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT

BEEN VERIFIED FOR MANUFACTURING AS AN END USER

PRODUCT. INTEL IS NOT RESPONSIBLE FOR THE

MISUSE OF THIS INFORMATION.

No license, express or implied, by estoppel or otherwise, to any

intellectual property rights is granted herein.

Intel disclaims all liability, including liability for infringement of

any proprietary rights, relating to use of information in this

specification. Intel does not warrant or represent that such use will

not infringe such rights.

Reference Design

Tabl

e of

Con

tent

sTable of Contents

Block Diagram

Pentium® III Processor - Low Power Part 1

Pentium® III Processor - Low Power Part 2

82443BX Part 1 Host, PCI, and AGP

82443BX Part 2 Memory, Power, and GND

Page 1

Routing Guidelines

ITP, Thermal Sensor, and Clock Throttling

Processor Voltage Regulator

Mini PCI Connector

DIMM0

DIMM1

DIMM2

System Clocks

PCI / ISA Pullups

PCI Connectors 0 and 1

PCI Connector 2

AGP Connector

PIIX4E Part 1

PIIX4E Part 2

THIS SCHEMATIC IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER, INCLUDING

ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY

WARRANTY OTHERWISE ARISING OUT OF PROPOSAL, SPECIFICATION OR SAMPLE.

IDE Connectors

Super I/O

USB Connectors

ISA Connectors

Serial / Parallel / Floppy

Flash BIOS / Port 80

ATX Power Connector

Unused Devices

Page 2

Page 3

Page 4

Page 5

Page 6

Page 7

Page 8

Page 9

Page 10

Page 11

Page 12

Page 13

Page 14

Page 15

Page 16

Page 17

Page 18

Page 19

Page 20

Page 21

Page 22

Page 23

Page 24

Page 25

Page 26

Page 27

Page 28

Revi

sion

His

tory

Aug-24-2001

- Moved location of pull-up resistor on STPCLK# closer to the PIIX4E.

A0

Inte

l® P

entiu

m®

III -

Low

Pow

er /

440B

X AG

Pset

Ref

eren

ce D

esig

n

Int

el C

orpo

ratio

n

Em

bedd

ed In

tel A

rchi

tect

ure

Div

isio

n 5

000

W. C

hand

ler B

lvd.

Cha

ndle

r, AZ

852

26-3

699

Des

igne

d By

: Ap

plic

atio

n D

esig

n-In

Cen

ter (

Fols

om, C

A)

C

128

Mon

day,

Aug

ust 2

7, 2

001

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

A A

B B

C C

D D

E E

44

33

22

11

ATX Power

Connector

Page 27

PCI / ISA

Pullups

Page 15

System Clocks

Page 14

Unused Devices

Page 28





ITP Connector

Thermal Sensor

Clock Throttle Controller

Page 8

Optional

Processor

Voltage Regulator

Page 9

ISA BUS

PS2 Keyboard /

Mouse

Connector

Page 22

Serial

Port

Page

2582443BX

Host Bus

Controller

Page 6, 7

ISA

Connectors

Page 24

AGP Connector

Page 18

Intel® Pentium® III

Processor - Low Power

Page 4, 5

PCI

Connectors

Page 16,17

USB

Page

23

Mini PCI Connector

(not populated)

Page 10

PCI BUS

PIIX4E

Page

19, 20

DRAM (DIMM)

Page 11, 12,

13

Super I/O

Page 22

APIC

Page

19

IDE

Page

21

Flash Bios

Port 80

Page 26

Floppy

Connector

Page 25

Parallel

Port

Page 25

Blo

ck D

iagr

am

A0

Inte

l® P

entiu

m®

III -

Low

Pow

er /

440B

X AG

Pset

Ref

eren

ce D

esig

n

Int

el C

orpo

ratio

n

Em

bedd

ed In

tel A

rchi

tect

ure

Div

isio

n 5

000

W. C

hand

ler B

lvd.

Cha

ndle

r, AZ

852

26-3

699

Des

igne

d By

: Ap

plic

atio

n D

esig

n-In

Cen

ter (

Fols

om, C

A)

C

228

Mon

day,

Aug

ust 2

7, 2

001

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

CPU

Rout

ing

Requ

irem

ents

>> Consult the Intel® Pentium® III Processor - Low Power/ 440BX AGPset Design Guide for routing

requirements for the following GTL+ signals:

BPRI#, DEFER#, HRESET#, RS#[2:0], HTRDY#, H_PRDY#, HA#[31:3], ADS#, BNR#, BREQ0#, HD#[63:0], DBSY#,

DRDY#, HIT#, HITM#, HLOCK#, HREQ#[4:0]

>> The capacitor C230 should be close to the PLL1 and PLL2 pins, with less than 0.1ohm per route.

The inductor L1 should be close to the capacitor. The PLL2 route should be parallel and next to

the PLL1 route (minimize loop area). Any routing resistance should be inserted between VCCT and

the inductor. Consult the PLL RLC Filter Specification in the Pentium® III processor - Low Power

datasheet to determine if routing resistance is required.

>> Route THERMDP and THERMDN close together as a pair (no more than 250 mil difference in length),

on same layer, in parallel, and 25 mils min from any other trace.

>> Route VREF using 24 mil minimum width trace, and separate from all other traces by 25 mils

minimum.

>> Place ITP port near the processor. ITP port must be at end of following traces: HRESET#,

H_PRDY#, H_TCK, H_TMS. Series termination resistors for HRESET#, H_PRDY#, H_TCK, H_TMS must be

placed less than 1" from port.

>> Consult the Decoupling Recommendations in the Intel® Pentium® III Processor - Low Power/ 440BX

AGPset Design Guide for processor decoupling capacitor layout recommendations.

Gene

ral

Boar

d De

sign

Req

uire

ment

s>> Right angle traces must not be used.

>> Vias for decoupling capacitors must be kept as close as possible to the capacitor pad.

>> Trace impedance must be 65 ohms, +/- 10% unless otherwise noted.

>> GND layers must not be split.

>> Series terminating resistors must be kept as close to the driving pin as possible.

>> Daisy chain signals going to more than one point, do not use stubs.

>> Specific routing requirements are included throughout schematic sheets.

Cloc

k Sp

ecif

ic R

outi

ng R

equi

reme

nts

Note: This design uses a CK100 clock synthesizer.

>> Clocks must be routed on the same layer internally to contain EMI. Space all other signals at

least 2W from clock traces.

>> Intel recommends that the clock series resistors not be placed in the R-packs to allow individual

tunability if necessary.

>> Minimize via’s on all clock traces.

>> Do not allow the clock traces to cross a plane split.

>> CPUCLK0 - Follow host clock layout guidelines in Pentium III processor - Low Power/ 440BX AGPset

design guide

>> PCICLK7 should be 0" to 4" greater than the length of CPUCLK0 (from CK100 to 82443BX). PCICLK7

should be the same length as PCICLKF. PCI Clocks PCICLK[4:1] must be matched in length and should

equal the length of PCICLK7 - 2.5".

>> GCLKOUT should be less than or equal to 1". GCLK should equal GCLKIN + 3.3"

>> BXDCLKO must be between 1" to 6" in length. All SDRAM clocks SDCLK[11:0] must be matched in

length; this length should be between 1" and 3". BxFBCLK must be 2.5" longer that SDCLKx.

IDE

Spec

ific

Rou

ting

Req

uire

ment

s>> Place IDE series terminating resistors within 1" of PIIX4E.

>> Place IDE connector within 4" of PIIX4E.

Powe

r Su

pply

Spe

cifi

c Ro

utin

g Re

quir

emen

ts>> All traces associated with the input power/ground connectors, and the

capacitors connected to these connectors, must be routed with minimum

length and maximum width.

>> All unrelated signals and power planes must be kept away from the

switching circuitry.

>> Consult the Voltage Regulator Datasheet for specific routing

requirements

Memo

ry B

us S

peci

fic

Rout

ing

Requ

irem

ents

>> Consult the 440BX Design Guide for DIMM

routing guidelines.

PCI

Bus

Spec

ific

Rou

ting

Req

uire

ment

s.>> The PIIX4E must be the last device on the

PCI bus.

Rou

ting

Req

uire

men

ts

THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR

MANUFACTURING AS AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR

THE MISUSE OF THIS INFORMATION.

A0

Inte

l® P

entiu

m®

III -

Low

Pow

er /

440B

X AG

Pset

Ref

eren

ce D

esig

n

Int

el C

orpo

ratio

n

Em

bedd

ed In

tel A

rchi

tect

ure

Div

isio

n 5

000

W. C

hand

ler B

lvd.

Cha

ndle

r, AZ

852

26-3

699

Des

igne

d By

: Ap

plic

atio

n D

esig

n-In

Cen

ter (

Fols

om, C

A)

C

328

Mon

day,

Aug

ust 2

7, 2

001

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

GTL+ Reference Voltage Divider Network

3 mOhm resistor

for current

measurement of

VCCT supply.

Do N

ot P

opul

ate

CPU Reset GTL+ Pull-up

Note: APIC is disabled.

System Bus Clock Reference

Divider Network (1.25V)

Pen

tium

® I

II P

roce

ssor

- Lo

w P

ower

P

art

1

* Reference voltage for processor. There are 8

VREF pins. Place 1 capacitor near every 2 VREF

pins.

Fairchild:

25V

Id=250uA @ Vgs=0.85V typ

Max = 1.5V

CPU PWROK Level Pull-up

FERR# Level Shifter

20pF

CMOS Reference Voltage

Divider Network (1V)

** Make VREF as short and fat as possible. Use

at least 24 mil line.

CPU Clock Decoupling

THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR

MANUFACTURING AS AN END USER PRODUCT. INTEL IS NOT RESPONSIBLE FOR

THE MISUSE OF THIS INFORMATION.

>> LAYOUT: Place as close

as possible to CPU

A0

Inte

l® P

entiu

m®

III -

Low

Pow

er /

440B

X AG

Pset

Ref

eren

ce D

esig

n

Int

el C

orpo

ratio

n

Em

bedd

ed In

tel A

rchi

tect

ure

Div

isio

n 5

000

W. C

hand

ler B

lvd.

Cha

ndle

r, AZ

852

26-3

699

Des

igne

d By

: Ap

plic

atio

n D

esig

n-In

Cen

ter (

Fols

om, C

A)

C

428

Mon

day,

Aug

ust 2

7, 2

001

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

RS#

2

HD

#22

HD

#3

CPU

CLK

0

RS#

1

HD

#62

HD

#36

H_C

MO

SREF

HA#

20

HD

#37 CPU

CLK

0

HA#

29

H_P

WR

OK

HD

#42

HA#

10

H_C

LKR

EF

HD

#14

RS#

0

HD

#52

HA#

24

H_C

MO

SREF

HD

#7

HD

#21

HA#

5

H_F

ERR

#

HD

#34

HD

#45

HA#

3

HD

#47

HA#

8

VID

0

HD

#10

HA#

7

HD

#11

HD

#56

H_P

WR

OK

VID

4

H_F

ERR

#

HD

#28

HD

#2

HD

#39

H_R

ST#

HD

#55

H_C

LKR

EF

HD

#33

HD

#30

HD

#0

VID

2

HD

#4

HD

#9

HD

#41

HA#

9

FLU

SH#

HD

#35

HD

#38

HA#

27

HD

#12

HD

#58

H_P

ICFL

USH

#

HA#

21

HD

#44

HA#

6

HD

#63

HA#

31

HD

#31

HD

#57

HD

#24

HD

#19

HD

#25

HA#

13

HD

#49

HD

#29

HA#

18

HD

#6

HD

#23

HD

#60

HD

#27

HD

#50

HD

#5

HA#

30

HA#

19

HA#

22

HD

#17

HD

#8

VID

1

HA#

11

HA#

26

HD

#13

HD

#1

HA#

15

HD

#54

HA#

25

HD

#53

HR

EQ#4

VID

3

HD

#48

VREF

HD

#40

HD

#43 H_P

IC

HD

#51

HD

#15

HR

EQ#1

HA#

23

HA#

28

HR

EQ#0

HR

EQ#3

HD

#46

HA#

4

HD

#61

HA#

17

HD

#20

HD

#26

HA#

12

VREF

HD

#32

HD

#16

H_R

ST#

HD

#18

HD

#59

HA#

14

HR

EQ#2

HA#

16

DEF

ER#

6

H_T

DO

8

BREQ

0#6

H_T

DI

8

H_T

RST

#8

HIT

M#

6

INIT

15,2

0

HR

EQ#[

4:0]

6

DBS

Y#6

DR

DY#

6

ADS#

6

HLO

CK#

6

THER

MD

P8

H_T

MS

8

HTR

DY#

6

HR

ESET

#6,

8

THER

MD

N8

HA#

[31:

3]6

HD

#[63

:0]

6

CPU

CLK

06,

14

SLP#

15,2

0

BNR

#6

INTR

15,1

9,20

FER

R#

20

NM

I15

,20

VID

[4:0

]9

H_P

RD

Y#8

SMI#

19

BPR

I#6

A20M

#15

,20

H_T

CK

8

HIT

#6

H_P

REQ

#8

RS#

[2:0

]6

IGN

NE#

15,2

0

STPC

LK#

8,20

H_P

WR

OK

27

V2_5

VCC

T

V2_5

VCC

T

VCC

T

V2_5

VCC

T

VCC

T

V2_5

VCC

T

VCC

T

R31

61K

R31

71K

R31

81K

R31

91K

C23

2

0.1u

F16

VX7

R

BGA2

Test/ Debug & Unused

VREF, VID

U26

C

BGA2

_10

A15

A16

A17

C14 D

8D

14D

16 E15

G2

G5

G18 H

3H

5 J5 M4

M5 P3 P4 AA5

AA19

AC3

AC17

AC20

AD15

AA11

AD13

AC15

AD14

AA14

AB20

W20

W19

W21

Y21

AA21

AB19

AD20

H4

AA17

G4

AD17

Y5 N5

L2 M2

R2

AD19

P2 AA9

AD18

E5 E16

E17 F5 F17

U5

Y17

Y18

AD2

AD3

AD4

AC4

AB4

AA16

AA12

AB15

NC

1N

C2

NC

3N

C4

NC

5N

C6

NC

7N

C8

NC

9N

C10

NC

11N

C12

NC

13N

C14

NC

15N

C16

NC

17N

C18

NC

19N

C20

NC

21N

C22

NC

23N

C24

TCLK TD

ITD

OTM

STR

ST#

PREQ

#PR

DY#

BPM

1#BP

MO

#BP

3#BP

2#

Res

TP1

TP2

TP3

TP4

TEST

HI

TEST

LO1

TEST

LO2

PLL1

PLL2

GH

I#

RTT

IMPE

DP

CLK

REF

CM

OSR

EF1

CM

OSR

EF2

VREF

1VR

EF2

VREF

3VR

EF4

VREF

5VR

EF6

VREF

7VR

EF8

VID

0VI

D1

VID

2VI

D3

VID

4

EDG

ECTR

LP

BSEL

0BS

EL1

C23

1EM

PTY

C23

4

0.1u

F16

VX7

R

Q2

FDV3

01N

1

3 2

C23

033

uF

Intel® Pentium® III Processor

Low Power

Host Interface

U26

A

BGA2

_10

D10

D11

C7

C8

B9 A9

C10

B11

C12

B13

A14

B12

E12

B16

A13

D13

D15

D12

B14

E14

C13

A19

B17

A18

C17

D17

C18

B19

D18

B20

A20

B21

D19

C21

E18

C20

F19

D20

D21

H18

F18

J18

F21

E20

H19

E21

J20

H21

L18

G20

P18

G21

K18

K21

M18

L21

R19

K19

T20

J21

L20

M19

U18

R18

L3 K3 J2 L4 L1 K5 K1 J1 J3 K4 G1

H1 E4 F1 F4 F2 E1 C4

D3

D1 E2 D5

D4

C3

C1 B3 A3 B2 C2 T2 V4 V2 W3

W5 U1

AA2

W1

AB2 T4C6

AA3 T1V1 Y4R1

U4

U3

U2 A6

AD10

AC9

AC13

AA10

AB18

AC19V5

AB10

AB12

AC11

AC12

AD9

M3

AA18

AB21

Y20

AB16

AA15

B4A4 A5 C5

V20

T21

U21

R21

V18

P21

P20

U19

W2

AA1

AB1 Y2 E6 V21 Y1

D#0

D#1

D#2

D#3

D#4

D#5

D#6

D#7

D#8

D#9

D#1

0D

#11

D#1

2D

#13

D#1

4D

#15

D#1

6D

#17

D#1

8D

#19

D#2

0D

#21

D#2

2D

#23

D#2

4D

#25

D#2

6D

#27

D#2

8D

#29

D#3

0D

#31

D#3

2D

#33

D#3

4D

#35

D#3

6D

#37

D#3

8D

#39

D#4

0D

#41

D#4

2D

#43

D#4

4D

#45

D#4

6D

#47

D#4

8D

#49

D#5

0D

#51

D#5

2D

#53

D#5

4D

#55

D#5

6D

#57

D#5

8D

#59

D#6

0D

#61

D#6

2D

#63

A#3

A#4

A#5

A#6

A#7

A#8

A#9

A#10

A#11

A#12

A#13

A#14

A#15

A#16

A#17

A#18

A#19

A#20

A#21

A#22

A#23

A#24

A#25

A#26

A#27

A#28

A#29

A#30

A#31

REQ

#0R

EQ#1

REQ

#2R

EQ#3

REQ

#4

RS#

0R

S#1

RS#

2

ADS#

BNR

#

BRQ

0#

DBS

Y#D

RD

Y#

HIT

#H

ITM

#

LOC

K#

BPR

I#

DEF

ER#

TRD

Y#

RES

ET#

A20M

#

FLU

SH#

IGN

NE#

INIT

#

LIN

T0/IN

TRLI

NT1

/NM

I

PWR

GO

OD

SMI#

SLP#

STPC

LK#

FER

R#

IER

R#

BCLK

PIC

CLK

PIC

D0

PIC

D1

THER

MD

CTH

ERM

DA

A#34

A#32

A#33

A#35

DEP

0#D

EP1#

DEP

2#D

EP3#

DEP

4#D

EP5#

DEP

6#D

EP7#

RP#

AER

R#

AP0#

AP1#

BER

R#

BIN

IT#

RSP

#

R31

456

1%R

315

110

1%

C23

60.

1uF

16V

X7R

R32

033

0

R32

71.

5K

C23

70.

1uF

16V

X7R

R32

856 1%

R32

515

01%

R33

31.

5K

R33

210

01%

R32

61K 1%

R32

310

K

C23

5

0.1u

F16

VX7

R

R33

11K 1%

R33

02K 1%

R32

41K 1%

R32

9

3m 5%

R31

11K

L1 4.7u

H

R31

21K

C23

3

0.1u

F16

VX7

R

R31

31K

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

< LAYOUT >

Place homogeneously underneath the die.

System Bus Buffer Voltage (VCCT)

High-Frequency Decoupling

Capacitors

Pen

tium

® I

II P

roce

ssor

- Lo

w P

ower

P

art

2

Processor Core Voltage (VCCCORE)

High-Frequency Decoupling Capacitors

Processor Core Voltage (VCCCORE)

Mid-Frequency Decoupling Capacitors

< LAYOUT >

Place around die. Less than 0.25 inches away

from VCCT vias (balls).

< LAYOUT >

Place around die as close to the die as flex

solution allows. Less than 0.8 inches away.





VCCCORE High Freqency

VCCCORE High Freqency

VCCT High Freqency

VCCT High Freqency

VCCCORE Mid Freqency

Decoupling Capacitor

C238-C249

C297-C299

C250-C276

C277-C296

C300-C304

< 700MHz

700MHz

0.1uF

No Pop

2.2uF

0.22uF

Ref Des

0.1uF

0.1uF

No Pop

No Pop

0.1uF

0.22uF

A0

Inte

l® P

entiu

m®

III -

Low

Pow

er /

440B

X AG

Pset

Ref

eren

ce D

esig

n

Int

el C

orpo

ratio

n

Em

bedd

ed In

tel A

rchi

tect

ure

Div

isio

n 5

000

W. C

hand

ler B

lvd.

Cha

ndle

r, AZ

852

26-3

699

Des

igne

d By

: Ap

plic

atio

n D

esig

n-In

Cen

ter (

Fols

om, C

A)

C

528

Mon

day,

Aug

ust 2

7, 2

001

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

VCC

CO

RE

VCC

CO

RE

VCC

CO

RE

VCC

T

VCC

T

VCC

CO

RE

VCC

T

VCC

CO

RE

VCC

T

C28

50.

1uF

16V

X7R

C25

90.

1uF

16V

X7R

C23

90.

1uF

16V

X7R

C28

00.

1uF

16V

X7R

C28

40.

1uF

16V

X7R

C25

60.

1uF

16V

X7R

C26

00.

1uF

16V

X7R

C27

70.

1uF

16V

X7R

C28

30.

1uF

16V

X7R

C28

10.

1uF

16V

X7R

C27

90.

1uF

16V

X7R

C29

30.

1uF

16V

X7R

C25

00.

1uF

16V

X7R

C26

10.

1uF

16V

X7R

C25

10.

1uF

16V

X7R

BGA2

Power Supply

U26

B

BGA2

_10

A2A7A8A12A21B1B5B6B7B8B10B15B18C9C11C15C16C19D2D6D7D9E3E7E8E9E10E11E13E19F3F6F7F8F9F10F11F12F13F14F15F16F20G3G19

H2

H7

H9

H11

H13

H15

H20

J4 J8 J10

J12

J14

J16

J19

K2 K7 K9 K11

K13

K15

K20

L5 L8 L10

L12

L14

L16

L19

M7

M9

M11

M13

M15

M20

N2

H8

H10

H12

H14

H16 J7 J9 J11

J13

J15 K8 K10

K12

K14

K16 L7 L9 L11

L13

L15

M8

M10

M12

M14

M16 N

7N

9N

11N

13N

15 P8 P10

P12

P14

P16

R7

R9

R11

R13

R15 T8 T10

T12

T14

T16

U7

U9

U11

U13

U15 G

6G

7G

8G

9G

10G

11G

12G

13G

14G

15G

16G

17 H6

H17 J6 J17 K6 K17 L6 L17

M6

M17 N

6N

17 P1

N3

N4

N8

N10

N12

N14

N16

N18

N19

P5 P7 P9 P11

P13

P15

P19

R3

R4

R5

R8

R10

R12

R14

R16

R20

T3 T5 T7 T9 T11

T13

T15

T18

T19

U8

U10

U12

U14

U16

U20

V3 V19

W4

W18

Y3 Y9 Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y19

AA4

AA13

AA20

AB3

AB5

AB9

AB11

AB13

AB14

AB17

AC1

AC2

AC5

AC10

AC14

AC16

AC18

AC21

AD1

AD5

AD16

AD21

P6 P17

R6

R17 U

6U

17 V6 V7 V8 V9 V10

V11

V12

V13

V14

V15

V16

V17

W6

W7

W8

W9

W10

W11

W12

W13

W14

W15

W16

W17 Y6 Y7 Y8

AA6

AA7

AA8

AB6

AB7

AB8

AC6

AC7AC8AD6AD7AD8

T6 T17

N20

GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

D

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

_CO

RE

VCC

TVC

CT

VCC

TVC

CT

VCC

TVC

CT

VCC

TVC

CT

VCC

TVC

CT

VCC

TVC

CT

VCC

TVC

CT

VCC

TVC

CT

VCC

TVC

CT

VCC

TVC

CT

VCC

TVC

CT

VCC

TVC

CT

VCC

_CO

RE

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

D

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

D

VCC

TVC

CT

VCC

TVC

CT

VCC

TVC

CT

VCC

TVC

CT

VCC

TVC

CT

VCC

TVC

CT

VCC

TVC

CT

VCC

TVC

CT

VCC

TVC

CT

VCC

TVC

CT

VCC

TVC

CT

VCC

TVC

CT

VCC

TVC

CT

VCC

TVC

CT

VCC

TVC

CT

VCC

TVC

CT

VCC

TVC

CT

VCC

TVC

CT

VCC

TVC

CT

VCC

TVC

CT

VCCTVCCTVCCTVCCTVCCT

VCC

TVC

CT

GN

D

C25

20.

1uF

16V

X7R

C29

50.

1uF

16V

X7R

C25

30.

1uF

16V

X7R

C26

50.

1uF

16V

X7R

C25

40.

1uF

16V

X7R

C28

80.

1uF

16V

X7R

C29

00.

1uF

16V

X7R

C24

00.

1uF

16V

X7R

C27

00.

1uF

16V

X7R

C26

20.

1uF

16V

X7R

C26

40.

1uF

16V

X7R

C24

60.

1uF

16V

X7R

C27

30.

1uF

16V

X7R

C29

60.

1uF

16V

X7R

C24

70.

1uF

16V

X7R

C26

30.

1uF

16V

X7R

C24

80.

1uF

16V

X7R

C23

80.

1uF

16V

X7R

C28

90.

1uF

16V

X7R

C24

90.

1uF

16V

X7R

C29

20.

1uF

16V

X7R

C27

20.

1uF

16V

X7R

C24

30.

1uF

16V

X7R

C29

70.

1uF

16V

X7R

C24

20.

1uF

16V

X7R

C29

40.

1uF

16V

X7R

C27

40.

1uF

16V

X7R

C26

80.

1uF

16V

X7R

C24

40.

1uF

16V

X7R

C29

80.

1uF

16V

X7R

C24

50.

1uF

16V

X7R

C29

90.

1uF

16V

X7R

C24

10.

1uF

16V

X7R

C26

60.

1uF

16V

X7R

C26

70.

1uF

16V

X7R

C30

00.

1uF

16V

X7R

C27

50.

1uF

16V

X7R

C30

10.

1uF

16V

X7R

C27

10.

1uF

16V

X7R

C30

20.

1uF

16V

X7R

C29

10.

1uF

16V

X7R

C30

30.

1uF

16V

X7R

C30

40.

1uF

16V

X7R

C28

70.

1uF

16V

X7R

C27

60.

1uF

16V

X7R

C25

70.

1uF

16V

X7R

C28

60.

1uF

16V

X7R

C26

90.

1uF

16V

X7R

C25

50.

1uF

16V

X7R

C28

20.

1uF

16V

X7R

C25

80.

1uF

16V

X7R

C27

80.

1uF

16V

X7R

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

GTLREF Decoupling

>>LAYOUT: Place cap

within 1/2 inch of

BX.

0.1u

F

>> LAYOUT: Place as

close as possible to

82443BX.

8244

3BX

P

art

1H

ost,

PC

I, a

ndA

GP

0.1u

F

>>LAYOUT: place cap within

1/2 inch of BX.

0.1u

F

82443BX Bottom View

Do N

ot P

opul

ate

Do N

ot P

opul

ate

BX Host Clock Decoupling

82443BX Power Decoupling Caps

Do N

ot P

opul

ate

AGP Clock Decoupling

>> LAYOUT: Place as close

as possible to BX.

BX PCI Clock Decoupling

>>LAYOUT: Place cap

within 1/2 inch of

BX.

>> LAYOUT: Place at corners of 82443BX

>>LAYOUT: GROUND PADS

within inner ring of balls

of BX on bottom layer

BX 5V Tolerant Sequencing

Circuit

< LAYOUT > Silkscreen

Put 82443BX pin numbers on both

top and bottom layers.

AGP clock signals

BX GTL+ Reference Voltage

( 2/3 VCCT +/- 2%)

BX AGP Reference Voltage

(1.18V < AGPREF < 1.45V)





A0

Inte

l® P

entiu

m®

III -

Low

Pow

er /

440B

X AG

Pset

Ref

eren

ce D

esig

n

Int

el C

orpo

ratio

n

Em

bedd

ed In

tel A

rchi

tect

ure

Div

isio

n 5

000

W. C

hand

ler B

lvd.

Cha

ndle

r, AZ

852

26-3

699

Des

igne

d By

: Ap

plic

atio

n D

esig

n-In

Cen

ter (

Fols

om, C

A)

C

628

Mon

day,

Aug

ust 2

7, 2

001

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

HA#

8

HA#

31

HD

#18

HA#

25

HD

#60

HD

#28

HD

#11

HA#

4

HR

EQ#3

HA#

20

HD

#51

HD

#19

HA#

13

HA#

9

HD

#58

HD

#61

HD

#34

HA#

26

HD

#46

HD

#12

HA#

5

HD

#20

HA#

10

HR

EQ#4

HA#

21

HD

#59

HA#

27

HD

#62

HD

#47

HA#

14

HD

#29

HA#

6

HD

#8

HD

#21

REF

VCC

HD

#52

HD

#13

HD

#2

HA#

11

HD

#38

HA#

22

HD

#30

HD

#1

HA#

15

HD

#22

HD

#53

HD

#9

HD

#14

HD

#3

RS#

2

HA#

12

HD

#39

HD

#31

HD

#24

HD

#35

HA#

28

HD

#4

RS#

0H

D#4

4

HD

#0

HD

#32

HR

EQ#0

HD

#40

HD

#23

HD

#10

HD

#48

HD

#25

HD

#15

HA#

16

HD

#55

RS#

1

HD

#36

HD

#43

HA#

29

HD

#45

HD

#5

HA#

18

HD

#41

HD

#33

HD

#49

HD

#16

HA#

17

HR

EQ#1

HA#

23

HD

#26

CPU

CLK

0

HD

#63

HA#

30

HD

#56

HD

#6

HA#

19

HD

#37

HA#

7

HD

#17

HD

#42

HA#

24

HD

#54

HD

#50

HD

#27

HA#

3

CPU

CLK

0

HD

#7

HR

EQ#2

HD

#57

GC

LKIN

GC

LKO

UT

PCIC

LK7

GC

LKIN

GAD

8

SBA2

AD4

GC

/BE#

0

GAD

13

SBA7

AD19

AD8

AD6

GAD

30

GAD

25G

AD24

GAD

19

GC

/BE#

3

SBA4

-C/B

E3

GST

2

GAD

10

GAD

20

GAD

6

SBA6

AD14

GAD

0

AD5

SBA1

GAD

28

GAD

11

AD28

GAD

29

GAD

4G

AD3

AD3

AD0

REF

VCC

AD29

AD20

AD16

AD15

GAD

31

GAD

14

GAD

9

GAD

5

GC

/BE#

1

SBA3

AD1

GC

LKO

UT

GAD

23

AD25

GC

/BE#

2-C

/BE2

GAD

18

GAD

7

GAD

1

AD26

AD18

AD12

AD9

AD7

AD2

GAD

22

AD24

AD22

GST

0

GAD

26

GAD

21

GAD

15

GAD

2

AD30

AD21

AD17

GST

1

-C/B

E0

GAD

17G

AD16

GAD

12

AD23

-C/B

E1

GC

LKIN

AD31

AD13

AD11

AD10

SBA0

GAD

27AD

27

SBA5

BNR

#4

GIR

DY#

18

GG

NT#

18

PAR

10,1

5,16

,17,

19

GC

/BE#

[3:0

]18

GPA

R18

HTR

DY#

4

DEF

ER#

4

PCIC

LK7

14

CPU

CLK

04,

14

-PG

NT0

15,1

6

GPI

PE#

18

HD

#[63

:0]

4

GST

OP#

18

-PG

NT1

15,1

6

HLO

CK#

4

-C/B

E[3:

0]10

,16,

17,1

9

GTR

DY#

18

GR

EQ#

18

-PR

EQ3

10,1

5,19

CLK

RU

N#

10,1

9

GFR

AME#

18

-STO

P10

,15,

16,1

7,19

-PG

NT4

15

DBS

Y#4

GSB

_STB

18

PWR

OK

20,2

7

RS#

[2:0

]4H

A#[3

1:3]

4

GAD

[31:

0]18

-PG

NT2

15,1

7

-FR

AME

10,1

5,16

,17,

19

-TR

DY

10,1

5,16

,17,

19

HIT

M#

4

ADS#

4

-PR

EQ2

15,1

7,19

BPR

I#4

-PLO

CK

10,1

5,16

,17

HR

EQ#[

4:0]

4

SBA[

7:0]

18

DR

DY#

4

AD[3

1:0]

10,1

6,17

,19

-IRD

Y10

,15,

16,1

7,19

HR

ESET

#4,

8

-SER

R10

,15,

16,1

7,19

GAD

_STB

118

-PG

NT3

10,1

5

BREQ

0#4

-PR

EQ1

15,1

6,19

-DEV

SEL

10,1

5,16

,17,

19

-PH

OLD

A15

,19

GD

EVSE

L#18

GST

[2:0

]18

GR

BF#

18

SUS_

STAT

1#20

GAD

_STB

018

-PH

OLD

15,1

9

-PC

IRST

10,1

6,17

,18,

19

-PR

EQ4

15

-PR

EQ0

15,1

6,19

HIT

#4

GC

LK18

WSC

#19

VAG

PREF

VGTL

REF

_BX

V3_3

V3_3

V3_3

V5_0

V3_3

V3_3

VGTL

REF

_BX

VCC

T

V3_3

VGTL

REF

_BX

VCC

T

VAG

PREF

V3_3

TP22

1TP

C31

1EM

PTY

R33

40

8244

3BX

492

BGA

HOST

INTE

RFAC

E

U27

-1

443B

X_10

C13

M26

B8A7 E11

K21

C10

C15

D19

D20

E21

D9

G25

C11

A18

A22

B19

D18

D21

A3B23

C21

C19

M25

H22

A21

G23

B22

H24

A19

C20

D22

H23

H26

B18

G24

C17

B21

L23

F26

E20

E17

A20

D17

E19

J26

B20

G26

E18

B17

C16

K23

A17

G22 L24

F22

K22

B16

F23

D16

A16

F24

B15

H25

A15

D14

F25

D15

L22

B13

K26

C14

E14

E23

D13

A13

L26

D12

B12

E26

B14

E25

E13

L25

D11

D25

A12

B11

D26

A11

J22

B7

B25

C12

C8

C26

B10

A10

A25

A9 A8

C25

B9

J23

A24

D24

C23 K24

B24

C24 K25

A23

E22

D23 J25

N23B26

P22

AE22

AE23

M23 E16

M24 F17

AB22

HD

44#

CR

ESET

#

HD

61#

HD

56#

HD

57#

ADS#

HD

60#

HD

28#

HD

15#

HD

14#

HD

2#

HD

58#

HA3

#

HD

59#

HD

19#

HD

3#

HD

18#

HD

16#

HD

4#

PCIR

ST#

CPU

RST

#

HD

5#

HD

17#

TEST

IN#

HA4

#

HD

6#

HA5

#

HD

0#

BNR

#

HD

20#

HD

7#

HD

1#

HA6

#

BPR

I#

HD

21#

HA7

#

HD

22#

HD

8#

DBS

Y#

HA8

#

HD

9#

HD

23#

HD

10#

HD

24#

HD

11#

DEF

ER#

HD

12#

HA9

#

HD

13#

HD

25#

HD

26#

DR

DY#

HD

27#

HA1

0#

HIT

#

HA1

1#

HLO

CK#

HD

29#

HA1

2#

HD

30#

HD

31#

HA1

3#

HD

32#

HTR

DY#

HD

33#

HD

34#

HA1

4#

HD

35#

HIT

M#

HD

36#

RS#

0

HD

37#

HD

38#

HA1

5#

HD

39#

HD

40#

RS#

1

HD

41#

HD

42#

HA1

6#

HD

43#

HA1

7#

HD

45#

RS#

2H

D46

#

HA1

8#

HD

47#

HD

48#

HA1

9#

HD

49#

HR

EQ#0

HD

50#

HA2

0#

HD

51#

HD

52#

HA2

1#

HD

53#

HD

54#

HA2

2#

HD

55#

HD

62#

HA2

3#

HD

63#

HR

EQ#1

HA2

4#H

A25#

HA2

6#

HR

EQ#2

HA2

7#H

A28#

HR

EQ#3

HA2

9#H

A30#

HA3

1#

HR

EQ#4

HC

LKIN

BREQ

0#

RES

VAR

ESVB

RES

VC

GTL

REF

AG

TLR

EFB

VTTA

VTTB

RES

VD

TP21

1TP

TP20

1TP

C31

90.

1uF

TP19

1TP

C32

0EM

PTY

D8 BA

T54

3 1

2

C31

20.

1uF

C31

30.

1uF

R33

610

K

C31

50.

1uF

16V

C31

60.

1uF

16V

R33

915

01%

C31

80.

1uF

16V

R33

815

01%

R34

11K

C32

1EM

PTY

C31

70.

1uF

16V

R33

775 1%

R34

210

01%

R34

322R

340

22

C31

40.

1uF

16V

C30

60.

1uF

16V

C30

50.

1uF

PCIINTERFACE

AGPINTERFACE

8244

3BX

492

BGA

PCI ARB & PWRMGT

U27

-2

443B

X_10

A6E2

N4

J4

T5

C7

AC2

K6 F3

L1

F10

L4N3

G3 E1 D8

M3

L2

E7

W3

F5

K1

E4K2 D7

AB2

K4 F4 D10C

4

M2

K3 E10F2K5 G5J1

W5

J2

M1

H2

AB5

H1 E8J5

N2

H3 F1H5 B6H4 B2G1

V5

G2

D6

G4 E9D1

P2

D3

AE3

D2

Y4

C1

P4

A2

W4

C3

P3

B3

R1

D4

Y1

E5

V4

A4

Y2

D5

AE2

B4

U2

B5

L5

A5

L3

E6

AD3

C6

AD2

AD1

AC3

AC1

AB4

AB1

AA5

AA3

AA4

AA2

AA1

AD4

Y5

AF3

Y3

AC4

C2

W1

V2 W2

U5

V1 U4

U3

U1

T3 T4 T2 T1 U6

R3

R4

R2

M4

P5 N5

PREQ

0#/IO

REQ

#

FRAM

E#

AGPR

EFV

C/B

E0#

GAD

STB-

B

PREQ

1#

GAD

STB-

A

AD0

DEV

SEL#

ST2

PREQ

2#

ST0

SB-S

TB

C/B

E1#

IRD

Y#

PREQ

3#

PIPE

#

ST1

PGN

T0#/

IOG

NT#

GFR

AME#

TRD

Y#

SBA0

C/B

E2#

AD1

PGN

T1#

GC

/BE0

#

AD2

STO

P#

PREQ

4#

C/B

E3#

SBA1

AD3

PGN

T2#

PLO

CK#

AD4

PAR

AD5

GD

EVSE

L#

AD6

SBA2

AD7

GAD

0

AD8

PGN

T3#

AD9

SBA3

AD10

SER

R#

AD11

PHO

LD#

AD12

PCLK

IN

AD13

GIR

DY#

AD14

PHLD

A#

AD15

PGN

T4#

AD16

SBA4

AD17

WSC

#

AD18

GC

/BE1

#

AD19

SBA5

AD20

GTR

DY#

AD21

SBA6

AD22

SBA7

AD23

GST

OP#

AD24

GC

/BE2

#

AD25

GPA

R

AD26

GAD

1

AD27

GC

/BE3

#

AD28

GR

EQ#

AD29

GG

NT#

AD30

GAD

2

AD31

GAD

3G

AD4

GAD

5G

AD6

GAD

7G

AD8

GAD

9G

AD10

GAD

11G

AD12

GAD

13

SUST

AT#

GAD

14

BX-P

WR

OK

GAD

15

CLK

RU

N#

REF

VCC

GAD

16G

AD17

GAD

18G

AD19

GAD

20G

AD21

GAD

22G

AD23

GAD

24G

AD25

GAD

26G

AD27

GAD

28G

AD29

GAD

30G

AD31

RBF

#

GC

LKO

UT

GC

LKIN

C31

00.

1uF

16V

C30

90.

1uF

16V

C30

80.

1uF

16V

R33

510

K

C30

70.

1uF

16V

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Memo

ry M

odul

eCo

nfig

urat

ion

Do N

ot S

tuff

10K

Sign

al

Host

Bus

Buf

fer

Mode

Sele

ctMA

B6#

See Table for Stuffing

R29

Stuf

f

>> LAYOUT

Place cap as close

to BX as possible

Boar

d De

faul

tSe

ttin

g

MAB9

#

R25

MAB1

1#

Func

tion

Do N

ot S

tuff

Do N

ot S

tuff

BX Strapping Options

AGP

Disa

ble

R27

Frequency Select BX Strapping

Option

MAB7

#

10K

Resi

stor

Do N

ot S

tuff

8244

3BX

P

art

2M

emor

y, P

ower

,an

d G

ND

10K

Quic

k St

art

Sele

ctMA

B10#

R26

DCLKWR Decoupling

10K

In-O

rder

Que

ue D

epth

Enab

le.

R28





A0

Inte

l® P

entiu

m®

III -

Low

Pow

er /

440B

X AG

Pset

Ref

eren

ce D

esig

n

Int

el C

orpo

ratio

n

Em

bedd

ed In

tel A

rchi

tect

ure

Div

isio

n 5

000

W. C

hand

ler B

lvd.

Cha

ndle

r, AZ

852

26-3

699

Des

igne

d By

: Ap

plic

atio

n D

esig

n-In

Cen

ter (

Fols

om, C

A)

C

728

Mon

day,

Aug

ust 2

7, 2

001

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

MAB

#11

MD

40

DQ

MA1

MD

41

MAB

#3

MAB

#5

MAA

7

MAB

#2

MD

62

MD

0M

D1

MD

42

MEC

C3

MAA

8

MD

27

MD

43

MD

10

MD

63

MD

44

MAA

9M

AA10

MD

11

MD

45

MAA

11M

AA12

MD

28

MD

46

MAA

13

MAA

0

MD

47

MD

12

MD

14M

D13

MAB

#12

MAB

#13

MD

29

DQ

MA3

MAB

10

MD

49M

D48

MAB

#4

DQ

MA0

MAB

#11

MAB

#12

MAA

1

MD

51M

D50

MAB

#6

MAB

10

MEC

C1

DQ

MA6

MD

52

MD

15

DQ

MA2

MD

30M

D31

BxFB

CLK

MD

2M

AA2

MD

3

MEC

C4

MD

32

MEC

C0

MAA

3

MD

34M

D33

MD

35

MEC

C7

MD

4

MD

53D

QM

A5

MD

36

MAB

#6

MAB

#9

MAB

#0

MD

54

MD

16

MAB

#7

MD

37

MD

18M

D17

MEC

C2

MAB

#8

MAB

#9

MD

55

MD

5

MD

56M

D57

MD

19

MD

58

MAA

4

MD

59

MD

20

MD

6

MEC

C5

MD

21

MD

7M

D8

MD

22

MAA

5

MD

23

MEC

C6

MD

24

MD

9

MAB

#7

DQ

MA7

DQ

MA4

MAB

#1

MD

60

MD

38

MD

61

MD

25

MAA

6

MD

39

MD

26

CKE

413

CKE

513

CS_

A2#

12

SCAS

A#11

,12

CS_

A3#

12C

S_A4

#13

CS_

A5#

13

SCAS

B#13

SRAS

B#13

SRAS

A#11

,12

WE_

A#11

,12

WE_

B#13

BxFB

CLK

14MAA

[13:

0]11

,12

BXD

CLK

O14

DQ

MB1

13

DQ

MA[

7:0]

11,1

2,13

CS_

A0#

11C

S_A1

#11

DQ

MB5

13

MEC

C[7

:0]

11,1

2,13

CKE

011

MD

[63:

0]11

,12,

13

CKE

111

CKE

212

FREQ

_SEL

14

CKE

312

MAB

#[13

:0]

13

V3_3

V3_3

V3_3

R34

510

K

MEM

OR

Y IN

TER

FAC

E

8244

3BX

492

BGA

U27

-3

443B

X_10

AE21

AF25

AF17

AD21

AD16

AF22

AB14

AC16

AB16

AF15

AE15

AE11

AD17

AC15

AD15

AB17

AE17

AE16

AE25

AE18

AC6

AD24

AD19

AC17

AD26

AC24

AC26

AB18

AB23

AA10

AF18

AB19

AD13

AC13

AF20

AC25

AB26

AE19

AC20

U23

AE14

AC14

AB20

AF19

AA22

AA24

AC18

AE13

AA23

AD14

AC19

AC22

AF23

AE20

AE24

AD23

AF6

AD20

AC23

AF24

AF21

AF12

AA26

AB13

AC21

AF16

AA17

AC10

AE12

AC12

AF11

AD25

AB21

AD7

AD12T22

AA25

AE7

Y22

AF4

AC8

T23

AD8

AF10

AF8

T26

AE8

AF9

R24

AD10

AD11

AE10

R25

AB11

AE4

AC11P2

3

Y23

Y24

Y26

N25

W22AF

5

V22

AC5

V23

Y25

V25

AE5

U22

U25

AB6

U26

W23 T2

4

AD6

T25

W24 U21

AE6

R23

W26 R26 P24

W25 P2

5

AB7

V26

AC7

U24

AF7

AB8

AB9

AC9

AE9

AB10

MAB

11#

MAA

13

MAA

0

MAB

12#

MAB

0#

MAB

13

CSA

0#/R

ASA0

#

MAB

1#

MAA

1

CSA

1#/R

ASA1

#C

SA2#

/RAS

A2#

MEC

C0

MAB

2#

CSA

3#/R

ASA3

#C

SA4#

/RAS

A4#

MAB

3#

MAA

2

CSA

5#/R

ASA5

#

CSB

0#/R

ASB0

#

MAB

4#

MD

35

CSB

1#/R

ASB1

#

MAB

5#

MAA

3

CSB

2#/R

ASB2

#C

SB3#

/RAS

B3#

CSB

4#/R

ASB4

#

MAB

6#

CSB

5#/R

ASB5

#

MEC

C1

MAA

4

MAB

7#

DQ

MA0

/CAS

A0#

DQ

MA1

/CAS

A1#

MAB

8#

DQ

MA2

/CAS

A2#

DQ

MA3

/CAS

A3#

MAA

5

MAB

9#M

D24

DQ

MA4

/CAS

A4#

DQ

MA5

/CAS

A5#

MAB

10

MAA

6

DQ

MA6

/CAS

A6#

DQ

MA7

/CAS

A7#

MAA

7

DQ

MB1

/CAS

B1#

MEC

C2

DQ

MB5

/CAS

B5#

MAA

8

CKE

0/FE

NA

CKE

1/G

CKE

MAA

9

CKE

2/C

SA6

CKE

3/C

SA7

MD

36

MAA

10

CKE

4/C

SB6

CKE

5/C

SB7

MAA

11

SCAS

A#

MEC

C3

SCAS

B#

MAA

12

SRAS

A#SR

ASB#

MD

13

WEA

#W

EB#

MEC

C4

DC

LKW

RD

CLK

0

MD

37

MEC

C5

MD

25

MEC

C6

MD

38

MEC

C7

MD

0

MD

39

MD

26

MD

40

MD

14

MD

41

MD

27

MD

42M

D43

MD

28

MD

44

MD

15

MD

45

MD

29

MD

46

MD

1

MD

47

MD

30

MD

48

MD

16

MD

49

MD

31

MD

50

MD

2

MD

51

MD

32

MD

52

MD

17

MD

53

MD

33

MD

54M

D55

MD

34

MD

56

MD

18

MD

57

MD

3

MD

58

MD

19

MD

59

MD

4

MD

60

MD

20

MD

61M

D62

MD

21

MD

63

MD

5

MD

22

MD

6

MD

23

MD

7M

D8

MD

9M

D10

MD

11M

D12

R35

1EM

PTY

R35

0

10K

8244

3BX

492

BGA

U27

-4

443B

X_10

B1 F7 F9 F18

F20

G6

G21 J6 J21

L11

L13

L14

L16

M12

M15

N11

N16

N22

N26 P1 P11

P16

R12

R15 T11

T13

T14

T16 V6 V21 Y6 Y21

AA7

AA9

AA18

AA20

AE1

AE26

AF2

AF14

A1 A14

A26

C5

C9

C18

C22

E3 E12

E15

E24

F6 F8 F19

F21

H6

H21

J3 J24

L12

L15

M5

M11

M13

M14

M16

M22

N1

N12

N13

N14

N15

N24

P12

P13

P14

P15

P26

R5

R11

R13

R14

R16

R22

T12

T15

V3 V24

W6

W21

AA6

AA8

AA19

AA21

AB3

AB12

AB15

AB24

AB25

AD5

AD9

AD18

AD22

AF1

AF13

AF26

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

R34

422

C32

220

pF

R34

6EM

PTY

R34

8EM

PTY

R34

9EM

PTY

R34

710

K

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

3

Do N

ot P

opul

ate

Do N

otPo

pula

te

Clock Throttling Circuit

10K

0.284

ITP/JTAG INTERFACE

1

0.794

Do N

otPo

pula

te

30

TYP

10K

Address Select Straps

Current Address: 1001

110

Processor

STPCLK CMOS Voltage Level Shifter

Do N

ot P

opul

ate

U28 will mount

onto a 28-pin

PDIP socket

(XU28).

>>> LAYOUT

1.5V

connector, AMP

104078-4 Vertical

Recepticle, Top View

of ITP connector

with component

keep-out area.

OPTIONAL

ITP/JTAG CONNECTOR

0.100 29

2

Routing Guidelines:

Route THERMDP &

TERMDN as a

differential pair

Fair

chil

d: 2

5V,

ID=2

50uA

@VGS

=0.8

5V typ

1.5V

max

THERMAL SENSOR

Make RX and TX through

hole so a test post can be

soldered in. This will

allow the connection of an

external board with a

MAX232 for connecting to a

terminal for debug.

0.700

1K

4

Place VDD

bypass as

close to pin

as possible.

Fair

chil

d:25

VID

=250

uA@V

GS=0

.85V

typ

1.5V

max

1.004

Microcontroller Bypass Cap

ITP

, The

rmal

Sen

sor,

and

Clo

ck T

hrot

tlin

g

0.449

1K

RESE

T#

0.60

PIN

1

THIS DRAWING CONTAINS

INFORMATION WHICH HAS NOT

BEEN VERIFIED FOR

MANUFACTURING AS AN END

USER PRODUCT. INTEL IS NOT

RESPONSIBLE FOR THE MISUSE

OF THIS INFORMATION.

Populate R366 and

remove R306 if

STPCLK controlled

by microcontroller

and not by PIIX4E.

A0

Inte

l® P

entiu

m®

III -

Low

Pow

er /

440B

X AG

Pset

Ref

eren

ce D

esig

n

Int

el C

orpo

ratio

n

Em

bedd

ed In

tel A

rchi

tect

ure

Div

isio

n 5

000

W. C

hand

ler B

lvd.

Cha

ndle

r, AZ

852

26-3

699

Des

igne

d By

: Ap

plic

atio

n D

esig

n-In

Cen

ter (

Fols

om, C

A)

C

828

Mon

day,

Aug

ust 2

7, 2

001

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

STPC

LK_M

ICR

O

STPC

LK_M

ICR

O

SMBC

LK11

,12,

13,1

4,15

,20

THER

MD

P4

SMBD

ATA

11,1

2,13

,14,

15,2

0

SMBD

ATA

11,1

2,13

,14,

15,2

0SM

BCLK

11,1

2,13

,14,

15,2

0

DBR

ESET

27

H_T

MS

4H

_TD

I4

H_T

RST

#4

H_P

RD

Y#4

THER

MD

N4

STPC

LK#

4,20

H_T

DO

4

HR

ESET

#4,

6

H_P

REQ

#4

H_T

CK

4

V3_3

VCC

T

V3_3

VCC

T

VCC

T

V3_3

V3_3

VCC

T

VCC

T

V3_3

VCC

T

V3_3

V3_3

U30

MAX

1617

161 13515 9

2

143 4

12 11

610 7 8N

C5

NC

1

NC

4

NC

2

STBY

#

NC

3

VCC

SMBC

LKD

XPD

XNSM

BDAT

A

ALER

T#

ADD

1AD

D0

GN

DG

ND

R37

31K

R38

724

0

12

C32

80.

1uF

R39

10

1 2

R38

915

0

R36

927

0

R38

31.

5K

1 2

R38

815

0

R36

627

01

2

R37

53.

3K

1 2

R35

31K

R38

456 1%

R39

21K

1 2

C32

615

pf

C32

515

pf

R37

61K1 2

R37

71K1 2

R37

83.

3K

1 2

R37

91K1 2

R37

0

EMPT

YY3

CSA

4_00

MG

R37

1

EMPT

Y

R36

01.

5K

Q4

FDV3

01N

1

3 2

C32

30.

1uF

R38

115

0

1 2

U28

PIC

16LF

873

1 2 3 4 5 6 7 8 9 10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

MC

LR#

RA0

RA1

RA2

RA3

RA4

RA5

VSS

OSC

1O

SC2

RC

0R

C1/

CC

P2R

C2/

CC

P1R

C3/

SCL

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

VDD

VSS

RC

7/R

XR

C6/

TXR

C5

RC

4/SD

A

R38

215

0

1 2

R36

110

K

J25

ITP

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

GN

D

GN

D

GN

D

TDI

TDO

TRST

#

BSEN

#

PREQ

0#

PRD

Y0#

PREQ

1#

PRD

Y1#

PREQ

2#

PRD

Y2#

PREQ

3#

PRD

Y3#

RES

ET#

DBR

ESET

#

TCK

TMS

POW

ERO

N

DBI

NST

#

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

BCLK

R35

91.

5K

R35

2EM

PTY

R38

024

01

2

R38

547

12

R38

647

12

R35

4EM

PTY

TP23

1TP

Q3

FDV3

01N

1

3 2

C32

70.

1uF

R37

21K

TP24

1TP

R39

015

0

R37

427

0

1 2

A A

B B

C C

D D

E E

44

33

22

11

6.3V

CER

Do N

ot P

opul

ate

SENS

E





Do N

ot P

opul

ate

Pro

cess

or V

olta

ge R

egul

ator

Vout1

1.35V @ 14A

4V

3 milliohm

Sense Resistor

Vout2

1.5V @ 2.5A

SENS

E

Hi Frequency Decoupling Caps

15 milliohm

Sense Resistor

< LAYOUT >

Tightly couple these

current sensing

feedback paths

< LAYOUT >

Tightly couple these

current sensing

feedback paths

10V

A0

Inte

l® P

entiu

m®

III -

Low

Pow

er /

440B

X AG

Pset

Ref

eren

ce D

esig

n

Int

el C

orpo

ratio

n

Em

bedd

ed In

tel A

rchi

tect

ure

Div

isio

n 5

000

W. C

hand

ler B

lvd.

Cha

ndle

r, AZ

852

26-3

699

Des

igne

d By

: Ap

plic

atio

n D

esig

n-In

Cen

ter (

Fols

om, C

A)

C

928

Mon

day,

Aug

ust 2

7, 2

001

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

VID

4

VID

0

VID

3

VID

2

VID

1

CPU

PWR

OK

27

VID

[4:0

]4

VCC

T

V5_0

VCC

CO

RE

V3_3

VCC

CO

RE

V5_0

V5_0

C35

127

0uF

2V

C33

910

00pF

R40

116

0K

U31

IRF7

811A

1

2

3

4

5678

C32

9

0.1u

F25

V

C35

90.

1uF

R41

01M

C33

0

0.1u

F25

V

C34

118

0pF

C34

41u

FC

343

4.7u

F

C33

510

uF16

V

C34

710

0pF

C34

633

0pF

C35

710

uF

R40

010

K1% R

404

7.5K

1%

R40

833

K

L3 2.2u

HC

338

0.1u

F

R40

668

K

D9

CM

DSH

-3

C35

018

0uF

U34

IRF7

809A

1

2

3

4

5678

C35

327

0uF

2V

U35

IRF7

809A

1

2

3

4

5678

C35

80.

1uF

U33

BFD

S698

2

7

2

18

L2 1uH

R39

310

U32 LTC

1708

-PG

32 36 3524

3326

3425

3127

5 7 2

1428

43 29 8

11

15 1622 1

2310

917 18 19 20 2113 1230 6

Vin

PGO

OD

TG1

TG2

BOO

ST1

BOO

ST2

SW1

SW2

BG1

BG2

FREQ

SET

FCB

SEN

SE1+

SEN

SE2+

PGN

D

EAIN

1

SEN

SE1-

INTV

cc

ITH

1

ITH

2

ATTN

OU

T

ATTN

IN

VID

Vcc

RU

N/S

S1

RU

N/S

S23.

3Vou

t

SGN

D

VID

0

VID

1

VID

2

VID

3

VID

4

SEN

SE2-

EAIN

2

EXTV

cc

STBY

MD

R40

710

K1%

R40

91M

C34

00.

01uF

C34

810

00pF

C33

70.

47uF

C35

627

0uF

2V

C35

527

0uF

2V

R39

510

0K

C33

60.

1uF

C33

110

uF16

V

C34

510

00pF

R40

515

K

C33

210

uF16

V

D12

MBR

M14

0T3

R39

610

R41

110

K1%

R40

215

m

R39

41M

U33

AFD

S698

2

5

4

36

D10

MBR

S340

T3

C33

310

uF16

V

R39

710

K

R40

33m 5%

C33

410

uF16

V R39

910

R39

810

K

D11

CM

DSH

-3

C34

210

00pF

C35

427

0uF

2V

C34

933

pF

C35

227

0uF

2V

A A

B B

C C

D D

E E

44

33

22

11





Do N

ot P

opul

ate

Min

i PC

I C

onne

ctor

A0

Inte

l® P

entiu

m®

III -

Low

Pow

er /

440B

X AG

Pset

Ref

eren

ce D

esig

n

Int

el C

orpo

ratio

n

Em

bedd

ed In

tel A

rchi

tect

ure

Div

isio

n 5

000

W. C

hand

ler B

lvd.

Cha

ndle

r, AZ

852

26-3

699

Des

igne

d By

: Ap

plic

atio

n D

esig

n-In

Cen

ter (

Fols

om, C

A)

C

1028

Mon

day,

Aug

ust 2

7, 2

001

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

AD29

AD30

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

AD8

AD9

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AD27

AD28

AD31

-C/B

E3

-C/B

E0

-C/B

E1

-C/B

E2

IDSE

LF

AD31

AD[3

1:0]

6,16

,17,

19

-C/B

E[3:

0]6,

16,1

7,19

-FR

AME

6,15

,16,

17,1

9

-PLO

CK

6,15

,16,

17

-DEV

SEL

6,15

,16,

17,1

9

-IRD

Y6,

15,1

6,17

,19

-TR

DY

6,15

,16,

17,1

9

-STO

P6,

15,1

6,17

,19

-PC

IRST

6,16

,17,

18,1

9

PAR

6,15

,16,

17,1

9

-SER

R6,

15,1

6,17

,19

-PR

EQ3

6,15

,19

-PG

NT3

6,15

CLK

RU

N#

6,19

PIR

QD

#15

,16,

17,1

9,20

PCIC

LK4

14

PIR

QC

#15

,16,

17,1

8,19

,20

PIR

QB#

15,1

6,17

,18,

19,2

0

PIR

QA#

15,1

6,17

,19,

20-P

ERR

15,1

6,17

V3_3

V3_3

V5_0

V5_0

V5_0

J10

2X70

RC

PT

321 332 343 354 365 376 387 398 409 4110 4211 4312 4413 4514 4615 4716 4817 4918 5019 5120 5221 5322 5423 5524 5625 5726 5827 5928 6029 6130 6231 63 64 65 66 67 68 69 70

71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

321 332 343 354 365 376 387 398 409 4110 4211 4312 4413 4514 4615 4716 4817 4918 5019 5120 5221 5322 5423 5524 5625 5726 5827 5928 6029 6130 6231 63 64 65 66 67 68 69 70

71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

R70

220

A A

B B

C C

D D

E E

44

33

22

11

Slave address 10100000b

Socket 0 THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT




DIM

M0

A0

Inte

l® P

entiu

m®

III -

Low

Pow

er /

440B

X AG

Pset

Ref

eren

ce D

esig

n

Int

el C

orpo

ratio

n

Em

bedd

ed In

tel A

rchi

tect

ure

Div

isio

n 5

000

W. C

hand

ler B

lvd.

Cha

ndle

r, AZ

852

26-3

699

Des

igne

d By

: Ap

plic

atio

n D

esig

n-In

Cen

ter (

Fols

om, C

A)

C

1128

Mon

day,

Aug

ust 2

7, 2

001

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

MD

3

MD

4

MD

26

MD

61

MD

53

MD

28M

D29

MD

6

MD

63

MD

33

MD

43

MD

47

MD

58

MD

13

MD

38M

D7

MD

49

MD

59

MD

16

MD

11

MD

30

MD

36

MD

42

MD

54

MD

60

MD

1

MD

22M

D23

MD

27

MD

52

MD

57

MD

8

MD

18M

D19

MD

35

MD

44

MD

50M

D51

MD

62

MD

37

MD

40

MD

41

MD

46

MD

5

MD

25

MD

48

MD

15

MD

24

MD

31

MD

34

MD

55

MD

20

MD

0

MD

10

MD

12

MD

39

MD

45

MD

32

MD

2

MD

9

MD

14

MD

17

MD

21

MD

56

MAA

0M

AA2

MAA

4M

AA6

MAA

8M

AA10

MAA

1M

AA3

MAA

5M

AA7

MAA

9M

AA11

MAA

13M

AA12

MAA

12

MEC

C0

MEC

C1

MEC

C4

MEC

C5

MEC

C6

MEC

C7

MEC

C2

MEC

C3

MD

[63:

0]7,

12,1

3

MAA

[13:

0]7,

12

MEC

C[7

:0]

7,12

,13

WE_

A#7,

12D

QM

A07,

12,1

3D

QM

A17,

12C

S_A0

#7

SDC

LK0

14

DQ

MA2

7,12

,13

DQ

MA3

7,12

,13

SDC

LK2

14 SMBD

ATA

8,12

,13,

14,1

5,20

SMBC

LK8,

12,1

3,14

,15,

20

SCAS

A#7,

12D

QM

A47,

12,1

3D

QM

A57,

12C

S_A1

#7

SRAS

A#7,

12

CKE

07

DQ

MA6

7,12

,13

DQ

MA7

7,12

,13

SDC

LK1

14

SDC

LK3

14

CKE

17

V3_3

V3_3

C19

90.

1uF

C17

50.

1uF

C22

80.

1uF

C22

60.

1uF

C15

547

uF

J18

SDR

AM D

IMM

B85

A1B8

6B8

7A2

B88

A3

B89

B90

A4

B91

A5

B92

B93

A6 A7 A8 A9 A10

B157

B148

B152

B143

A41

A42

A43

A44

A45

A46

A47

A48

A49

A50

A51

A52

A53

A54

A55

A56

A57

A58

A59

A60

A61

A62

A63

A64

A65

A66

A67

A68

A69

A70

A71

A72

A73

A74

A75

A76

A77

A78

A79

A80

A81

A82

A83

A84

B140

B141

B142

B144

B145

B146

B147

B149

B150

B151

B153

B154

B155

B156

B158

B159

B160

B161

B162

B163

B164

B165

B166

B167

B168

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

A32

A33

A34

A35

A36

A37

A38

A39

A40

B94

B95

B96

B97

B98

B99

B100

B101

B102

B103

B104

B105

B106

B107

B108

B109

B110

B111

B112

B113

B114

B115

B116

B117

B118

B119

B120

B121

B122

B123

B124

B125

B126

B127

B128

B129

B130

B131

B132

B133

B134

B135

B136

B137

B138

B139

GN

DG

ND

DQ

32D

Q33

DQ

0

DQ

34D

Q1

DQ

35V3

_3

DQ

2

DQ

36

DQ

3

DQ

37D

Q38

V3_3

DQ

4D

Q5

DQ

6D

Q7

V3_3

GN

D

GN

D

V3_3

V3_3

CK0

GN

DD

U/S

2D

QM

B2D

QBM

3D

UV3

_3N

CN

CC

B2C

B3G

ND

DQ

16D

Q17

DQ

18D

Q19

V3_3

DQ

20N

CVR

EF (N

C)

CKE

1G

ND

DQ

21D

Q22

DQ

23G

ND

DQ

24D

Q25

DQ

26D

Q27

V3_3

DQ

28D

Q29

DQ

30D

Q31

GN

DC

K2N

CW

PSD

ASC

LV3

_3

DQ

49D

Q50

DQ

51

DQ

52 NC

DU

REG

E

DQ

53D

Q54

DQ

55

DQ

56D

Q57

DQ

58D

Q59

DQ

60D

Q61

DQ

62D

Q63

GN

DC

K3 NC

SA0

SA1

SA2

V3_3

DQ

8G

ND

DQ

9D

Q10

DQ

11D

Q12

DQ

13V3

_3D

Q14

DQ

15C

B0C

B1G

ND

NC

NC

V3_3

WE0

DQ

MB0

DQ

MB1

/S0

DU

GN

DA0 A2 A4 A6 A8 A1

0(AP

)BA

1V3

_3

DQ

39

DQ

40G

ND

DQ

41D

Q42

DQ

43D

Q44

DQ

45V3

_3D

Q46

DQ

47C

B4C

B5G

ND

NC

NC

V3_3

/CAS

DQ

MB4

DQ

MB5 /S

1/R

ASG

ND A1 A3 A5 A7 A9 BA0

A11

V3_3

CK1 A1

2G

ND

CKE

0/S

3D

QM

B6D

QM

B7 A13

V3_3 NC

NC

CB6

CB7

GN

DD

Q48

C10

547

uF R52

0

R48

0

C20

20.

01uF

C20

10.

01uF

C20

70.

01uF

C20

40.

01uF

A A

B B

C C

D D

E E

44

33

22

11


Socket 1





DIM

M1

A0

Inte

l® P

entiu

m®

III -

Low

Pow

er /

440B

X AG

Pset

Ref

eren

ce D

esig

n

Int

el C

orpo

ratio

n

Em

bedd

ed In

tel A

rchi

tect

ure

Div

isio

n 5

000

W. C

hand

ler B

lvd.

Cha

ndle

r, AZ

852

26-3

699

Des

igne

d By

: Ap

plic

atio

n D

esig

n-In

Cen

ter (

Fols

om, C

A)

C

1228

Mon

day,

Aug

ust 2

7, 2

001

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

MD

3

MD

4

MD

26

MD

61

MD

53

MD

28M

D29

MD

6

MD

63

MD

33

MD

43

MD

47

MD

58

MD

13

MD

38M

D7

MD

49

MD

59

MD

16

MD

11

MD

30

MD

36

MD

42

MD

54

MD

60

MD

1

MD

22M

D23

MD

27

MD

52

MD

57

MD

8

MD

18M

D19

MD

35

MD

44

MD

50M

D51

MD

62

MD

37

MD

40

MD

41

MD

46

MD

5

MD

25

MD

48

MD

15

MD

24

MD

31

MD

34

MD

55

MD

20

MD

0

MD

10

MD

12

MD

39

MD

45

MD

32

MD

2

MD

9

MD

14

MD

17

MD

21

MD

56

MAA

0M

AA2

MAA

4M

AA6

MAA

8M

AA10

MAA

1M

AA3

MAA

5M

AA7

MAA

9M

AA11

MAA

13M

AA12

MAA

12

MEC

C0

MEC

C1

MEC

C4

MEC

C5

MEC

C6

MEC

C7

MEC

C2

MEC

C3

MD

[63:

0]7,

11,1

3

MAA

[13:

0]7,

11

MEC

C[7

:0]

7,11

,13

WE_

A#7,

11D

QM

A07,

11,1

3D

QM

A17,

11C

S_A2

#7 SD

CLK

414

DQ

MA2

7,11

,13

DQ

MA3

7,11

,13

SDC

LK6

14 SMBD

ATA

8,11

,13,

14,1

5,20

SMBC

LK8,

11,1

3,14

,15,

20

SCAS

A#7,

11D

QM

A47,

11,1

3D

QM

A57,

11C

S_A3

#7

SRAS

A#7,

11

CKE

27

DQ

MA6

7,11

,13

DQ

MA7

7,11

,13

SDC

LK5

14

SDC

LK7

14

CKE

37

V3_3

V3_3

V3_3

C18

10.

1uF

C18

30.

1uF

C19

80.

1uF

C18

20.

1uF

C10

347

uF

J17

SDR

AM D

IMM

B85

A1B8

6B8

7A2

B88

A3

B89

B90

A4

B91

A5

B92

B93

A6 A7 A8 A9 A10

B157

B148

B152

B143

A41

A42

A43

A44

A45

A46

A47

A48

A49

A50

A51

A52

A53

A54

A55

A56

A57

A58

A59

A60

A61

A62

A63

A64

A65

A66

A67

A68

A69

A70

A71

A72

A73

A74

A75

A76

A77

A78

A79

A80

A81

A82

A83

A84

B140

B141

B142

B144

B145

B146

B147

B149

B150

B151

B153

B154

B155

B156

B158

B159

B160

B161

B162

B163

B164

B165

B166

B167

B168

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

A32

A33

A34

A35

A36

A37

A38

A39

A40

B94

B95

B96

B97

B98

B99

B100

B101

B102

B103

B104

B105

B106

B107

B108

B109

B110

B111

B112

B113

B114

B115

B116

B117

B118

B119

B120

B121

B122

B123

B124

B125

B126

B127

B128

B129

B130

B131

B132

B133

B134

B135

B136

B137

B138

B139

GN

DG

ND

DQ

32D

Q33

DQ

0

DQ

34D

Q1

DQ

35V3

_3

DQ

2

DQ

36

DQ

3

DQ

37D

Q38

V3_3

DQ

4D

Q5

DQ

6D

Q7

V3_3

GN

D

GN

D

V3_3

V3_3

CK0

GN

DD

U/S

2D

QM

B2D

QBM

3D

UV3

_3N

CN

CC

B2C

B3G

ND

DQ

16D

Q17

DQ

18D

Q19

V3_3

DQ

20N

CVR

EF (N

C)

CKE

1G

ND

DQ

21D

Q22

DQ

23G

ND

DQ

24D

Q25

DQ

26D

Q27

V3_3

DQ

28D

Q29

DQ

30D

Q31

GN

DC

K2N

CW

PSD

ASC

LV3

_3

DQ

49D

Q50

DQ

51

DQ

52 NC

DU

REG

E

DQ

53D

Q54

DQ

55

DQ

56D

Q57

DQ

58D

Q59

DQ

60D

Q61

DQ

62D

Q63

GN

DC

K3 NC

SA0

SA1

SA2

V3_3

DQ

8G

ND

DQ

9D

Q10

DQ

11D

Q12

DQ

13V3

_3D

Q14

DQ

15C

B0C

B1G

ND

NC

NC

V3_3

WE0

DQ

MB0

DQ

MB1

/S0

DU

GN

DA0 A2 A4 A6 A8 A1

0(AP

)BA

1V3

_3

DQ

39

DQ

40G

ND

DQ

41D

Q42

DQ

43D

Q44

DQ

45V3

_3D

Q46

DQ

47C

B4C

B5G

ND

NC

NC

V3_3

/CAS

DQ

MB4

DQ

MB5 /S

1/R

ASG


A11

V3_3

CK1 A1

2G

ND

CKE

0/S

3D

QM

B6D

QM

B7 A13

V3_3 NC

NC

CB6

CB7

GN

DD

Q48

C10

447

uF

R10

80

R12

54.

7K

R99

0

A A

B B

C C

D D

E E

44

33

22

11


Socket 2

Note: J16 is not populated





DIM

M2

A0

Inte

l® P

entiu

m®

III -

Low

Pow

er /

440B

X AG

Pset

Ref

eren

ce D

esig

n

Int

el C

orpo

ratio

n

Em

bedd

ed In

tel A

rchi

tect

ure

Div

isio

n 5

000

W. C

hand

ler B

lvd.

Cha

ndle

r, AZ

852

26-3

699

Des

igne

d By

: Ap

plic

atio

n D

esig

n-In

Cen

ter (

Fols

om, C

A)

C

1328

Mon

day,

Aug

ust 2

7, 2

001

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

MD

28

MD

35

MD

54

MD

59

MD

7

MD

53

MD

4

MD

48

MD

37

MD

44

MD

56

MD

42

MD

38

MD

61

MEC

C6

MD

21

MD

32

MD

20

MD

25

MD

52

MEC

C5

MD

45

MD

55

MD

19

MD

27

MD

43

MD

62

MD

5

MD

18

MD

36

MD

30

MD

13

MD

33

MD

63

MD

17

MD

46

MD

23

MD

47M

ECC

4

MD

14

MD

39

MD

34

MD

58

MD

6

MD

3

MEC

C1

MD

51

MD

22

MD

16M

D49

MEC

C3

MD

41

MD

50

MD

1

MD

11

MD

29

MD

12

MD

31

MD

24

MD

8

MD

26

MEC

C2

MD

9M

D10

MD

15

MD

40

MD

60

MEC

C7

MEC

C0

MD

2

MD

0

MD

57

MAB

#12

MAB

#5

MAB

#9

MAB

#3M

AB#0

MAB

#6M

AB#4

MAB

#8M

AB#1

0

MAB

#1

MAB

#12

MAB

#13

MAB

#2

MAB

#7

MAB

#11

SDC

LK11

14

DQ

MA7

7,11

,12

CKE

57

MEC

C[7

:0]

7,11

,12

SCAS

B#7

SDC

LK10

14

DQ

MA2

7,11

,12

CKE

47

SMBD

ATA

8,11

,12,

14,1

5,20

DQ

MB1

7D

QM

A47,

11,1

2

SDC

LK9

14

DQ

MA6

7,11

,12

CS_

A5#

7

MAB

#[13

:0]

7

MD

[63:

0]7,

11,1

2

SRAS

B#7

DQ

MA3

7,11

,12

WE_

B#7

SMBC

LK8,

11,1

2,14

,15,

20

CS_

A4#

7

DQ

MA0

7,11

,12

DQ

MB5

7

SDC

LK8

14

V3_3

V3_3

V3_3

C17

40.

1uF

C17

60.

1uF

C19

70.

1uF

C22

70.

1uF

C12

847

uF

J16

SDR

AM D

IMM

B85

A1B8

6B8

7A2

B88

A3

B89

B90

A4

B91

A5

B92

B93

A6 A7 A8 A9 A10

B157

B148

B152

B143

A41

A42

A43

A44

A45

A46

A47

A48

A49

A50

A51

A52

A53

A54

A55

A56

A57

A58

A59

A60

A61

A62

A63

A64

A65

A66

A67

A68

A69

A70

A71

A72

A73

A74

A75

A76

A77

A78

A79

A80

A81

A82

A83

A84

B140

B141

B142

B144

B145

B146

B147

B149

B150

B151

B153

B154

B155

B156

B158

B159

B160

B161

B162

B163

B164

B165

B166

B167

B168

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

A32

A33

A34

A35

A36

A37

A38

A39

A40

B94

B95

B96

B97

B98

B99

B100

B101

B102

B103

B104

B105

B106

B107

B108

B109

B110

B111

B112

B113

B114

B115

B116

B117

B118

B119

B120

B121

B122

B123

B124

B125

B126

B127

B128

B129

B130

B131

B132

B133

B134

B135

B136

B137

B138

B139

GN

DG

ND

DQ

32D

Q33

DQ

0

DQ

34D

Q1

DQ

35V3

_3

DQ

2

DQ

36

DQ

3

DQ

37D

Q38

V3_3

DQ

4D

Q5

DQ

6D

Q7

V3_3

GN

D

GN

D

V3_3

V3_3

CK0

GN

DD

U/S

2D

QM

B2D

QBM

3D

UV3

_3N

CN

CC

B2C

B3G

ND

DQ

16D

Q17

DQ

18D

Q19

V3_3

DQ

20N

CVR

EF (N

C)

CKE

1G

ND

DQ

21D

Q22

DQ

23G

ND

DQ

24D

Q25

DQ

26D

Q27

V3_3

DQ

28D

Q29

DQ

30D

Q31

GN

DC

K2N

CW

PSD

ASC

LV3

_3

DQ

49D

Q50

DQ

51

DQ

52 NC

DU

REG

E

DQ

53D

Q54

DQ

55

DQ

56D

Q57

DQ

58D

Q59

DQ

60D

Q61

DQ

62D

Q63

GN

DC

K3 NC

SA0

SA1

SA2

V3_3

DQ

8G

ND

DQ

9D

Q10

DQ

11D

Q12

DQ

13V3

_3D

Q14

DQ

15C

B0C

B1G

ND

NC

NC

V3_3

WE0

DQ

MB0

DQ

MB1

/S0

DU

GN

DA0 A2 A4 A6 A8 A1

0(AP

)BA

1V3

_3

DQ

39

DQ

40G

ND

DQ

41D

Q42

DQ

43D

Q44

DQ

45V3

_3D

Q46

DQ

47C

B4C

B5G

ND

NC

NC

V3_3

/CAS

DQ

MB4

DQ

MB5 /S

1/R

ASG


A11

V3_3

CK1 A1

2G

ND

CKE

0/S

3D

QM

B6D

QM

B7 A13

V3_3 NC

NC

CB6

CB7

GN

DD

Q48

C15

647

uf

R10

60

R12

64.

7K

R10

00

A A

B B

C C

D D

E E

44

33

22

11

Note: Stuff only to enable

stopping of clocks Note: Keep crystal close to clock and

caps close to crystal. All lead

lengths should be equal.

Note: R15 and R16 should be placed as

close as possible to U5

1% 1%





Sys

tem

Clo

cks

A0

Inte

l® P

entiu

m®

III -

Low

Pow

er /

440B

X AG

Pset

Ref

eren

ce D

esig

n

Int

el C

orpo

ratio

n

Em

bedd

ed In

tel A

rchi

tect

ure

Div

isio

n 5

000

W. C

hand

ler B

lvd.

Cha

ndle

r, AZ

852

26-3

699

Des

igne

d By

: Ap

plic

atio

n D

esig

n-In

Cen

ter (

Fols

om, C

A)

C

1428

Mon

day,

Aug

ust 2

7, 2

001

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

PCIC

LKF_

RPC

ICLK

R_1

PCIC

LKR

_2PC

ICLK

R_3

PCIC

LKR

_4

PCIC

LKR

_6PC

ICLK

R_7

USB

CLK

R_0

REF

R_0

REF

R_1

REF

R_2

APIC

CLK

R_0

V2_5

SDC

LKR

0SD

CLK

R1

SDC

LKR

2SD

CLK

R3

SDC

LKR

10SD

CLK

R11

SDC

LKR

8SD

CLK

R9

SDC

LKR

7SD

CLK

R6

SDC

LKR

4SD

CLK

R5

CPU

CLK

R_0

1C

PUC

LK0

4,6

PCIC

LKF

20PC

ICLK

116

PCIC

LK2

16PC

ICLK

317

PCIC

LK4

10

PCLK

APIC

19PC

ICLK

76

USB

CLK

020

REF

024

REF

122

REF

220

APIC

CLK

019

FREQ

_SEL

7

SMBD

ATA

8,11

,12,

13,1

5,20

SMBC

LK8,

11,1

2,13

,15,

20

BXD

CLK

O7

SDC

LK0

11SD

CLK

111

SDC

LK2

11SD

CLK

311

SDC

LK4

12SD

CLK

512

SDC

LK6

12

SDC

LK8

13SD

CLK

913

SDC

LK10

13SD

CLK

1113

BxFB

CLK

7

CPU

_STO

P#20

PCI_

STO

P#20

SUSA

#20

SDC

LK7

12

V3_3

V5_0

V3_3

V3_3

V2_5

RP2

010

K18273645

C16

30.

01uF

RP2

210

K

18273645

TP17

1TP

R12

20

C21

30.

01uF

R30

833

R11

80

C21

70.

01uF

R23

33

R12

00

C22

30.

01uF

R26

33

R12

10

C22

10.

01uF

R28

33

R11

90

C21

20.

01uF

R32

33

R11

30

C22

50.

01uF

R30

33

R10

90

C22

00.

01uF

R36

33

R11

10

C22

40.

01uF

R34

33

R11

60

C22

20.

01uF

R38

33

R11

40

C21

60.

01uF

R18

33

R11

20

C21

10.

01uF

R17

33

R11

00

R35

0

R19

33

U16

CY2

318N

Z

4

6

5

3

8

10

9 13

15

14

7

17

19

18 31

22

32

12

35

26

36 40

27

41

16

44

30

45 21

34

28

20

3943

232933374246

11 38 24 251 2 47 48

SDR

AM0

VSS

SDR

AM1

VDD

SDR

AM2

VSS

SDR

AM3

SDR

AM4

VSS

SDR

AM5

VDD

SDR

AM6

VSS

SDR

AM7

SDR

AM8

VSS

SDR

AM9

VDD

SDR

AM10

VSS

SDR

AM11

SDR

AM12

VSS

SDR

AM13

VDD

SDR

AM14

VSSSDR

AM15

SDR

AM16

VSS

SDR

AM17

VDD

VSSVSS

VDDVDDVDDVDDVDDVDD

CLK

_IN

OE

SDAT

ASC

LK

NC

NC

NC

NC

R33

0

R21

33

C14

915

uF

R37

0

C17

00.

01uF

R11

50

C95

100u

FC

171

0.01

uF

U6

CY2

280

15 39

30

216

48

31

46

12

41

1

37

18

33

29

19 20

7

24

2

32

40

34

47

38

8

43

39 1036 1135 13 14 16 17 22 23 45 44

2827 26 25 4 542

VDDPCI VSSVDDPCI

CPU

_STO

P#

VDDUSBVSS

VDDREF

PCI_

STO

P#

VDDAPIC

VSS

VDDCPU

REF

0

VDDCPU

VSS

AVDD

PWR

_DW

N#

AVDD VSS

PCIC

LK_F

VSS

REF

1

VSS

CPU

CLK

0

VSS

REF

2

VSS

PCI_

CLK

1

VSS

CPU

CLK

1

PCI_

CLK

2

CPU

CLK

2

PCI_

CLK

3

CPU

CLK

3

PCI_

CLK

4PC

I_C

LK5

PCI_

CLK

6PC

I_C

LK7

USB

CLK

0U

SBC

LK1

APIC

0AP

IC1

SEL_

SS#

SEL0

SEL1

SEL1

00

XTAL

INXT

ALO

UT

RES

ERVE

D

U5 LT

117

123

4

Adj/G

ND

Out

InO

utTa

b

C94

10uF

C10

10.

01uF

Y1

14.3

18M

Hz

12

C16

20.

1uF

C15

015

uF

C16

80.

01uF

C10

010

pf

C14

815

uF

C16

40.

01uF

C99

10pf

C93

47uF

C16

90.

01uF

J15

JUM

P2

1 2

R15

124

R24

22

C17

30.

01uF

J14

HD

R2

1 2

R16

124

C16

50.

01uF

A A

B B

C C

D D

E E

44

33

22

11

ISA

Pull

ups

PCI

Pull

ups

Note IRQ8 Pull-up

is on PIIX4 page





PC

I / I

SA

Pul

lups

A0

Inte

l® P

entiu

m®

III -

Low

Pow

er /

440B

X AG

Pset

Ref

eren

ce D

esig

n

Int

el C

orpo

ratio

n

Em

bedd

ed In

tel A

rchi

tect

ure

Div

isio

n 5

000

W. C

hand

ler B

lvd.

Cha

ndle

r, AZ

852

26-3

699

Des

igne

d By

: Ap

plic

atio

n D

esig

n-In

Cen

ter (

Fols

om, C

A)

C

1528

Mon

day,

Aug

ust 2

7, 2

001

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

SD0

SD1

SD2

SD3

SD4

SD5

SD6

SD7

SD9

SD10

SD11

SD12

SD13

SD14

SD15

SD8

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

LA17

LA18

LA19

LA20

LA21

LA22

LA23

SD[1

5:0]

19,2

2,24

,26

SA[1

9:0]

19,2

2,24

,26

LA[2

3:17

]19

,24

IRQ

119

,20,

22IR

Q3

19,2

0,22

,24

IRQ

419

,20,

22,2

4IR

Q5

19,2

0,22

,24

IRQ

619

,20,

22,2

4IR

Q7

19,2

0,22

,24

IRQ

919

,20,

24IR

Q10

19,2

0,22

,24

IRQ

1119

,20,

24IR

Q12

19,2

0,22

,24

IRQ

1419

,20,

21,2

2,24

IRQ

1519

,20,

21,2

2,24

DR

Q0

20,2

2,24

MEM

R#

19,2

4,26

IOR

#19

,22,

24

IOC

S16#

19,2

4M

EMC

S16#

19,2

4IO

CH

K#19

,24

REF

RES

H#

19,2

4M

ASTE

R16

#24

DR

Q1

20,2

2,24

DR

Q2

20,2

2,24

DR

Q3

20,2

2,24

DR

Q5

20,2

4D

RQ

620

,24

DR

Q7

20,2

4

MEM

W#

19,2

4,26

IOW

#19

,22,

24,2

6

IOC

HR

DY

19,2

2,24

ZER

OW

S#19

,24

-PER

R10

,16,

17-S

ERR

6,10

,16,

17,1

9

-FR

AME

6,10

,16,

17,1

9

-IRD

Y6,

10,1

6,17

,19

-TR

DY

6,10

,16,

17,1

9-D

EVSE

L6,

10,1

6,17

,19

-STO

P6,

10,1

6,17

,19

-PLO

CK

6,10

,16,

17

PIR

QB#

10,1

6,17

,18,

19,2

0

PIR

QD

#10

,16,

17,1

9,20

PIR

QC

#10

,16,

17,1

8,19

,20

-PR

EQ0

6,16

,19

-PR

EQ1

6,16

,19

-PR

EQ2

6,17

,19

PIR

QA#

10,1

6,17

,19,

20

-PR

EQ3

6,10

,19

-PG

NT0

6,16

-PG

NT1

6,16

-PG

NT2

6,17

-PG

NT3

6,10

SDO

NE

16,1

7-S

BO16

,17

REQ

64#

16,1

7AC

K64#

16,1

7

PAR

6,10

,16,

17,1

9

-PR

EQ4

6

-PH

OLD

6,19

-PH

OLD

A6,

19 -PG

NT4

6

SMEM

W#

19,2

4SM

EMR

#19

,24

SBH

E#19

,24

BALE

19,2

4

A20M

#4,

20IN

IT4,

20

CPU

RST

20

IGN

NE#

4,20

NM

I4,

20IN

TR4,

19,2

0

STPC

LK_P

#20

SLP#

4,20

APIC

CS#

19,2

0SM

BDAT

A8,

11,1

2,13

,14,

20SM

BCLK

8,11

,12,

13,1

4,20

APIC

D1

19

APIC

D0

19

PX4_

SMI#

19,2

0

V5_0

V5_0

V3_3

V3_3

V2_5

VCC

T

R44

2.7K

RP1

3

10K

18

27

36

45

R40

10K

RP1

1

10K

18

27

36

45

R41

10K

RP2

7

10K

18

27

36

45

M2

1TP

RP2

4

10K

18

27

36

45

R49

1K

RP1

6

10K

18

27

36

45

RP1

4

10K

18

27

36

45

RP2

6

10K

18

27

36

45

RP1

2

5.6K

18

27

36

45

RP3

4

5.6K

18

27

36

45

M1

1TP

RP2

9

10K

18

27

36

45

M3

1TP

RP1

0

1K

18

27

36

45

M4

1TP

RP2

3

1K

18

27

36

45

M5

1TP

RP5

0

2.7K

18

27

36

45

M6

1TP

RP5

3

2.7K

18

27

36

45

M7

1TP

RP4

9

2.7K

18

27

36

45

M8

1TP

RP5

2

10K

18

27

36

45

M9

1TP

RP2

5

2.7K

18

27

36

45

M10

1TP

R43

10K

RP5

1

10K

18

27

36

45

M11

1TP

RP2

1

10K

18

27

36

45

RP9

10K

18

27

36

45

RP3

8

280

18

27

36

45

RP8

10K

18

27

36

45

RP4

0

280

18

27

36

45

RP3

3

10K

18

27

36

45

RP3

7

2.7K

18

27

36

45

RP3

5

10K

18

27

36

45

R46

124

RP1

9

10K

18

27

36

45

R47

124

RP1

7

10K

18

27

36

45

R71

2.7K

RP1

5

10K

18

27

36

45

A A

B B

C C

D D

E E

44

33

22

11

PCI SLOT 0

PCI SLOT 1

J7/J8 V5_0:

A5, A8, A10, A16, A59, A61, A62 | A1, A3, A4

B5, B6, B19, B22, B59, B61, B62

J7/J8 V3_3:

A21, A27, A33, A39 A45, A53

B25, B31, B36, B41, B43, B54

J7/J8 NC:

A9, A11, A14, A19

B10, B14

J7/J8 GND:

A12, A13, A18, A24, A30, A35, A37, A42, A48, A56

B3, B12, B13, B15, B17, B28, B34, B38, B46, B49,

B57

J7/J8 +12V: A2

-12V: B1





PC

I C

onne

ctor

s 0

and

1

A0

Inte

l® P

entiu

m®

III -

Low

Pow

er /

440B

X AG

Pset

Ref

eren

ce D

esig

n

Int

el C

orpo

ratio

n

Em

bedd

ed In

tel A

rchi

tect

ure

Div

isio

n 5

000

W. C

hand

ler B

lvd.

Cha

ndle

r, AZ

852

26-3

699

Des

igne

d By

: Ap

plic

atio

n D

esig

n-In

Cen

ter (

Fols

om, C

A)

C

1628

Mon

day,

Aug

ust 2

7, 2

001

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

-C/B

E[3:

0]

-C/B

E3

-C/B

E2

-C/B

E1

-C/B

E0

AD4

AD9

AD17

AD5

AD13

AD14

AD3

AD20

AD31

AD26

AD22

AD24

AD25

AD2

AD11

AD21

AD10

AD7

AD15

AD0

AD29

AD30

AD16

AD28

AD8

AD1

AD18

AD12

AD23

AD19

AD27

AD6

PCIA

2

AD28

-C/B

E3

-C/B

E2

-C/B

E1

-C/B

E0

PIR

QA#

PIR

QC

#

PIR

QD

#PI

RQ

B#

AD16

AD3

AD17

AD18

AD22

AD13

AD5

AD24

AD8

AD25

AD12

AD6

AD10

AD21

AD27

AD1

AD29

AD11

AD7

AD26

AD20

AD4

AD23

AD30

AD15

AD31

AD19

AD28

AD0

AD2

AD14

AD9

-IRD

Y

-DEV

SEL

-PLO

CK

-PER

R-S

ERR

PCIB

2

SDO

NE

-SBO

PAR

AD29

-STO

P

-TR

DY

-FR

AME

-PC

IRST

ACK6

4#R

EQ64

#

PCIC

LK1

PCI_

TCLK

PCI_

TRST

PCI_

TMS

PCI_

TDI

AD[3

1:0]

6,10

,17,

19

-C/B

E[3:

0]6,

10,1

7,19

PCIC

LK1

14-P

REQ

06,

15,1

9

-IRD

Y6,

10,1

5,17

,19 -D

EVSE

L6,

10,1

5,17

,19

-PLO

CK

6,10

,15,

17-P

ERR

10,1

5,17

-SER

R6,

10,1

5,17

,19

-PC

IRST

6,10

,17,

18,1

9

-PG

NT0

6,15

-FR

AME

6,10

,15,

17,1

9

-TR

DY

6,10

,15,

17,1

9

-STO

P6,

10,1

5,17

,19

SDO

NE

15,1

7-S

BO15

,17

PAR

6,10

,15,

17,1

9

PCIC

LK2

14-P

GN

T16,

15-P

REQ

16,

15,1

9

PIR

QD

#10

,15,

17,1

9,20

PIR

QB#

10,1

5,17

,18,

19,2

0PI

RQ

C#

10,1

5,17

,18,

19,2

0PI

RQ

A#10

,15,

17,1

9,20

ACK6

4#15

,17

REQ

64#

15,1

7

PCI_

TDI

17PC

I_TM

S17

PCI_

TRST

17PC

I_TC

LK17

V3_3

V5_0

V3_3

V5_0

AD[3

1:0]

C86

0.1u

FC

117

0.1u

FC

67 0.01

uFC

740.

01uF

C11

40.

1uF

C11

910

uFC

5510

uFC

120

10uF

C56

10uF

R12

220

R13

220

J7 PCI C

onn

A8A1 A9 A10

A2B1

A3 A4

B60

A5 A6

B36

A7 A11

B61

A12

A13

B2

A14

A15

B37

A16

A17

B3

A18

B38

A19

B62

A20

B4

A21

B39B5 B40B6 B41B7 B42B8 B43B9 B44

A22

B10

A23

B45

A24

B11

A25

B12

A26

B13

A27

B14

A28

B46

A29

B15

A30

B16

A31

B47

A32

B17

A33

B18

A34

B48

A35

B19

A36

B20

A37

B49

A38

B21

A39

B22

A40

B52

A41

B23

A42

B24

A43

B53

A44

B25

A45

B26

A46

B54

A47

B27

A48

B28

A49

B55

A52

B29

A53

B30

A54

B56

A55

B31

A56

B32

A57

B57

A58

B33

A59

B34

A60

B58

A61

B35

A62

B59

V5_0

TRST N

CV5

_0

+12V

-12V

TMS

TDI

ACK6

4

V5_0

INTA

V3_3

INTC N

C

V5_0

GN

DG

ND

TCK

NC

RST

DEV

SEL

V5_0

GN

T

GN

D

GN

D

GN

D

NC

V5_0

AD[3

0]

TDO

V3_3

LOC

K

V5_0

PER

R

V5_0

V3_3

INTB

SER

R

INTD

V3_3

PRSN

T1

C/B

E1

AD[2

8]

NC

AD[2

6]

AD[1

4]

GN

D

PRSN

T2

AD[2

4]

GN

D

IDSE

L

GN

D

V3_3

NC

AD[2

2]

GN

D

AD[2

0]

GN

D

GN

D

CLK

AD[1

8]

AD[1

2]

AD[1

6]

GN

D

V3_3

REQ

FRAM

E

AD[1

0]

GN

D

V5_0

TRD

Y

AD[3

1]

GN

D

GN

D

STO

P

AD[2

9]

V3_3

GN

D

SDO

NE

AD[0

8]

SBO

AD[2

7]

GN

D

AD[2

5]

PAR

AD[0

7]

AD[1

5]

V3_3

V3_3

C/B

E3

AD[1

3]

V3_3

AD[1

1]

AD[2

3]

GN

D

GN

D

AD[0

9]

AD[0

5]

C/B

E0

AD[2

1]

V3_3

AD[1

9]

AD[0

6]

AD[0

3]AD

[04]

V3_3

GN

D

AD[1

7]

AD[0

2]G

ND

AD[0

0]

C/B

E2

V5_0

GN

D

REQ

64

AD[0

1]

V5_0

IRD

Y

V5_0

V5_0

J8 PCI C

onn

A8A1 A9 A10

A2B1

A3 A4

B60

A5 A6

B36

A7 A11

B61

A12

A13

B2

A14

A15

B37

A16

A17

B3

A18

B38

A19

B62

A20

B4

A21

B39B5 B40B6 B41B7 B42B8 B43B9 B44

A22

B10

A23

B45

A24

B11

A25

B12

A26

B13

A27

B14

A28

B46

A29

B15

A30

B16

A31

B47

A32

B17

A33

B18

A34

B48

A35

B19

A36

B20

A37

B49

A38

B21

A39

B22

A40

B52

A41

B23

A42

B24

A43

B53

A44

B25

A45

B26

A46

B54

A47

B27

A48

B28

A49

B55

A52

B29

A53

B30

A54

B56

A55

B31

A56

B32

A57

B57

A58

B33

A59

B34

A60

B58

A61

B35

A62

B59

V5_0

TRST N

CV5

_0

+12V

-12V

TMS

TDI

ACK6

4

V5_0

INTA

V3_3

INTC N

C

V5_0

GN

DG

ND

TCK

NC

RST

DEV

SEL

V5_0

GN

T

GN

D

GN

D

GN

D

NC

V5_0

AD[3

0]

TDO

V3_3

LOC

K

V5_0

PER

R

V5_0

V3_3

INTB

SER

R

INTD

V3_3

PRSN

T1

C/B

E1

AD[2

8]

NC

AD[2

6]

AD[1

4]

GN

D

PRSN

T2

AD[2

4]

GN

D

IDSE

L

GN

D

V3_3

NC

AD[2

2]

GN

D

AD[2

0]

GN

D

GN

D

CLK

AD[1

8]

AD[1

2]

AD[1

6]

GN

D

V3_3

REQ

FRAM

E

AD[1

0]

GN

D

V5_0

TRD

Y

AD[3

1]

GN

D

GN

D

STO

P

AD[2

9]

V3_3

GN

D

SDO

NE

AD[0

8]

SBO

AD[2

7]

GN

D

AD[2

5]

PAR

AD[0

7]

AD[1

5]

V3_3

V3_3

C/B

E3

AD[1

3]

V3_3

AD[1

1]

AD[2

3]

GN

D

GN

D

AD[0

9]

AD[0

5]

C/B

E0

AD[2

1]

V3_3

AD[1

9]

AD[0

6]

AD[0

3]AD

[04]

V3_3

GN

D

AD[1

7]

AD[0

2]G

ND

AD[0

0]

C/B

E2

V5_0

GN

D

REQ

64

AD[0

1]

V5_0

IRD

Y

V5_0

V5_0

C10

60.

1uF

C90

0.1u

F

C80

0.01

uF

C77

0.01

uFC

810.

01uF

C78

0.01

uF

C73

0.1u

FC

116

0.1u

FC

66 0.01

uFC

113

0.01

uFC

850.

1uF

C91

0.1u

FC

107

0.1u

F

A A

B B

C C

D D

E E

44

33

22

11

PCI SLOT 2





PC

I C

onne

ctor

2

A0

Inte

l® P

entiu

m®

III -

Low

Pow

er /

440B

X AG

Pset

Ref

eren

ce D

esig

n

Int

el C

orpo

ratio

n

Em

bedd

ed In

tel A

rchi

tect

ure

Div

isio

n 5

000

W. C

hand

ler B

lvd.

Cha

ndle

r, AZ

852

26-3

699

Des

igne

d By

: Ap

plic

atio

n D

esig

n-In

Cen

ter (

Fols

om, C

A)

C

1728

Mon

day,

Aug

ust 2

7, 2

001

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

AD4

AD9

AD17

AD5

AD13

AD14

AD3

AD20

AD31

AD26

AD22

AD24

AD25

AD2

AD11

AD21

AD10

AD7

AD15

AD0

AD29

AD30

AD16

AD28

AD8

AD1

AD18

AD12

AD23

AD19

AD27

AD6

PCIC

2

AD30

-C/B

E2

-C/B

E3

-C/B

E1

-C/B

E0

-C/B

E[3:

0]

PCI_

TDI

PCI_

TMS

PCI_

TCLK

PCI_

TRST

AD[3

1:0]

6,10

,16,

19

-C/B

E[3:

0]6,

10,1

6,19

PCIC

LK3

14

-PR

EQ2

6,15

,19

-IRD

Y6,

10,1

5,16

,19 -D

EVSE

L6,

10,1

5,16

,19

-PLO

CK

6,10

,15,

16-P

ERR

10,1

5,16

-SER

R6,

10,1

5,16

,19

-PC

IRST

6,10

,16,

18,1

9

-PG

NT2

6,15

-FR

AME

6,10

,15,

16,1

9

-TR

DY

6,10

,15,

16,1

9

-STO

P6,

10,1

5,16

,19

SDO

NE

15,1

6-S

BO15

,16

PAR

6,10

,15,

16,1

9

PIR

QB#

10,1

5,16

,18,

19,2

0PI

RQ

D#

10,1

5,16

,19,

20PI

RQ

C#

10,1

5,16

,18,

19,2

0PI

RQ

A#10

,15,

16,1

9,20

ACK6

4#15

,16

REQ

64#

15,1

6

PCI_

TDI

16PC

I_TM

S16

PCI_

TRST

16PC

I_TC

LK16

V3_3

V5_0

V5_0

AD[3

1:0]

C68

0.01

uFC

750.

1uF

C12

110

uFC

5710

uF

R14

220

R69

4.7K

R66

4.7K

R68

4.7K

R67

4.7K

J9 PCI C

onn

A8A1 A9 A10

A2B1

A3 A4

B60

A5 A6

B36

A7 A11

B61

A12

A13

B2

A14

A15

B37

A16

A17

B3

A18

B38

A19

B62

A20

B4

A21

B39B5 B40B6 B41B7 B42B8 B43B9 B44

A22

B10

A23

B45

A24

B11

A25

B12

A26

B13

A27

B14

A28

B46

A29

B15

A30

B16

A31

B47

A32

B17

A33

B18

A34

B48

A35

B19

A36

B20

A37

B49

A38

B21

A39

B22

A40

B52

A41

B23

A42

B24

A43

B53

A44

B25

A45

B26

A46

B54

A47

B27

A48

B28

A49

B55

A52

B29

A53

B30

A54

B56

A55

B31

A56

B32

A57

B57

A58

B33

A59

B34

A60

B58

A61

B35

A62

B59

V5_0

TRST N

CV5

_0

+12V

-12V

TMS

TDI

ACK6

4

V5_0

INTA

V3_3

INTC N

C

V5_0

GN

DG

ND

TCK

NC

RST

DEV

SEL

V5_0

GN

T

GN

D

GN

D

GN

D

NC

V5_0

AD[3

0]

TDO

V3_3

LOC

K

V5_0

PER

R

V5_0

V3_3

INTB

SER

R

INTD

V3_3

PRSN

T1

C/B

E1

AD[2

8]

NC

AD[2

6]

AD[1

4]

GN

D

PRSN

T2

AD[2

4]

GN

D

IDSE

L

GN

D

V3_3

NC

AD[2

2]

GN

D

AD[2

0]

GN

D

GN

D

CLK

AD[1

8]

AD[1

2]

AD[1

6]

GN

D

V3_3

REQ

FRAM

E

AD[1

0]

GN

D

V5_0

TRD

Y

AD[3

1]

GN

D

GN

D

STO

P

AD[2

9]

V3_3

GN

D

SDO

NE

AD[0

8]

SBO

AD[2

7]

GN

D

AD[2

5]

PAR

AD[0

7]

AD[1

5]

V3_3

V3_3

C/B

E3

AD[1

3]

V3_3

AD[1

1]

AD[2

3]

GN

D

GN

D

AD[0

9]

AD[0

5]

C/B

E0

AD[2

1]

V3_3

AD[1

9]

AD[0

6]

AD[0

3]AD

[04]

V3_3

GN

D

AD[1

7]

AD[0

2]G

ND

AD[0

0]

C/B

E2

V5_0

GN

D

REQ

64

AD[0

1]

V5_0

IRD

Y

V5_0

V5_0

C82

0.01

uFC

790.

01uF

C10

80.

1uF

C92

0.1u

FC

118

0.1u

FC

870.

1uF

C11

50.

01uF

A A

B B

C C

D D

E E

44

33

22

11

Stub length from connector to resistor

must be less than 0.1"

Pin A3 is tied to ground per AGP Specification

Rev 1.0





AG

P C

onne

ctor

A0

Inte

l® P

entiu

m®

III -

Low

Pow

er /

440B

X AG

Pset

Ref

eren

ce D

esig

n

Int

el C

orpo

ratio

n

Em

bedd

ed In

tel A

rchi

tect

ure

Div

isio

n 5

000

W. C

hand

ler B

lvd.

Cha

ndle

r, AZ

852

26-3

699

Des

igne

d By

: Ap

plic

atio

n D

esig

n-In

Cen

ter (

Fols

om, C

A)

C

1828

Mon

day,

Aug

ust 2

7, 2

001

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

SBA6

SBA4

SBA7

SBA5

SBA3

SBA1

SBA2

SBA0

GAD

30G

AD28

GAD

26G

AD24

GAD

22G

AD20

GAD

18G

AD16

GAD

15

GAD

13G

AD11

GAD

9

GAD

6

GAD

4G

AD2

GAD

0G

AD1

GAD

3G

AD5

GAD

7

GAD

8G

AD10

GAD

12G

AD14

GAD

17

GAD

19G

AD21

GAD

23

GAD

25G

AD27

GAD

29G

AD31

GC

/BE#

1

GC

/BE#

2

GC

/BE#

3

GC

/BE#

0

GAD

_STB

0

GAD

_STB

1

GSB

_STB

GFR

AME#

GIR

DY#

GTR

DY#

GST

OP#

GD

EVSE

L#

GR

EQ#

GG

NT#

GPI

PE#

GR

BF#

GPA

R

GPM

E#

SBA[

7:0]

6

GAD

[31:

0]6

GC

/BE#

[3:0

]6

GIR

DY#

6

GD

EVSE

L#6

GAD

_STB

06G

AD_S

TB1

6

GSB

_STB

6

GC

LK6

GR

EQ#

6

GST

26

GR

BF#

6

GST

06

GPA

R6

GPM

E#20

GST

OP#

6G

TRD

Y#6

GFR

AME#

6

GPI

PE#

6

GST

16

GG

NT#

6-P

CIR

ST6,

10,1

6,17

,19

PIR

QB#

10,1

5,16

,17,

19,2

0PI

RQ

C#

10,1

5,16

,17,

19,2

0

V5_0

V3_3

V3_3

+12V

V3_3

V3.3

SUS

V3_3

V3_3

V3_3

V5_0

V5_0

V3_3

R78

8.2K

C18

60.

01uF

R79

8.2K

R80

8.2K

R82

8.2K

R81

8.2K

R72

8.2K

R73

8.2K

R74

8.2K

R86

8.2K

R75

8.2K

R84

8.2K

R83

8.2K

R85

8.2K

R65

4.7K

U2B

74AS

07

34

14 7

R64

4.7K

U2A

74AS

07

12

14 7

C18

50.

01uF

C18

40.

01uF

C17

90.

01uF

C17

80.

01uF

C16

60.

01uF

J13

AGP

Con

nect

or

A26

B26

A1B1 B2

7A2

7

A2

B28

A3 A28

B29B2

A4

B30

A29

B3 B31

A5 A30

B32

A6

B4 B33

A31

A7

B34B5

A32

B35

A8 A9

B36

A33

B6 B37

A10

A34

B38B7

A11

B39

A35

A12

B40B8

A36

B41

A13

B9 B42

A37

A14

B43

A15

A38

B44

B10

A16

B45

A39

B11

B46

A17

A40

B47

A18

B12

B48

A41

A19

B49

B13

A42

B50

A20

A21

B51

A43

B14

B52

B15

A44

B53

B16

B17

B54

A45

B18

B55

B19

A46

B56

B20

B21

B57

A47

B58

A48

B59

A49

B60

A50

B61

A51

B62

A52

B63

A53

B64

A54

B65

A55

B66

A56

A57

A58

A59

A60

A61

A62

A63

A64

A65

A66

AD30

AD31

12V

OVR

CN

T#

AD29

AD28

SPAR

E

3.3V

RES

ERVE

D

3.3V

AD27

5.0V

USB

-

AD25

AD26

5.0V

GN

D

GN

D

AD24

AD_S

TB1

INTA

#

USB

+

AD23

GN

D

RST

#

VDD

Q3.

3

GN

D

RES

ERVE

D

AD21

GN

T#3.

3V

AD19

C/B

E3#

INTB

#

GN

D

ST1

VDD

Q3.

3

AD17

CLK

RES

ERVE

D

C/B

E2#

AD22

PIPE

#

VDD

Q3.

3

REQ

#

AD20

IRD

Y#

GN

D

3.3V

SPAR

E

GN

D

SPAR

E

GN

D

SBA1

AD18

SPAR

E

ST0

3.3V

3.3V

AD16

ST2

DEV

SEL#

SBA3

VDD

Q3.

3

VDD

Q3.

3

RES

ERVE

D

RBF

#

PER

R#

FRAM

E#

GN

D

GN

D

GN

D

NC

SER

R#

SBA5

SBA7

C/B

E1#

GN

D

SPAR

E

VDD

Q3.

3

SBA0

NC

AD14

3.3V

SBA2

AD12

3.3V

SB_S

TB

GN

D

GN

D

TRD

Y#

AD10

SBA4

SBA6

AD8

STO

P#

VDD

Q3.

3

PME#

AD_S

TB0

GN

D

AD7

PAR

GN

D

AD15

AD5

VDD

Q3.

3

AD3

AD13

VDD

Q3.

3

AD11

AD1

GN

D

SMB0

AD9

C/B

E0#

3.3V

RES

ERVE

DAD

6G

ND

AD4

AD2

VDD

Q3.

3AD

0SM

B1

C16

70.

01uF

R87

8.2K

C17

70.

01uF

R77

8.2K

C17

20.

01uF

R76

8.2K

C18

00.

01uF

A A

B B

C C

D D

E E

44

33

22

11

PIIX4 is PCI

device #8

This circuit is to prevent IOAPIC

from being powered by IRQ#8

when in suspend and power

is not applied to device.

Note: U14, C203,C215, C210 and

R51 are not populated





Plac

e ne

ar P

IIX4

PII

X4E

Par

t 1

A0

Inte

l® P

entiu

m®

III -

Low

Pow

er /

440B

X AG

Pset

Ref

eren

ce D

esig

n

Int

el C

orpo

ratio

n

Em

bedd

ed In

tel A

rchi

tect

ure

Div

isio

n 5

000

W. C

hand

ler B

lvd.

Cha

ndle

r, AZ

852

26-3

699

Des

igne

d By

: Ap

plic

atio

n D

esig

n-In

Cen

ter (

Fols

om, C

A)

C

1928

Mon

day,

Aug

ust 2

7, 2

001

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

AD8

AD9

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AD27

AD28

AD29

AD30

AD31

PDD

0PD

D1

PDD

2PD

D3

PDD

4PD

D5

PDD

6PD

D7

PDD

8PD

D9

PDD

10PD

D11

PDD

12PD

D13

PDD

14PD

D15

SDD

0SD

D1

SDD

2SD

D3

SDD

4SD

D5

SDD

6SD

D7

SDD

8SD

D9

SDD

10SD

D11

SDD

12SD

D13

SDD

15SD

D14

SD0

SD1

SD2

SD3

SD4

SD5

SD6

SD7

SD8

SD9

SD10

SD11

SD12

SD13

SD14

SD15

LA17

LA18

LA19

LA20

LA21

LA22

LA23

SA4

SA0

SA12

SA6

SA9

SA0

SA18

SA5

SA8

SA11

SA17

SA16

SA7

SA19

SA10

SA4

SA3

SA15

SA2

SA14

SA13

SA1

SA1

MEM

R#

MEM

W#

RST

DR

V

SD0

SD1

SD2

SD3

SD4

SD5

SD6

SD7

XD0

XD1

XD2

XD3

XD4

XD5

XD6

XD7

IRQ

8_Bu

f

I13R

I13R

I21R

I22R

I21R

I22R

R_A

D18

AD18

-C/B

E0-C

/BE1

-C/B

E2-C

/BE3

RST

DR

V

IRQ

8_Bu

f

RST

DR

V

AD[3

1:0]

6,10

,16,

17

-PR

EQ0

6,15

,16

-PR

EQ1

6,15

,16

-PR

EQ2

6,15

,17

-PR

EQ3

6,10

,15

PDD

[15:

0]21

SDD

[15:

0]21

SDA0

21SD

A121

SDA2

21PD

DAC

K#21

SDD

ACK#

21PD

REQ

21SD

REQ

21PD

IOR

#21

PDIO

W#

21PI

OR

DY

21SD

IOR

#21

SDIO

W#

21SI

OR

DY

21PD

A021

PDA1

21PD

A221

SDC

S3#

21PD

CS3

#21

SDC

S1#

21PD

CS1

#21 SA

[19:

0]15

,22,

24,2

6

SD[1

5:0]

15,2

2,24

,26

LA[2

3:17

]15

,24

MEM

CS1

6#15

,24

MEM

R#

15,2

4,26

MEM

W#

15,2

4,26

SMEM

R#

15,2

4

SMEM

W#

15,2

4SY

SCLK

24BA

LE15

,24

IOC

HK#

15,2

4

REF

RES

H#

15,2

4IO

CS1

6#15

,24

ZER

OW

S#15

,24

SBH

E#15

,24

RST

DR

V22

,24

IOR

#15

,22,

24IO

W#

15,2

2,24

,26

IOC

HR

DY

15,2

2,24

AEN

22,2

4,26

APIC

CS#

15,2

0 APIC

REQ

#20

APIC

ACK1

#20

WSC

#6

PCLK

APIC

14

APIC

D0

15AP

ICD

115

APIC

CLK

014

XOE#

20XD

IR#

20

XD[7

:0]

26

PIR

QA#

10,1

5,16

,17,

20PI

RQ

B#10

,15,

16,1

7,18

,20

PIR

QC

#10

,15,

16,1

7,18

,20

PIR

QD

#10

,15,

16,1

7,20

IRQ

1515

,20,

21,2

2,24

IRQ

1215

,20,

22,2

4IR

Q11

15,2

0,24

IRQ

1015

,20,

22,2

4IR

Q9

15,2

0,24

IRQ

715

,20,

22,2

4IR

Q6

15,2

0,22

,24

IRQ

515

,20,

22,2

4IR

Q4

15,2

0,22

,24

IRQ

020

IRQ

115

,20,

22IN

TR4,

15,2

0

IRQ

315

,20,

22,2

4

IRQ

1415

,20,

21,2

2,24

IRQ

9OU

T#20

CLK

RU

N#

6,10

-DEV

SEL

6,10

,15,

16,1

7-F

RAM

E6,

10,1

5,16

,17

-IRD

Y6,

10,1

5,16

,17

PAR

6,10

,15,

16,1

7

-PH

OLD

A6,

15-S

ERR

6,10

,15,

16,1

7-S

TOP

6,10

,15,

16,1

7-T

RD

Y6,

10,1

5,16

,17

-C/B

E[3:

0]6,

10,1

6,17

RST

DR

V#21

IRQ

#820

PX4_

SMI#

15,2

0

SMI#

4

-PH

OLD

6,15

-PC

IRST

6,10

,16,

17,1

8

V5_0

V3.3

SUS

V2_5

V5_0

VCC

T

R50

680

C22

947

pF

R51

1K

R39

220

RP5

9

10K

18

27

36

45

D4

Bat5

4

31

2

PCI

SIGNALS

IDE

SIGNALS

IDE

SIGNALS

ISA/EIO

SIGNALS

PIIX4E

U8A PI

IX4E

C8

G16C

6

G19D

4

G18D

2

C17

C10

G17E5 A17A5

Y15

A3 F18B5 B17B6 A16A1

V3B1

2

F17

A12

A18A6 F16

D5

T14

C5

G20

U11

C16

W14

B16

W3

D16

U13

E15

V13

U2

Y13

T11

T12

T2

F20

W2

W11

Y2B15

T1Y11

V1 W16

T10

T16

D14

Y17

W10

V17

E18

Y18

U9

W18

C14

Y19

V9 W19

B10

Y9A14

T8

E20

W8

C13

U7

V7A13

Y7

D18

V6C12

Y6

A10

T5D12

W5

D20

U4

B13

V4D13

C20

B14

D9

E14

B20

A15

C15

A20

D15

C9

A19B9 B19A9 C

19D8

D19E8 D17B8 E19A8 E17

D7

F19

C7 B7 A7 D6 E6 E4 C4 B4 A4 D3 E3 C3 B3 E2 C2 B2 A2 D1 E1 C1 B1

C18

H16

B18

H17

E10

A11

B11

C11

Y12

V15

U15

W4

U3

T7 U10

Y1 W7

V12

Y3 W12

W1

Y5 T4 T3 Y4

C/B

E#0

PDA0

C/B

E#1

PDD

ACK#

C/B

E#2

PDA1

C/B

E#3

SDA0

CLO

CKR

UN

#

PDA2

DEV

SEL#

SDD

ACK#

FRAM

E#

GPO

1/LA

17

IDSE

L

PDR

EQ#

IRD

Y#

SDA1

PAR

SDR

EQ#

PCIR

ST#

SD0

PHO

LD#

PDIO

R#

PHO

LDA#

SDA2

SER

R#

PDIO

W#

STO

P#

GPO

2/LA

18

TRD

Y#

PIO

RD

Y

SA0

SDIO

R#

GPO

3/LA

19

SDIO

W#

SD1

SIO

RD

Y

GPO

4/LA

20

SDD

0

GPO

5/LA

21

SD2

GPO

6/LA

22

SA1

GPO

7/LA

23

SD3

PDD

0

SD4

SA2

SD5

SDD

1

SD6

SA3

SD7

SD8

SA4

SD9

SDD

2

SD10

SA5

SD11

PDD

1

SD12

SA6

SD13

SDD

3

SD14

SA7

SD15

AD0

SA8

SDD

4

SA9

PDD

2

SA10

SDD

5

SA11

SA12

SDD

6

SA13

PDD

3

SA14

SDD

7

SA15

AD1

SA16

SDD

8

SA17

PDD

4

SA18

SDD

9

SA19

SDD

10

PDD

5

SDD

11

AD2

SDD

12

PDD

6

SDD

13SD

D14

PDD

7

SDD

15

AD3

PDD

8

AD4

PDD

9

AD5

PDD

10

AD6

PDD

11

AD7

PDD

12

AD8

PDD

13

AD9

PDD

14

AD10

PDD

15

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AD27

AD28

AD29

AD30

AD31

DS3

S#D

S3P#

DS1

S#D

S1P#

REQ

0#R

EQ1#

REQ

2#R

EQ3#

MEM

CS1

6#M

EMR

#M

EMW

#SM

EMR

#

SMEM

W#

SYSC

LKG

PO0/

BALE

GPI

0/IO

CH

K#

REF

RES

H#

IOC

S16#

ZER

OW

S#

SBH

E#R

STD

RV

IOR

#IO

W#

IOC

HR

DY

AEN

U14 82

093A

A

7

1

20

64

32

33

36

17

45

52

46

19

47

4

48

51

49

34

63

5 35

59

25

58

26

57

27

56

28

55

29

54

31

53

30

50

24

15

23

13

22

14

16

12

18

11

21

61

37

9

38

10

39

8

40

2

41

60

4262 43 44 6

3

NC

GND

NC

VCC

NC

GND

NC

INTI

N0

NC

GND

NC

VCC

NC

APIC

D0

NC

VCC

NC

INTI

N1

NC

APIC

D1

INTI

N2

D0

INTI

N3

D1

INTI

N4

D2

INTI

N5

D3

INTI

N6

D4

INTI

N7

D5

INTI

N8

D6

INTI

N9

D7

INTI

N10

D/I#

INTI

N11

A0

INTI

N12

A1

INTI

N13

RD

#

INTI

N14

WR

#

INTI

N15

CS#

INTI

N16

APIC

REQ

#

INTI

N17

APIC

ACK1

#

INTI

N18

APIC

ACK2

#

INTI

N19

PCIC

LK

INTI

N20

RES

ET

INTI

N21

APIC

CLK

INTI

N22

INTI

N23

/SM

I#SM

IOU

T#

TEST

IN#

U7

74AL

S245

2 3 4 5 6 7 8 9 19 1

18 17 16 15 14 13 12 11

A1 A2 A3 A4 A5 A6 A7 A8 G DIR

B1 B2 B3 B4 B5 B6 B7 B8

C20

30.

1uF

C21

50.

1uF

C21

00.

1uF

U21

B

74H

CT1

4

34

U15

A74

LVC

125

23

14

1

7

R11

710

K

J23

JUM

P3

1

2

3

A A

B B

C C

D D

E E

44

33

22

11

1-2 Normal Operation

2-3 Clear CMOS

Keep crystal close to PIIX4 and

caps close to crystal

Trace lengths

should be equal





Do not populate.

R110

PII

X4E

Par

t 2

Populate R366 and

remove R306 if

STPCLK controlled

by microcontroller

and not by PIIX4E.

A0

Inte

l® P

entiu

m®

III -

Low

Pow

er /

440B

X AG

Pset

Ref

eren

ce D

esig

n

Int

el C

orpo

ratio

n

Em

bedd

ed In

tel A

rchi

tect

ure

Div

isio

n 5

000

W. C

hand

ler B

lvd.

Cha

ndle

r, AZ

852

26-3

699

Des

igne

d By

: Ap

plic

atio

n D

esig

n-In

Cen

ter (

Fols

om, C

A)

C

2028

Mon

day,

Aug

ust 2

7, 2

001

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

EXTS

MI#

THER

M#

SER

IRQ

BATL

OW

#

TEST

#C

ON

FIG

2

SMBA

LER

T#

LID

LID

EXTS

MI#

CO

NFI

G2

SER

IRQ

BATL

OW

#

TEST

#

SMBA

LER

T#

IRQ

#8

THER

M#

IRQ

1415

,19,

21,2

2,24

DAC

K5#

24

DR

Q1

15,2

2,24

PIR

QA#

10,1

5,16

,17,

19

IRQ

415

,19,

22,2

4

TC22

,24

DAC

K3#

22,2

4U

SBP1

+23

APIC

CS#

15,1

9

DAC

K6#

24

NM

I4,

15

OC

0#23

USB

P0+

23

DR

Q0

15,2

2,24

DR

Q5

15,2

4

CPU

RST

15

IRQ

1015

,19,

22,2

4

FER

R#

4

IRQ

9OU

T#19

PCIC

LKF

14

PIR

QC

#10

,15,

16,1

7,18

,19

IRQ

715

,19,

22,2

4

SMBD

ATA

8,11

,12,

13,1

4,15

IRQ

1515

,19,

21,2

2,24

IRQ

615

,19,

22,2

4

DR

Q3

15,2

2,24

KBD

RST

#22

IRQ

019

PIR

QD

#10

,15,

16,1

7,19

DAC

K2#

22,2

4

PX4_

SMI#

15,1

9

CPU

_STO

P#14

XOE#

19

KBD

A20G

ATE

22

USB

P1-

23

DR

Q2

15,2

2,24

A20M

#4,

15

APIC

ACK1

#19

DAC

K0#

22,2

4

USB

P0-

23

APIC

REQ

#19

DR

Q7

15,2

4

DAC

K1#

22,2

4

IRQ

115

,19,

22

XDIR

#19

PIR

QB#

10,1

5,16

,17,

18,1

9

IRQ

#819

PWR

OK

6,27

SLP#

4,15

REF

214

BIO

SCS#

26

DAC

K7#

24

IRQ

915

,19,

24

IRQ

515

,19,

22,2

4

IRQ

315

,19,

22,2

4

USB

CLK

014

OC

1#23

IRQ

1215

,19,

22,2

4IR

Q11

15,1

9,24

DR

Q6

15,2

4

SMBC

LK8,

11,1

2,13

,14,

15

RSM

RST

#27

GPM

E#18

SUSA

#14

SUS_

STAT

1#6

PWR

BTN

#27

PWR

ON

#27

IGN

NE#

4,15

INTR

4,15

,19

INIT

4,15

PCI_

STO

P#14

STPC

LK#

4,8

STPC

LK_P

#15

V3_3

V3_3

V3.3

SUS

V5_0

V3_3

V3.3

SUS

V3.3

SUS

V3_3

V3.3

SUS

V3.3

SUS

RP3

110

K1

82

73

64

5

RP3

2

10K

18

27

36

45

RP3

610

K1

82

73

64

5

RP2

810

K1

82

73

64

5

RP3

0

10K

18

27

36

45

R30

90

D3

Bat5

4

31

2

Y2 32.7

68KH

z

12

R30

00

D6

Bat5

4

31

2

C13

3

10pF

R30

10

D7

Bat5

4

3 1

2

U24

E

74LV

C14

1110

14 7

C13

2

10pF

R30

20

DMA/IRQ

SIGNALS

USB

SIGNALS

POWER

MGMT.

CPU

INTERFACE

SYSTEM

X-BUS

PIIX4E

VSS

- D1

0,E7

,E13

,J[9

:12]

K[9:

12],

L[9:

12],

M[9:

12]

VSSU

SB J

5

U8B

PIIX

4E

D10

K5

E7

T6

E13

N16

J9R15J10

R16

J11

P15

J12

J4

K9

R7

K10

R6

K11

G6

K12

N18

L9

F14L10

F15

L11F5 L12

G4

M9E16M10

E11

M11E12

M12

N3

J5

E9

F6

M16

P19

M5

R5

T19

R1

G5

L2 F2V20

F3J3 F4R2

L5

K20

K3K16

K4W20

H1

T17

H4

M19

H5

T18

G3

V19

H19

H20

U19

U18

M17

K19

U20

L17

P16

U6

T20

L18

R19

L19

N17

J20

P18

P1 L20

U14 P20

J18T9 N

20M

20V2

M18 K17

W9

V18

R17W6

R18U

8

U5 V8Y10 Y8Y16

Y20V5 U1

U16

U12T15

W13U17 T13

V16

V14

W17 Y1

4

W15 M

1N

2 P3 N1 P2 P4 V10

J17

H18 K18

J19

R3

R4 P5 G1

M4

M3

M2 L1 K2 K1 R

20N

19 L16

P17 L3 V11

D11

F1 H2

G2

H3

J1 J2 J16

N4

L4 N5

VSS

VCCSUSB

VSS

VCCP

VSS

VCCSUS

VSSVCCVSS

VCCSUS

VSS

VCCP

VSS

N/C

VSS

VCCP

VSS

VCC

VSS

VCCP

VSS

N/C

VSS

VCCPVSS

VCC

VSSVCCP VSS

GPO

0

VSSVCCPVSS

VCC

VSSVCCP

VSS

N/C

VSSUSB

VCCP

VCC

N/C

GPI

1

N/C

N/C

GPO

8

GPO

17/C

PU_S

TP#

GPO

27

GPI

13

GPO

28

EXTS

MI#

GPO

29/IR

Q9O

ut

GPI

14

GPO

30

GPO

18/P

CI_

STP#

GPI

15

SLP#

GPI

16

GPO

19/Z

Z

GPI

17

SUSA

#

GPI

18

GPO

20/S

US_

STAT

1#

GPI

19

CPU

RST

GPI

20

GPO

21/S

US_

STAT

2#

GPI

21

GPO

15/S

USB

#

GPI

8/H

CT#

IRQ

0/G

P014

GPI

9/BA

TLO

W#

GPO

16/S

USC

#

RSM

RST

#

FER

R#

PWR

BT#

IGN

NE#

GPI

10/L

ID

DR

EQ1

SMBD

ATA

INIT

SMBC

LK

INTR

GPI

11/S

MBA

LER

T#IR

Q1

GPI

12/R

I#A

A20G

ATE#

NM

I

DAC

K0#

SMI#

STPC

LK#

IRQ

3

RC

IN#

A20M

#

DR

EQ2

PWR

OK

SPKR

IRQ

4

TEST

#C

ON

FIG

1

DAC

K1#

CO

NFI

G2

IRQ

5

DR

EQ3

IRQ

6

DAC

K2#

IRQ

7

DR

EQ5

IRQ

8/G

PI6

DAC

K3#

IRQ

9

DR

EQ6

IRQ

10

DAC

K5#

IRQ

11

DR

EQ7

IRQ

12

DAC

K6#

IRQ

14

DAC

K7#

IRQ

15

DR

EQ0

REQ

A#/G

PI2

REQ

B#/G

PI3

REQ

C#/

GPI

4G

NTA

#/G

PO9

GN

TB#/

GPO

10G

NTC

#/G

PO11

TC APIC

ACK#

/GPO

12AP

ICC

S#/G

PO13

APIC

REQ

#/G

P15

SER

IRG

/GPI

7PI

RQ

A#PI

RQ

B#PI

RQ

C#

PIR

QD

#

XOE#

/GPO

23XD

IR#/

GPO

22BI

OSC

S#R

TCAL

E/G

PO25

RTC

CS#

/GPO

24KB

CC

S#/G

PO26

RTC

X2R

TCX1

VBAT

SUSC

LK48

Mhz

OSC

PCIC

LK

USB

P1+

USB

P1-

USB

P0+

USB

P0-

OC

0#O

C1#

VREF

MC

CS#

PCS0

#PC

S1#

BT1

BATT

ERY

1 2

R30

30

TP11

1TP

J24

JUM

P3

1

2

3

R30

40

TP13

1TP

C14

70.

1uF

R30

50

TP4

1TP

C18

90.

1uF

R30

60

TP15

1TP

C19

00.

1uF

R30

70

R31

0

1M

TP5

1TP

C19

20.

1uF

TP3

1TP

C18

70.

1uF

C18

80.

1uF

C12

90.

1uF

C19

30.

1uF

C19

10.

1uF

C19

50.

1uF

C19

40.

1uF

C13

410

uF

R42

1K

R63

1K

RP3

910

K1

82

73

64

5

A A

B B

C C

D D

E E

44

33

22

11

Primary IDE Connector

Secondary IDE Connector

HD Active LED





IDE

Con

nect

ors

A0

Inte

l® P

entiu

m®

III -

Low

Pow

er /

440B

X AG

Pset

Ref

eren

ce D

esig

n

Int

el C

orpo

ratio

n

Em

bedd

ed In

tel A

rchi

tect

ure

Div

isio

n 5

000

W. C

hand

ler B

lvd.

Cha

ndle

r, AZ

852

26-3

699

Des

igne

d By

: Ap

plic

atio

n D

esig

n-In

Cen

ter (

Fols

om, C

A)

C

2128

Mon

day,

Aug

ust 2

7, 2

001

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

PDD

3PD

D2

PDD

1PD

D0

PDD

12PD

D13

PDD

14PD

D15

PDD

8PD

D9

PDD

10PD

D11

PDD

4PD

D5

PDD

6PD

D7

PDIO

RD

YR

PDIR

QR

IDER

STP#

R

PDA1

RPD

A0R

PDC

S1#R

IDER

STP#

R

PDR

EQR

PDIO

W#R

PDIO

R#R

PDD

ACK#

R

PDIO

RD

YRPD

IRQ

RSD

IOR

DYR

SDIR

QR

SDD

3SD

D2

SDD

1SD

D0

SDD

12SD

D13

SDD

14SD

D15

SDD

8SD

D9

SDD

10SD

D11

SDD

4SD

D5

SDD

6SD

D7

SDIO

RD

YR

SDIR

QR

IDER

STS#

R

SDA1

RSD

A0R

SDC

S1#R

IDER

STS#

R

SDR

EQR

SDIO

W#R

SDIO

R#R

SDD

ACK#

R

RST

DR

V#

PDA2

RPD

CS3

#R

SDC

S3#R

SDA2

R

PDA2

RSD

A2R

PDC

S3#R

SDC

S3#R

CSE

L1

CSE

L2

HD

_AC

T2#

HD

_AC

T2#

SDD

7

PDD

7

PDD

[15:

0]19

PDR

EQ19

PDIO

W#

19PD

IOR

#19

PDD

ACK#

19

PDA1

19PD

A019

PDC

S1#

19R

STD

RV#

19

PIO

RD

Y19

IRQ

1415

,19,

20,2

2,24

SIO

RD

Y19

IRQ

1515

,19,

20,2

2,24

SDD

[15:

0]19

SDR

EQ19

SDIO

W#

19SD

IOR

#19

SDD

ACK#

19

SDA1

19SD

A019

SDC

S1#

19

PDA2

19SD

A219

PDC

S3#

19SD

CS3

#19

V5_0

V5_0

V5_0

R54

10k

R10

11K

R10

21K

R55

10k

R10

78.

2K R96

8.2K

R12

410

kR12

310

kR

P61

331

82

73

64

5

RP6

033

18

27

36

45

RP4

733

18

27

36

45

RP4

433

18

27

36

45

RP5

833

18

27

36

45

RP5

533

18

27

36

45

RP5

747

18

27

36

45

RP4

633

18

27

36

45

RP4

333

18

27

36

45

RP4

533

18

27

36

45

JP4

HEA

DER

20X

2

12

34

56

78

910

1112

1314

1516

1718

1920

2122

2324

2526

2728

2930

3132

3334

3536

3738

3940

RP4

233

18

27

36

45

JP3

HEA

DER

20X

2

12

34

56

78

910

1112

1314

1516

1718

1920

2122

2324

2526

2728

2930

3132

3334

3536

3738

3940

RP4

133

18

27

36

45

D5

LGS2

60-D

O

2

13

IN

NCOUT

RP5

633

18

27

36

45

U22

A

74AL

S00

1 23

RP5

433

18

27

36

45

U25

A

74AC

T05

12

14 7

R10

347

0

R10

447

0

R58

220

A A

B B

C C

D D

E E

44

33

22

11

PULL romCs# high so as not to

interfere with boot rom!

Install for 370 Config

address

Install for 3F0 Config

address

Do not stuff

Install only one

resistor!

This disables the ROM buffers.

BIOS needs to enable and

configure IRQs





Sup

er I

/O

A0

Inte

l® P

entiu

m®

III -

Low

Pow

er /

440B

X AG

Pset

Ref

eren

ce D

esig

n

Int

el C

orpo

ratio

n

Em

bedd

ed In

tel A

rchi

tect

ure

Div

isio

n 5

000

W. C

hand

ler B

lvd.

Cha

ndle

r, AZ

852

26-3

699

Des

igne

d By

: Ap

plic

atio

n D

esig

n-In

Cen

ter (

Fols

om, C

A)

C

2228

Mon

day,

Aug

ust 2

7, 2

001

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

SD0

SD1

SD2

SD3

SD4

SD5

SD6

SD7

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SD[1

5:0]

15,1

9,24

,26

SA[1

9:0]

15,1

9,24

,26

AEN

19,2

4,26

IOC

HR

DY

15,1

9,24

RST

DR

V19

,24

DAC

K3#

20,2

4D

ACK2

#20

,24

DR

Q0

15,2

0,24

DR

Q1

15,2

0,24

DR

Q2

15,2

0,24

DR

Q3

15,2

0,24

DAC

K0#

20,2

4D

ACK1

#20

,24

TC20

,24

IOR

#15

,19,

24IO

W#

15,1

9,24

,26

REF

114

RXD

025

TXD

025

RTS

0#25

CTS

0#25

DTR

0#25

DSR

0#25

DC

D0#

25R

I0#

25R

XD1

25TX

D1

25R

TS1#

25C

TS1#

25D

TR1#

25D

SR1#

25D

CD

1#25

RI1

#25

PDR

025

PDR

125

PDR

225

PDR

325

PDR

425

PDR

525

PDR

625

PDR

725

-SLC

TRIN

25-IN

IT25

-ALF

25-S

TRO

BE25

-BU

SY25

-AC

K25

PE25

SLC

T25

-ER

R25

KBD

A20G

ATE

20KB

DR

ST#

20

DR

ATE0

25H

DEN

25-IN

DEX

25-T

RK0

25-W

PT25

-MO

TEB

25-M

OTE

A25

-DR

VSB

25-D

RVS

A25

-DSK

CH

G25

-STE

P25

-DIR

25-S

IDE1

25-W

DAT

A25

-WG

ATE

25-R

DAT

A25

IRQ

115

,19,

20IR

Q3

15,1

9,20

,24

IRQ

415

,19,

20,2

4IR

Q5

15,1

9,20

,24

IRQ

615

,19,

20,2

4IR

Q7

15,1

9,20

,24

IRQ

1215

,19,

20,2

4

IRQ

1015

,19,

20,2

4

IRQ

1515

,19,

20,2

1,24

IRQ

1415

,19,

20,2

1,24

V5_0

V5_0

V5_0

V5_0

V5_0

V5_0

V3_3

FB9

BLM

41P7

50S

12 12

F3

SMD250-002

C29

470p

FC

3047

0pF

C28

470p

FC

3147

0pF

C32

470p

F

Floppy

Uarts

Parallel

ISA/Host

U1 FD

C37

B78X

8377

84 85

78

8670 87

79

88 89

80

90

96

91

81

92

82

71

113

72

97

73

7

75

98

76

115

9916 100

116

101

4810

2

117

103

56

95114

9474

110

119

111

11 107

118

108

104

106

123

105

55

109

124

10 126

58

127

12 128

40

125

8 122

60

120

9

57

17

63

5

34

3

41

15

59

14

42

13

39

1

66

2

6823 3544 3624 37 382545 26

62

2746 28 2947 30 3149 32

93

3350 51 52

12169

112

43 64 53 2261 54 18

6 4

65

67

192021

IRQ

1G

P10

IRQ

3IR

Q4

GP1

1

IRQ

5

KDAT

IRQ

6

GP1

2

IRQ

7IR

Q8

GP1

3

IRQ

10

PD0

IRQ

11/R

OM

CS#

GP1

4

IRQ

12

GP1

5

KCLK

TXD

1

MD

AT

PD1

MC

LK

VSS

KBD

RST

#

PD2

A20M

RTS

1#/S

YSO

P

PD3

RD

ATA#

PD4

CTS

1#

PD5

VSSPD

6

DTR

1#

PD7

DAC

K1#

SLC

TIN

#

DSR

1#

PIN

IT#

VSS

ALF#

DC

D1#

STR

OBE

#

WG

ATE#

BUSY

RI1

#

ACK#

VSS

PE

RXD

2/IR

RX

SLC

T

DR

Q0

ERR

OR

#

TXD

2/IR

TX

WD

ATA#

RTS

2#

DAC

K2#

CTS

2#

HD

SEL#

DTR

2#SE

R/IR

Q15

DSR

2#

DIR

#

DC

D2#

DAC

K3#

RI2

#

STEP

#

DR

Q1

DSK

CH

G#

TC

DS0

#

SA11

MTR

0#

IOR

#

WR

TPR

T#

DR

Q2

TRK0

#

IOW

#

IND

EX#

PCI_

CLK

/IRQ

14/G

P50

DR

VDEN

0

XTL1

DR

VDEN

1

XTL2

SA0

SA12

SD0

SA13

SA1

SA14

SA15

SA2

SD1

SA3

VCC

SA4

SD2

SA5

SA6

SD3

SA7

SA8

SD4

SA9

VCC

SA10

SD5

SD6

SD7

VCCVTR

RXD

1

AEN

IOC

HR

DY

RES

ET_D

RV

CLO

CK1

4

DR

Q3

DAC

K0#

CLK

32O

UT

DS1

#

MTR

1

VBAT

AVSS

POWERONBUTTON_INPME#/IRQ9

R6

1KR5

10K

R11

10K

RP4

84.

7K

18273645

C15

90.

1uF

C16

00.

1uF

C16

10.

1uF

TOP

BOTT

OM

J1 PS2

STAC

K

13 14 15 16 17

T1 T2 T3 T4 T5 T6 B1 B3 B4 B5 B6B2

GN

DG

ND

GN

DG

ND

GN

D

KBD

ATA

NC

GN

DKB

_VC

CKB

_CLK

NC

MD

ATA

GN

DM

_VC

CM

_CLK

NC

NC

FB8

BLM

41A8

00S

12

12

FB5

BLM

41A8

00S

12

12

FB7

BLM

41A8

00S

12

12

FB6

BLM

41A8

00S

12

12

A A

B B

C C

D D

E E

44

33

22

11

NOTE 1: USB differential traces route together (Z0- & Z0+) and (Z1- & Z1+).

Must be 45 Ohm Matched

Stripline width 0.015 (for 1 oz)->44.88/45.45 Ohm.

75 Ohm/100

MHz/3A

75 Ohm/100

MHz/3A

PCB Trace 45 Ohm Matched, Routed Together

Stripline width 0.015 (1 oz) 44.88/45.45

Ohm

Poly

-Fus

ePo

ly-F

use

NOTE 2: Protect differential traces w/ guard traces or

double space to any other signal.

Place As Close as

Possible to PIIX4

Place As Close as

Possible to PIIX4

PCB Trace 45 Ohm Matched,

Routed Together

Stripline width 0.015 (1 oz)

44.88/45.45 Ohm

NOTE 3: Place ferrites at connector.

NOTE 4: Poly-fuse min 1.5A

max 5A.

BOTTOM of Stacked

USB Connector

TOP of Stacked

USB Connector

Poly fuses should be in range

of 1.5A to 5A

Place these caps within 1 inch

of USB Connector stack





US

B C

onne

ctor

s

A0

Inte

l® P

entiu

m®

III -

Low

Pow

er /

440B

X AG

Pset

Ref

eren

ce D

esig

n

Int

el C

orpo

ratio

n

Em

bedd

ed In

tel A

rchi

tect

ure

Div

isio

n 5

000

W. C

hand

ler B

lvd.

Cha

ndle

r, AZ

852

26-3

699

Des

igne

d By

: Ap

plic

atio

n D

esig

n-In

Cen

ter (

Fols

om, C

A)

C

2328

Mon

day,

Aug

ust 2

7, 2

001

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

Z1_V

CC

Z0_V

CC

Z1_G

ND

Z0+

Z1-

Z1+

Z0-

USB

VFIL

1

USB

VFIL

2

USB

VFIL

1U

SBVF

IL2

Z0_G

ND

USB

P1-

20

USB

P1+

20

OC

0#20

OC

1#20

USB

P0+

20

USB

P0-

20

V5_0

R94

27

R88

15K

R95

27

R91

15K

R89

15K

FB3

BLM

41P7

50S

12 12

R92

27

F2SM

D25

0-00

2

R4

10K

FB4

BLM

41P7

50S

12 12

R3

15K

J2 USB

Sta

ck

1 2 3 4 5 6 7 8

9 10 11 12

VCC

0D

0-D

0+G

ND

0

VCC

1D

1-D

1+G

ND

1

GN

DG

ND

GN

DG

ND

R2

10K

FB1

BLM

41P7

50S

1 21 2

R1

15K

FB2

BLM

41P7

50S

1 21 2

F1SM

D25

0002

C15

80.

01uF

C15

70.

1uF

C23

0.01

uFC

220.

1uF

C12

547

pF

C12

347

pFC

122

47pF

C12

447

pF

C1

0.01

UF

C7

0.01

UF

C2

100u

FC

610

0uF

R93

27

R90

15K

A A

B B

C C

D D

E E

44

33

22

11

J5/J6 V5_0:

B03, B29,

B31, D16

J5/J6 GND:

B01,

B10, D18

J5/J6: +12V B09

-12V B07

-5V B05

Note Cap Direction

Note Cap Direction





ISA

Con

nect

ors

A0

Inte

l® P

entiu

m®

III -

Low

Pow

er /

440B

X AG

Pset

Ref

eren

ce D

esig

n

Int

el C

orpo

ratio

n

Em

bedd

ed In

tel A

rchi

tect

ure

Div

isio

n 5

000

W. C

hand

ler B

lvd.

Cha

ndle

r, AZ

852

26-3

699

Des

igne

d By

: Ap

plic

atio

n D

esig

n-In

Cen

ter (

Fols

om, C

A)

C

2428

Mon

day,

Aug

ust 2

7, 2

001

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

LA[2

3:17

]

SD[1

5:0]

SA[1

9:0]

SA7

SA12

LA21

SD12

DR

Q7

DAC

K6#

SA14

AEN

SD9

SD7

RST

DR

V

SA15

SA5

MAS

TER

16#

IOC

HR

DY

SD1

SA17

SD7

SD11

SD5

IOC

HK#

IRQ

14

SD10

LA23

SA9

DR

Q6

SD15

IOC

S16#

LA19

SD13

SA3

SD8

ZER

OW

S#

LA23

SA2

SD1

LA17

DR

Q3

LA20

SA16

LA19

SD9

LA22

SA6

SA15

SA16

SA17

IOW

#

SD6

SBH

E#

SA0

LA20

IRQ

7

MEM

W#

REF

RES

H#

DAC

K1#

LA18

SA0

SA11

SD13

IRQ

5

SD2

LA21

SD3

SD6

SA1

IRQ

6

LA17

IOR

#

MEM

R#

SD2

SA14

SA13

SD15

MEM

CS1

6#

SYSC

LK

DAC

K3#

SA2

SA4

SA6

SA18

DAC

K2#

SD4

SA4

IRQ

12

REF

0

IRQ

4

SD3

SD8

SA18

SD14

DAC

K7#

SA10

SA12

DAC

K5#

DAC

K0#

IRQ

15

SD14

SD12

SA19

SD11

TC

SD5

SA8

SA9

SA11

SA5

SA13

MEM

W#

LA22

IRQ

9

SA10

LA18

SD0

SA3

SA1

SA7

SA8

DR

Q5

DR

Q0

IRQ

11IR

Q10

BALE

IRQ

3

MEM

R#

DR

Q2

SA19

SD10

SD0

DR

Q1

SD4

MAS

TER

16#

15

IRQ

1015

,19,

20,2

2

IOC

HR

DY

15,1

9,22

MEM

W#

15,1

9,26

IRQ

1515

,19,

20,2

1,22

IOC

S16#

15,1

9M

EMC

S16#

15,1

9

TC20

,22

IRQ

1415

,19,

20,2

1,22

IRQ

1215

,19,

20,2

2

AEN

19,2

2,26

IRQ

1115

,19,

20

IRQ

915

,19,

20

IOC

HK#

15,1

9

ZER

OW

S#15

,19

MEM

R#

15,1

9,26

SA[1

9:0]

15,1

9,22

,26

SD[1

5:0]

15,1

9,22

,26 LA

[23:

17]

15,1

9

SBH

E#15

,19

RST

DR

V19

,22

BALE

15,1

9

REF

RES

H#

15,1

9

IRQ

615

,19,

20,2

2

IRQ

315

,19,

20,2

2IR

Q4

15,1

9,20

,22

IRQ

515

,19,

20,2

2

IRQ

715

,19,

20,2

2

DR

Q5

15,2

0D

ACK5

#20

DR

Q0

15,2

0,22

DAC

K0#

20,2

2

DR

Q7

15,2

0D

ACK7

#20

DR

Q6

15,2

0D

ACK6

#20

DAC

K2#

20,2

2

DR

Q3

15,2

0,22

DAC

K1#

20,2

2D

RQ

115

,20,

22

DR

Q2

15,2

0,22

SYSC

LK19

IOR

#15

,19,

22D

ACK3

#20

,22

SMEM

R#

15,1

9IO

W#

15,1

9,22

,26

SMEM

W#

15,1

9

REF

014

+12V

+12V

-12V

-12V

-5V

-5V

V5_0

-12V

+12V

-5V

C59

0.1u

FC

127

0.1u

FC

126

0.1u

FC

810

uFC

410

uFC

510

uFC

310

uF

J6 ISA

Con

n B

B1

C1

B2A2

B3

C2

B4A3

B5

C3

B6

C4

B7

A4

B8 B9

C5

B10

A5

B11

C6

B12

A6

B13

C7

B14

B15

A7

B16

C8

B17

C9

B18

A8

B19

C10

B20

A9

B21

C11

B22

B23

C12

B24

A10

B25

C13

B26

A11

B27

C14

B28

B29

A12

B30

C15

B31

C16

D1

A13

D2

C17

D3

A14

D4

A15

D5

C18

D6

A16

D7

D8

A17

D9

A18

D10

A19

D11

D12

A20

D13

A21

D14

A22

D15

D16

A23

D17

A24

D18

A1 A25

A26

A27

A28

A29

A30

A31

GN

D

SBH

E

RST

DR

VSD

7V5

_0

LA23

IRQ

9SD

6

-5V

LA22

DR

Q2

LA21

-12V

SD5

0WS

+12V

LA20

GN

D

SD4

SMEM

W

LA19

SMEM

R

SD3

IOW

LA18

IOR

DAC

K3

SD2

DR

Q3

LA17

DAC

K1

MEM

R

DR

Q1

SD1

REF

RES

H

MEM

W

CLK

SD0

IRQ

7

SD8

IRQ

6IR

Q5

SD9

IRQ

4

IOC

HR

DY

IRQ

3

SD10

DAC

K2

AEN

TC

SD11

BALE

V5_0

SA19

OSC

SD12

GN

D

SD13

MC

S16

SA18

IOC

S16

SD14

IRQ

10

SA17

IRQ

11

SA16

IRQ

12

SD15

IRQ

15

SA15

IRQ

14D

ACK0

SA14

DR

Q0

SA13

DAC

K5

SA12

DR

Q5

DAC

K6

SA11

DR

Q6

SA10

DAC

K7

SA9

DR

Q7

V5_0

SA8

MAS

TER

SA7

GN

D

IOC

HC

K

SA6

SA5

SA4

SA3

SA2

SA1

SA0

J5 ISA

Con

n A

B1

C1

B2A2

B3

C2

B4A3

B5

C3

B6

C4

B7

A4

B8 B9

C5

B10

A5

B11

C6

B12

A6

B13

C7

B14

B15

A7

B16

C8

B17

C9

B18

A8

B19

C10

B20

A9

B21

C11

B22

B23

C12

B24

A10

B25

C13

B26

A11

B27

C14

B28

B29

A12

B30

C15

B31

C16

D1

A13

D2

C17

D3

A14

D4

A15

D5

C18

D6

A16

D7

D8

A17

D9

A18

D10

A19

D11

D12

A20

D13

A21

D14

A22

D15

D16

A23

D17

A24

D18

A1 A25

A26

A27

A28

A29

A30

A31

GN

D

SBH

E

RST

DR

VSD

7V5

_0

LA23

IRQ

9SD

6

-5V

LA22

DR

Q2

LA21

-12V

SD5

0WS

+12V

LA20

GN

D

SD4

SMEM

W

LA19

SMEM

R

SD3

IOW

LA18

IOR

DAC

K3

SD2

DR

Q3

LA17

DAC

K1

MEM

R

DR

Q1

SD1

REF

RES

H

MEM

W

CLK

SD0

IRQ

7

SD8

IRQ

6IR

Q5

SD9

IRQ

4

IOC

HR

DY

IRQ

3

SD10

DAC

K2

AEN

TC

SD11

BALE

V5_0

SA19

OSC

SD12

GN

D

SD13

MC

S16

SA18

IOC

S16

SD14

IRQ

10

SA17

IRQ

11

SA16

IRQ

12

SD15

IRQ

15

SA15

IRQ

14D

ACK0

SA14

DR

Q0

SA13

DAC

K5

SA12

DR

Q5

DAC

K6

SA11

DR

Q6

SA10

DAC

K7

SA9

DR

Q7

V5_0

SA8

MAS

TER

SA7

GN

D

IOC

HC

K

SA6

SA5

SA4

SA3

SA2

SA1

SA0

C42

0.1u

FC

112

0.1u

FC

111

0.1u

FC

620.

1uF

C63

0.1u

FC

710.

1uF

C70

0.1u

FC

600.

1uF

A A

B B

C C

D D

E E

44

33

22

11

SERIAL

FLOPPY

PARALLEL

COM1

COM0





Ser

ial /

Par

alle

l / F

lopp

y

A0

Inte

l® P

entiu

m®

III -

Low

Pow

er /

440B

X AG

Pset

Ref

eren

ce D

esig

n

Int

el C

orpo

ratio

n

Em

bedd

ed In

tel A

rchi

tect

ure

Div

isio

n 5

000

W. C

hand

ler B

lvd.

Cha

ndle

r, AZ

852

26-3

699

Des

igne

d By

: Ap

plic

atio

n D

esig

n-In

Cen

ter (

Fols

om, C

A)

C

2528

Mon

day,

Aug

ust 2

7, 2

001

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

SP_R

I0

PDR

0

PDR

6

PPD

R4

PPD

R0

PPD

R3

PDR

4PD

R5

-AC

K-B

USY

SLC

TPEPD

R7

PDR

1PD

R2

PDR

3

-ALF

-ER

R-IN

IT

-STR

OBE

PPD

R5

PPD

R6

PPD

R7

-PPA

CK

-PPB

USY

PPSL

CT

PPE

PPD

R1

-PST

RO

BE

-PPE

RR

-PAL

F

-PPI

NIT

PPD

R2

-PSL

CTI

N

SP_D

SR0

SP_D

TR0

SP_R

XD0

SP_D

CD

0

SP_C

TS0

SP_T

XD0

SP_R

TS0

SP_C

TS1

SP_D

SR1

SP_T

XD1

SP_R

I1SP

_DTR

1

SP_R

XD1

SP_D

CD

1

SP_R

TS1

-RD

ATA

22-W

PT22

-IND

EX22

-SID

E122

-DSK

CH

G22

HD

EN22

-MO

TEA

22

-DIR

22

DR

ATE0

22

-DR

VSA

22

-WG

ATE

22-W

DAT

A22

-STE

P22

PDR

022

PDR

122

PDR

222

PDR

322

PDR

422

PDR

522

PDR

622

PDR

722

-INIT

22-E

RR

22-A

LF22

-STR

OBE

22

-AC

K22

PE22

-BU

SY22

SLC

T22

RXD

022

TXD

022

CTS

0#22

DTR

0#22

RI0

#22

DC

D0#

22D

SR0#

22

RTS

0#22

-SLC

TRIN

22

-TR

K022

RXD

122

RI1

#22

DTR

1#22

RTS

1#22

CTS

1#22

DSR

1#22

TXD

122

DC

D1#

22

-MO

TEB

22

-DR

VSB

22

V5_0

-12V

+12V

V5_0

V5_0

V5_0

+12V

+12V

-12V

-12V

+12V

-12V

R9

22

C10

220p

F

R25

1K

C20

220p

F

RP5

4.7K

18273645

C15

220p

F

RP6

4.7K

18273645

C25

220p

F

RP7

4.7K

18273645

C14

220p

F

RP2

33

18

27

36

45

C12

220p

F

RP4

22

18

27

36

45

C9

220p

F

J3 DB2

5

13251224112310229218207196185174163152141

2627

RP1

22

18

27

36

45

C11

220p

F

JP1

FLO

PPY

HEA

DER

17X

2

12

34

56

78

910

1112

1314

1516

1718

1920

2122

2324

2526

2728

2930

3132

3334

RP3

33

18

27

36

45

C24

220p

F

U4

GD

7523

2SO

P

120

2 3 4 5 6 7 8 9 101213141516171819 11

+12V

V5_0

RA1

RA2

RA3

DY1

DY2

RA4

DY3

RA5

-12V

RY5

DA3

RY4

DA2

DA1

RY3

RY2

RY1

GN

D

RP1

81K

1 82 73 64 5

C26

220p

F

J4 SER

IAL

STAC

K

14 18 13 17 12 16 11 15 105 9 4 8 3 7 2 6 1

14 18 13 17 12 16 11 15 105 9 4 8 3 7 2 6 1

C64

0.1u

F

U3

GD

7523

2SO

P

120

2 3 4 5 6 7 8 9 101213141516171819 11

+12V

V5_0

RA1

RA2

RA3

DY1

DY2

RA4

DY3

RA5

-12V

RY5

DA3

RY4

DA2

DA1

RY3

RY2

RY1

GN

D

C65

0.1u

F

C18

220p

F

C54

0.1u

F

C52

470p

F

C48

0.1u

F

C38

470p

F

C43

0.1u

F

C40

470p

F

C49

0.1u

F

C53

470p

F

C33

470p

FC50

470p

F

C45

470p

F

C37

470p

F

C34

470p

F

C39

470p

F C46

470p

F

C21

220p

F

C36

470p

F

C51

470p

F

C44

470p

F

C19

220p

F

C35

470p

F

C17

220p

F

C47

470p

F

C13

220p

F

R7

4.7K

C16

220p

F

A A

B B

C C

D D

E E

44

33

22

11

Expect All 0's except

SA7=1 for P80 Decode

Standard

Stuff

Option

Port 80





or28F004B5

Flas

h B

IOS

/ P

ort

80

Flash BIOS

A0

Inte

l® P

entiu

m®

III -

Low

Pow

er /

440B

X AG

Pset

Ref

eren

ce D

esig

n

Int

el C

orpo

ratio

n

Em

bedd

ed In

tel A

rchi

tect

ure

Div

isio

n 5

000

W. C

hand

ler B

lvd.

Cha

ndle

r, AZ

852

26-3

699

Des

igne

d By

: Ap

plic

atio

n D

esig

n-In

Cen

ter (

Fols

om, C

A)

C

2628

Mon

day,

Aug

ust 2

7, 2

001

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

SD[1

5:0]

SA[1

9:0]

SD4

SD5

SD6

SD7

SD0

SD1

SD2

SD3

SA4

SA1

SA9

SA0

SA5

SA3

SA2

SA6

SA7

SA8

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

XD0

XD1

XD2

XD3

XD4

XD5

XD6

XD7

SA17

SA18

SD[1

5:0]

15,1

9,22

,24

IOW

#15

,19,

22,2

4

AEN

19,2

2,24

SA[1

9:0]

15,1

9,22

,24

XD[7

:0]

19

MEM

W#

15,1

9,24

MEM

R#

15,1

9,24

BIO

SCS#

20

PWR

OK5

27

V5_0

V5_0

V5_0

V5_0

V5_0

V5_0

+12V

+12V

V5_0

R10

510

K

R98

0

TP8

1 TP

TP14

1TP

TP2

1 TP

TP7

1 TP

TP6

1 TP

TP16

1TP

TP10

1TPTP

91 TP

TP12

1TP

C14

510

uF

U10 QST

3384

3 4 7 8 14 17 18 2111 22

2 5 6 9 10 15 16 19 20 23

12

24

1 13

1A1

1A2

1A3

1A4

2A1

2A2

2A3

2A4

1A5

2A5

1B1

1B2

1B3

1B4

1B5

2B1

2B2

2B3

2B4

2B5

GN

D

V5_0

BEA

BEB

U13

TIL3

11 S

OC

KET

14 1 78

53 2 13 12

10 4

V5_0

V5_0

GN

DG

ND

LATC

H

A B C D

RTD

ECLF

TDEC

U12

TIL3

11 S

OC

KET

14 1 78

53 2 13 12

10 4

V5_0

V5_0

GN

DG

ND

LATC

H

A B C D

RTD

ECLF

TDEC

U9

22V1

0

1 817 15 22

218

319

420

521

623

724

925

1026

1127

12 13 16N

CN

CO1

NC

NC

I1/C

LKO

2I2

O3

I3O

4I4

O5

I5O

6I6

O7

I7O

8I8

O9

I9O

10I1

0I1

1I1

2

U11

28F0

02BC

1231 139

3730 3825 39

24

23

21 22

26

1020

2719

2818

3217

3316

3415

3514 8 7 36 6 5 4 3 2 1 40

11

NC

VCC

NC

WE#

NC

VCC

NC

DQ

0

GN

D

OE#

GN

D

A0 CE#

DQ

1

RP#

A1

DQ

2A2

DQ

3A3

DQ

4A4

DQ

5A5

DQ

6A6

DQ

7A7 A8 A9 A1

0A1

1A1

2A1

3A1

4A1

5A1

6A1

7

VPP

J22

HD

R3

1

2

3

J21

1x3

1

2

3

C19

60.

1uF

C20

00.

1uF

C20

60.

1uF

C20

50.

1uF

C20

80.

1uF

C13

10.

1uF

C13

00.

1uF

A A

B B

C C

D D

E E

44

33

22

11





AT

X P

ower

Con

nect

or

Place at ATX Connector



Note Cap Direction


Note: Add screen marking for V5_0 LED, V3_3 LED

Open Collector

PS_OK = OR of PW_OK,-DBRESET,RESET SWITCH


Power Indicators

Note

Cap

Dir

ection

A0

Inte

l® P

entiu

m®

III -

Low

Pow

er /

440B

X AG

Pset

Ref

eren

ce D

esig

n

Int

el C

orpo

ratio

n

Em

bedd

ed In

tel A

rchi

tect

ure

Div

isio

n 5

000

W. C

hand

ler B

lvd.

Cha

ndle

r, AZ

852

26-3

699

Des

igne

d By

: Ap

plic

atio

n D

esig

n-In

Cen

ter (

Fols

om, C

A)

C

2728

Mon

day,

Aug

ust 2

7, 2

001

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

PS_O

K

PWR

ON

#20

PWR

BTN

#20

RSM

RST

#20

CPU

PWR

OK

9PW

RO

K6,

20

DBR

ESET

8

PWR

OK5

26

H_P

WR

OK

4V3

.3SU

S

V5_0

V3_3

V5_0

V5_0

V3.3

SUS

-5V

-12V

V3.3

SUS

+12V

V3_3

V3.3

SUS

V3.3

SUS

V5_0

V5_0

V5_0

V5_0

C14

20.

1uF

C61

0.1u

F

J20

JUM

P3

1

2

3

C41

470p

F

C15

247

uF

C76

0.1u

F

C15

447

uF

C97

0.1u

F

R10

220

U25

D

74AC

T05

98

14 7

C10

20.

1uF

R53

10K

C96

0.1u

F

R8

124

C27

470p

F

R12

84.

7K

C14

10.

01uF

R57

2.7K

C72

100u

F

R56

10K

C84

100u

F

U25

C

74AC

T05

56

14 7

C13

810

uF

U24

A

74LC

T14

12

14 7

C11

022

0uF

R12

710

K

C83

220u

F

J12

AMP1

7398

1-3

1 2 3

1 2 3

C98

220u

F

TP1

1TP

C10

910

0uF

U23 LT

117-

3.3

123

4

Adj/G

ND

Out

InO

utTa

b

C89

100u

F

C58

100u

F

C69

220u

F

S2

RES

ET S

WIT

CH

C88

100u

F

C15

310

uF

U22

B

74AL

S00

4 56

U24

D

74LC

T14

98

14 7

J11

ATX

PO

W C

ON

N

8 9 10

12 14 18 19 20

3 5 7

13 15 16 17

4 61 211

PW_O

K5V

SB+1

2V

-12V

PS_O

N

-5V

V5_0

V5_0

GN

D

GN

D

GN

D

GN

D

GN

DG

ND

GN

D

V5_0

V5_0

V3_3

V3_3

V3_3

U24

C

74LC

T14

56

14 7

D2

LGS2

60-D

O

2

13

IN

NCOUT

TP18

1TP

D1

LGS2

60-D

O

2

13

IN

NCOUT

S1

POW

ER S

WIT

CH

U25

B

74AC

T05

34

14 7

U24

B

74LC

T14

34

14 7

U21

C

74H

CT1

4

56

A A

B B

C C

D D

E E

44

33

22

11

Make these connections

Cutable


Cutable


Cutable


Cutable


CutableMake these connections

Cutable





Unu

sed

Dev

ices

A0

Inte

l® P

entiu

m®

III -

Low

Pow

er /

440B

X AG

Pset

Ref

eren

ce D

esig

n

Int

el C

orpo

ratio

n

Em

bedd

ed In

tel A

rchi

tect

ure

Div

isio

n 5

000

W. C

hand

ler B

lvd.

Cha

ndle

r, AZ

852

26-3

699

Des

igne

d By

: Ap

plic

atio

n D

esig

n-In

Cen

ter (

Fols

om, C

A)

C

2828

Mon

day,

Aug

ust 2

7, 2

001

Title

Size

Doc

umen

t Num

ber

Rev

Dat

e:Sh

eet

of

V5_0

V5_0

V3.3

SUS

V5_0

V5_0

V3.3

SUS

U15

C74

LVC

125

98

14

10

7 U15

D74

LVC

125

1211

14

13

7

U22

C

74AL

S00

9 108

14 7 U22

D

74AL

S00

12 1311

14 7

U25

E

74AC

T05

1110

14 7 U25

F

74AC

T05

1312

14 7

U24

F

74LC

T14

1312

14 7

U21

D

74H

CT1

4

98

14 7 U21

E

74H

CT1

4

1110

14 7 U21

F

74H

CT1

4

1312

14 7

U2C

74AS

07

56

14 7 U2D

74AS

07

98

14 7 U2E

74AS

07

1110

14 7 U2F

74AS

07

1312

14 7

U15

B74

LVC

125

56

14

4

7


Design Guide 155

Appendix C PLD Code Listing

The code listing below is for the 22V10 PLD.

TITLE 22V10 PORT 80 ADDRESS DECODER / FLASH DECODE

PATTERN 1

REVISION B

AUTHOR CHRIS BANYAI

COMPANY INTEL CORPORATION

DATE 10/1/97

OPTIONS

SECURITY = OFF

; ( part was 22V10FN before conversion )

CHIP P80B iPLD22V10N

PIN 19 IOWR_BAR

PIN 3 AEN

PIN [6:7] SA[0:1]

PIN [9:13] SA[2:6]

PIN 16 SA7

PIN [5:4] SA[8:9]

PIN [26:23] SA[19:16]

PIN [21:20] SA[15:14]

PIN 2 SEL

PIN 18 /CS_BAR

PIN 17 /CS_DOC

PIN 27 OX

EQUATIONS

CS_BAR = /IOWR_BAR * /AEN * /SA0 * /SA1 * /SA2 * /SA3 * /SA4 * /SA5 * /SA6

* SA7 * /SA8 * /SA9

CS_BAR.TRST = VCC

CS_DOC = /SEL * /AEN * SA19 * SA18 * /SA17 * /SA16 * SA15 * /SA14

+ SEL * /AEN * SA19 * SA18 * /SA17 * SA16 * /SA15 * /SA14

CS_DOC.TRST = VCC

OX = /IOWR_BAR

OX.TRST = VCC

SIMULATION

SETF /AEN /SA0 /SA1 /SA2 /SA3 /SA4 /SA5 /SA6 /SA7 /SA8 /SA9 IOWR_BAR

SETF SA7 IOWR_BAR

SETF /IOWR_BAR

SETF IOWR_BAR

SETF AEN /IOWR_BAR

SETF /AEN


156 Design Guide

SETF IOWR_BAR

SETF SA0 /IOWR_BAR

SETF /SA0 /IOWR_BAR

SETF IOWR_BAR

SETF /SA0 /SA1 /SA2 /SA3 /SA4 /SA5 /SA6 /SA7 /SA8 /SA9

SETF /SA19 /SA18 /SA17 /SA16 /SA15 /SA14

SETF /SEL

SETF SA19 SA18 /SA17 /SA16 SA15 /SA14

SETF /SEL

SETF /AEN

SETF /SA19

SETF SA19

SETF /SA18

SETF SA18

SETF SA17

SETF /SA17

SETF SA16

SETF /SA16

SETF /SA15

SETF SA15

SETF SA14

SETF /SA14

SETF /SEL

SETF SA19 SA18 /SA17 SA16 /SA15 /SA14

SETF /SEL

SETF /AEN

SETF SEL

SETF /SA19

SETF SA19

SETF /SA18

SETF SA18

SETF SA17

SETF /SA17

SETF /SA16

SETF SA16

SETF SA15

SETF /SA15

SETF SA14

SETF /SA14

SETF /SEL

Intel Pentium III Processor Low Power/440BX AGPsetapplication-notes.digchip.com/027/27-46183.pdf ·...

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Transcript of Intel Pentium III Processor Low Power/440BX AGPsetapplication-notes.digchip.com/027/27-46183.pdf ·...