Intel Pentium Dual-Core Mobile Processor 7 Introduction 1 Introduction The Intel® Pentium®...

Intel® Pentium® Dual-Core Mobile ProcessorDatasheet

July 2007

Revision 003

2 Datasheet

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Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Intel® Virtualization Technology requires a computer system with a processor, chipset, BIOS, virtual machine monitor (VMM) and applications enabled for VT. Functionality, performance or other VT benefit will vary depending on hardware and software configurations. VT-enabled BIOS and VMM applications are currently in development.

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Copyright © 2007, Intel Corporation. All rights reserved.

Datasheet 3

Contents

1 Introduction ..............................................................................................................71.1 Terminology .......................................................................................................71.2 References .........................................................................................................8

2 Low Power Features ..................................................................................................92.1 Clock Control and Low Power States ......................................................................9

2.1.1 Core Low-Power States ........................................................................... 112.1.2 Package Low Power States ...................................................................... 12

2.2 Enhanced Intel SpeedStep® Technology .............................................................. 132.3 FSB Low Power Enhancements ............................................................................ 142.4 Processor Power Status Indicator (PSI#) Signal..................................................... 15

3 Electrical Specifications ........................................................................................... 173.1 Power and Ground Pins ...................................................................................... 173.2 FSB Clock (BCLK[1:0]) and Processor Clocking...................................................... 173.3 Voltage Identification......................................................................................... 173.4 Catastrophic Thermal Protection .......................................................................... 203.5 Signal Terminations and Unused Pins ................................................................... 213.6 FSB Frequency Select Signals (BSEL[2:0])............................................................ 213.7 FSB Signal Groups............................................................................................. 213.8 CMOS Signals ................................................................................................... 233.9 Maximum Ratings.............................................................................................. 233.10 Processor DC Specifications ................................................................................ 24

4 Package Mechanical Specifications and Pin Information .......................................... 294.1 Package Mechanical Specifications ....................................................................... 294.2 Processor Pinout and Pin List .............................................................................. 324.3 Alphabetical Signals Reference ............................................................................ 55

5 Thermal Specifications and Design Considerations .................................................. 635.1 Monitoring Processor Temperature....................................................................... 64

5.1.1 Thermal Diode ....................................................................................... 645.1.2 Thermal Diode Offset .............................................................................. 665.1.3 Intel® Thermal Monitor........................................................................... 675.1.4 Digital Thermal Sensor............................................................................ 685.1.5 Out of Specification Detection .................................................................. 69

Figures1 Package-Level Low Power States................................................................................ 102 Core Low Power States ............................................................................................. 103 Active VCC and ICC Loadline for the Processor ............................................................. 264 Micro-FCPGA Processor Package Drawing Sheet 1 of 2 .................................................. 305 Micro-FCPGA Processor Package Drawing Sheet 2 of 2 .................................................. 31

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Tables1 References ............................................................................................................... 82 Coordination of Core-Level Low Power States at the Package Level .................................. 93 Voltage Identification Definition..................................................................................174 BSEL[2:0] Encoding for BCLK Frequency......................................................................215 FSB Pin Groups ........................................................................................................226 Processor DC Absolute Maximum Ratings.....................................................................237 Voltage and Current Specifications for Standard Voltage Processor..................................248 FSB Differential BCLK Specifications ............................................................................279 AGTL+ Signal Group DC Specifications ........................................................................2710 CMOS Signal Group DC Specifications..........................................................................2811 Open Drain Signal Group DC Specifications ..................................................................2812 Processor Pin Coordinates from Top of the Package (Sheet 1 of 2) ..................................3213 Processor Pin Coordinates from Top of the Package (Sheet 2 of 2) ..................................3314 Pin Listing by Pin Name .............................................................................................3515 Pin Listing by Pin Number ..........................................................................................4616 Signal Description.....................................................................................................5517 Power Specifications .................................................................................................6318 Thermal Diode Interface............................................................................................6419 Thermal Diode Parameters using Diode Mode ...............................................................6520 Thermal Diode Parameters using Transistor Mode .........................................................6521 Thermal Diode ntrim and Diode Correction Toffset..........................................................66

Datasheet 5

Revision History

§

Document Number Revision Description Date

316519 001 Initial release February 2007

316519 002 Added T2080 SKU March 2007

316519 003 Added T2130 SKU July 2007

6 Datasheet

Datasheet 7

Introduction

1 Introduction

The Intel® Pentium® dual-core mobile processor is built on Intel’s 65-nanometer process technology. This document provides specifications for the Pentium dual-core mobile processor.

Note: All instances of “processor” in this document refer to the Pentium dual-core mobile processor with 1-MB L2 cache and 533-MHz Front Side Bus (FSB), unless specified otherwise.

The following list provides some of the key features on this processor:

• Dual-core processor

• Supports Intel® Architecture with Dynamic Execution

• On-die, primary 32-KB instruction cache and 32-KB write-back data cache

• On-die, 1-MB second level cache with Advanced Transfer Cache Architecture

• Data prefetch logic

• Streaming SIMD Extensions 2 (SSE2) and Streaming SIMD Extensions 3 (SSE3)

• 533-MHz FSB

• Enhanced Intel SpeedStep® Technology

• Digital Thermal Sensor

• Processor is offered in only Micro-FCPGA packages

• Execute Disable Bit support for enhanced security

1.1 Terminology

Term Definition

#

A “#” symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the “#” symbol implies that the signal is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’, and D[3:0]# = “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level). XXXX means that the specification or value is yet to be determined.

Front Side Bus (FSB)

Refers to the interface between the processor and system core logic (also known as the chipset components).

AGTL+ Advanced Gunning Transceiver Logic. Used to refer to Assisted GTL+ signaling technology on some Intel processors.

Introduction

8 Datasheet

1.2 References

Material and concepts available in the following documents may be beneficial when reading this document.

§

Table 1. References

DocumentDocument Number

Intel® Pentium® Dual-Core Processor on 65-nm Technology Specification Update

316515

Mobile Intel® 945 Express Chipset Family Datasheet 309219

Mobile Intel® 945 Express Chipset Family Specification Update 309220

Intel® I/O Controller Hub 7 (ICH7) Family Datasheet 307013

Intel® I/O Controller Hub 7 (ICH7) Family Specification Update 307014

Intel® 64 and IA-32 Architectures Software Developer's Manuals

http://www.intel.com/

products/processor/manuals/index.htm

Volume 1 Basic Architecture 253665

Volume 2A: Instruction Set Reference (A-M) 253666

Volume 2B: Instruction Set Reference (N-Z) 253667

Volume 3A: System Programming Guide 253668

Volume 3B: System Programming Guide 253669

AP-485, Intel® Processor Identification and CPUID Instruction Application Note

241618

Datasheet 9

Low Power Features

2 Low Power Features

2.1 Clock Control and Low Power States

The processor supports low power states at the core level and the package level. A core may independently enter the C1/AutoHALT, C1/MWAIT, C2 and C3 low power states. Package low power states include Normal, Stop Grant, Stop Grant Snoop, Sleep and Deep Sleep. When both cores are in a common core, low-power state the central power management logic ensures the entire processor enters the respective package low power state by initiating a P_LVLx (P_LVL2 and P_LVL3) I/O read to the chipset.

The processor implements two software interfaces for requesting low power states, MWAIT instruction extensions with sub-state hints and P_LVLx reads to the ACPI P_BLK register block mapped in the processor’s I/O address space. The P_LVLx I/O reads are converted to equivalent MWAIT C-state requests inside the processor and do not directly result in I/O reads on the processor FSB. The monitor address does not need to be setup before using the P_LVLx I/O read interface. The sub-state hints used for each P_LVLx read can be configured in a software programmable MSR. If a core encounters a chipset break event while STPCLK# is asserted, then it asserts the PBE# output signal. Assertion of PBE# when STPCLK# is asserted indicates to system logic that individual cores should return to the C0 state and the processor should return to the Normal state.

Figure 1 shows the package low-power states Figure 2 shows the core low-power states. Table 2 provides a mapping of core, low-power states to package low power states.

NOTES:1. AutoHALT or MWAIT/C1.

Table 2. Coordination of Core-Level Low Power States at the Package Level

Resolved Package State

SingleCore:

Dual Core: Core1 State

C0 C11 C2 C3

Co

re0

/ F

un

ctio

nal

Co

re S

tate

C0 Normal Normal Normal Normal Normal

C11 Normal Normal Normal Normal Normal

C2 Stop Grant Normal Normal Stop Grant Stop Grant

C3 Deep Sleep Normal Normal Stop Grant Deep Sleep

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10 Datasheet

Figure 1. Package-Level Low Power States

Figure 2. Core Low Power States

Stop GrantSnoop

Normal StopGrant

STPCLK# asserted

Snoopserviced

Snoopoccurs

Sleep

SLP# asserted

SLP# de-assertedSTPCLK# de-asserted

Deep Sleep

DPSLP# asserted

DPSLP# de-asserted

C2†

C0

StopGrant

Core statebreak

P_LVL2 orMWAIT(C2)

C3†

Corestatebreak

P_LVL3 orMWAIT(C3)

C1/MWAIT

Core statebreak

MWAIT(C1)

C1/Auto Halt

Halt break

HLT instruction

STPCLK#de-asserted

STPCLK#asserted

STPCLK#de-asserted

STPCLK#asserted

STPCLK#de-asserted

STPCLK#asserted

halt break = A20M# transition, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interruptcore state break = (halt break OR Monitor event) AND STPCLK# high (not asserted)† — STPCLK# assertion and de-assertion have no effect if a core is in C2 or C3.

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Low Power Features

2.1.1 Core Low-Power States

2.1.1.1 C0 State

This is the normal operating state for both cores of the processor.

2.1.1.2 C1/AutoHALT Powerdown State

C1/AutoHALT is a low power state entered when the processor core executes the HALT instruction. The processor core will transition to the C0 state upon the occurrence of SMI#, INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt message. RESET# will cause the processor to immediately initialize itself.

A System Management Interrupt (SMI) handler will return execution to either Normal state or the AutoHALT Powerdown state. See the Intel® Architecture Software Developer's Manual, Volume 3A/3B: System Programming Guide for more information.

The system can generate a STPCLK# while the processor is in the AutoHALT Powerdown state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state.

While in AutoHALT Powerdown state, the Intel Pentium Dual-Core processor will process bus snoops and snoops from the other core.The processor core will enter a snoopable sub-state (not shown in Figure 2) to process the snoop and then return to the AutoHALT Powerdown state.

2.1.1.3 C1/MWAIT Powerdown State

MWAIT is a low power state entered when the processor core executes the MWAIT instruction. Processor behavior in the MWAIT state is identical to the AutoHALT state except that there is an additional event that can cause the processor core to return to the C0 state: the Monitor event. See the Intel® Architecture Software Developer's Manual, Volume 2A/2B: Instruction Set Reference for more information.

2.1.1.4 Core C2 State

Individual cores of the processor can enter the C2 state by initiating a P_LVL2 I/O read to the P_BLK or an MWAIT(C2) instruction, but the processor will not issue a Stop Grant Acknowledge special bus cycle unless the STPCLK# pin is also asserted.

While in C2 state, the processor will process bus snoops and snoops from the other core. The processor core will enter a snoopable sub-state (not shown in Figure 2) to process the snoop and then return to the C2 state.

2.1.1.5 Core C3 State

Core C3 state is a very low power state the processor core can enter while maintaining context. Individual cores of the Intel Pentium Dual-Core processor can enter the C3 state by initiating a P_LVL3 I/O read to the P_BLK or an MWAIT(C3) instruction. Before entering the C3 state, the processor core flushes the contents of its L1 caches into the processor’s L2 cache. Except for the caches, the processor core maintains all its architectural state in the C3 state. The Monitor remains armed if it is configured. All of the clocks in the processor core are stopped in the C3 state.

Because the core’s caches are flushed the processor keeps the core in the C3 state when the processor detects a snoop on the FSB or when the other core of the processor accesses cacheable memory. The processor core will transition to the C0 state upon the occurrence of a Monitor event, SMI#, INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt message. RESET# will cause the processor core to immediately initialize itself.

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12 Datasheet

2.1.2 Package Low Power States

All package level low power states are described as follows:

2.1.2.1 Normal State

This is the normal operating state for the processor. The processor enters the Normal state when at least one of its cores is in the C0, C1/AutoHALT, or C1/MWAIT state.

2.1.2.2 Stop-Grant State

When the STPCLK# pin is asserted each core of the Intel Pentium Dual-Core processor enters the Stop-Grant state within 20 bus clocks after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle. Processor cores that are already in the C2, or C3 state remain in their current low-power state. When the STPCLK# pin is deasserted, each core returns to its previous core low power state.

Since the AGTL+ signal pins receive power from the FSB, these pins should not be driven (allowing the level to return to VCCP) for minimum power drawn by the termination resistors in this state. In addition, all other input pins on the FSB should be driven to the inactive state.

RESET# will cause the processor to immediately initialize itself, but the processor will stay in Stop-Grant state. When RESET# is asserted by the system the STPCLK#, SLP#, and DPSLP# pins must be deasserted more than 450 µs prior to RESET# deassertion. When re-entering the Stop-Grant state from the Sleep state, STPCLK# should be deasserted ten or more bus clocks after the deassertion of SLP#.

While in Stop-Grant state, the processor will service snoops and latch interrupts delivered on the FSB. The processor will latch SMI#, INIT# and LINT[1:0] interrupts and will service only one of each upon return to the Normal state.

The PBE# signal may be driven when the processor is in Stop-Grant state. PBE# will be asserted if there is any pending interrupt or monitor event latched within the processor. Pending interrupts that are blocked by the EFLAGS.IF bit being clear will still cause assertion of PBE#. Assertion of PBE# indicates to system logic that the entire Intel Pentium Dual-Core processor should return to the Normal state.

A transition to the Stop Grant Snoop state will occur when the processor detects a snoop on the FSB (see Section 2.1.2.3). A transition to the Sleep state (see Section 2.1.2.4) will occur with the assertion of the SLP# signal.

2.1.2.3 Stop Grant Snoop State

The processor will respond to snoop or interrupt transactions on the FSB while in Stop-Grant state by entering the Stop-Grant Snoop state. The processor will stay in this state until the snoop on the FSB has been serviced (whether by the processor or another agent on the FSB) or the interrupt has been latched. The processor will return to the Stop-Grant state once the snoop has been serviced or the interrupt has been latched.

2.1.2.4 Sleep State

The Sleep state is a low power state in which the processor maintains its context, maintains the phase-locked loop (PLL), and stops all internal clocks. The Sleep state is entered through assertion of the SLP# signal while in the Stop-Grant state. The SLP# pin should only be asserted when the processor is in the Stop-Grant state. SLP# assertions while the processor is not in the Stop-Grant state is out of specification and may result in unapproved operation.

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Low Power Features

In the Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions or assertions of signals (with the exception of SLP#, DPSLP# or RESET#) are allowed on the FSB while the processor is in Sleep state. Snoop events that occur while in Sleep state or during a transition into or out of Sleep state will cause unpredictable behavior. Any transition on an input signal before the processor has returned to the Stop-Grant state will result in unpredictable behavior.

If RESET# is driven active while the processor is in the Sleep state, and held active as specified in the RESET# pin specification, then the processor will reset itself, ignoring the transition through Stop-Grant State. If RESET# is driven active while the processor is in the Sleep State, the SLP# and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the processor correctly executes the Reset sequence.

While in the Sleep state, the processor is capable of entering an even lower power state, the Deep Sleep state, by asserting the DPSLP# pin. (See Section 2.1.2.5.) While the processor is in the Sleep state, the SLP# pin must be deasserted if another asynchronous FSB event needs to occur.

2.1.2.5 Deep Sleep State

Deep Sleep state is a very low power state the processor can enter while maintaining context. Deep Sleep state is entered by asserting the DPSLP# pin while in the Sleep state. BCLK may be stopped during the Deep Sleep state for additional platform level power savings. BCLK stop/restart timings on appropriate chipset based platforms with the CK410M clock chip are as follows:

• Deep Sleep entry: the system clock chip may stop/tristate BCLK within 2 BCLKs of DPSLP# assertion. It is permissible to leave BCLK running during Deep Sleep.

• Deep Sleep exit: the system clock chip must drive BCLK to differential DC levels within 2-3 ns of DPSLP# deassertion and start toggling BCLK within 10 BCLK periods.

To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be re-started after DPSLP# deassertion as described above. A period of 15 microseconds (to allow for PLL stabilization) must occur before the processor can be considered to be in the Sleep state. Once in the Sleep state, the SLP# pin must be deasserted to re-enter the Stop-Grant state.

While in Deep Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions of signals are allowed on the FSB while the processor is in Deep Sleep state. When the processor is in Deep Sleep state, it will not respond to interrupts or snoop transactions. Any transition on an input signal before the processor has returned to Stop-Grant state will result in unpredictable behavior.

2.2 Enhanced Intel SpeedStep® Technology

The Intel Pentium Dual-Core processors feature Enhanced Intel SpeedStep Technology. Following are the key features of Enhanced Intel SpeedStep technology:

• Multiple voltage/frequency operating points provide optimal performance at the lowest power.

• Voltage/Frequency selection is software controlled by writing to processor MSR’s (Model Specific Registers).

— If the target frequency is higher than the current frequency, VCC is ramped up in steps by placing new values on the VID pins and the PLL then locks to the new frequency.

Low Power Features

14 Datasheet

— If the target frequency is lower than the current frequency, the PLL locks to the new frequency and the VCC is changed through the VID pin mechanism.

— Software transitions are accepted at any time. If a previous transition is in progress, the new transition is deferred until the previous transition completes.

• The processor controls voltage ramp rates internally to ensure glitch free transitions.

• Low transition latency and large number of transitions possible per second.

— Processor core (including L2 cache) is unavailable for up to 10 µs during the frequency transition.

— The bus protocol (BNR# mechanism) is used to block snooping.

• Improved Intel® Thermal Monitor mode.

— When the on-die thermal sensor indicates that the die temperature is too high, the processor can automatically perform a transition to a lower frequency/voltage specified in a software programmable MSR.

— The processor waits for a fixed time period. If the die temperature is down to acceptable levels, an up transition to the previous frequency/voltage point occurs.

— An interrupt is generated for the up and down Intel Thermal Monitor transitions enabling better system level thermal management.

• Enhanced thermal management features.

— Digital thermal sensor and thermal interrupts with Out of Specification detection and interrupt generation.

— TM1 in addition to TM2 in case of non successful TM2 transition.

— Dual-core thermal management synchronization.

Each core in the processor implements an independent MSR for controlling Enhanced Intel SpeedStep Technology, but both cores must operate at the same frequency and voltage. The processor has performance state coordination logic to resolve frequency and voltage requests from the two cores into a single frequency and voltage request for the package as a whole. If both cores request the same frequency and voltage then the processor will transition to the requested common frequency and voltage. If the two cores have different frequency and voltage requests then the processor will take the highest of the two frequencies and voltages as the resolved request and transition to that frequency and voltage.

2.3 FSB Low Power Enhancements

The Intel Pentium Dual-Core processors incorporate FSB low power enhancements:

• Dynamic FSB Power Down

• BPRI# control for address and control input buffers

• Dynamic Bus Parking

• Dynamic On Die Termination disabling

• Low VCCP (I/O termination voltage)

The processor incorporates the DPWR# signal that controls the data bus input buffers on the processor. The DPWR# signal disables the buffers when not used and activates them only when data bus activity occurs, resulting in significant power savings with no performance impact. BPRI# control also allows the processor address and control input buffers to be turned off when the BPRI# signal is inactive. Dynamic Bus Parking allows a reciprocal power reduction in chipset address and control input buffers when the

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Low Power Features

processor deasserts its BR0# pin. The On Die Termination on the processor FSB buffers is disabled when the signals are driven low, resulting in additional power savings. The low I/O termination voltage is on a dedicated voltage plane independent of the core voltage, enabling low I/O switching power at all times.

2.4 Processor Power Status Indicator (PSI#) Signal

The processor incorporates the PSI# signal that is asserted when the processor is in a reduced power consumption state. PSI# can be used to improve intermediate and light load efficiency of the voltage regulator, resulting in platform power savings and extended battery life. The algorithm that the processor uses for determining when to assert PSI# is different from the algorithm used in previous Intel® Pentium® M processors.

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Low Power Features

16 Datasheet

Datasheet 17

Electrical Specifications

3 Electrical Specifications

3.1 Power and Ground Pins

For clean, on-chip power distribution, the processor will have a large number of VCC (power) and VSS(ground) inputs. All power pins must be connected to VCC power planes while all VSS pins must be connected to system ground planes. Use of multiple power and ground planes is recommended to reduce I*R drop. Please contact your Intel representative for more details. The processor VCC pins must be supplied the voltage determined by the VID (Voltage ID) pins.

3.2 FSB Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous generation processors, the processor’s core frequency is a multiple of the BCLK[1:0] frequency. The processor uses a differential clocking implementation.

3.3 Voltage Identification

The processor uses seven voltage identification pins, VID[6:0], to support automatic selection of power supply voltages. The VID pins for the processor are CMOS outputs driven by the processor VID circuitry. Table 3 specifies the voltage level corresponding to the state of VID[6:0]. A 1 in this refers to a high-voltage level and a 0 refers to low-voltage level.

Table 3. Voltage Identification Definition (Sheet 1 of 4)

VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V)

0 0 0 0 0 0 0 1.5000

0 0 0 0 0 0 1 1.4875

0 0 0 0 0 1 0 1.4750

0 0 0 0 0 1 1 1.4625

0 0 0 0 1 0 0 1.4500

0 0 0 0 1 0 1 1.4375

0 0 0 0 1 1 0 1.4250

0 0 0 0 1 1 1 1.4125

0 0 0 1 0 0 0 1.4000

0 0 0 1 0 0 1 1.3875

0 0 0 1 0 1 0 1.3750

0 0 0 1 0 1 1 1.3625

0 0 0 1 1 0 0 1.3500

0 0 0 1 1 0 1 1.3375

0 0 0 1 1 1 0 1.3250

0 0 0 1 1 1 1 1.3125


18 Datasheet

0 0 1 0 0 0 0 1.3000

0 0 1 0 0 0 1 1.2875

0 0 1 0 0 1 0 1.2750

0 0 1 0 0 1 1 1.2625

0 0 1 0 1 0 0 1.2500

0 0 1 0 1 0 1 1.2375

0 0 1 0 1 1 0 1.2250

0 0 1 0 1 1 1 1.2125

0 0 1 1 0 0 0 1.2000

0 0 1 1 0 0 1 1.1875

0 0 1 1 0 1 0 1.1750

0 0 1 1 0 1 1 1.1625

0 0 1 1 1 0 0 1.1500

0 0 1 1 1 0 1 1.1375

0 0 1 1 1 1 0 1.1250

0 0 1 1 1 1 1 1.1125

0 1 0 0 0 0 0 1.1000

0 1 0 0 0 0 1 1.0875

0 1 0 0 0 1 0 1.0750

0 1 0 0 0 1 1 1.0625

0 1 0 0 1 0 0 1.0500

0 1 0 0 1 0 1 1.0375

0 1 0 0 1 1 0 1.0250

0 1 0 0 1 1 1 1.0125

0 1 0 1 0 0 0 1.0000

0 1 0 1 0 0 1 0.9875

0 1 0 1 0 1 0 0.9750

0 1 0 1 0 1 1 0.9625

0 1 0 1 1 0 0 0.9500

0 1 0 1 1 0 1 0.9375

0 1 0 1 1 1 0 0.9250

0 1 0 1 1 1 1 0.9125

0 1 1 0 0 0 0 0.9000

0 1 1 0 0 0 1 0.8875

0 1 1 0 0 1 0 0.8750

0 1 1 0 0 1 1 0.8625

0 1 1 0 1 0 0 0.8500

0 1 1 0 1 0 1 0.8375



Datasheet 19


0 1 1 0 1 1 0 0.8250

0 1 1 0 1 1 1 0.8125

0 1 1 1 0 0 0 0.8000

0 1 1 1 0 0 1 0.7875

0 1 1 1 0 1 0 0.7750

0 1 1 1 0 1 1 0.7625

0 1 1 1 1 0 0 0.7500

0 1 1 1 1 0 1 0.7375

0 1 1 1 1 1 0 0.7250

0 1 1 1 1 1 1 0.7125

1 0 0 0 0 0 0 0.7000

1 0 0 0 0 0 1 0.6875

1 0 0 0 0 1 0 0.6750

1 0 0 0 0 1 1 0.6625

1 0 0 0 1 0 0 0.6500

1 0 0 0 1 0 1 0.6375

1 0 0 0 1 1 0 0.6250

1 0 0 0 1 1 1 0.6125

1 0 0 1 0 0 0 0.6000

1 0 0 1 0 0 1 0.5875

1 0 0 1 0 1 0 0.5750

1 0 0 1 0 1 1 0.5625

1 0 0 1 1 0 0 0.5500

1 0 0 1 1 0 1 0.5375

1 0 0 1 1 1 0 0.5250

1 0 0 1 1 1 1 0.5125

1 0 1 0 0 0 0 0.5000

1 0 1 0 0 0 1 0.4875

1 0 1 0 0 1 0 0.4750

1 0 1 0 0 1 1 0.4625

1 0 1 0 1 0 0 0.4500

1 0 1 0 1 0 1 0.4375

1 0 1 0 1 1 0 0.4250

1 0 1 0 1 1 1 0.4125

1 0 1 1 0 0 0 0.4000

1 0 1 1 0 0 1 0.3875

1 0 1 1 0 1 0 0.3750

1 0 1 1 0 1 1 0.3625




20 Datasheet

3.4 Catastrophic Thermal Protection

The processor supports the THERMTRIP# signal for catastrophic thermal protection. An external thermal sensor should also be used to protect the processor and the system against excessive temperatures. Even with the activation of THERMTRIP#, which halts all processor internal clocks and activity, leakage current can be high enough such that the processor cannot be protected in all conditions without the removal of power to the processor. If the external thermal sensor detects a catastrophic processor temperature of 125°C (maximum), or if the THERMTRIP# signal is asserted, the VCC supply to the processor must be turned off within 500 ms to prevent permanent silicon damage due to thermal runaway of the processor.

1 0 1 1 1 0 0 0.3500

1 0 1 1 1 0 1 0.3375

1 0 1 1 1 1 0 0.3250

1 0 1 1 1 1 1 0.3125

1 1 0 0 0 0 0 0.3000

1 1 0 0 0 0 1 0.2875

1 1 0 0 0 1 0 0.2750

1 1 0 0 0 1 1 0.2625

1 1 0 0 1 0 0 0.2500

1 1 0 0 1 0 1 0.2375

1 1 0 0 1 1 0 0.2250

1 1 0 0 1 1 1 0.2125

1 1 0 1 0 0 0 0.2000

1 1 0 1 0 0 1 0.1875

1 1 0 1 0 1 0 0.1750

1 1 0 1 0 1 1 0.1625

1 1 0 1 1 0 0 0.1500

1 1 0 1 1 0 1 0.1375

1 1 0 1 1 1 0 0.1250

1 1 0 1 1 1 1 0.1125

1 1 1 0 0 0 0 0.1000

1 1 1 0 0 0 1 0.0875

1 1 1 0 0 1 0 0.0750

1 1 1 0 0 1 1 0.0625

1 1 1 0 1 0 0 0.0500

1 1 1 0 1 0 1 0.0375

1 1 1 0 1 1 0 0.0250

1 1 1 0 1 1 1 0.0125



Datasheet 21


3.5 Signal Terminations and Unused Pins

All RSVD (RESERVED) pins must remain unconnected. Connection of these pins to VCC, VSS, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Section 4.2 for a pin listing of the processor and the location of all RSVD pins.

For reliable operation, always connect unused inputs or bidirectional signals to an appropriate signal level. Unused active low AGTL+ inputs may be left as no connects if AGTL+ termination is provided on the processor silicon. Unused active high inputs should be connected through a resistor to ground (VSS). Unused outputs can be left unconnected.

The TEST1 pin must have a stuffing option connection to VSS. The TEST2 pin must have a 51-Ω ±5%, pull-down resistor to VSS.

3.6 FSB Frequency Select Signals (BSEL[2:0])

The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). These signals should be connected to the clock chip and the Mobile Intel 945 Express Chipset family on the platform. The BSEL encoding for BCLK[1:0] is shown in Table 4.

3.7 FSB Signal Groups

In order to simplify the following discussion, the FSB signals have been combined into groups by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as a reference level. In this document, the term “AGTL+ Input” refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the AGTL+ output group as well as the AGTL+ I/O group when driving.

With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. One set is for common clock signals which are dependant upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle. Table 5 identifies which signals are common clock, source synchronous, and asynchronous.

Table 4. BSEL[2:0] Encoding for BCLK Frequency

BSEL[2] BSEL[1] BSEL[0] BCLK Frequency

L L L RESERVED

L L H 133 MHz

L H L RESERVED

L H H RESERVED


22 Datasheet

NOTES:1. Refer to Table 16 for signal descriptions and termination requirements.2. In processor systems where there is no debug port implemented on the system board,

these signals are used to support a debug port interposer. In systems with the debug port implemented on the system board, these signals are no connects.

3. BPM[2:1]# and PRDY# are AGTL+ output only signals.4. PROCHOT# signal type is open drain output and CMOS input.

Table 5. FSB Pin Groups

Signal Group Type Signals1

AGTL+ Common Clock Input

Synchronous to BCLK[1:0]

BPRI#, DEFER#, DPWR#, PREQ#, RESET#, RS[2:0]#, TRDY#

AGTL+ Common Clock I/OSynchronous to BCLK[1:0]

ADS#, BNR#, BPM[3:0]#3, BR0#, DBSY#, DRDY#, HIT#, HITM#, LOCK#, PRDY#3

AGTL+ Source Synchronous I/O

Synchronous to assoc. strobe

AGTL+ StrobesSynchronous to BCLK[1:0]

ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#

CMOS Input AsynchronousA20M#, DPRSTP#, DPSLP#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PWRGOOD, SMI#, SLP#, STPCLK#

Open Drain Output Asynchronous FERR#, IERR#, THERMTRIP#

Open Drain I/O Asynchronous PROCHOT#4

CMOS Output Asynchronous PSI#, VID[6:0], BSEL[2:0]

CMOS InputSynchronous to TCK

TCK, TDI, TMS, TRST#

Open Drain OutputSynchronous to TCK

TDO

FSB Clock Clock BCLK[1:0]

Power/OtherCOMP[3:0], DBR#2, GTLREF, RSVD, TEST2, TEST1, THERMDA, THERMDC, VCC, VCCA, VCCP, VCC_SENSE, VSS, VSS_SENSE

Signals Associated Strobe

REQ[4:0]#, A[16:3]#

ADSTB[0]#

A[31:17]# ADSTB[1]#

D[15:0]#, DINV0# DSTBP0#, DSTBN0#




Datasheet 23


3.8 CMOS Signals

CMOS input signals are shown in Table 5. Legacy output FERR#, IERR# and other non-AGTL+ signals (THERMTRIP# and PROCHOT#) utilize Open Drain output buffers. These signals do not have setup or hold time specifications in relation to BCLK[1:0]. However, all of the CMOS signals are required to be asserted for at least three BCLKs in order for the processor to recognize them. See Section 3.10 for the DC specifications for the CMOS signal groups.

3.9 Maximum Ratings

Table 6 specifies absolute maximum and minimum ratings. Only within specified operation limits, can functionality and long-term reliability be expected.

At condition outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long term reliability can be expected. If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits, but within the absolute maximum and minimum ratings, the device may be functional, but with its lifetime degraded on exposure to conditions exceeding the functional operation condition limits.

At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long term reliability can be expected. Moreover, if a device is subjected to these conditions for any length of time then, when returned to conditions within the functional operating condition limits, it will either not function or its reliability will be severely degraded.

Although the processor contains protective circuitry to resist damage from electro static discharge, precautions should always be taken to avoid high static voltages or electric fields.

NOTES:1. This rating applies to any processor pin.2. Contact Intel for storage requirements in excess of one year.

Table 6. Processor DC Absolute Maximum Ratings

Symbol Parameter Min Max Unit Notes

TSTORAGE Processor storage temperature -40 85 °C 2

VCCAny processor supply voltage with respect to VSS

-0.3 1.6 V 1

VinAGTL+AGTL+ buffer DC input voltage with respect to VSS

-0.3 1.6 V 1, 2

VinAsynch_CMOSCMOS buffer DC input voltage with respect to VSS

-0.3 1.6 V 1, 2


24 Datasheet

3.10 Processor DC Specifications

The processor DC specifications in this section are defined at the processor core (pads) unless noted otherwise. See Table 5 for the pin signal definitions and signal pin assignments. Most of the signals on the FSB are in the AGTL+ signal group. The DC specifications for these signals are listed in Table 9. DC specifications for the CMOS group are listed in Table 10.

Table 7 through Table 11 list the DC specifications for the processor and are valid only while meeting specifications for junction temperature, clock frequency, and input voltages. The Highest Frequency Mode (HFM) and Lowest Frequency Mode (LFM) refer to the highest and lowest core operating frequencies supported on the processor. Active mode load line specifications apply in all states. VCC,BOOT is the default voltage driven by the voltage regulator at power up in order to set the VID values. Unless specified otherwise, all specifications for the processor are at Tjunction = 100°C. Care should be taken to read all notes associated with each parameter.

NOTES:

Table 7. Voltage and Current Specifications for Standard Voltage Processor

Symbol Parameter Min Typ Max Unit Notes

VCCHFM VCC at Highest Frequency Mode (HFM) 1 1.3 V 1, 2

VCCLFM VCC at Lowest Frequency Mode (LFM) 1.025 V 2

VCC,BOOTDefault VCC Voltage for Initial Power- up

1.2 V 2, 7, 9

VCCP AGTL+ Termination Voltage 1.102 V 2

VCCA PLL Supply Voltage 1.425 1.5 1.575 V

ICCDES

ICC for Intel® Pentium Dual-Core Mobile Processor Recommended Design Target

36 A 5

ICC

ICC for Pentium Dual-Core Mobile Processor

Processor Number

Core Frequency/Voltage

T2060 1.60 GHz and HFM VCC 36 A 3

T2080 1.73 GHz and HFM Vcc 36 A 3

T2130 1.86 GHz and HFM Vcc 36 A 3

IAH,Isgnt

ICC Auto-Halt & Stop-GrantLFMHFM

12.523.3

A 3,4

ISLP

ICC SleepLFMHFM

12.423.2

A 3,4

dICC/DTVCC Power Supply Current Slew Rate at CPU Package Pin

600 A/µs 6, 8

ICCA ICC for VCCA Supply 120 mA

ICCPICC for VCCP Supply before VCC StableICC for VCCP Supply after VCC Stable

6.02.5

AA

1110

Datasheet 25


1. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and can not be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. Note that this differs from the VID employed by the processor during a power management event (Intel ®Thermal Monitor 2, Enhanced Intel SpeedStep Technology, or Enhanced Halt state).

2. The voltage specifications are assumed to be measured across VCC_SENSE and VSS_SENSE pins at socket with a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe.

3. Specified at 100°C Tj. 4. Specified at the VID voltage.5. The ICCDES(max) specification of 36 A comprehends only processor standard voltage HFM

frequencies. Platforms should be designed to 44 A to be compatible with Intel® Centrino® Duo Processor Technology.

6. Based on simulations and averaged over the duration of any change in current. Specified by design/characterization at nominal VCC. Not 100% tested.

7. Measured at the bulk capacitors on the motherboard.8. VCC,BOOT tolerance is shown in Figure 3.9. This is a steady-state ICCP current specification, which is applicable when both VCCP and

VCC_CORE are high.10. This is a power-up peak current specification, which is applicable when VCCP is high and

VCC_CORE is low. 11. Specified at the nominal VCC.


26 Datasheet

NOTE: For low voltage, if PSI# is not asserted then the 13-mV ripple allowance becomes 10 mV.

Figure 3. Active VCC and ICC Loadline for the Processor

ICC max {HFM|LFM}

VCC [V]

VCC nom {HFM|LFM}

+/-VCC nom * 1.5%= VR St. Pt. Error 1/

VCC, DC min {HFM|LFM}

VCC, DC max {HFM|LFM}

VCC max {HFM|LFM}

VCC min {HFM|LFM}

10mV= RIPPLE

ICC [A]0

Slope = -2.1 mV/A at packageVccSense, VssSense pins.Differential Remote Sense required.

Note 1/ VCC Set Point Error Tolerance is per below:

Tolerance VCC Active Mode VID Code Range--------------- -------------------------------------------------------- +/-1.5% VCC > 0.7500V (VID 0111100).+/-11.5mV VCC < 0.7500V (VID 0111100)

Datasheet 27


NOTES:1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.2. Crossing Voltage is defined as absolute voltage where rising edge of BCLK0 is equal to the falling edge of

BCLK1. 3. Threshold Region is defined as a region entered about the crossing voltage in which the differential receiver

switches. It includes input threshold hysteresis.4. For Vin between 0 V and VIH.5. Cpad includes die capacitance only. No package parasitics are included.6. ΔVCROSS is defined as the total variation of all crossing voltages as defined in note 2.

NOTES:1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.2. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low

value.3. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high

value.4. VIH and VOH may experience excursions above VCCP. However, input signal drivers must comply with the

signal quality specifications.5. This is the pull-down driver resistance. Refer to processor I/O Buffer Models for I/V characteristics.

Measured at 0.31*VCCP. RON (min) = 0.38*RTT, RON (typ) = 0.45*RTT, RON (max) = 0.52*RTT.6. GTLREF should be generated from VCCP with a 1% tolerance resistor divider. Tolerance of resistor divider

decides the tolerance of GTLREF. The VCCP referred to in these specifications is the instantaneous VCCP.7. RTT is the on-die termination resistance measured at VOL of the AGTL+ output driver. Measured at

0.31*VCCP. RTT is connected to VCCP on die. Refer to processor I/O buffer models for I/V characteristics.8. Specified with on die RTT and RON are turned off.9. Cpad includes die capacitance only. No package parasitics are included.10. This spec applies to all AGTL+ signals except for PREQ#. RTT for PREQ# is between 1.5 kΩ to 6.0 kΩ.

Table 8. FSB Differential BCLK Specifications


VIH Input High Voltage 0.660 0.710 0.85 V 1

VIL Input Low Voltage 0 V 1

VCROSS Crossing Voltage 0.25 0.35 0.55 V 1, 2

ΔVCROSS Range of Crossing Points 0.14 V 1, 6

VTH Threshold Region VCROSS -0.100 VCROSS+0.100 V 1, 3

ILI Input Leakage Current ±100 µA 1, 4

Cpad Pad Capacitance 0.95 1.2 1.45 pF 1, 5

Table 9. AGTL+ Signal Group DC Specifications


VCCP I/O Voltage 0.997 1.05 1.102 V 1

GTLREF Reference Voltage 2/3 VCCP V 1, 6

VIH Input High Voltage GTLREF+0.1 VCCP+0.1 V 1, 3,6

VIL Input Low Voltage -0.1 0 GTLREF-0.1 V 1, 2,4

VOH Output High Voltage VCCP 1, 6

RTT Termination Resistance 50 55 61 Ω 1, 7,10

RON Buffer on Resistance 22.3 25.5 28.7 Ω 1, 5

ILI Input Leakage Current ± 100 µA 1, 8



28 Datasheet

.

NOTES:1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.2. The VCCP referred to in these specifications refers to instantaneous VCCP.3. Refer to the processor I/O Buffer Models for I/V characteristics.4. Measured at 0.1*VCCP. 5. Measured at 0.9*VCCP. 6. For Vin between 0 V and VCCP. Measured when the driver is tristated.7. Cpad1 includes die capacitance only for DPSLP#,PWRGOOD. No package parasitics are included.8. Cpad2 includes die capacitance for all other CMOS input signals. No package parasitics are included.

NOTES:1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.2. Measured at 0.2*VCCP.3. VOH is determined by value of the external pull-up resistor to VCCP. Please refer to platform design guide for

details.4. For Vin between 0 V and VOH.5. Cpad includes die capacitance only. No package parasitics are included.

§

Table 10. CMOS Signal Group DC Specifications


VCCP I/O Voltage 1.0 1.05 1.10 V 1

VIH Input High Voltage 0.7 1.05 1.20 V 1, 2

VIL Input Low Voltage CMOS -0.1 0.0 0.33 V 1, 2, 3

VOH Output High Voltage 0.9 VCCP 1.20 V 1, 2

VOL Output Low Voltage -0.1 0 0.11 V 1, 2

IOH Output High Current 1.3 4.1 mA 1, 5

IOL Output Low Current 1.3 4.1 mA 1, 4

ILI Input Leakage Current ±100 µA 1, 6

Cpad1 Pad Capacitance 1.8 2.3 2.75 pF 1, 7

Cpad2 Pad Capacitance for CMOS Input 0.95 1.2 1.45 pF 1, 8

Table 11. Open Drain Signal Group DC Specifications


VOH Output High Voltage 1.0 1.05 1.10 V 1, 3

VOL Output Low Voltage 0 0.20 V

IOL Output Low Current 11.40 50 mA 1, 2

ILO Output Leakage Current ±200 µA 1, 4


Datasheet 29

Package Mechanical Specifications and Pin Information

4 Package Mechanical Specifications and Pin Information

4.1 Package Mechanical Specifications

The processor is available in 478-pin Micro-FCPGA package. The package mechanical dimensions are shown in Figure 4 through Figure 5.


30 Datasheet

Figure 4. Micro-FCPGA Processor Package Drawing Sheet 1 of 2

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Datasheet 31


Figure 5. Micro-FCPGA Processor Package Drawing Sheet 2 of 2

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32 Datasheet

4.2 Processor Pinout and Pin List

Table 12 shows the top view pinout of the processor. The pin list is arranged in two different formats is shown in the following pages.

Table 12. Processor Pin Coordinates from Top of the Package (Sheet 1 of 2)

1 2 3 4 5 6 7 8 9 10 11 12 13

A SMI# VSS FERR# A20M# VCC VSS VCC VCC VSS VCC VCC A

B RESET# RSVD INIT# LINT1 DPSLP# VSS VCC VSS VCC VCC VSS VCC VSS B

C RSVD VSS RSVD IGNNE# VSS LINT0 THERM

TRIP# VSS VCC VCC VSS VCC VCC C

D VSS RSVD RSVD VSS STPCLK#

PWRGOOD SLP# VSS VCC VCC VSS VCC VSS D

E DBSY# BNR# VSS HITM# DPRSTP# VSS VCC VSS VCC VCC VSS VCC VCC E

F BR0# VSS RS[0]# RS[1]# VSS RSVD VCC VSS VCC VCC VSS VCC VSS F

G VSS TRDY# RS[2]# VSS BPRI# HIT# G

H ADS# REQ[1]# VSS LOCK# DEFER# VSS H

J A[9]# VSS REQ[3]# A[3]# VSS VCCP J

K VSS REQ[2]#

REQ[0]# VSS A[6]# VCCP K

L A[13]# ADSTB[0]# VSS A[4]# REQ[4]

# VSS L

M A[7]# VSS A[5]# RSVD VSS VCCP M

N VSS A[8]# A[10]# VSS RSVD VCCP N

P A[15]# A[12]# VSS A[14]# A[11]# VSS P

R A[16]# VSS A[19]# A[24]# VSS VCCP R

T VSS RSVD A[26]# VSS A[25]# VCCP T

U COMP[2] A[23]# VSS A[21]# A[18]# VSS U

V COMP[3] VSS RSVD ADSTB[1]# VSS VCCP V

W VSS A[30]# A[27]# VSS A[28]# A[20]# W

Y A[31]# A[17]# VSS A[29]# A[22]# VSS Y

AA RSVD VSS RSVD RSVD VSS TDI VCC VSS VCC VCC VSS VCC VCC AA

AB VSS RSVD TDO VSS TMS TRST# VCC VSS VCC VCC VSS VCC VSS AB

AC PREQ# PRDY# VSS BPM[3]# TCK VSS VCC VSS VCC VCC VSS VCC VCC AC

AD BPM[2]# VSS BPM[1]#

BPM[0]# VSS VID[0] VCC VSS VCC VCC VSS VCC VSS AD

AE VSS VID[6] VID[4] VSS VID[2] PSI# VSSSENSE VSS VCC VCC VSS VCC VCC AE

AF RSVD VID[5] VSS VID[3] VID[1] VSS VCCSENSE VSS VCC VCC VSS VCC VSS AF

1 2 3 4 5 6 7 8 9 10 11 12 13

Datasheet 33


§

Table 13. Processor Pin Coordinates from Top of the Package (Sheet 2 of 2)

14 15 16 17 18 19 20 21 22 23 24 25 26

A VSS VCC VSS VCC VCC VSS VCC BCLK[1] BCLK[0] VSS THRMDA THRMDC VSS A

B VCC VCC VSS VCC VCC VSS VCC VSS BSEL[0] BSEL[1] VSS RSVD VCCA B

C VSS VCC VSS VCC VCC VSS DBR# BSEL[2] VSS RSVD RSVD VSS TEST1 C

D VCC VCC VSS VCC VCC VSS IERR# PROCHOT# RSVD VSS DPWR# TEST2 VSS D

E VSS VCC VSS VCC VCC VSS VCC VSS D[0]# D[7]# VSS D[6]# D[2]# E

F VCC VCC VSS VCC VCC VSS VCC DRDY# VSS D[4]# D[1]# VSS D[13]# F

G VCCP DSTBP[0]# VSS D[9]# D[5]# VSS G

H VSS D[3]# DSTBN[0]# VSS D[15]# D[12]# H

J VCCP VSS D[11]# D[10]# VSS DINV[0]# J

K VCCP D[14]# VSS D[8]# D[17]# VSS K

L VSS D[21]# D[22]# VSS D[20]# D[29]# L

M VCCP VSS D[23]# DSTBN[1]# VSS DINV[1

]# M

N VCCP D[16]# VSS D[31]# DSTBP[1]# VSS N

P VSS D[25]# D[26]# VSS D[24]# D[18]# P

R VCCP VSS D[19]# D[28]# VSS COMP[0] R

T VCCP RSVD VSS D[27]# D[30]# VSS T

U VSS D[39]# D[37]# VSS D[38]# COMP[1] U

V VCCP VSS DINV[2]# D[34]# VSS D[35]# V

W VCCP D[41]# VSS DSTBN[2]# D[36]# VSS W

Y VSS D[45]# D[42]# VSS DSTBP[2]# D[44]# Y

AA VSS VCC VSS VCC VCC VSS VCC D[51]# VSS D[32]# D[47]# VSS D[43]# AA

AB VCC VCC VSS VCC VCC VSS VCC D[52]# D[50]# VSS D[33]# D[40]# VSS AB

AC VSS VCC VSS VCC VCC VSS DINV[3]# VSS D[48]# D[49]# VSS D[53]# D[46]# AC

AD VCC VCC VSS VCC VCC VSS D[54]# D[59]# VSS DSTBN[3]

# D[57]# VSS GTLREF AD

AE VSS VCC VSS VCC VCC VSS VCC D[58]# D[55]# VSS DSTBP[3]# D[60]# VSS AE

AF VCC VCC VSS VCC VCC VSS VCC VSS D[62]# D[56]# VSS D[61]# D[63]# AF

14 15 16 17 18 19 20 21 22 23 24 25 26


34 Datasheet

Datasheet 35


Table 14. Pin Listing by Pin Name

(Sheet 1 of 22)

Pin NamePin

Number

Signal Buffer Type

Direction

A[3]# J4Source Synch

Input/Output

A[4]# L4Source Synch

Input/Output

A[5]# M3Source Synch

Input/Output

A[6]# K5Source Synch

Input/Output

A[7]# M1Source Synch

Input/Output

A[8]# N2Source Synch

Input/Output

A[9]# J1Source Synch

Input/Output

A[10]# N3Source Synch

Input/Output

A[11]# P5Source Synch

Input/Output


Input/Output

A[13]# L1Source Synch

Input/Output


Input/Output


Input/Output

A[16]# R1Source Synch

Input/Output

A[17]# Y2Source Synch

Input/Output

A[18]# U5Source Synch

Input/Output


Input/Output

A[20]# W6Source Synch

Input/Output


Input/Output


Input/Output


Input/Output


Input/Output

A[25]# T5Source Synch

Input/Output

A[26]# T3Source Synch

Input/Output


Input/Output


Input/Output


Input/Output


Input/Output


Input/Output

A20M# A6 CMOS Input

ADS# H1Common Clock

Input/Output

ADSTB[0]# L2Source Synch

Input/Output

ADSTB[1]# V4Source Synch

Input/Output

BCLK[0] A22 Bus Clock Input

BCLK[1] A21 Bus Clock Input

BNR# E2Common Clock

Input/Output

BPM[0]# AD4Common Clock

Input/Output


Output


Output

BPM[3]# AC4Common Clock

Input/Output

BPRI# G5Common Clock

Input

BR0# F1Common Clock

Input/Output

BSEL[0] B22 CMOS Output

BSEL[1] B23 CMOS Output

BSEL[2] C21 CMOS Output

Table 14. Pin Listing by Pin Name (Sheet 2 of 22)

Pin NamePin

Number

Signal Buffer Type

Direction


36 Datasheet

COMP[0] R26Power/Other

Input/Output

COMP[1] U26Power/Other

Input/Output

COMP[2] U1Power/Other

Input/Output

COMP[3] V1Power/Other

Input/Output

D[0]# E22Source Synch

Input/Output

D[1]# F24Source Synch

Input/Output


Input/Output

D[3]# H22Source Synch

Input/Output


Input/Output

D[5]# G25Source Synch

Input/Output


Input/Output


Input/Output

D[8]# K24Source Synch

Input/Output

D[9]# G24Source Synch

Input/Output

D[10]# J24Source Synch

Input/Output

D[11]# J23Source Synch

Input/Output


Input/Output


Input/Output


Input/Output


Input/Output

D[16]# N22Source Synch

Input/Output


Pin NamePin

Number

Signal Buffer Type

Direction


Input/Output

D[18]# P26Source Synch

Input/Output

D[19]# R23Source Synch

Input/Output

D[20]# L25Source Synch

Input/Output


Input/Output


Input/Output

D[23]# M23Source Synch

Input/Output


Input/Output


Input/Output


Input/Output

D[27]# T24Source Synch

Input/Output

D[28]# R24Source Synch

Input/Output


Input/Output

D[30]# T25Source Synch

Input/Output

D[31]# N24Source Synch

Input/Output

D[32]# AA23Source Synch

Input/Output

D[33]# AB24Source Synch

Input/Output

D[34]# V24Source Synch

Input/Output

D[35]# V26Source Synch

Input/Output

D[36]# W25Source Synch

Input/Output

D[37]# U23Source Synch

Input/Output


Pin NamePin

Number

Signal Buffer Type

Direction

Datasheet 37



Input/Output


Input/Output


Input/Output

D[41]# W22Source Synch

Input/Output

D[42]# Y23Source Synch

Input/Output


Input/Output


Input/Output


Input/Output

D[46]# AC26Source Synch

Input/Output


Input/Output


Input/Output


Input/Output


Input/Output


Input/Output


Input/Output


Input/Output

D[54]# AD20Source Synch

Input/Output

D[55]# AE22Source Synch

Input/Output

D[56]# AF23Source Synch

Input/Output


Input/Output


Input/Output


Pin NamePin

Number

Signal Buffer Type

Direction


Input/Output


Input/Output


Input/Output


Input/Output


Input/Output

DBR# C20 CMOS Output

DBSY# E1Common Clock

Input/Output

DEFER# H5Common Clock

Input

DINV[0]# J26Source Synch

Input/Output

DINV[1]# M26Source Synch

Input/Output

DINV[2]# V23Source Synch

Input/Output

DINV[3]# AC20Source Synch

Input/Output

DPRSTP# E5 CMOS Not used

DPSLP# B5 CMOS Input

DPWR# D24Common Clock

Input

DRDY# F21Common Clock

Input/Output

DSTBN[0]# H23Source Synch

Input/Output

DSTBN[1]# M24Source Synch

Input/Output

DSTBN[2]# W24Source Synch

Input/Output

DSTBN[3]# AD23Source Synch

Input/Output

DSTBP[0]# G22Source Synch

Input/Output

DSTBP[1]# N25Source Synch

Input/Output


Pin NamePin

Number

Signal Buffer Type

Direction


38 Datasheet

DSTBP[2]# Y25Source Synch

Input/Output

DSTBP[3]# AE24Source Synch

Input/Output

FERR# A5 Open Drain Output

GTLREF AD26Power/Other

Input

HIT# G6Common Clock

Input/Output

HITM# E4Common Clock

Input/Output

IERR# D20 Open Drain Output

IGNNE# C4 CMOS Input

INIT# B3 CMOS Input

LINT0 C6 CMOS Input

LINT1 B4 CMOS Input

LOCK# H4Common Clock

Input/Output

PRDY# AC2Common Clock

Output

PREQ# AC1Common Clock

Input

PROCHOT# D21 Open DrainInput/Output

PSI# AE6 CMOS Output

PWRGOOD D6 CMOS Input

REQ[0]# K3Source Synch

Input/Output

REQ[1]# H2Source Synch

Input/Output

REQ[2]# K2Source Synch

Input/Output

REQ[3]# J3Source Synch

Input/Output

REQ[4]# L5Source Synch

Input/Output

RESET# B1Common Clock

Input

RS[0]# F3Common Clock

Input


Pin NamePin

Number

Signal Buffer Type

Direction

RS[1]# F4Common Clock

Input

RS[2]# G3Common Clock

Input

RSVD D2 Reserved

RSVD F6 Reserved

RSVD D3 Reserved

RSVD C1 Reserved

RSVD AF1 Reserved

RSVD D22 Reserved

RSVD C23 Reserved

RSVD C24 Reserved

RSVD AA1 Reserved

RSVD AA4 Reserved

RSVD AB2 Reserved

RSVD AA3 Reserved

RSVD M4 Reserved

RSVD N5 Reserved

RSVD T2 Reserved

RSVD V3 Reserved

RSVD B2 Reserved

RSVD C3 Reserved

RSVD T22 Reserved

RSVD B25 Reserved

SLP# D7 CMOS Input

SMI# A3 CMOS Input

STPCLK# D5 CMOS Input

TCK AC5 CMOS Input

TDI AA6 CMOS Input

TDO AB3 Open Drain Output

TEST1 C26 Test

TEST2 D25 Test

THERMDA A24Power/Other

THERMDC A25Power/Other


Pin NamePin

Number

Signal Buffer Type

Direction

Datasheet 39


THERMTRIP#

C7 Open Drain Output

TMS AB5 CMOS Input

TRDY# G2Common Clock

Input

TRST# AB6 CMOS Input

VCC AB20Power/Other

VCC AA20Power/Other

VCC AF20Power/Other

VCC AE20Power/Other

VCC AB18Power/Other

VCC AB17Power/Other

VCC AA18Power/Other

VCC AA17Power/Other

VCC AD18Power/Other

VCC AD17Power/Other

VCC AC18Power/Other

VCC AC17Power/Other

VCC AF18Power/Other

VCC AF17Power/Other

VCC AE18Power/Other

VCC AE17Power/Other

VCC AB15Power/Other

VCC AA15Power/Other


Pin NamePin

Number

Signal Buffer Type

Direction

VCC AD15Power/Other

VCC AC15Power/Other

VCC AF15Power/Other

VCC AE15Power/Other

VCC AB14Power/Other

VCC AA13Power/Other

VCC AD14Power/Other

VCC AC13Power/Other

VCC AF14Power/Other

VCC AE13Power/Other

VCC AB12Power/Other

VCC AA12Power/Other

VCC AD12Power/Other

VCC AC12Power/Other

VCC AF12Power/Other

VCC AE12Power/Other

VCC AB10Power/Other

VCC AB9Power/Other

VCC AA10Power/Other

VCC AA9Power/Other

VCC AD10Power/Other


Pin NamePin

Number

Signal Buffer Type

Direction


40 Datasheet

VCC AD9Power/Other

VCC AC10Power/Other

VCC AC9Power/Other

VCC AF10Power/Other

VCC AF9Power/Other

VCC AE10Power/Other

VCC AE9Power/Other

VCC AB7Power/Other

VCC AA7Power/Other

VCC AD7Power/Other

VCC AC7Power/Other

VCC B20Power/Other

VCC A20Power/Other

VCC F20Power/Other

VCC E20Power/Other

VCC B18Power/Other

VCC B17Power/Other

VCC A18Power/Other

VCC A17Power/Other

VCC D18Power/Other

VCC D17Power/Other


Pin NamePin

Number

Signal Buffer Type

Direction

VCC C18Power/Other

VCC C17Power/Other

VCC F18Power/Other

VCC F17Power/Other

VCC E18Power/Other

VCC E17Power/Other

VCC B15Power/Other

VCC A15Power/Other

VCC D15Power/Other

VCC C15Power/Other

VCC F15Power/Other

VCC E15Power/Other

VCC B14Power/Other

VCC A13Power/Other

VCC D14Power/Other

VCC C13Power/Other

VCC F14Power/Other

VCC E13Power/Other

VCC B12Power/Other

VCC A12Power/Other

VCC D12Power/Other


Pin NamePin

Number

Signal Buffer Type

Direction

Datasheet 41


VCC C12Power/Other

VCC F12Power/Other

VCC E12Power/Other

VCC B10Power/Other

VCC B9Power/Other

VCC A10Power/Other

VCC A9Power/Other

VCC D10Power/Other

VCC D9Power/Other

VCC C10Power/Other

VCC C9Power/Other

VCC F10Power/Other

VCC F9Power/Other

VCC E10Power/Other

VCC E9Power/Other

VCC B7Power/Other

VCC A7Power/Other

VCC F7Power/Other

VCC E7Power/Other

VCCA B26Power/Other

VCCP K6Power/Other


Pin NamePin

Number

Signal Buffer Type

Direction

VCCP J6Power/Other

VCCP M6Power/Other

VCCP N6Power/Other

VCCP T6Power/Other

VCCP R6Power/Other

VCCP K21Power/Other

VCCP J21Power/Other

VCCP M21Power/Other

VCCP N21Power/Other

VCCP T21Power/Other

VCCP R21Power/Other

VCCP V21Power/Other

VCCP W21Power/Other

VCCP V6Power/Other

VCCP G21Power/Other

VCCSENSE AF7Power/Other

VID[0] AD6 CMOS Output

VID[1] AF5 CMOS Output

VID[2] AE5 CMOS Output





VSS AB26Power/Other


Pin NamePin

Number

Signal Buffer Type

Direction


42 Datasheet

VSS AA25Power/Other

VSS AD25Power/Other

VSS AE26Power/Other

VSS AB23Power/Other

VSS AC24Power/Other

VSS AF24Power/Other

VSS AE23Power/Other

VSS AA22Power/Other

VSS AD22Power/Other

VSS AC21Power/Other

VSS AF21Power/Other

VSS AB19Power/Other

VSS AA19Power/Other

VSS AD19Power/Other

VSS AC19Power/Other

VSS AF19Power/Other

VSS AE19Power/Other

VSS AB16Power/Other

VSS AA16Power/Other

VSS AD16Power/Other

VSS AC16Power/Other


Pin NamePin

Number

Signal Buffer Type

Direction

VSS AF16Power/Other

VSS AE16Power/Other

VSS AB13Power/Other

VSS AA14Power/Other

VSS AD13Power/Other

VSS AC14Power/Other

VSS AF13Power/Other

VSS AE14Power/Other

VSS AB11Power/Other

VSS AA11Power/Other

VSS AD11Power/Other

VSS AC11Power/Other

VSS AF11Power/Other

VSS AE11Power/Other

VSS AB8Power/Other

VSS AA8Power/Other

VSS AD8Power/Other

VSS AC8Power/Other

VSS AF8Power/Other

VSS AE8Power/Other

VSS AA5Power/Other


Pin NamePin

Number

Signal Buffer Type

Direction

Datasheet 43


VSS AD5Power/Other

VSS AC6Power/Other

VSS AF6Power/Other

VSS AB4Power/Other

VSS AC3Power/Other

VSS AF3Power/Other

VSS AE4Power/Other

VSS AB1Power/Other

VSS AA2Power/Other

VSS AD2Power/Other

VSS AE1Power/Other

VSS B6Power/Other

VSS C5Power/Other

VSS F5Power/Other

VSS E6Power/Other

VSS H6Power/Other

VSS J5Power/Other

VSS M5Power/Other

VSS L6Power/Other

VSS P6Power/Other

VSS R5Power/Other


Pin NamePin

Number

Signal Buffer Type

Direction

VSS V5Power/Other

VSS U6Power/Other

VSS Y6Power/Other

VSS A4Power/Other

VSS D4Power/Other

VSS E3Power/Other

VSS H3Power/Other

VSS G4Power/Other

VSS K4Power/Other

VSS L3Power/Other

VSS P3Power/Other

VSS N4Power/Other

VSS T4Power/Other

VSS U3Power/Other

VSS Y3Power/Other

VSS W4Power/Other

VSS D1Power/Other

VSS C2Power/Other

VSS F2Power/Other

VSS G1Power/Other

VSS K1Power/Other


Pin NamePin

Number

Signal Buffer Type

Direction


44 Datasheet

VSS J2Power/Other

VSS M2Power/Other

VSS N1Power/Other

VSS T1Power/Other

VSS R2Power/Other

VSS V2Power/Other

VSS W1Power/Other

VSS A26Power/Other

VSS D26Power/Other

VSS C25Power/Other

VSS F25Power/Other

VSS B24Power/Other

VSS A23Power/Other

VSS D23Power/Other

VSS E24Power/Other

VSS B21Power/Other

VSS C22Power/Other

VSS F22Power/Other

VSS E21Power/Other

VSS B19Power/Other

VSS A19Power/Other


Pin NamePin

Number

Signal Buffer Type

Direction

VSS D19Power/Other

VSS C19Power/Other

VSS F19Power/Other

VSS E19Power/Other

VSS B16Power/Other

VSS A16Power/Other

VSS D16Power/Other

VSS C16Power/Other

VSS F16Power/Other

VSS E16Power/Other

VSS B13Power/Other

VSS A14Power/Other

VSS D13Power/Other

VSS C14Power/Other

VSS F13Power/Other

VSS E14Power/Other

VSS B11Power/Other

VSS A11Power/Other

VSS D11Power/Other

VSS C11Power/Other

VSS F11Power/Other


Pin NamePin

Number

Signal Buffer Type

Direction

Datasheet 45


VSS E11Power/Other

VSS B8Power/Other

VSS A8Power/Other

VSS D8Power/Other

VSS C8Power/Other

VSS F8Power/Other

VSS E8Power/Other

VSS G26Power/Other

VSS K26Power/Other

VSS J25Power/Other

VSS M25Power/Other

VSS N26Power/Other

VSS T26Power/Other

VSS R25Power/Other

VSS V25Power/Other

VSS W26Power/Other

VSS H24Power/Other

VSS G23Power/Other

VSS K23Power/Other

VSS L24Power/Other

VSS P24Power/Other


Pin NamePin

Number

Signal Buffer Type

Direction

VSS N23Power/Other

VSS T23Power/Other

VSS U24Power/Other

VSS Y24Power/Other

VSS W23Power/Other

VSS H21Power/Other

VSS J22Power/Other

VSS M22Power/Other

VSS L21Power/Other

VSS P21Power/Other

VSS R22Power/Other

VSS V22Power/Other

VSS U21Power/Other

VSS Y21Power/Other

VSSSENSE AE7Power/Other

Output


Pin NamePin

Number

Signal Buffer Type

Direction


46 Datasheet

Table 15. Pin Listing by Pin Number (Sheet 1 of 16)

Pin Number

Pin NameSignal

Buffer TypeDirection

A3 SMI# CMOS Input

A4 VSS Power/Other

A5 FERR# Open Drain Output

A6 A20M# CMOS Input

A7 VCC Power/Other

A8 VSS Power/Other

A9 VCC Power/Other

A10 VCC Power/Other

A11 VSS Power/Other

A12 VCC Power/Other

A13 VCC Power/Other

A14 VSS Power/Other

A15 VCC Power/Other

A16 VSS Power/Other

A17 VCC Power/Other

A18 VCC Power/Other

A19 VSS Power/Other

A20 VCC Power/Other

A21 BCLK[1] Bus Clock Input

A22 BCLK[0] Bus Clock Input

A23 VSS Power/Other

A24 THERMDA Power/Other

A25 THERMDC Power/Other

A26 VSS Power/Other

AA1 RSVD Reserved

AA2 VSS Power/Other

AA3 RSVD Reserved

AA4 RSVD Reserved

AA5 VSS Power/Other

AA6 TDI CMOS Input

AA7 VCC Power/Other

AA8 VSS Power/other

AA9 VCC Power/Other

AA10 VCC Power/Other

AA11 VSS Power/Other










AA21 D[51]# Source SynchInput/Output






AB1 VSS Power/Other

AB2 RSVD Reserved

AB3 TDO Open Drain Output

AB4 VSS Power/Other

AB5 TMS CMOS Input

AB6 TRST# CMOS Input

AB7 VCC Power/Other

AB8 VSS Power/Other

AB9 VCC Power/Other

AB10 VCC Power/Other

AB11 VSS Power/Other










Pin Number

Pin NameSignal


Datasheet 47



AB21 D[52]# Source SynchInput/Output






AC1 PREQ#Common Clock

Input

AC2 PRDY#Common Clock

Output

AC3 VSS Power/Other

AC4 BPM[3]#Common Clock

Input/Output

AC5 TCK CMOS Input

AC6 VSS Power/Other

AC7 VCC Power/Other

AC8 VSS Power/Other

AC9 VCC Power/Other

AC10 VCC Power/Other

AC11 VSS Power/Other









AC20 DINV[3]# Source SynchInput/Output


AC22 D[48]# Source SynchInput/Output



Pin Number

Pin NameSignal





AD1 BPM[2]#Common Clock

Output

AD2 VSS Power/Other


Output


Input/Output

AD5 VSS Power/Other

AD6 VID[0] CMOS Output

AD7 VCC Power/Other

AD8 VSS Power/Other

AD9 VCC Power/Other

AD10 VCC Power/Other

AD11 VSS Power/Other









AD20 D[54]# Source SynchInput/Output



AD23DSTBN[3]#

Source SynchInput/Output



AD26 GTLREF Power/Other Input

AE1 VSS Power/Other


Pin Number

Pin NameSignal



48 Datasheet

AE2 VID[6] CMOS Output


AE4 VSS Power/Other


AE6 PSI# CMOS Output

AE7 VSSSENSE Power/Other Output

AE8 VSS Power/Other

AE9 VCC Power/Other

AE10 VCC Power/Other

AE11 VSS Power/Other










AE21 D[58]# Source SynchInput/Output



AE24 DSTBP[3]# Source SynchInput/Output



AF1 RSVD Reserved

AF2 VID[5] CMOS Output

AF3 VSS Power/Other



AF6 VSS Power/Other

AF7 VCCSENSE Power/Other

AF8 VSS Power/Other

AF9 VCC Power/Other


Pin Number

Pin NameSignal


AF10 VCC Power/Other

AF11 VSS Power/Other











AF22 D[62]# Source SynchInput/Output





B1 RESET#Common Clock

Input

B2 RSVD Reserved

B3 INIT# CMOS Input

B4 LINT1 CMOS Input

B5 DPSLP# CMOS Input

B6 VSS Power/Other

B7 VCC Power/Other

B8 VSS Power/Other

B9 VCC Power/Other

B10 VCC Power/Other

B11 VSS Power/Other

B12 VCC Power/Other

B13 VSS Power/Other

B14 VCC Power/Other

B15 VCC Power/Other

B16 VSS Power/Other


Pin Number

Pin NameSignal


Datasheet 49


B17 VCC Power/Other

B18 VCC Power/Other

B19 VSS Power/Other

B20 VCC Power/Other

B21 VSS Power/Other

B22 BSEL[0] CMOS Output

B23 BSEL[1] CMOS Output

B24 VSS Power/Other

B25 RSVD Reserved

B26 VCCA Power/Other

C1 RSVD Reserved

C2 VSS Power/Other

C3 RSVD Reserved

C4 IGNNE# CMOS Input

C5 VSS Power/Other

C6 LINT0 CMOS Input

C7THERMTRIP#

Open Drain Output

C8 VSS Power/Other

C9 VCC Power/Other

C10 VCC Power/Other

C11 VSS Power/Other

C12 VCC Power/Other

C13 VCC Power/Other

C14 VSS Power/Other

C15 VCC Power/Other

C16 VSS Power/Other

C17 VCC Power/Other

C18 VCC Power/Other

C19 VSS Power/Other

C20 DBR# CMOS Output

C21 BSEL[2] CMOS Output

C22 VSS Power/Other

C23 RSVD Reserved

C24 RSVD Reserved

C25 VSS Power/Other

C26 TEST1 Test


Pin Number

Pin NameSignal


D1 VSS Power/Other

D2 RSVD Reserved

D3 RSVD Reserved

D4 VSS Power/Other

D5 STPCLK# CMOS Input

D6 PWRGOOD CMOS Input

D7 SLP# CMOS Input

D8 VSS Power/Other

D9 VCC Power/Other

D10 VCC Power/Other

D11 VSS Power/Other

D12 VCC Power/Other

D13 VSS Power/Other

D14 VCC Power/Other

D15 VCC Power/Other

D16 VSS Power/Other

D17 VCC Power/Other

D18 VCC Power/Other

D19 VSS Power/Other

D20 IERR# Open Drain Output

D21 PROCHOT# Open DrainInput/Output

D22 RSVD Reserved

D23 VSS Power/Other

D24 DPWR#Common Clock

Input

D25 TEST2 Test

D26 VSS Power/Other

E1 DBSY#Common Clock

Input/Output

E2 BNR#Common Clock

Input/Output

E3 VSS Power/Other

E4 HITM#Common Clock

Input/Output

E5 DPRSTP# CMOS Not used

E6 VSS Power/Other

E7 VCC Power/Other


Pin Number

Pin NameSignal



50 Datasheet

E8 VSS Power/Other

E9 VCC Power/Other

E10 VCC Power/Other

E11 VSS Power/Other

E12 VCC Power/Other

E13 VCC Power/Other

E14 VSS Power/Other

E15 VCC Power/Other

E16 VSS Power/Other

E17 VCC Power/Other

E18 VCC Power/Other

E19 VSS Power/Other

E20 VCC Power/Other

E21 VSS Power/Other

E22 D[0]# Source SynchInput/Output


E24 VSS Power/Other



F1 BR0#Common Clock

Input/Output

F2 VSS Power/Other

F3 RS[0]#Common Clock

Input

F4 RS[1]#Common Clock

Input

F5 VSS Power/Other

F6 RSVD Reserved

F7 VCC Power/Other

F8 VSS Power/Other

F9 VCC Power/Other

F10 VCC Power/Other

F11 VSS Power/Other

F12 VCC Power/Other

F13 VSS Power/Other


Pin Number

Pin NameSignal


F14 VCC Power/Other

F15 VCC Power/Other

F16 VSS Power/Other

F17 VCC Power/Other

F18 VCC Power/Other

F19 VSS Power/Other

F20 VCC Power/Other

F21 DRDY#Common Clock

Input/Output

F22 VSS Power/Other

F23 D[4]# Source SynchInput/Output


F25 VSS Power/Other


G1 VSS Power/Other

G2 TRDY#Common Clock

Input

G3 RS[2]#Common Clock

Input

G4 VSS Power/Other

G5 BPRI#Common Clock

Input

G6 HIT#Common Clock

Input/Output

G21 VCCP Power/Other

G22 DSTBP[0]# Source SynchInput/Output

G23 VSS Power/Other

G24 D[9]# Source SynchInput/Output

G25 D[5]# Source SynchInput/Output

G26 VSS Power/Other

H1 ADS#Common Clock

Input/Output

H2 REQ[1]# Source SynchInput/Output

H3 VSS Power/Other


Pin Number

Pin NameSignal


Datasheet 51


H4 LOCK#Common Clock

Input/Output

H5 DEFER#Common Clock

Input

H6 VSS Power/Other

H21 VSS Power/Other

H22 D[3]# Source SynchInput/Output

H23DSTBN[0]#


H24 VSS Power/Other



J1 A[9]# Source SynchInput/Output

J2 VSS Power/Other

J3 REQ[3]# Source SynchInput/Output

J4 A[3]# Source SynchInput/Output

J5 VSS Power/Other

J6 VCCP Power/Other

J21 VCCP Power/Other

J22 VSS Power/Other

J23 D[11]# Source SynchInput/Output

J24 D[10]# Source SynchInput/Output

J25 VSS Power/Other

J26 DINV[0]# Source SynchInput/Output

K1 VSS Power/Other

K2 REQ[2]# Source SynchInput/Output

K3 REQ[0]# Source SynchInput/Output

K4 VSS Power/Other

K5 A[6]# Source SynchInput/Output


Pin Number

Pin NameSignal


K6 VCCP Power/Other

K21 VCCP Power/Other

K22 D[14]# Source SynchInput/Output

K23 VSS Power/Other



K26 VSS Power/Other

L1 A[13]# Source SynchInput/Output

L2 ADSTB[0]# Source SynchInput/Output

L3 VSS Power/Other

L4 A[4]# Source SynchInput/Output

L5 REQ[4]# Source SynchInput/Output

L6 VSS Power/Other

L21 VSS Power/Other

L22 D[21]# Source SynchInput/Output


L24 VSS Power/Other



M1 A[7]# Source SynchInput/Output

M2 VSS Power/Other

M3 A[5]# Source SynchInput/Output

M4 RSVD Reserved

M5 VSS Power/Other

M6 VCCP Power/Other

M21 VCCP Power/Other

M22 VSS Power/Other


Pin Number

Pin NameSignal



52 Datasheet

M23 D[23]# Source SynchInput/Output

M24DSTBN[1]#


M25 VSS Power/Other

M26 DINV[1]# Source SynchInput/Output

N1 VSS Power/Other

N2 A[8]# Source SynchInput/Output

N3 A[10]# Source SynchInput/Output

N4 VSS Power/Other

N5 RSVD Reserved

N6 VCCP Power/Other

N21 VCCP Power/Other

N22 D[16]# Source SynchInput/Output

N23 VSS Power/Other

N24 D[31]# Source SynchInput/Output

N25 DSTBP[1]# Source SynchInput/Output

N26 VSS Power/Other

P1 A[15]# Source SynchInput/Output


P3 VSS Power/Other



P6 VSS Power/Other

P21 VSS Power/Other

P22 D[25]# Source SynchInput/Output


P24 VSS Power/Other


Pin Number

Pin NameSignal




R1 A[16]# Source SynchInput/Output

R2 VSS Power/Other



R5 VSS Power/Other

R6 VCCP Power/Other

R21 VCCP Power/Other

R22 VSS Power/Other

R23 D[19]# Source SynchInput/Output

R24 D[28]# Source SynchInput/Output

R25 VSS Power/Other

R26 COMP[0] Power/OtherInput/Output

T1 VSS Power/Other

T2 RSVD Reserved

T3 A[26]# Source SynchInput/Output

T4 VSS Power/Other

T5 A[25]# Source SynchInput/Output

T6 VCCP Power/Other

T21 VCCP Power/Other

T22 RSVD Reserved

T23 VSS Power/Other

T24 D[27]# Source SynchInput/Output

T25 D[30]# Source SynchInput/Output

T26 VSS Power/Other

U1 COMP[2] Power/OtherInput/Output


Pin Number

Pin NameSignal


Datasheet 53


U2 A[23]# Source SynchInput/Output

U3 VSS Power/Other



U6 VSS Power/Other

U21 VSS Power/Other

U22 D[39]# Source SynchInput/Output


U24 VSS Power/Other


U26 COMP[1] Power/OtherInput/Output

V1 COMP[3] Power/OtherInput/Output

V2 VSS Power/Other

V3 RSVD Reserved

V4 ADSTB[1]# Source SynchInput/Output

V5 VSS Power/Other

V6 VCCP Power/Other

V21 VCCP Power/Other

V22 VSS Power/Other

V23 DINV[2]# Source SynchInput/Output

V24 D[34]# Source SynchInput/Output

V25 VSS Power/Other

V26 D[35]# Source SynchInput/Output

W1 VSS Power/Other

W2 A[30]# Source SynchInput/Output


W4 VSS Power/Other


Pin Number

Pin NameSignal




W21 VCCP Power/Other

W22 D[41]# Source SynchInput/Output

W23 VSS Power/Other

W24DSTBN[2]#


W25 D[36]# Source SynchInput/Output

W26 VSS Power/Other

Y1 A[31]# Source SynchInput/Output


Y3 VSS Power/Other



Y6 VSS Power/Other

Y21 VSS Power/Other

Y22 D[45]# Source SynchInput/Output


Y24 VSS Power/Other

Y25 DSTBP[2]# Source SynchInput/Output



Pin Number

Pin NameSignal



54 Datasheet

Datasheet 55


4.3 Alphabetical Signals Reference

Table 16. Signal Description (Sheet 1 of 8)

Name Type Description

A[31:3]#Input/Output

A[31:3]# (Address) define a 232-byte physical memory address space. In sub-phase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of both agents on the processor FSB. A[31:3]# are source synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#. Address signals are used as straps which are sampled before RESET# is deasserted.

A20M# Input

If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit 20 (A20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting A20M# emulates the 8086 processor's address wrap-around at the 1-MB boundary. Assertion of A20M# is only supported in real mode.A20M# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction.

ADS#Input/Output

ADS# (Address Strobe) is asserted to indicate the validity of the transaction address on the A[31:3]# and REQ[4:0]# pins. All bus agents observe the ADS# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction.

ADSTB[1:0]#Input/Output

Address strobes are used to latch A[31:3]# and REQ[4:0]# on their rising and falling edges. Strobes are associated with signals as shown below:.

BCLK[1:0] Input

The differential pair BCLK (Bus Clock) determines the FSB frequency. All FSB agents must receive these signals to drive their outputs and latch their inputs.All external timing parameters are specified with respect to the rising edge of BCLK0 crossing VCROSS.

BNR#Input/Output

BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is unable to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new transactions.

BPM[2:1]#BPM[3,0]#

OutputInput/Output

BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[3:0]# should connect the appropriate pins of all processor FSB agents.This includes debug or performance monitoring tools.For termination requirements please contact your Intel representative.


REQ[4:0]#, A[16:3]# ADSTB[0]#

A[31:17]# ADSTB[1]#


56 Datasheet

BPRI# Input

BPRI# (Bus Priority Request) is used to arbitrate for ownership of the FSB. It must connect the appropriate pins of both FSB agents. Observing BPRI# active (as asserted by the priority agent) causes the other agent to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by deasserting BPRI#.

BR0#Input/Output

BR0# is used by the processor to request the bus. The arbitration is done between the processor (Symmetric Agent) and Mobile Intel® 945 Express Chipset family GMCH-M (High Priority Agent).

BSEL[2:0] Output

BSEL[2:0] (Bus Select) are used to select the processor input clock frequency. Table 4 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset and clock synthesizer. All agents must operate at the same frequency. The Intel® Pentium® dual-core mobile processor operates at 533-MHz system bus frequency (133-MHz BCLK[1:0] frequency).

COMP[3:0] AnalogCOMP[3:0] must be terminated on the system board using precision (1% tolerance) resistors. For termination requirements please contact your Intel representative.

D[63:0]#Input/Output

D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the FSB agents, and must connect the appropriate pins on both agents. The data driver asserts DRDY# to indicate a valid data transfer.D[63:0]# are quad-pumped signals and will thus be driven four times in a common clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP# and one DSTBN#. The following table shows the grouping of data signals to data strobes and DINV#.

Furthermore, the DINV# pins determine the polarity of the data signals. Each group of 16 data signals corresponds to one DINV# signal. When the DINV# signal is active, the corresponding data group is inverted and therefore sampled active high.

DBR# Output

DBR# (Data Bus Reset) is used only in processor systems where no debug port is implemented on the system board. DBR# is used by a debug port interposer so that an in-target probe can drive system reset. If a debug port is implemented in the system, DBR# is a no connect in the system. DBR# is not a processor signal.



Quad-Pumped Signal Groups

Data Group

DSTBN#/DSTBP#

DINV#

D[15:0]# 0 0

D[31:16]# 1 1

D[47:32]# 2 2

D[63:48]# 3 3

Datasheet 57


DBSY#Input/Output

DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the FSB to indicate that the data bus is in use. The data bus is released after DBSY# is deasserted. This signal must connect the appropriate pins on both FSB agents.

DEFER# Input

DEFER# is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or Input/Output agent. This signal must connect the appropriate pins of both FSB agents.

DINV[3:0]#Input/Output

DINV[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity of the D[63:0]# signals. The DINV[3:0]# signals are activated when the data on the data bus is inverted. The bus agent will invert the data bus signals if more than half the bits, within the covered group, would change level in the next cycle.

DPRSTP# Not used DPRSTP# is not used by Pentium dual-core mobile processor.

DPSLP# Input

DPSLP# when asserted on the platform causes the processor to transition from the Sleep State to the Deep Sleep state. In order to return to the Sleep State, DPSLP# must be deasserted. DPSLP# is driven by the ICH7-M chipset.

DPWR# InputDPWR# is a control signal from the Intel 945 Express Chipset used to reduce power on the processor data bus input buffers.

DRDY#Input/Output

DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the appropriate pins of both FSB agents.

DSTBN[3:0]#Input/Output

Data strobe used to latch in D[63:0]#.



DINV[3:0]# Assignment to Data Bus

Bus Signal Data Bus Signals

DINV[3]# D[63:48]#

DINV[2]# D[47:32]#

DINV[1]# D[31:16]#

DINV[0]# D[15:0]#


D[15:0]#, DINV[0]# DSTBN[0]#

D[31:16]#, DINV[1]# DSTBN[1]#

D[47:32]#, DINV[2]# DSTBN[2]#

D[63:48]#, DINV[3]# DSTBN[3]#


58 Datasheet

DSTBP[3:0]#Input/Output

Data strobe used to latch in D[63:0]#.

FERR#/PBE# Output

FERR# (Floating-point Error)PBE#(Pending Break Event) is a multiplexed signal and its meaning is qualified with STPCLK#. When STPCLK# is not asserted, FERR#/PBE# indicates a floating point when the processor detects an unmasked floating-point error. FERR# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using MS-DOS*-type floating-point error reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the processor has a pending break event waiting for service. The assertion of FERR#/PBE# indicates that the processor should be returned to the Normal state. When FERR#/PBE# is asserted, indicating a break event, it will remain asserted until STPCLK# is deasserted. Assertion of PREQ# when STPCLK# is active will also cause an FERR# break event. For additional information on the pending break event functionality, including identification of support of the feature and enable/disable information, refer to Volume 3 of the Intel® 64 and IA-32 Architectures Software Developer's Manuals and the Intel®

Processor Identification and CPUID Instruction Application Note.For termination requirements please contact your Intel representative.

GTLREF Input

GTLREF determines the signal reference level for AGTL+ input pins. GTLREF should be set at 2/3 VCCP. GTLREF is used by the AGTL+ receivers to determine if a signal is a logical 0 or logical 1.For termination requirements please contact your Intel representativefor details on GTLREF implementation.

HIT#

HITM#

Input/Output

Input/Output

HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Either FSB agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together.

IERR# Output

IERR# (Internal Error) is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the FSB. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#, BINIT#, or INIT#. For termination requirements please contact your Intel representative.




D[15:0]#, DINV[0]# DSTBP[0]#

D[31:16]#, DINV[1]# DSTBP[1]#

D[47:32]#, DINV[2]# DSTBP[2]#

D[63:48]#, DINV[3]# DSTBP[3]#

Datasheet 59


IGNNE# Input

IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating-point instructions. If IGNNE# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction.

INIT# Input

INIT# (Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. The processor then begins execution at the power-on Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output Write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction. INIT# must connect the appropriate pins of both FSB agents.If INIT# is sampled active on the active to inactive transition of RESET#, then the processor executes its Built-in Self-Test (BIST).For termination requirements please contact your Intel representative.

LINT[1:0] Input

LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all APIC Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Pentium processor. Both signals are asynchronous.Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC is enabled by default after Reset, operation of these pins as LINT[1:0] is the default configuration.

LOCK#Input/Output

LOCK# indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins of both FSB agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction to the end of the last transaction.When the priority agent asserts BPRI# to arbitrate for ownership of the FSB, it will wait until it observes LOCK# deasserted. This enables symmetric agents to retain ownership of the FSB throughout the bus locked operation and ensure the atomicity of lock.

PRDY# OutputProbe Ready signal used by debug tools to determine processor debug readiness.

PREQ# InputProbe Request signal used by debug tools to request debug operation of the processor.




60 Datasheet

PROCHOT#Input/Output

As an output, PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit (TCC) has been activated, if enabled. As an input, assertion of PROCHOT# by the system will activate the TCC, if enabled. The TCC will remain active until the system deasserts PROCHOT#.By default PROCHOT# is configured as an output only. Bidirectional PROCHOT# must be enabled via the BIOS.This signal may require voltage translation on the motherboard. For termination requirements please contact your Intel representative.

PSI# Output

Processor Power Status Indicator signal. This signal is asserted when the processor is in a normal state (HFM and LFM) and lower state (Deep Sleep).For termination requirements please contact your Intel representative.

PWRGOOD Input

PWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. ‘Clean’ implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high state. The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout boundary scan operation.For termination requirements please contact your Intel representative.

REQ[4:0]#Input/Output

REQ[4:0]# (Request Command) must connect the appropriate pins of both FSB agents. They are asserted by the current bus owner to define the currently active transaction type. These signals are source synchronous to ADSTB[0]#.

RESET# Input

Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least two milliseconds after VCC and BCLK have reached their proper specifications. On observing active RESET#, both FSB agents will deassert their outputs within two clocks. All processor straps must be valid within the specified setup time before RESET# is deasserted.For termination requirements please contact your Intel representative.There is a 55 Ω (nominal) on die pull-up resistor on this signal.

RS[2:0]# InputRS[2:0]# (Response Status) are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins of both FSB agents.

RSVDReserved

/No Connect

These pins are RESERVED and must be left unconnected on the board. However, it is recommended that routing channels to these pins on the board be kept open for possible future use. For termination requirements please contact your Intel representative.



Datasheet 61


SLP# Input

SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter the Sleep state. During Sleep state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in this state will not recognize snoops or interrupts. The processor will recognize only assertion of the RESET# signal, deassertion of SLP#, and removal of the BCLK input while in Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to Stop-Grant state, restarting its internal clock signals to the bus and processor core units. If DPSLP# is asserted while in the Sleep state, the processor will exit the Sleep state and transition to the Deep Sleep state.

SMI# Input

SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a System Management Interrupt, the processor saves the current state and enter System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler.If SMI# is asserted during the deassertion of RESET# the processor will tristate its outputs.

STPCLK# Input

STPCLK# (Stop Clock), when asserted, causes the processor to enter a low power Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the FSB and APIC units. The processor continues to snoop bus transactions and service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the processor restarts its internal clock to all units and resumes execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input.

TCK Input

TCK (Test Clock) provides the clock input for the processor Test Bus (also known as the Test Access Port). For termination requirements please contact your Intel representative.

TDI Input

TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support.For termination requirements please contact your Intel representative.

TDO Output

TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support.For termination requirements please contact your Intel representative.

TEST1 InputTEST1 must have a stuffing option of separate pull down resistor to VSS. For termination requirements please contact your Intel representative.

TEST2 InputTEST2 must have a 51-Ω ±5% pull-down resistor to VSS. For termination requirements please contact your Intel representative.

THERMDA Other Thermal Diode Anode.

THERMDC Other Thermal Diode Cathode.




62 Datasheet

THERMTRIP# Output

The processor protects itself from catastrophic overheating by use of an internal thermal sensor. This sensor is set well above the normal operating temperature to ensure that there are no false trips. The processor will stop all execution when the junction temperature exceeds approximately 125°C. This is signalled to the system by the THERMTRIP# (Thermal Trip) pin.For termination requirements please contact your Intel representative.

TMS Input

TMS (Test Mode Select) is a JTAG specification support signal used by debug tools.For termination requirements please contact your Intel representative.

TRDY# Input

TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of both FSB agents.For termination requirements please contact your Intel representative.

TRST# Input

TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset. For termination requirements please contact your Intel representative.

VCC Input Processor core power supply.

VCCA InputVCCA provides isolated power for the internal processor core PLL’s. For termination requirements please contact your Intel representative.

VCCP Input Processor I/O Power Supply.

VCC_SENSE Output

VCC_SENSE together with VSS_SENSE are voltage feedback signals to IMVP6 that control the 2.1-mΩ loadline at the processor die. It should be used to sense voltage near the silicon with little noise. For termination requirements please contact your Intel representative.

VID[6:0] Output

VID[6:0] (Voltage ID) pins are used to support automatic selection of power supply voltages (VCC). Unlike some previous generations of processors, these are CMOS signals that are driven by the processor. The voltage supply for these pins must be valid before the VR can supply Vcc to the processor. Conversely, the VR output must be disabled until the voltage supply for the VID pins becomes valid. The VID pins are needed to support the processor voltage specification variations. See Table 3.3 for definitions of these pins. The VR must supply the voltage that is requested by the pins, or disable itself.

VSS_SENSE Output

VSS_SENSE together with VCC_SENSE are voltage feedback signals to Intel® MVP6 that control the 2.1-mΩ loadline at the processor die. It should be used to sense ground near the silicon with little noise. For termination requirements please contact your Intel representative.



Datasheet 63

Thermal Specifications and Design Considerations

5 Thermal Specifications and Design Considerations

The processor requires a thermal solution to maintain temperatures within operating limits.

For optimal operation and long-term reliability of Intel processor-based systems, the system/processor thermal solution should be designed so that the processor remains within the minimum and maximum junction temperature (Tj) specifications at the corresponding thermal design power (TDP) value listed in Table 17 to Table 21.

Warning: Any attempt to operate that processor outside these operating limits may result in permanent damage to the processor and potentially other components in the system.

NOTES:1. The TDP specification should be used to design the processor thermal solution. The TDP is

not the maximum theoretical power the processor can generate. 2. Not 100% tested. These power specifications are determined by characterization of the

processor currents at higher temperatures and extrapolating the values for the temperature indicated.

3. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic mode is used to indicate that the maximum TJ has been reached. Refer to Section 5.1 for more details.

4. The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within specifications.

Table 17. Power Specifications

SymbolProcessor Number

Core Frequency & Voltage

Thermal Design Power

Unit Notes

TDP T2060 1.60 GHz & HFM Vcc 31 WAt 100°C

Notes 1, 4, 5


Notes 1, 4, 5


Notes 1, 4, 5


PAH,

PSGNT

Auto Halt, Stop Grant Powerat HFM VCC

at LFM VCC

15.84.8

WAt 50°CNote 2

PSLP

Sleep Power at HFM VCC

at LFM VCC

15.54.7

WAt 50°CNote 2

PDSLP

Deep Sleep Power at HFM VCC

at LFM VCC

10.53.4

WAt 35°CNote 2

TJ Junction Temperature 0 100 °C Notes 3, 4


64 Datasheet

5.1 Monitoring Processor Temperature

The processor incorporates three methods of monitoring die temperature:

• Digital thermal sensor

• Intel Thermal Monitor

• Thermal Diode

5.1.1 Thermal Diode

The processor incorporates an on-die PNP transistor whose base emitter junction is used as a thermal “diode”, with its collector shorted to Ground. The thermal diode, can be read by an off-die analog/digital converter (a thermal sensor) located on the motherboard, or a stand-alone measurement kit. The thermal diode may be used to monitor the die temperature of the processor for thermal management or instrumentation purposes but is not a reliable indication that the maximum operating temperature of the processor has been reached. When using the thermal diode, a temperature offset value must be read from a processor Model Specific Register (MSR) and applied. See Section 5.1.2 for more details. Please see Section 5.1.3 for thermal diode usage recommendation when the PROCHOT# signal is not asserted.

Note: The reading of the external thermal sensor (on the motherboard) connected to the processor thermal diode signals, will not necessarily reflect the temperature of the hottest location on the die. This is due to inaccuracies in the external thermal sensor, on-die temperature gradients between the location of the thermal diode and the hottest location on the die, and time based variations in the die temperature measurement. Time based variations can occur when the sampling rate of the thermal diode (by the thermal sensor) is slower than the rate at which the TJ temperature can change.

Offset between the thermal diode based temperature reading and the Intel Thermal Monitor reading may be characterized using the Intel Thermal Monitor’s Automatic mode activation of thermal control circuit. This temperature offset must be taken into account when using the processor thermal diode to implement power management events. This offset is different than the diode Toffset value programmed into the processor Model Specific Register (MSR).

Table 18, Table 19, Table 20, and Table 21 provide the diode interface and specifications. Two different sets of diode parameters are listed in Table 19 and Table 20. The Diode Model parameters (Table 19) apply to traditional thermal sensors that use the Diode Equation to determine the processor temperature. Transistor Model parameters (Table 20) have been added to support thermal sensors that use the transistor equation method. The Transistor Model may provide more accurate temperature measurements when the diode ideality factor is closer to the maximum or minimum limits. Please contact your external thermal sensor supplier for their recommendation. This thermal diode is separate from the Intel Thermal Monitor's thermal sensor and cannot be used to predict the behavior of the Intel Thermal Monitor.

Table 18. Thermal Diode Interface

Signal Name Pin/Ball Number Signal Description

THERMDA A24 Thermal diode anode

THERMDC A25 Thermal diode cathode

Datasheet 65


NOTES:1. Intel does not support or recommend operation of the thermal diode under reverse bias.

Intel does not support or recommend operation of the thermal diode when the processor power supplies are not within their specified tolerance range.

2. Characterized across a temperature range of 50 - 100°C.3. Not 100% tested. Specified by design characterization.4. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by

the diode equation:

IFW = IS * (e qVD/nkT –1)where IS = saturation current, q = electronic charge, VD = voltage across the diode, k =Boltzmann Constant, and T = absolute temperature (Kelvin).

5. The series resistance, RT, is provided to allow for a more accurate measurement of the junction temperature. RT, as defined, includes the lands of the processor but does not include any socket resistance or board trace resistance between the socket and the external remote diode thermal sensor. RT can be used by remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term. Another application is that a temperature offset can be manually calculated and programmed into an offset register in the remote diode thermal sensors as exemplified by the equation:

Terror = [RT * (N-1) * IFWmin] / [nk/q * ln N]where Terror = sensor temperature error, N = sensor current ratio, k = Boltzmann Constant,q = electronic charge.

NOTES:1. Intel does not support or recommend operation of the thermal diode under reverse bias.2. Same as IFW in Table 18.3. Characterized across a temperature range of 50 - 100 °C.4. Not 100% tested. Specified by design characterization.5. The ideality factor, nQ, represents the deviation from ideal transistor model behavior as

exemplified by the equation for the collector current:

IC = IS * (e qVBE/nQkT –1)Where IS = saturation current, q = electronic charge, VBE = voltage across the transistorbase emitter junction (same nodes as VD), k = Boltzmann Constant, and T = absolutetemperature (Kelvin).

6. The series resistance, RT, provided in the Diode Model Table (Table 19) can be used for more accurate readings as needed.

Table 19. Thermal Diode Parameters using Diode Mode


IFW Forward Bias Current 5 - 200 µA 1

n Diode Ideality Factor 1.000 1.009 1.050 - 2, 3, 4

RT Series Resistance 2.79 4.52 6.24 Ω 2, 3, 5

Table 20. Thermal Diode Parameters using Transistor Mode


IFW Forward Bias Current 5 - 200 µA 1, 2

IE Emitter Current 5 200 µA

nQ Transistor Ideality 0.997 1.001 1.005 - 3, 4, 5

Beta 0.3 0.760 3, 4

RT Series Resistance 2.79 4.52 6.24 Ω 3, 6


66 Datasheet

When calculating a temperature based on thermal diode measurements, a number of parameters must be either measured or assumed. Most devices measure the diode ideality and assume a series resistance and ideality trim value, although some are capable of also measuring the series resistance. Calculating the temperature is then accomplished using the equations listed under Table 18. In most temperature sensing devices, an expected value for the diode ideality is designed-in to the temperature calculation equation. If the designer of the temperature sensing device assumes a perfect diode the ideality value (also called ntrim) will be 1.000. Given that most diodes are not perfect, the designers usually select an ntrim value that more closely matches the behavior of the diodes in the processor. If the processors diode ideality deviates from that of ntrim, each calculated temperature will be offset by a fixed amount. This temperature offset can be calculated with the equation:

Terror(nf) = Tmeasured X (1 - nactual/ntrim)Where Terror(nf) is the offset in degrees C, Tmeasured is in Kelvin, nactual is the measured ideality of the diode, and ntrim is the diode ideality assumed by the temperature sensing device.

5.1.2 Thermal Diode Offset

In order to improve the accuracy of diode based temperature measurements, a temperature offset value (specified as Toffset) will be programmed into a processor Model Specific Register (MSR) which will contain thermal diode characterization data. During manufacturing each processors thermal diode will be evaluated for its behavior relative to a theoretical diode. Using the equation above, the temperature error created by the difference between ntrim and the actual ideality of the particular processor will be calculated. If the ntrim value used to calculate Toffset differs from the ntrim value used in a temperature sensing device, the Terror(nf) may not be accurate. If desired, the Toffset can be adjusted by calculating nactual and then recalculating the offset using the actual ntrim as defined in the temperature sensor manufacturers' datasheet.

The ntrim used to calculate the Diode Correction Toffset are listed in Table 21.

Table 21. Thermal Diode ntrim and Diode Correction Toffset

Symbol Parameter Unit

ntrim Diode ideality used to calculate Toffset 1.01

Datasheet 67


5.1.3 Intel® Thermal Monitor

The Intel Thermal Monitor helps control the processor temperature by activating the TCC (Thermal Control Circuit) when the processor silicon reaches its maximum operating temperature. The temperature at which the Intel Thermal Monitor activates the TCC is not user configurable. Bus traffic is snooped in the normal manner, and interrupt requests are latched (and serviced during the time that the clocks are on) while the TCC is active.

With a properly designed and characterized thermal solution, it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications. The processor performance impact due to these brief periods of TCC activation is expected to be minor and hence not detectable. An under-designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss, and may affect the long-term reliability of the processor. In addition, a thermal solution that is significantly under designed may not be capable of cooling the processor even when the TCC is active continuously.

The Intel Thermal Monitor controls the processor temperature by modulating (starting and stopping) the processor core clocks or by initiating an Enhanced Intel SpeedStep Technology transition when the processor silicon reaches its maximum operating temperature. The Intel Thermal Monitor uses two modes to activate the TCC: Automatic mode and on-demand mode. If both modes are activated, Automatic mode takes precedence.

Note: The Intel Thermal Monitor automatic mode must be enabled through BIOS for the processor to be operating within specifications.

There are two automatic modes called Intel Thermal Monitor 1 (TM1) and Intel Thermal Monitor 2 (TM2). These modes are selected by writing values to the Model Specific Registers (MSRs) of the processor. After Automatic mode is enabled, the TCC will activate only when the internal die temperature reaches the maximum allowed value for operation.

Likewise, when Intel Thermal Monitor 2 is enabled, and a high temperature situation exists, the processor will perform an Enhanced Intel SpeedStep technology transition to a lower operating point. When the processor temperature drops below the critical level, the processor will make an Enhanced Intel SpeedStep technology transition to the last requested operating point.

TM1 and TM2 can co-exist within the processor. If both TM1 and TM2 bits are enabled in the auto-throttle MSR, TM2 will take precedence over TM1. However, if TM2 is not sufficient to cool the processor below the maximum operating temperature then TM1 will also activate to help cool down the processor. Intel recommends Thermal Monitor 1 and Thermal Monitor 2 be enabled on the Intel Pentium Dual-Core processor.

If a processor load based Enhanced Intel SpeedStep technology transition (through MSR write) is initiated when an Intel Thermal Monitor 2 period is active, there are two possible results:

1. If the processor load based Enhanced Intel SpeedStep technology transition target frequency is higher than the Intel Thermal Monitor 2 transition based target frequency, the processor load-based transition will be deferred until the Intel Thermal Monitor 2 event has been completed.

2. If the processor load-based Enhanced Intel SpeedStep technology transition target frequency is lower than the Intel Thermal Monitor 2 transition based target frequency, the processor will transition to the processor load-based Enhanced Intel SpeedStep technology target frequency point.


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When Intel Thermal Monitor 1 is enabled while a high temperature situation exists, the clocks will be modulated by alternately turning the clocks off and on at a 50% duty cycle. Cycle times are processor speed dependent and will decrease linearly as processor core frequencies increase. Once the temperature has returned to a non-critical level, modulation ceases and TCC goes inactive. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near the trip point. The duty cycle is factory configured and cannot be modified. Also, automatic mode does not require any additional hardware, software drivers, or interrupt handling routines. Processor performance will be decreased by the same amount as the duty cycle when the TCC is active.

The TCC may also be activated via on-demand mode. If bit 4 of the ACPI Intel Thermal Monitor control register is written to a 1, the TCC will be activated immediately, independent of the processor temperature. When using on-demand mode to activate the TCC, the duty cycle of the clock modulation is programmable via bits 3:1 of the same ACPI Intel Thermal Monitor control register. In automatic mode, the duty cycle is fixed at 50% on, 50% off, however in on-demand mode, the duty cycle can be programmed from 12.5% on/ 87.5% off, to 87.5% on/12.5% off in 12.5% increments. On-demand mode may be used at the same time automatic mode is enabled, however, if the system tries to enable the TCC via on-demand mode at the same time automatic mode is enabled and a high temperature condition exists, automatic mode will take precedence.

An external signal, PROCHOT# (processor hot) is asserted when the processor detects that its temperature is above the thermal trip point. Bus snooping and interrupt latching are also active while the TCC is active.

Besides the thermal sensor and thermal control circuit, the Intel Thermal Monitor also includes one ACPI register, one performance counter register, three Model Specific Registers (MSR), and one I/O pin (PROCHOT#). All are available to monitor and control the state of the Intel Thermal Monitor feature. The Intel Thermal Monitor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#.

Note: PROCHOT# will not be asserted when the processor is in the Stop Grant, Sleep and Deep Sleep low power states (internal clocks stopped), hence the thermal diode reading must be used as a safeguard to maintain the processor junction temperature within maximum specification. If the platform thermal solution is not able to maintain the processor junction temperature within the maximum specification, the system must initiate an orderly shutdown to prevent damage. If the processor enters one of the above low power states with PROCHOT# already asserted, PROCHOT# will remain asserted until the processor exits the low power state and the processor junction temperature drops below the thermal trip point.

If Thermal Monitor automatic mode is disabled, the processor will be operating out of specification. Regardless of enabling the automatic or on-demand modes, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature of approximately 125°C. At this point the THERMTRIP# signal will go active. THERMTRIP# activation is independent of processor activity and does not generate any bus cycles. When THERMTRIP# is asserted, the processor core voltage must be shut down within the time specified in Chapter 3.

5.1.4 Digital Thermal Sensor

The Intel Pentium Dual-Core processor also contains an on die digital thermal sensor that can be read via a MSR (no I/O interface). In a dual core implementation of the processor, each core will have a unique digital thermal sensor whose temperature is accessible via processor MSR. The digital thermal sensor is the preferred method of reading the processor die temperature since it can be located much closer to the hottest portions of the die and can thus more accurately track the die temperature and

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potential activation of processor core clock modulation via the Thermal Monitor. The digital thermal sensor is only valid while the processor is in the normal operating state (C0 state).

Unlike traditional thermal devices, the Digital Thermal sensor will output a temperature relative to the maximum supported operating temperature of the processor (TJ,MAX). It is the responsibility of software to convert the relative temperature to an absolute temperature. The temperature returned by the digital thermal sensor will always be at or below TJ,MAX. Over temperature conditions are detectable via an Out Of Spec status bit. This bit is also part of the Digital Thermal sensor MSR. When this bit is set, the processor is operating out of specification and immediate shutdown of the system should occur. The processor operation and code execution is not guaranteed once the activation of the Out of Spec status bit is set.

The Digital Thermal Sensor (DTS) relative temperature readout corresponds to the Intel Thermal Monitor (TM1/TM2) trigger point. When the DTS indicates maximum processor core temperature has been reached the TM1 or TM2 hardware thermal control mechanism will activate. The DTS and TM1/TM2 temperature may not correspond to the thermal diode reading since the thermal diode is located in a separate portion of the die and thermal gradient between the individual core DTS. Additionally, the thermal gradient from DTS to thermal diode can vary substantially due to changes in processor power, mechanical and thermal attach and software application. The system designer is required to use the DTS to guarantee proper operation of the processor within its temperature operating specifications.

Changes to the temperature can be detected via two programmable thresholds located in the processor MSRs. These thresholds have the capability of generating interrupts via the core's local APIC. Refer to the Intel® Architecture Software Developer's Manual for specific register and programming details

5.1.5 Out of Specification Detection

Overheat detection is performed by monitoring the processor temperature and temperature gradient. This feature is intended for graceful shut down before the THERMTRIP# is activated. If the processor’s TM1 or TM2 are triggered and the temperature remains high, an “Out Of Spec” status and sticky bit are latched in the status MSR register and generates thermal interrupt. PROCHOT# Signal Pin.

An external signal, PROCHOT# (processor hot), is asserted when the processor die temperature has reached its maximum operating temperature. If the Intel Thermal Monitor 1 or Intel Thermal Monitor 2 is enabled (note that the Thermal Monitor 1 or Thermal Monitor 2 must be enabled for the processor to be operating within specification), the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#.

The processor implement a bi-directional PROCHOT# capability to allow system designs to protect various components from over-temperature situations. The PROCHOT# signal is bi-directional in that it can either signal when the processor has reached its maximum operating temperature or be driven from an external source to activate the TCC. The ability to activate the TCC via PROCHOT# can provide a means for thermal protection of system components.

In a dual-core implementation, only a single PROCHOT# pin exists at a package level. When either core's thermal sensor trips, PROCHOT# signal will be driven by the processor package. If only TM1 is enabled, PROCHOT# will be asserted and only the core that is above TCC temperature trip point will have its core clocks modulated. If TM2 is enabled, then regardless of which core(s) are above TCC temperature trip point, both cores will enter the lowest programmed TM2 performance state.


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Note: Intel recommends both Intel Thermal Monitors be enabled.

When PROCHOT# is driven by an external agent, if only TM1 is enabled on both cores, then both processor cores will have their core clocks modulated. If TM2 is enabled on both cores, then both processor core will enter the lowest programmed TM2 performance state.

One application is the thermal protection of voltage regulators (VR). System designers can create a circuit to monitor the VR temperature and activate the TCC when the temperature limit of the VR is reached. By asserting PROCHOT# (pulled-low) and activating the TCC, the VR can cool down as a result of reduced processor power consumption. Bi-directional PROCHOT# can allow VR thermal designs to target maximum sustained current instead of maximum current. Systems should still provide proper cooling for the VR, and rely on bi-directional PROCHOT# only as a backup in case of system cooling failure. The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its TDP. With a properly designed and characterized thermal solution, it is anticipated that bi-directional PROCHOT# would only be asserted for very short periods of time when running the most power intensive applications. An under-designed thermal solution that is not able to prevent excessive assertion of PROCHOT# in the anticipated ambient environment may cause a noticeable performance loss.

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