Intel Itanium Reference Manual - marcel/refs/ia64/itanium2/...4 Intel Itanium 2 Processor Reference...

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Transcript of Intel Itanium Reference Manual - marcel/refs/ia64/itanium2/...4 Intel Itanium 2 Processor Reference...

  • Intel Itanium 2 Processor Reference ManualFor Software Development and Optimization

    May 2004

    Order Number: 251110-003

  • 2 Intel Itanium 2 Processor Reference Manual For Software Development and Optimization

    THIS DOCUMENT IS PROVIDED AS IS WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE.

    Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications.

    Intel may make changes to specifications and product descriptions at any time, without notice.

    Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined. Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

    The Pentium, Itanium and IA-32 architecture processors may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

    Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

    Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725, or by visiting Intel's web site at http://www.intel.com.

    Intel, Itanium, Pentium, and VTune are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.

    Copyright 2002-2004, Intel Corporation. All rights reserved.

    *Other names and brands may be claimed as the property of others.

  • Contents1 About this Manual.............................................................................................................13

    1.1 Overview .............................................................................................................131.2 Contents ..............................................................................................................141.3 Terminology.........................................................................................................141.4 Related Documentation.......................................................................................15

    2 Itanium 2 Processor Enhancements ..............................................................................17

    2.1 Implemented Instructions ....................................................................................172.2 Functional Units and Issue Rules........................................................................172.3 Operation Latencies ............................................................................................172.4 Data Operations ..................................................................................................18

    2.4.1 Data Speculation and the ALAT .............................................................182.4.2 Data Alignment.......................................................................................182.4.3 Control Speculation ................................................................................20

    2.5 Memory Hierarchy ...............................................................................................202.6 Branch Prediction ................................................................................................222.7 Instruction Prefetching.........................................................................................232.8 IA-32 Execution Layer .........................................................................................23

    3 Functional Units and Issue Rules.....................................................................................25

    3.1 Execution Model..................................................................................................253.2 Number and Types of Functional Units ...............................................................253.3 Instruction Slot to Functional Unit Mapping.........................................................26

    3.3.1 Execution Width .....................................................................................283.3.2 Dispersal Rules ......................................................................................293.3.3 Split Issue and Bundle Types.................................................................31

    4 Latencies and Bypasses ..................................................................................................33

    4.1 Control and Data Speculation Penalties..............................................................334.2 Branch Related Latencies and Penalties ............................................................334.3 Latencies for OS Related Instructions.................................................................34

    5 Data Operations ...............................................................................................................37

    5.1 Data Speculation and the ALAT..........................................................................375.1.1 Allocation/Replacement Policy ...............................................................385.1.2 Rules and Special Cases .......................................................................38

    5.2 Speculative and Predicated Loads/Stores ..........................................................385.3 Floating-Point Loads ...........................................................................................405.4 Data Cache Prefetching and Load Hints .............................................................40

    5.4.1 lfetch Implementation .............................................................................405.4.2 Load Temporal Locality Completers.......................................................41

    5.5 Data Alignment....................................................................................................425.6 Write Coalescing .................................................................................................43

    5.6.1 WC Buffer Eviction Conditions ...............................................................435.6.2 WC Buffer Flushing Behavior .................................................................43

    5.7 Register Stack Engine.........................................................................................445.8 FC Instructions ....................................................................................................44

    Intel Itanium 2 Processor Reference Manual For Software Development and Optimization 3

  • 6 Memory Subsystem ......................................................................................................... 45

    6.1 Translation Lookaside Buffers............................................................................. 466.1.1 Instruction TLBs ..................................................................................... 466.1.2 Data TLBs .............................................................................................. 46

    6.2 Hardware Page Walker ....................................................................................... 476.3 Cache Summary ................................................................................................. 486.4 First-Level Instruction Cache .............................................................................. 486.5 Instruction Stream Buffer .................................................................................... 496.6 First-Level Data Cache ....................................................................................... 49

    6.6.1 L1D Loads.............................................................................................. 506.6.2 L1D Stores ............................................................................................. 506.6.3 L1D Load and Store Considerations ...................................................... 516.6.4 L1D Misses ............................................................................................52

    6.7 Second-Level Unified Cache...............................................................................536.7.1 L1D Requests to L2 ...............................................................................546.7.2 L2 OzQ...................................................................................................546.7.3 L2 Cancels ............................................................................................. 566.7.4 L2 Recirculate ........................................................................................ 576.7.5 Memory Ordering ................................................................................... 586.7.6 L2 Instruction Prefetch FIFO ..................................................................586.7.7 L2 Load and Store Considerations......................................................... 59

    6.8 System Bus/L3 Interactions ....................................