AG620 Derivative for low-end Wearable/IoT

AG620 Variant

Intel Requirement OverviewIntel wishes to develop an SoC variant for Wearables & IoT devices, based upon the existing XMM6321/SoFIA 2G/3G platforms AG620Currently a 2-die solution targeting smartphone productsThe AG620 variant to be developed with additional processing powerTargeted A0 by Sept/Oct 2015IA basedCPU SubsystemGPUWIFI/ BT4.2New Audio Subsystem/ New PMUSDIO, Debug?mm?mm

2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#Content Slide: This is usually the most frequently used slide in every presentation.

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Please note you can also press the tab key to create the different levels of bulleted content4Technical Requirements 2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#Section breaker slideUsed for a section heading. You may add a sub heading not exceeding one line also hereSection heading Arial Headings, bold, 34 font size, should not exceed beyond 1 lineSub Head Arial Headings, normal, 18 font size, should not exceed beyond 1 line7Executive Summary This proposal describes the development of the Enhanced AG620-based WiFi/BT4.2 SoC for Intel, targeting wearables & IoT.

Wipro will own the complete spec to GDSII tasksSoC Integration, functional verification, AMS verification for basic bring-upSynthesis, Scan, Physical Design targeting to IMC-65nmWLAN, BT Macro (including RF components) integrationTiming closure and Gate Level simulationsPhysical Verification and GDSII release.

ScheduleWipro will perform scoping for about 6 weeks for Architecture finalization along with Intel team and does initial ramp-up on existing data base.Part of this scoping phase, Intel and Wipro will finalize the project scope, deliverables, schedules and sign-off with a project execution SoW.

2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#Risks, Assumptions, Issues & Dependencies 2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#Wipro : Capability Matrix Area of expertiseCapability Team Size Analog DesignStrength10Analog and Mixed signal Verification & Standard cell characterizationStrength60Analog layoutStrength80IP/SoC DesignStrength100IP/SoC VerificationStrength475DFTStrength25Physical DesignStrength150For RF specific expertise, we have external consultants/partners who will work as integral part of Wipro teamRequired Domain of expertiseWipros experience65nm Analog experienceUMC 65nm IP designs (PLL, LDO, BandGap reference etc)65nm Digital Experience5 Derivative and one Scratch SoC (Spec2GDSII) designs for one of the major European customer in DTV spaceInway FlowWe have worked on clusters at FC level on XG7160, XG736 and SoFIA-LTE2Wipro has done three full chip designs(one Spec2GDSII and 2 derivatives) in InWay flow for Non-Intel projectsQuark Processor ExperienceWipro is working with Intel on SealBeach IoT SoC development End2End Design ExperienceDelivered multiple End2End Designs (Spec2GDSII) up to 28nm nodes 2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#Baseline Design

2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#SoC Preliminary SpecificationsWLAN 11 abg with RFBT 4.2 with RFPMU (with on chip Switches)CPU Intels CPU (mostly LMT 5+ version) with AXI-like NOC as main fabric Audio interfaces Accelerators like GPU with Display interface SDIO interface for NVM StorageStandard Peripherals for communications and interconnections Trace/Debug interfaces (Assume like standard ARMs Coresight)No DDRNo Temp sensors on chip as Chip is not expected to heat up

2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#Design Subsystem Partition DetailsWiFi & BT SubsystemsEach consists of Digital, Analog and RFIntel will provide these 2 as Subsystems for Integration Audio Subsystem, PMU SubsystemWipro needs to integrate Intel-provided Analog, Digital components/IPs to create the subsystemsCPU Subsystem CPU Subsystem will be provided by IntelWipro will integrate this along with NoC, DSP and other Peripherals. 2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#Other Requirements from IntelPower RequirementsDynamic Power target of X WattDeep sleep power target of X WattNo Back Biasing required DVFS No voltage domains~6 Power domains in DigitalEach Subsystem potentially may be in a separate power domainPower gating is required with internal power switch Clock gatingVerificationEnhance the AG620 verification environment as per the new SoC requirementsAMSIntel will provide Verilog-AMS models & verification environment.Analog-Mixed signal simulations to be done by Wipro

2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#Other RequirementsDFTAssume Standard Flow, Standard ATPG, MBIST MBIST wrappers need to be added in the RTL All Analog/RF components will come with their own BIST logic Assume 97% Stuck-at & 80% At-speed coverageBSD might need to be included, assume it is required; however it is part of the IO ring automated flow At-Speed MBIST testing needed Physical DesignTechnology node: IMC 65nm LP INWAY flowFlip chip implementationIP constraints will be provided by IntelWipro needs to define chip level and subsystem constraints as neededCore voltage: 1.1 V, IO Voltage: 2.5V and 1.8V ESD need to be taken care as part of IO ring creation; (Intel will review and approve)

2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#Wipro Technical Proposal 2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#Target SoC Preliminary ArchitectureJTAGSDIOI2CUARTNOCClocksPMU Subsystem WLAN SubsystemWLAN MAC+BBWLAN RADIOTx/Rx BT SubsystemBT BBBTRADIOTx/RXPeripheral SubsystemCPU SubsystemIntel CPU + CacheTimers, WDOG, GICSDIOAccelerator SubsystemDSPGPUHSICUARTI2CSRAMROMCLK/RStAudio SubsystemDACADCI2SInI2SoutEncoderDecoderSPDIFInSPDIFoutHSICSPIDMASPISecuritySubsystem ?

Wipro to IntegrateGeneratedIntelModifyLDOFSMLDODAC 2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#Responsibility MatrixFunctionsOwnerChip level Specifications, architecture, IP Selection, IP Configs and all IPs IntelInputs for STA constraints updates, Sign-off criteria, IO order inputs etcIntelRF, Analog Design & Verification environmentIntelFab, Assembly, Test & Product Engg (ATE testing, char, qualification, production ramp-up etc)IntelPackage Design/SimulationsIntelFW/SW development and Emulation bring up/testing, Silicon bring up/testing, Board designsIntelSubsystem RTL for CPU, Security, WLAN and BT subsystemsIntelSubsystem RTL integration for Peripheral, Audio and Accelerator SubsystemsWiproSoC RTL integration, Testbench updates & verification, GLSWiproAMS VerificationWiproDFT : MBIST updates integration, Scan & WGL patterns;WiproESD, IO Padring, Ballout, Packaging SI/PIWiproStructural Design : Synthesis, Equivalence, STA & timing closure, Floor-plan, P&R, PVWiproGDSII Tape-out, ATE pattern deliveryWiproReviews for Design, Verification, ATPG closure, GDSII sign-offIntel + Wipro 2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#Out of ScopeFollowing are the Out of Scope activities for the current Project: This project does not require any modifications/enhancements to Digital/analog IPs, Verification IPsExceptions : clock/reset and integration glue logicThis project does not require any of the following tasks for Analog/RF IPDesign/layout modificationsDesign verification, Circuit level analog/RF simulationsUpdates to RF/Analog modelsEmulation or FPGA validation (currently kept out of scope)Support beyond GDSII and pattern delivery. Can be included on a T&M basisPackaging analysis/simulationsWipro will however, align on the IO pad ring with Intel package team.Board Design and related activities (currently kept out of scope)Firmware and Software related work (currently kept out of scope)

2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#Design Details and RTL ScopeIP/Subsystem NameHard block?RTL OwnershipRemarks/Structural DetailsCPU SubsystemYesIntel IA based. Assuming a simple core with small cache sizes.WiFi abg SubsystemYesIntel Complete HardMacro delivered by Intel and it Consists of MAC and BaseBand, Analog and RF;Bluetooth4.2 SubsystemYesIntel Complete HardMacro delivered by Intel and it Consists of BaseBand, Analog and RF;NOCNoWiproWill be generated as per system requirements based on Intel provided tools.Audio SubsystemNoWiproNeeds to be integrated using Intel-provided analog & digital components/IPsGPU+DisplayNo?Intel Graphics Specs. Assuming Similar to Vivante-2D Graphics core.DSPYesIntel Tensilica? Assuming very simple DSP.Peripheral Subsystem (SDIO + Standard Serial Peripherals)NoWiproNeeds to be integrated using Intel-provided IPs; List of all IPs?Security SubsystemNoIntel Specs? Do we need a separate subsystem?PMU SubsystemNoWiproNeeds to be integrated using Intel-provided digital and All Analog IPs. PMU specifications depend on power strategyClock/Reset logicNoWiproNeeds to be modified as per system requirements 2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#SoC Design/Integration : DeliverablesRequirement Specification Detailed Architecture documentsFunctional ArchitectureMicro Architecture Debug Architecture Power Architecture All IP RTLs including memory, Analog/RF models, PLL etc models

IntelIntegrated RTLLint, CLP and CDC Reports WiproNote: All deliverables from Intel are expected in the beginning of the projectQC Checks using Intel methodology/Frame workCDC at Subsystem and Top level Lint checks CLP Checks 2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#SoC Verification FlowDesign Requirements/Architecture documentTest Plan Create/UpdateTest Bench & Testcase Development/UpdateCoverage Development/UpdateSimulations, Regressions, Coverage ReviewTiming Simulations with Netlist and SDFCreate/Update TB DesignCreate/Update Coverage Plan 2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#SoC Verification StrategyFollowing Test-benches expected to be provided by IntelBase platform Top level Verification Environment Clock and Rest controller Block level test benchNOC Block level test benchVerification StrategyBlock level verificationSanity verification of the generated NOC using Intel-provided Test benchVerification of the Clock and Rest controller block for the changesSubsystem level verification CPU, WLAN, BT and Security Subsystem level verification is assumed to be owned by Intel Assuming there is no separate test benches required for Audio, Peripheral and Accelerator Subsystems and will be covered as part of the Chip level verification Chip level verificationFunctional coverage based on Architecture/Requirement documentBlock level focused testingSoC Connectivity testing and some amount of performance/latency testing Verification completion Criteria100% Toggle coverage at Top level and Wipro integrated Subsystem level100% functional coverage , Verification report confirming passing of all test cases in the test plan

2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#SoC Verification Testbench DetailsNOC Level Testbench (Intel-provided)Digital Test bench with behavioral models for masters & slavesSet Testbench configurations as per NOC configuration chosenRe-Run available testcases suite to validate sanity operationsTop level TestbenchDigital Test bench with behavioral models for RF/Analog blocksUpdate Testbench as per the Architecture changes using VIPs provided by IntelUpdate the Test cases/Coverage pointsIdentify and port new test cases for various blocks and interfacesFunctional, Concurrency/LatencyBOOT Sims (Basic), DFx, Power , Analog BIST Timing simulations with netlist and SDF for few identified test cases Simulations, Regressions, Bug trackingCoverage Analysis & Closure

2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#Functional Verification Activity DiagramSoC SpecificationsBaselineTest & Design DocumentsCreate SoC Test Plan & Coverage PlanTestbench Design &Coverage Plan UpdateSoC Testbench IntegrationNOC Testbench Configuration Testcase Development & UpdatesTestcase SimulationsTestcase SimulationsCoverage Analysis & ClosurePerformance Testing PlanPerformance Testcase Development with Intels helpTestcase SimulationsResults Analysis & Closure 2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#Verification Deliverables - DigitalSoC Requirement SpecificationBase line SV Verification data base with docs/logs/ reports/waveformsBehavioral models RF/Analog blocksIntel IP and Subsystem level verification database for Reference Review and Signoff of Wipro updated verification planBoot Code for verificationVerification PlansTest-planCoverage PlanUpdated Test-Bench , Modified/Ported Test casesBug trackingCoverage Reports

Intel Wipro 2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#SoC AMS Verification: Scope / FlowTop level Verification AMSSame digital Test bench is expected to be used by AMS Verilog-AMS models provided by Intel for Analog/RF blocks will be usedPort the Subsystem level test cases on AMS for DC scheme, Power-onThe number of such simulations is expected to be small (with run times of 1-2 days for each test case).All RF/Analog IPs are expected to be pre-verified by respective IP teams

Verification completion CriteriaBasic Bring-up with Analog/RF models

2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#AMS Verification : DeliverablesTop level AMS verification environmentSoC Requirement SpecificationVarious Verilog-AMS models for different RF/Analog blocksIP and Subsystem level AMS verification data base for referenceReview and Signoff of Wipro updated verification planAll required VIPsPDK

Intel Verification PlansTest-planCoverage PlanAMS test casesBug trackingCoverage Reports

WiproNote: All deliverables from Intel are expected in the beginning of the project 2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#DFT FlowDesign Requirements/Architecture/Test specUpdate DFT PlanScan and MBIST insertion in the netlist for Partitions and top levelCoverage analysisScan Pin Muxing updates (if needed)RTL updates for DFT(EDT etc)Gate level simulations with/with out SDFATE pattern delivery 2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#DFT Scope/FlowUpdate DFT plan based on Intel Test specifications and Architecture changesDFT Insertion and simulationsWork with RTL team and update the required RTL changes, if any MBIST wrapper generation and integrationScan insertion for the Partitioning blocks & at Top level ATPG coverage analysis and achieve the following SoC level ATPG targetsStuck-at ATPG: 97%At-speed ATPG: 80%IO Test pattern(provided by Intel) simulationsGate Level simulations with and with out SDF for Scan and MBISTSupport STA teams for Test mode timing analysis ATE pattern delivery for Normal MBIST, At-speed MBIST Stuck-at ATPG, At-speed ATPGQC ChecksATPG Warnings/Errors clean up

2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#DFT : DeliverablesTest Specifications Architecture documentAll DFT ready IPs including memory, Analog blocks.All relevant documentationReview and Signoff DFT plan document updated by WiproUpdated DFT approach documentScan insertion logsATPG coverage logs/reportsMBIST simulation logs/reportsATE patterns (WGL / VCD) generated for Stuck-At ATPG, AT-Speed ATPGMBIST, AT-Speed MBISTIO Test pattern, Analog Test patternSimulation logs for tester translated pattern simulations

Intel Wipro 2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#Physical Design: Representative floor planIndicative floorplan shown in next slideThe floorplan will change based on actual blocks, block sizes and block footprints.The relative sizes of the blocks are not accurate and are just estimatesIndicative Placement of decoupling cap and guard-bands are shown.Guard bands will be tied to the appropriate supplyDeep nwell will be used, if available? and as necessary Decoupling cap will be added based on Noise Analysis/Budgetting

2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#Physical Design: Representative floor planWLAN SubsystemWLAN BB+ MACWLAN RADIOTx/Rx BT SubsystemBT BBBTRADIOTx/RXNOCSecuritySubsystem

PMU Subsystem Accelerator SubsystemDSPGPUDMABT supply pinsBT ground pinsBT Substrate pinsWLAN Supply pinsWLAN ground pinsWLAN Substrate pins

JTAGCPU SubsystemTimers, WDOG, GICIntel CPU + CacheSDIOI2CUARTClocksSDIOHSICUARTI2CRAMROMCLOCKSHSICSPISPIDACADCI2SInI2SoutEncoderDecoderSPDIFInSPDIFoutPeripheral subsystemAudio subsystemDecoupling capDecoupling cap : guard bandDecoupleDecoupleDecoupling capDecoupling cap 2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#Physical Design: PartitionsList of Digital Hard Macros provided by Intel

List of Partitions to be hardened (RTL2GDSII) by Wipro

S.NoBlock/Partition1CPU Subsystem2WLAN Subsystem with Analog and RF 3BT Subsystem with Analog and RF4DSPS.NoBlock/Partition1Audio Subsystem2Blocks in accelerator subsystem GPU+Display3Security Subsystem ?4Power Management UnitPartitions to be decided by Based on power strategy, Size of the IP/Subsystem etc 2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#Implementation phase PD Flow Feasibility Phase Specification

Choice of libraryLIB QAInitial SynthesisIO Planning (power/ESD/Package)Floorplaning & power planningPlacement & Timing optCTSIO Die size EstInitial Route (congestion)Implementation Margin s EstimationChoice of PackageImplementation Approach & toolsFeasibility Review Sign offTiming Signoff checkPower analysis/ LEC / LP checks PV checks (DRC/LVS/ERC/Density)PV Fixes / DFM IterationsTiming Signoff checkGDS checks(Macro LVL/ Wafer level Density Checks) GDS CreationTapeout Reviews/ DocumentationBlock & IP View creation Final PhaseTiming Cons modificationsPre Layout STA / LEC/ LP checksFloorplan & Power Plan (Minor Refinements)Placement & Timing optCTSPower analysis/ LEC / LP checks / FP review DFT Aware Synthesis Final PhaseSign-off RCSI Timing & Noise analysis & closurePower Analysis/ LEC / LP checks

Hold Fix With SIPrelim PVECOMock Tapeout Trial PhaseDFT PlanningTiming Cons developmentIO Planning (power / ESD/Package)Floorplan Trials & Power PlanPlacement & Timing optCTSDFT Aware SynthesisPre Layout STA / LEC/ CLPTiming Cons ReviewDie-Package Co-designDie Size /IO Plan ReviewPower analysis / LEC / LP Checks / FP review Post CTS opt(setup)Route & route Opt (setup) Trial PhaseSign-off RCSI Timing & Noise analysis & closurePower analysis/ LEC / LP Checks Hold Fix With SIPV SetupTrial PVPartitioning & timing Budgeting Top Level Timing IterationsTrial Phase reviewPower Intent creationPost CTS opt(setup)Route & route Opt (setup)Top level Timing IterationsIntel Syn/STA/PD/PV Flows will be followed; Appendix slides explain Wipro PD flow, however for this project Wipro will follow Intel flows and hence all the steps explained may not be applicable. 2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#32PD : DeliverablesViews, tech files for EDA tool set for all library components and HardmacrosRTL ( of IPs/Subsystems)Timing SpecIO spec/ESD-SSO guidelinesDetailed Integration guidelines for RF/Analog MacrosTiming/Quality/Power signoff criterionGuidelines/Reference floor plans/relevant scripts/documentationDie size estimations, IO pad ring definitionPnR /floorplan implementationUpdated Timing constraintsSign off check reportsSTA, PV, Power, RF Integration checks Final GDSII, Netlist, spef, sdf Updated PnR scripts, Final DB at each stageChecklist/quality check reports ( any specific lists to be followed for Intel)Intel Wipro 2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#Low power FlowFollowing low power methods will be used in this projectSmall always on Logic with external wake-upPower gating using internal power switchesMulti Voltage (not a requirement for this design)DVFS (Dynamic Voltage Frequency Scaling)Multi-Vt librariesMulti-Channel(poly width) librariesMBR ( MultiBit Registers) ?SW controlled Functional clock gating as part of Clk control unitTool inserted clock gatingLow Power checksLow power Lint at RTL and various Netlist stages using UCF/CPF flowLow Power verification at RTL Few basic Low power test cases to run at Gate level

2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#Schedule & Execution Plan 2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#Project Execution Schedule - TentativeNote: This is an indicative execution schedule. The actual schedules will be finalized at the end of scoping phase.

2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#Resource EstimatesSyn/STA/PD Team split: Out of 6 member peak team estimated for Syn/STA/PD, half of the team members will work on Block level PD and half on Top level PD during peak execution. This might vary based on the number partitions we actually decide. Resource experience Mix

Note: This is an indicative resource estimate. The actual estimates will be finalized at the end of scoping phase. 2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#37Schedule : Key DependenciesThe below table indicates the key Intel handoff points that are required to meet the schedule #KEY DeliverableNo Later than1SoC requirement Specification and SoC Architecture documents (Functional, Debug, Power, Test)T02Base platform complete data base (Design, Verification, AMS, Constraints) with documentation3CPU, WLAN, BT, Security Subsystems along with required Analog/RF IPs with all required documents, views/models4All Digital IPs preliminary release with all required docs, related scripts etc 5IMC-65 LP Libraries, Memories, CPU tool kits, NoC generation kitsT0 + 2 w6EDA tools, Compute farm7All VIPs (for all interfaces) and module level test bench and test cases8Interface Timing Specification, Functional timing specification, IO Order9All Digital IPs Final release with updated docs, related scriptsT0 + 10 w10Initial ROM code release. Final release of Intel owned Hard macrosT0 + 20 w11Verified ROM code releaseT0 + 28 wNote: RF simulation related dependencies need to be updated 2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#38Contract Hire for RF Simulation expertiseWipro propose to have a few contract hires in France for the current RF simulation related activities in this program.

This team will report into the offshore project team

Data base access for the contract hiresThe RF engineers can potentially work from the local Intel offices in France.

2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#39Key RisksRisk DescriptionMitigation PlanRF IPs are including some changes and integrated first time in the SoC Intel is planning testchips which will tapeout before this devices tapeout. However the risk of schedule impact due to RF respin remainsSpecific RF Integration & Simulation skillsWipro to leverage contract hires to define RF integration guidelines in the beginning of the project, perform continuous checks at every stage, and carry out and support the integration/simulation/verification activitiesStringent Die size and power requirements for IoT/Wearable applicationsDefine Physical partitions carefully to reduce the power overheads.Early analysis and estimates on Die size and power to identify potential issues.65LP RF process node is tool slow to meet the timing requirements of the designDuring Trial PD phase, do the required analysis and tune the Synthesis/PD flows as needed to improve the timing for critical blocksIntegration of the LDOs supplying to the various blocks -- IR drop-- Electron Migration-- Cross talk

Obtain maximum resistance/voltage drop for each IP from Intel. Perform IR drop analysis for each block.Obtain current consumption information for all Ips. Power routing width to take care of current density Ensure independent power routing to IP blocks from the LDOs.Integration of Audio subsystem-- ADC & DAC integration

Ensure adequate guardbands and isolation distance from other blocks. Ensure independent power and ground routing to the blocks to reduce crosstalk.Ensure adequate care to reduce capacitive coupling.IR drop analysis to be done. 2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#Key Challenges and Intel support neededCategoryKey ChallengesSupport needed from IntelDesignLegacy IPsIP documentation Walk-thru during initial Ramp-upKey IP integration reviewsAccess to IP teams and Clarifications on need basisVerificationPorting of Subsystems (which itself has own CPUs) / IP test cases to Chip levelLegacy IPs/ VIPs

Issues with 3rd party VIPsHuge number of test cases at Subsystem or IP

Help during ramp-upSubsystem/IP level documentationAccess to complete Subsystem/IP Verif environment Debug support from Subsystem/IP team to finalize the issue/bug seenAccess to IP bug data base Access to 3rd party VIP vendorsDiscuss with Subsystem/IP and Identify the key test cases needed for top level simulations 2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#Key Challenges and Intel support neededCategoryKey ChallengesSupport needed from IntelImplementationStringent Die size and power targets

Meeting DFT coverage targets with multiple analog/RF componentsProvide IP inputs to perform early analysis on Die Size and check for potential risksEnable Discussions with Architect and IP teams to potential change in IP configurations to save areaIntel IP teams help might be needed to potential test case identification to improve the coverage using functional coverage mechanisms RF IntegrationWipro to work with 3rd party RF partnerIntel support needed to enable the data base access to 3rd party RF partner remotelyPeriodic technical reviews

CommonIntel specific flows in different streamsHelp on initial ramp-up for hands-on experience 2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#Assumptions: 1/2No functional changes in IPs /VIPs expected. Assuming no IP level verification and Subsystem verification (including AMS) to be done by WiproAG620 verification environments are available All VIPs, Sequences, other Test-bench components can be reusedSignificant changes needed in Test benchNew SoC Test-bench will involve significant changesMany new test cases might need to be added.Frequency targets are achievable in the chosen technology node.ATPG coverage targets will not involve significant challenges No process/temperature/voltage corner AMS simulations to be doneNo circuit level analog/RF simulations for IPFollowing Response norms are assumedCritical/Blocking issues/Bug fixes in two Business daysNon blocking/ Non-critical issues/Bug fixes in four business daysIntel or 3rd party IP provider will respond to Wipro within 2 working days for any critical issues / bugs found in the supplied IP blocks

2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#Assumptions 2/2No logic retention required. Memories may need retention and assumed Intel memories support retention and no need for additional logic outside the memories.Limited performance simulations are assumed. Performance to be measured is provided by Intel and also relevant subsystem or IP level test cases will be provided by Intel for the same.Total Number of timing corners for timing closure are expected to be handful. No voltage domains; only power domains will be there in the chip. WLAN Subsystem and BT Subsystem are completely verified by Intel including the analog and RF simulations at sub-system level. WLAN Subsystem and BT Subsystem hardmacros delivered by Intel includes digital, Analog and RF components. And it also includes the required bump assignments.PMU does not have CPU and Intel provides the required functional blocks which implements FSM and Analog blocks along with the required digital wrappers for PMU integration. Die size and power targets are achievable with the chosen architecture, IPs, technology node.On-chip bus protocols are assumed same or similar to Standard AXI/AHB/APB.

2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#Relevant Profiles - Analog 2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#Profile: Analog Architect/ConsultantAnalog Architect/consultantQualification: B.E in EC from Univ. of Roorkee (now IIT-Roorkee)Experience in VLSI : 28 YearsAreas of Expertise : Analog & Mixed-signal architecture, Analog circuit Design & Verification, technical project managementExperience Summary Architect for a 16 channel Laser driver ASIC for Silicon Photonics system.Architect for ultra low power FRAM based one wire memory device for silicon ID.Architect and technical lead for a mixed-signal low-frequency near-field telemetry transceiver for medical applications. Key circuits designed: waveform synthesizer using high-speed DAC, LNA, high-gain bandpass filters, analog envelope detectors and an ADC for Rx signal processing in digital domain. Status: first-pass silicon.Worked on 4 port USB3 HUB as analog lead. Responsible for defining regulation scheme and pin out of the family of HUB products . Also defined the modifications required in previous generation PHY to optimize area and power and incorporate USB battery charger signaling protocol.Architected a unique Decision Feedback Equalizer for reducing area and power as part of USB3 PHY designDesigned a high linearity, large bandwidth ( ~1GHz) buffer to drive large capacitive and resistive load. Also designed low noise Bandgap voltage and current reference. These blocks were used in VDSL chipset.Worked on DC to DC converter, 10 bit A/D converter, an on chip oscillator and a differential DAC buffer with post smoothing filter for a Delta Sigma D to A converter. Conceptualized the multi phase DC to DC converter which has capability of boost and buck at the same instant. The linear regulators used for smoothing and regulating the DCDC converter outputs consume as low as 4 uA current while sourcing 4 mA load current in active modeDesign lead for 1394a PHY developmentDesign migration of a 2G Mobile phone chipFull-speed and low-speed USB transceiver IO cellManaged and technically led analog design and layout teams of upto 25 team members 2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#Profile: Analog DesignerAnalog DesignerQualification : B.E. and M.S.E.E. (Analog Design)Experience in Analog VLSI Design : 11yrsArea of Expertise : Analog VLSI Design

Experience Summary

More than 10 years of industry experience in the area of Analog VLSI Design and preliminary experience in RF design. Experienced complete cycle for Bluetooth transceiver IC from circuit design to Si-validation flow in 65nm node.Experience in designing variety of analog blocks ranging from LDOs, VGAs to Poly-phase filter in submicron technology nodes.

AchievementsGPA 4.0/4.0 for M.S.E.E.Got awarded several times for impressive technical contribution.

Tools Experience Summary :Simulators: Cadence ICFB Design tools (version 5.4 and 6.1 OA), SpectreRF, Calibre 2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#MeghRaj48Profile: Analog DesignerAnalog DesignerQualification : M. E. ( Electronics )Experience in VLSI : 08 years 04 monthsArea of Expertise : Analog Circuit Design/VerificationExperience Summary : Analog and Mixed Signal design and verification (8.4 years of experience).Technologies worked on 1um to 28nm CMOS/BiCMOS technologies.Worked on Design and Verification of Voltage Regulators, BGR, DLL, PLL, LVDS, CMOS Analog Buffers, Comparators, Level Shifters, Logic gates, Flip-flops and counters etc.Have experience in circuit design, circuit simulation, behavioral modeling with VerilogA, layout design, LVS, DRC.Coordinated with Reliability Verification & Mixed signal verification team for design validation.Worked with IC layout engineers for fine tuning the requirements for the physical design and post-layout verification.Executed Aging & Burn In testing.Circuit Design and Verification using EDA tools like Cadence Virtuoso (Schematic,XL,ADE, AMS).Experience in OCEAN script for simulation automation.Analog Behavioral Modeling with VerilogA.

Specialized Areas of Expertise : Analog & Mixed signal circuit design and verification. Behavioral modeling.

Tools Experience Summary :Tools : Virtuoso Schematic, Spectre, TIspice, ADExl, SpectreAMS, NCSim and Layout Editor. 2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#Profile: Analog Mixed Signal VerificationAMS verification EngineerQualification : M. Tech ( Electronics)Experience in VLSI : 7.4 years Area of Expertise : Analog and Mixed Signal Verification

Experience Summary Analog Mix Signal verification of Power Management ICs (4.5 Years of Experience)Technologies worked on 180nm, 90nmFunctional verification of Modules such as Power , Charger, USB, AudioExpertise in handling technical coordination with Clients, System understanding, complete Verification database handling for all flowsSpice and Nanosim simulations, Analog to Digital Interface verificationManaging Releases,Client calls, Weekly StatusTest Plan development, Top level test scenariosWorked on Battery charger verification, Audio Tx/Rx Path verification, Power modules such as LDOs/DCDCs/FG/ADCWorked on the mixed signal simulation using co-simulationsPerl Scripting for verif flow automationIBIS Modeling, SPICE Models, TINA Model updates (1.5 Years of Experience)Analog Modeling, Behavioral Modeling

Tools Experience Summary :Tools/Simulators: Spice, Nanosim, Cadence: Ultrasim, NcSim, SIMDE, PSPICE, TINA-TIBasic Specman, Matlab. Perl, VerilogA, Wreal 2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#Qualification: MS by Research in IC design for Communications from IIT, MadrasOverall Experience: ~13 yearsArea of Expertise: Design and verification of ASIC/Embedded based IPs for Digital Communications and DSP using Verilog/VHDL, SystemC, C/C++.Experience Summary:ASIC/FPGA based Design and Verification for Baseband Demodulators (DVB-T, ISDB-T): Pipelined programmable FFT/IFFT processorForward Error Correction codes codecs (Reed-Solomon codes, Convolutional codes)ISDB-T one segment: Low IF block, DQPSK modulator & DQPSK OFDM frameAnalog TV demodulator - Audio part: IF frequency translation, CIC filterFrequency modulation and demodulation with emphasis and de-emphasisPicture quality improvement for LCDs:Color spaces and their inter conversionsSaturation controllerDesign and Verification of Embedded Applications for Sanyo 32-bit Low Power DSP10-band Stereo Audio Graphic Equalizer with pre-amplifier (Fs = 44.1k Hz)Noise CancellerComplex FIR Filter, IIR Lattice filter, IIR ARMA filter, Auto correlation function, Matrix Multiplication, MDCT/IMDCT in the MP3 decoderSpecialized Work Areas: Developing and Implementing algorithms from specification for ASIC and Embedded Applications

Profile : Algorithm/Design Engineer 2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#Sri LakshmiConfidential 2008 Wipro Ltd52Profile of Algorithm/Design Engineer (cont..)Specialized Work Areas: Developing and Implementing algorithms from specification for ASIC and Embedded ApplicationsASIC/ Embedded Applications Development Tools:Synopsys Design Compiler, Designware and Designware I2C Verification IPForte Cynthesizer tool, Mentor Graphics Catapult C toolPowerMill, , Conformal equivalence checking toolCadence Palladium simulation acceleration toolAltera FPGA synthesis, Xlinx ISETarget Complier Technologies IP designer and IP Programmer for LPDSP32 Programming Language: Verilog/ VHDL, SystemC, C/C++, MATLAB/Scilab, Visual BasicScripting Language: PERL 2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#Qualification: BTech in Electronics And Communication from COE TrivandrumOverall Experience: 10+ yearsArea of Expertise: Modem/DSP blocks Design and verification, ASIC synthesis, Linting, Timing analysis. FPGA synthesis. Board testing and debugging Project Summary:Design and bit true testing of baseband blocks like auto/cross correlation, Cannel compensation, frequency error compensation, viterbi decoder, AGC etc for 802.11a/b/g/n modem. Testing and debugging of Hardware on FPGA and ASIC board. Design of SONET data processing and error monitoring blocks for physical layer interface.Design and bit true validation for various Transmit blocks like power measurement and scaling, modulator and control blocks for Flexible RF Interface ASIC.Design GPIO and Interrupt controller and SoC integration of low power sensor hub SoC.Design of digital control FSMs for high frequency Radar block.Design and testing of SPI interface, FIR/IIR filter, and control FSMs for analog sensor ASIC.Design and testing of OTP ROM and boot controller for programmable USB interface SOC.Tools :NCSIM, VCS, Spyglass, Design Compiler, synplify_pro, Xilinx ISE, CVS. Board testing tools like Logic analyzer, Oscilloscope, Spectrum analyzer, VSG, Vector signal analyzer.Programming Language, Protocols: Verilog, VHDLScripting: Perl and Shell scripts(Basics)Profile : Designer with Wireless design experience -1 2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#Ajeesh RadhakrishnaConfidential 2008 Wipro Ltd54Qualification: M. Tech in Digital Electronics from CUSAT, Kochi. B.Tech in ECE from Govt. College of Engineering, ThrissurOverall Experience: ~13+ yearsArea of Expertise: Design, RTL coding, FPGA prototyping, Verification Project Summary: Design, Algorithm modeling and FPGA based implementation of Wireless Modems Implementation and verification of FPGA based IPs for wireless standards.Algorithm modeling in MATLAB and SimulinkDesign and verification of PCS protocols for PCIE, Ethernet and Fiber Channel Design and verification of High speed dividers for PLL targeting PCIePCS PHY.FPGA based prototyping and validation of SOCs having ARM and multiple peripheralsDesign and Implementation of Aux Channel Module for Display port Receiver.Experienced with Virtex-5, StratixIII,Virtex-4,StratixII and CycloneIIExpertise in using debugging tools - Chipscope, Signal Tap and Logic AnalyzerTools :Synplify Pro, Quartus, ISE, ,Libero, ModelSim, Design Compiler, Spyglass, VCS, Active-HDL, MATLAB, Clearcase, CVSProgramming Language, Protocols: C, Verilog, VHDL and basic knowledge in SV PCS Protocols, Wireless Modems, Display port, FPGA prototypingScripting: Perl scripting (Basic Knowledge)Profile : Designer with Wireless design experience -2 2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#Jaison Martin P J Confidential 2008 Wipro Ltd55Qualification: BTech in Electrical and Electronics Engineering from Mahatma Gandhi UniversityOverall Experience: 7 yearsArea of Expertise: Verilog, VHDL, familiar with C, on board debugging and validation of FPGA/ASIC, AHB and APB bus protocols, familiar with lab equipments like Logic analyzer and Spectrum analyzer, RTL coding of : digital filters, CORDIC, peak detection and signal clipping.Project Summary: Worked on RTL coding of up-sampling/down-sampling using FIR filters, up-conversion and down conversion using CORDIC, signal combining and peak clipping for a Baseband-transmitter interface chip that handles GSM, LTE and WCDMA carriers.AMBA AHB assertions coding for Verification IP development.FPGA/ASIC Wireless LAN IP system board debuggingWorked on Perl scripts that identify the CMOS connected to high voltage inside the netlist.Automating the test environment and creating GUI using Tcl/Tk for 802.11n WLAN MAC and PHY.Worked on automated RF characterization environment using Python for 802.11 b Wireless LANTools :NcSim, vcs, spyglass, dc_compiler. Programming Language, Protocols: Verilog, VHDL, AMBA Scripting: Shell, Perl, Tcl and PythonProfile : Designer with Wireless Design experience -3 2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#Clinston P CConfidential 2008 Wipro Ltd56Qualification: M.Tech VLSI Design IIITM, GwaliorB.Tech - Electronics and Communication engineering JNTU, HyderabadOverall Experience: 8 yearsArea of Expertise: ASIC/SOC verification, IP Verification, System Verilog, UVM, VMM, AHB, AXI.Project Summary: Design and Development of VMM Compliant Verification environment for verification of a highly-integrated RF baseband SoC ASIC for Mobile Chip Vendors multi-radio base stations which supports GSM, LTE and WCDMADevelopmed UVM compliant verification suite for verification of control block and Skyblue network of a Layerscape SoC.Have contributed towards verification of QorIQ SoC using SVBCL language. Have contributed towards verification of Designware - Ethernet IPs - GMAC and XGMAC.Design and Development of AHB VIP.Have been contributing as technical lead for a team of 14 members which have successfully completed verification of 4 SoCs in collaboration with customer teams.Tools :VCS, DVE, NcSim, Debussy. Programming Language, Protocols: C, Verilog, System Verilog, AHB, AXI, Ethernet.Scripting: PerlProfile : Verification Engineer with Wireless experience 2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#FasiConfidential 2008 Wipro Ltd57Thank you 2015 WIPRO LTD | WWW.WIPRO.COM | CONFIDENTIAL#Thank you slideThank You font size 30, Arial HeadingsName & Designation font size 18, Arial HeadingsYour/contact email id font size 18, Arial Headings58