System-Level Thermal Modeling for 3D Circuits: Characterization with a 65nm Memory-on-Logic

Circuit

Cristiano Santos1,3, Pascal Vivet1, Denis Dutoit1, Philippe Garrault2, Nicolas Peltier2, Ricardo Reis3

1CEA-Leti, Grenoble, France 2DOCEA Power Inc., Moirans, France

3UFRGS, Porto Alegre, Brazil

Abstract— Considering the effects of thinned silicon dies and structures like TSVs and µ-bumps is essential for accurate thermal analysis of vertically integrated circuits. This paper presents an innovative compact thermal modeling approach for 3D ICs targeting system-level thermal analysis. This method uses material homogenization and formal reduction techniques for model simplification. It enables taking into account the microscopic structures required for 3D integration while keeping the model complexity affordable for fast simulations. A complete system including a packaged 65nm memory-on-logic circuit, socket and board has been modeled using the proposed thermal modeling approach. Power dissipation hot spots are emulated in the 3D circuit by using a set of resistive heaters while temperature is monitored using integrated thermal sensors. Simulation results from both steady-state and transient analyses show the thermal model is able to capture the hot spot effects with fast simulation times. Thermal data extracted from the 3D circuit demonstrate that simulation fits the thermal transient response and that steady-state analysis for various power profiles presents a worst case temperature error lower than 12% and an average error of 4.2%.

Keywords—thermal modeling; 3DIC; material homogenization; characterization; temperature; CTM.

I. INTRODUCTION Heat dissipation is assumed to be one of the major

challenges in the promising 3D integration technology due to its higher power density and reduced heat dissipation properties when compared to a traditional single die fabrication process [3]. Individual dies are aggressively thinned down and stacked on top of each other, resulting in a higher thermal resistance caused by the reduced lateral heat spreading capacity of the silicon dies and the poorly conductive adhesive materials used to bond them together. Several techniques have been proposed to address the thermal issue at different design stages, ranging from temperature-aware task allocation for multiprocessors at software level [4] to insertion of dummy thermal vias at the layout level [5]. In this scenario, reliable models which are able to capture the effects of the structures existent in 3D technology on thermal simulations play an important role to enable both early stage design decisions and accurate thermal analysis. PCB, package and silicon die structures are all thermally coupled while exhibiting very different length scales,

hence considering individualized details is still a challenge for efficient system-level thermal analysis. Accounting for every TSV, µ-bump and solder ball results in a complex model and time consuming simulations while simplistically averaging material thermal conductivity for the whole layer may imply on spatial accuracy loss and thus fail to detect hot spots.

Various thermal modeling techniques can be found in literature for different abstraction levels. Fine grain [7] and finite element modeling (FEM) approaches [8][9][13] present good accuracy when compared to experimental data, although they are time consuming methods and thus not suitable for system-level simulations. The use of compact thermal models (CTM) is a good tradeoff between accuracy and computational efficiency for early design stage analysis [11][12][15]. However, most of the proposed CTMs fail to address one of the following issues:

• Board and package details should be properly modeled along with silicon device. Oversimplified board and package modeling may place considerable importance on the heat dissipation properties of the system. Besides that, it is needed to account for the impact on the silicon die caused by the power dissipation of other components mounted on the same PCB.

• In addition to the die stacking information, other technology integration structures required for 3D such as TSVs and copper pillars should be properly considered. Those structures usually have heterogeneous distribution thus resulting in anisotropic heat dissipation properties of the hosting layers.

The modeling approach described in this paper takes into account both macroscopic board and package details and microscopic structures required for 3D integration while keeping the thermal model simple enough to be used for fast thermal analysis. This modeling approach was validated by using DOCEA Power™ [2] tools for system-level thermal simulations and experimental data from a fabricated 3D test chip with integrated heaters and thermal sensor. Section II of this paper describes the CTM generation approach and the recommended usage flow for 3D integrated circuits. Characteristics of the fabricated memory-on-logic test chip and details of the implemented thermal model is show in section

III. Comparisons between simulation results and measurement data are discussed in section III.C and some conclusions are finally presented in section V.

II. SYSTEM-LEVEL THERMAL MODELING FOR 3D ICS DOCEA AceThermalModeler™ tool uses a generic

thermal modeling approach to generate a compact thermal model for both static and transient temperature simulations. This CTM is built based on a realistic physical representation of the circuit containing geometry dimensions and material properties of the die, package and PCB structures. Heat transfer is modeled via full 3D heat diffusion in solid materials and no assumption is made on the heat flow paths. This approach supports materials with isotropic and anisotropic thermal conductivity. Convective heat transfer on the boundaries of the system is approximated by using user-defined heat transfer coefficients on its surfaces. When an extraction is requested, a meshing of the entire system is performed in order to obtain an electrically equivalent representation. Using a classical numerical analysis approach, it consists in discretizing the heat transfer partial differential equation system on a grid.

The innovative contribution of this modeling approach relies on two techniques for modeling simplification: material homogenization and model size reduction. These techniques enable a large reduction in terms of node count: one order of magnitude for homogenization (typically 1 million to 100 K nodes), and three orders of magnitude for model reduction (typically 100K nodes to 100 nodes). These two techniques allow maintaining model accuracy while reducing simulation time targeting system-level exploration. These two methods will be described as follows.

A. Material Homogenization for 3D Objects Material homogenization consists in calculating the

equivalent anisotropic thermal properties of a heterogeneous layer containing multiple geometries made of multiple materials [10]. Structures like TSVs and µ-bumps have typically a heterogeneous distribution thus causing localized areas with anisotropic heat dissipation properties. While a conventional mesher would output some million nodes for the complete system, the proposed homogenization methodology results in only some thousands of nodes. In order to achieve such reduction, AceThermalModeler™ merges all selected geometries and calculates the equivalent thermal conductivity and thermal capacitance for the specified areas. This method supposes a regular distribution of the selected geometries, as show in Fig. 1.

Merged areas aftermaterial homogenization

Fig. 1. Illustration of the material homogenization approach for specified areas.

Properly selecting the size and placement of those homogenization areas is important to keep the spatial resolution of the generated CTM. This material homogenization approach allows considering the effects of fine grain structures on local heat dissipation properties while keeping model complexity affordable for system-level simulations.

B. Model Reduction The proposed reduction technique is based on Taylor

expansion of thermal transfer functions. The main advantage of this reduction technique compared to a mesh simplification method is to preserve the relevant details of the original mesh for accurate dynamic response analysis. In fact, the obtained reduced model allows decreasing the simulation time by several orders of magnitude. For example, if we consider a typical original model of 100K nodes, the reduced model will have only a few hundred nodes. Such reduced model enables a simulation time step around 1ms which offers the possibility of running complex scenarios instead of evaluating only steady-state temperature or considering only single step functions. Running complex scenarios open new perspectives such as exploring multiple thermal and power management strategies at system-level.

C. Modeling Flow

Fig. 2. CTM generation flow for 3D ICs using AceThermalModeler™.

Fig. 2 shows the recommended usage flow for CTM generation of 3D ICs using AceThermalModelerTM (ATM). After setting thermal properties for essential materials like copper, epoxy and aluminum, the material homogenization procedure is used to calculate the equivalent thermal properties of elementary structures which are made of multiple stacked materials, such as the package substrate and µ-bumps. Some of those elementary structures may be instantiated several times during the detailed physical/geometry representation of the system, hence keeping them simple from the beginning helps to reduce the time required for CTM generation. Power sources may be defined for every PCB component or silicon IP over the corresponding layer while heat transfer areas and heat

transfer coefficients should be defined on the boundaries of the system. Those heat transfer areas are not limited to the top and bottom surfaces since there is no restriction to the heat flow paths in AceThermalmodeler™.

Once the required input data are properly set, some areas including matrixes of TSVs, copper pillars, C4-bumps and solder balls are defined to go through material homogenization, which is now used to reduce model complexity. A detailed thermal RC representation of the system is extracted before applying the model reduction technique. Finally, the final compact thermal model is generated.

III. MEMORY-ON-LOGIC 3D IC TEST CHIP The proposed thermal modeling flow for 3D has been

exercised on a real 3D circuit. The main objective of the work is to correlate the proposed thermal model with thermal measurement data. Fig. 3 illustrates the system used for thermal characterization which includes a packaged 3D test chip, a small PCB interposer, a socket with a heat sink mounted on a large PCB. The packaged 3D test chip is a WideIO memory-on-logic 3D circuit where the dies are stacked in a face-to-back configuration and are connected through TSVs and µ-bumps. The SoC logic die implements a WIOMING circuit and is only 80um thick to accommodate the integrated TSVs. Table I has additional technology and circuit information.

TABLE I. TECHNOLOGY AND CIRCUIT CHARACTERISTICS

Technology process 65nm Stacking configuration Face-to-back Logic die size 8.5mm x 8.5mm Memory die size 7.8mm x 8.0mm # TSVs (diam.) 1016 (10um) # µ-bumps (diam.) 1042 (20um) # C4-bumps (diam.) 985 (55um) # Package solder balls (diam.) 581 (250um) # PCB interposer solder balls (diam.) 388 (760um) # Socket solder balls (diam.) 388 (760um)

Fig. 3. System including packaged memory-on-logic 3D circuit, PCB interposer, circuit socket and PCB.

A. 3D IC Architecture The WIOMING circuit [1] is based on an asynchronous

Network-on-Chip, including various IP units, and is instrumented with eight resistive heaters to emulate hot spot power dissipation. Depicted in Fig. 4, the WIOMING circuit contains:

• Four memory controllers in the center, one per WideIO memory channel, plus the corresponding TSV and µ-bump matrixes to connect to a WideIO compatible DRAM memory. Each memory controller integrates one heater and one thermal sensor (C1 to C4).

• Four heaters and three thermal sensors in the bottom left corner (BL1 to BL4) to emulate a quad-core processor (such as an ARM Cortex A9, for instance).

The thermal heaters are made of poly resistance and can dissipate up to 1W each. Each heater is independently controlled on the board via embedded software, while integrated thermal sensors are monitored in real time. Thermal sensor accuracy is ±1°C within the calibration temperature range (room temperature @ 27°C), but it has lower accuracy of up to ±4°C at 100°C. Sensor resolution is 1°C for the entire temperature range.

Fig. 4. Floorplanning of the WIOMING circuit which is instrumented with 4 heaters and 4 thermal sensors in the center area (C1-C4), one per wideIO memory channell, and 4 heaters and 3 thermal sensor in the bottom-left corner (BL1-BL4).

B. 3D IC Thermal Model All the steps to generate the CTM for this board-package-

circuit system are fully automated by Python scripts. A simplified view of the detailed physical representation of the system is shown in Fig. 5 with details of the packaged test chip in Fig. 6.

Fig. 5. 3D view of the physical representation of the system.

Fig. 6. Details of the packaged 3D circuit in AceThermalModeler™.

Initially, the physical representation includes every structure of the Table I, therefore resulting in more than 6k geometries, where half of them are associated to structures required for 3D integration. After homogenization the number of geometries in the physical representation is reduced by almost two orders of magnitude, as presented in Table II, while the number of defined materials increases due to the resulting homogenized anisotropic materials. The model reduction technique dramatically decreases the number of extracted nodes, hence resulting in a highly compacted thermal model.

TABLE II. THERMAL MODEL GENERATION RESULTS

System physical representation Before

homogenization After

homogenization After

reduction # geometries +6k 71 -- # defined materials 19 40 -- # extracted nodes 18 million 200k 330

C. Power Modeling DOCEA Aceplorer™ tool [2] is used for running coupled

power and thermal simulations considering the generated CTM. Every power source defined in the CTM should have its power consumption behavior modeled in Aceplorer™, not only those at the silicon level but also components and ICs mounted on the board should be properly considered. Neglecting power sources which are outside the packaged circuit may severely impact the thermal simulation results. The complete list of power devices considered in the modeled system includes silicon IPs such as the ARM core and the memory controllers, the WideIO compatible DRAM memory, heaters and thermal sensor used for temperature characterization, which are in the packaged 3D circuit. It also includes a FPGA and some memory and peripheral ICs at the board level.

IV. EXPERIMENTAL RESULTS The memory-on-logic circuit has been fabricated, tested

and proved functional for the 3D memory communication scheme in all the measured temperature ranges. (see [1] for detailed WideIO memory transfer bandwidth and energy efficiency results). A board has been developed including embedded software for thermal measurements using the thermal heaters and temperature sensors. The measured temperature data is used for comparisons with simulation results for steady-state and transient analyses. Those analyses consider a total of 6 power scenarios to account for hot spot and distributed power dissipation over the silicon area. Each power scenario corresponds to a specific set of active heaters, as described in Table III, with six power density levels for each heater (106mW/level). All measurements on the application

board have been performed at room temperature without any kind of forced convection.

TABLE III. POWER DISSIPATION SCENARIOS

Scenario Active heaters a

Max power C1 C2 C3 C4 BL1 BL2 BL3 BL4 1 1.27W 2 2.54W 3 0.64W 4 2.54W 5 1.91W 6 1.91W

a. Placement of the heaters is shown in Fig. 4

A. Steady-State Analysis Fig. 7 shows steady-state simulation and measurement

results for power scenario 4 which has four active heaters in the bottom-left corner of the logic die. This graph indicates the generated CTM is able to capture the spatial temperature distribution where the points closer to the hot spot have a higher peak temperature. Simulation results present a linear relation between power dissipation and temperature increase. Moreover, measurement data include the effects of the sensor resolution and lower sensor accuracy at higher temperatures but also accounts for the temperature dependency of the material thermal properties.

Fig. 8 shows the difference in steady-state temperature between simulation and measurement results computed for all power scenarios in Table III with an average error of 4.22% and a worst case error lower than 12%. It is again important to note that the 1°C sensor resolution introduces a considerable uncertainty for the measurements at low temperature and may correspond up to 7% of the error for the measured temperature range. Besides that, the CTM was generated using nominal values for the material properties and geometry dimensions, therefore any deviation from those values in the real circuit will also introduce some error to the simulation results.

Fig. 7. Simulation results (solid lines) and measurement results (dashed lines) for steady-state analysis with multiple power densities. Indicated distance is the average distance from sensor to the active heaters in power scenario 4.

Fig. 8. Steady-state analysis error (min/max/avg) for all power scenarios in Table III for each thermal sensor.

B. Time Response The transient temperature responses of the sensor BL2 for

two power scenarios with different average distance from the active heaters are shown in Fig. 9 and Fig. 10.

Fig. 9. Transient temperature response for sensor BL2 which has an average distance of 3.8mm from active heaters in power scenario 2.

Fig. 10. Transient temperature response for sensor BL2 which has an average distance of 1.0mm from active heaters in power scenario 4.

In order to accommodate the effects of the heating of the package, socket and PCB, the simulation step was selected to be much longer than the thermal time constant at this sensor for these power profiles. It is possible to see the evolution of the simulated temperature is in agreement with measurement data, although the same temperature offset present in the steady-state analysis can be noticed. The difference in the measured temperature for the same power level, which can be observed on the mirrored steps of a same power scenario, are also related to the sensor accuracy and sensor resolution issues.

C. Tool Performance Computation time for different steps of the CTM generation

flow and thermal simulations can be found in Table IV. The most time consuming step required for material homogenization is highly dependent on the number of geometries and areas selected to go through this step, exposing a tradeoff between desired spatial resolution and resulting CPU time. However, this step only needs to be done when there is a change in the concerned geometries, otherwise the CTM generation approach can benefit from reusing previously homogenized data. Model reduction is an optional step during CTM generation which proves to be worth the extra time.

TABLE IV. TOOL PERFORMANCE RESULTS (RUNNING ON A INTEL® CORE™ I3 CPU MACHINE)

CTM generation Material homogenization 1h27m09s Thermal RC extraction 4m27s Model reduction 14m38s

Simulation Before model

reduction After model

reduction Steady-state analysis b 213s 26ms Transient analysis b 213s 12ms

b. Per simulation time step.

Each power dissipation scenario presented in Table III takes approximately 1100 simulation steps to complete in a time response simulation with resolution lower than 1°C. It means that before model reduction each simulation takes more than 65 hours to complete while it takes only 13.2s after model reduction. Since steady-state analysis requires only 2 steps to complete, the small overhead for simulation setup causes the calculated simulation step after model reduction to be longer than one calculated for transient analysis.

V. CONCLUSION This paper presents the comparison between simulation and

characterization temperature data for a system including 3D memory-on-logic test chip. The thermal model used in this work is able to take into account the microscopic structures required for 3D integration like TSVs and copper pillars at the same time macroscopic details of the board and package are not neglected or oversimplified. Material homogenization and formal model reduction techniques are employed to keep the model node count typically at a few hundred nodes. The demonstrated computational performance of the generated compact thermal model makes this modeling approach very effective for system-level thermal simulations.

Results of the steady-state analysis show an average error of 4.22% while the worst-case error is lower than 12%. This analysis also indicates the CTM is able to properly capture the spatial temperature distribution and thus account for hot spot effects during thermal analysis. A more detailed study on the effectiveness of the material homogenization technique is required, though. The evolution of the simulated temperature over time is in good agreement with characterization as demonstrated by the transient analysis. The existing difference between simulation and measurement data, however, exposes the need of a parameter sensitivity or an automated min/max thermal analysis. Considering only nominal data during thermal simulation is not realistic since it does not account for the process variability of modern integration technology nodes. It is also suggested to improve the characterization setup to mitigate the undesired effects of sensor accuracy and resolution, thus increasing the comparison reliability.

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