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  • ®®

    * Other brands and names may be claimed as the property of others. Copyright © 2002 Intel Corporation. All rights reserved.

    Intel® Compilers and Libraries for Itanium® Architecture

    Intel® Compilers and Libraries for Itanium® Architecture

    Intel, Itanium, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States or other countries

    Heinz Bast Heinz.Bast@Intel.com Intel Software Enabling Group EMEA

  • ®® 2 Copyright © 2002 Intel Corporation. All rights reserved.* Other brands and names may be claimed as the property of others.

    Intel® Software Development Products

  • ®® 3 Copyright © 2002 Intel Corporation. All rights reserved.* Other brands and names may be claimed as the property of others.

    Libraries

    Development Tools RoadmapDevelopment Tools Roadmap Products Q4 ‘04 Q1 ‘05 Q2 ’05 2H '05 2006

    Compilers

    Threading Tools Threading Tools 2.1 (Linux RDC)

    Wabash (Native Linux)

    Cluster Tools

    Trace Analyzer & Trace Collector 4.0

    Intel Cluster Toolkit 1.0

    C++ & Ftn 8.1

    C++ for Win CE.NET 1.2 C++ Tool Suite 1.2

    WinCE .NET 2.0

    eIA MV CGE 8.1

    eIA QNX 8.1 eIA QNX/ MV 9.0

    C++ Tool Suite 2.0

    C++ & Ftn 9.0

    MKL 8.0

    Cluster MKL 8.0

    VTune™ Performance

    Analyzers

    VTune™ 7.2

    VTune™ Linux *2.0 VTune™ Linux 3.0

    Eclipse GUI

    VTune™ Update Xscale™ (Windows*)

    Intel Cluster ToolKit 1.0

    EM64T Support

    Eclipse* 2.1.3 Additional

    MKL 7.2

    Trace Collector 5.0

    Mobile Platform SDK 1.0

    VTune™ 7.2

    VTune Linux 3.1

    VTune7.3

    VTune Linux 4.0

    PCA MV CEE ISV

    C++ & Ftn “NR” C++ Bi-Endian

    Threading Tools 2.1

    OXL 1.0

    MKL 7.2

    IPP 4.1

    Cluster MKL 7.2

    VTune 8.0

    Data Collector for CE5.0, next gen. Windows Mobile

    Cluster MKL 7.2

    C++ & Ftn 8.1

    Eclipse* 3.0

    ITT 2.2

    IPP 5.0

    OXL

    MPI Library 1.0

    Trace Analyzer 6.0 (Mosel) Trace Collector 6.0

  • ®® 4 Copyright © 2002 Intel Corporation. All rights reserved.* Other brands and names may be claimed as the property of others.

    The Intel® Compiler Family Easiest Way to take advantage of Intel Architecture

    The Intel® Compiler Family Easiest Way to take advantage of Intel Architecture

    Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States or other countries

    iecWindows / EFI Byte Code (EBC) Virtual Machine

    IA32 and Itanium®

    C

    Name / Name since 8.0 release

    OS/PlatformArchitectureLanguage

    ccxsccePlatform Builder for Win CE .NET*

    ccxscceMicrosoft eMbedded Visual C++Xscale™

    efc→ ifortLinux*

    Efl → ifortWindows*Itanium®

    Ifc → ifortLinux*

    ifl → ifortWindows*IA32Fortran

    eccLinux*

    eclWindows*Itanium®

    icc → eccLinux*

    iclWindows*IA32C/C++

  • ®® 5 Copyright © 2002 Intel Corporation. All rights reserved.* Other brands and names may be claimed as the property of others.

    EPIC Architecture PrinciplesEPIC Architecture Principles 1. “The compiler should play the key role in designing

    the plan of execution, and the architecture should provide the requisite support for it to do so successfully

    2. The Architecture should provide features that assist the compiler in exploiting ILP

    3. The Architecture should provide mechanisms to communicate the compiler’s plan of execution to the hardware.”

    Schlansker, Michael S. and Rau, B. Ramakrishna (HP

    1. “The compiler should play the key role in designing the plan of execution, and the architecture should provide the requisite support for it to do so successfully

    2. The Architecture should provide features that assist the compiler in exploiting ILP

    3. The Architecture should provide mechanisms to communicate the compiler’s plan of execution to the hardware.”

    Schlansker, Michael S. and Rau, B. Ramakrishna (HP

    The Intel logo is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States or other countries

    From: Schlansker et. al (HP Labs) “EPIC: Explicitly Parallel Instruction Computing” Computer, Vol 33 Issue: 2 , Feb. 2000 pp 37-45

  • ®® 6 Copyright © 2002 Intel Corporation. All rights reserved.* Other brands and names may be claimed as the property of others.

    Intel Compiler ArchitectureIntel Compiler Architecture

    Profiler

    C++ Front End

    Interprocedural analysis and optimizations: inlining, constant prop, whole program detect, mod/ref, points-to

    Loop optimizations: data deps, prefetch, vectorizer, unroll/interchange/fusion/dist, auto-parallel/OpenMP

    Global scalar optimizations: partial redundancy elim, dead store elim, strength reduction, dead code elim

    Code generation: predication, software pipelining, global scheduling, register allocation, code generation

    FORTRAN 95 Front End

    Disambiguation: types, array,

    pointer, structure, directives

  • ®® 7 Copyright © 2002 Intel Corporation. All rights reserved.* Other brands and names may be claimed as the property of others.

    Generic FeaturesGeneric Features • Compatibility to standards ( ANSI C, C99,

    Fortran95, Fortran2003) • Compatibility to leading open-source tools (

    ICC vs. GCC, IDB vs GBD) • OpenMP 2.0 support • Automatic parallelization • Profile-guided optimization • Multi-file interprocedural optimization • Support of other Intel® tools

    – E.g –tcheck for Threading Tools

    • Compatibility to standards ( ANSI C, C99, Fortran95, Fortran2003)

    • Compatibility to leading open-source tools ( ICC vs. GCC, IDB vs GBD)

    • OpenMP 2.0 support • Automatic parallelization • Profile-guided optimization • Multi-file interprocedural optimization • Support of other Intel® tools

    – E.g –tcheck for Threading Tools

  • ®® 8 Copyright © 2002 Intel Corporation. All rights reserved.* Other brands and names may be claimed as the property of others.

    Generic Features ( cont. )Generic Features ( cont. ) • Support for gprof (-p switch) • Inlined math intrinsics • Code Coverage Tool • Test Prioritization Tool

    • Support for gprof (-p switch) • Inlined math intrinsics • Code Coverage Tool • Test Prioritization Tool

  • ®® 9 Copyright © 2002 Intel Corporation. All rights reserved.* Other brands and names may be claimed as the property of others.

    Target Processor SelectionTarget Processor Selection

    Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States or other countries

    • Itanium® and Itanium®-2 processor – tpp1 ( Linux ) for Itanium® – tpp2 (Linux) for Itanium®-2 – Itanium-2 now default ( since 7.0 release )

    • Current “Madison” Processor – No compiler changes – Same as for Itanium®-2

    • Be prepared for new options for future Itanium processors ( Montecito, Tukwila)

    • Itanium® and Itanium®-2 processor – tpp1 ( Linux ) for Itanium® – tpp2 (Linux) for Itanium®-2 – Itanium-2 now default ( since 7.0 release )

    • Current “Madison” Processor – No compiler changes – Same as for Itanium®-2

    • Be prepared for new options for future Itanium processors ( Montecito, Tukwila)

  • ®® 10 Copyright © 2002 Intel Corporation. All rights reserved.* Other brands and names may be claimed as the property of others.

    Target Selection is relevant Target Selection is relevant

    Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States or other countries

    int csum(double a[], double b[], double c[], double x, int max) for (i=0; i

  • ®® 11 Copyright © 2002 Intel Corporation. All rights reserved.* Other brands and names may be claimed as the property of others.

    Some General SwitchesSome General Switches

    -openmpOpenMP 2.0 support

    -fno-fnaliasAssume no aliasing

    -fastAggressive optimizations ( == -O3 –ipo –static)

    -SGenerate assembly files

    -parallelAutomatic parallelization for OpenMP threading

    -gCreate symbols for debugging

    -O3High-level optimizer, incl. prefetch, unroll, -FTZ

    -O2Optimize for speed (default), includes SWP

    -O1Optimize for speed (no code size increase), no SWP

    -O0Disable optimization

    Itanium and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States or other countries

  • ®® 12 Copyright © 2002 Intel Corporation. All rights reserved.* Other brands and names may be claimed as the property of others.

    High-level Optimizer OverviewHigh-level Optimizer Overview

    • Data dependence analysis – Array subscript analysis

    • Eliminating memory operations – Scalar replacement, unroll-and-jam, register blocking

    • Cache optimizations – Loop interchange, fusion, distribution, blocking, data

    layout • Overlapping memory latency

    – Data prefetch • Ins