Intel 631xESB/632xESB I/O Controller Hub€¦ · · 2015-09-25standalone microcontroller with...

Document Number: 313082-001

Intel 631xESB/632xESB I/O Controller HubDatasheet

May 2006

2 Intel 631xESB/632xESB I/O Controller Hub Datasheet

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Intel 631xESB/632xESB I/O Controller Hub Datasheet 3

Intel 631xESB/632xESB I/O Controller Hub Features

Interfaces to Memory Controller Hub Enterprise South Bridge Interface: 1 GB/s

each direction, full duplex, transparent to software

x4/x8 PCI Express* interfacePCI Express Root Port

4 PCI Express root ports Fully PCI Express 1.0a compliant Can be statically configured as 4x1, or 1x4 Support for full 2.5 Gb/s bandwidth in each

direction Module-based Hot-Plug supported

PCI Express Downstream Ports Two x4 or one x8 PCI Express 1.0a compliant

ports Hot-Plug support for Evolutionary (card-edge)

form factorPCI Bus Interface

Supports PCI Rev 2.3 Specification at 33 MHz Seven available PCI REQ/GNT pairs Support for 64-bit addressing on PCI using

DAC protocolPCI/PCI-X* Bus Interface

Configurable as 33- or 66- MHz PCI, 66-, 100-, or 133-MHz PCI-X

Supports Standard Hot-Plug Controller 1.0 Specification

Integrated Serial ATA Host Controller Independent DMA operation on six ports Data transfer rates up to 3.0 Gb/s (300 MB/s) Tri-state modes to enable swap bay

Integrated IDE Controller Independent timing of up to two drives Ultra ATA/100/66/33, BMIDE and PIO modes

USB 2.0 Includes four UHCI Host Controllers,

increasing the number of external ports to eight

Includes one EHCI Host Controller that supports all eight ports

Includes one USB 2.0 High-speed Debug Port Supports wake-up from sleeping states S1-S5 Supports legacy Keyboard/Mouse software

High Definition Audio Interface Independent Bus Master logic for eight

general purpose streams: four input and four output

Support three external Codecs Supports variable length stream slots Supports 8 channel, 24-bit samples, 192 kHz

sample rate output Supports an array of up to six microphone

inputs Supports memory-based command/response

transport Provides cadence for non-48 kHz sampling

output

AC-Link for Audio and Telephony CODECs Support for three AC 97 2.3 codecs. Independent Bus Master logic for 8 channels

(PCM In/Out, PCM 2 In, Mic 1 Input, Mic 2 Input, Modem In/Out, S/PDIF Out)

Support for up to six channels of PCM audio output (full AC3 decode)

Timers Based on 82C54 System timer, Refresh request, speaker tone

outputPower Management Logic

ACPI 2.0 compliant ACPI-defined power states ACPI Power Management Timer PME# support SMI# generation All registers readable/restorable for proper

resume from 0 V suspend statesExternal Glue Integration

Integrated pull-up, pull-down and series termination resistors on IDE, processor interface

Integrated pull-down and series resistors on USB

Enhanced DMA Controller Two cascaded 8237 DMA controllers Supports LPC DMA

Integrated dual-gigabit Media Access Controller Compliant with the 1000 Mb/sec

Ethernet/802.3z specification Multi-speed operation: 10/100/1000Mb/s Serial FLASH interface and SPI EEPROM

interface. No support for uWire EEPROM. SERDES interface for System interconnect

Kumeran interface to external Gigabit Ethernet PHY Dual Kumeran interface to two external

1000BASE-T PHYs 4 pin per port interface (dual port) In band MDIO for faster accesses Remote PHY debug and diagnostics

Integrated Board Management Controller Full BMC implementation, meaning a

standalone microcontroller with independent I/Os and memory

Expansion bus for use with external FLASH device, SRAM and SDRAM

256 Kbytes of internal SRAM Support for RMCP+ Cryptographic module, supporting AES and

RC4 encryption algorithms and SHA1 and MD5 authentication algorithms

External Board Management Controller Support Pass Through and Super Pass Through

capable via a TCO port TCO port supports SMBus, Fast Management

Link (FML), and I2C commands for passing traffic

Manageability Fail-Over IDE re-direction Serial over LAN (SoL) RMCP+ support


Intel 631xESB/632xESB I/O Controller Hub Diagram


Contents

1 Introduction ............................................................................................................ 371.1 About This Document......................................................................................... 371.2 Overview ......................................................................................................... 401.3 Intel 631xESB/632xESB I/O Controller Hub SKU Definition ................................... 48

2 Signal Descriptions .................................................................................................. 492.1 Enterprise South Bridge Interface (ESI) to Host Controller ...................................... 532.2 PCI Express* Interface....................................................................................... 532.3 PCI Interface .................................................................................................... 542.4 PCI/PCI-X* Bus Interface ................................................................................... 572.5 PCI/PCI-X* Bus Interface 64-bit Extension............................................................ 592.6 PCI/PCI-X Hot-Plug Interface .............................................................................. 592.7 Interrupt Interface ............................................................................................ 632.8 Kumeran and SERDES Interface .......................................................................... 642.9 Serial ATA Interface........................................................................................... 642.10 IDE Interface .................................................................................................... 652.11 Firmware Hub Interface...................................................................................... 662.13 USB Interface ................................................................................................... 672.14 AC 97 Link....................................................................................................... 682.15 Processor Interface............................................................................................ 682.16 SMBus Interface................................................................................................ 702.17 Power Management Interface.............................................................................. 702.18 System Management Interface............................................................................ 712.19 Flash and EEPROM Interface ............................................................................... 722.20 Expansion Bus Interface..................................................................................... 722.21 RS-232 Interface............................................................................................... 732.22 Real Time Clock Interface................................................................................... 732.23 JTAG Interface .................................................................................................. 742.24 Other Clocks..................................................................................................... 742.25 General Purpose I/O .......................................................................................... 742.26 Miscellaneous Signals ........................................................................................ 762.27 Power and Ground............................................................................................. 772.28 Pin Straps ........................................................................................................ 792.29 Intel 631xESB/632xESB I/O Controller Hub Revision and Device ID Table ............... 82

3 Intel 631xESB/632xESB I/O Controller Hub and System Clock Domains ............... 85

4 Intel 631xESB/632xESB I/O Controller Hub Pin States ......................................... 874.1 Integrated Pull-Ups and Pull-Downs ..................................................................... 874.2 IDE Integrated Series Termination Resistors ......................................................... 914.3 Output and I/O Signals Planes and States............................................................. 914.4 Power Planes for Input Signals ............................................................................ 97

5 Functional Description ........................................................................................... 1015.1 PCI Express* Bridge, Switch, and Endpoints........................................................ 103

5.1.1 PCI Express* Upstream Ports .............................................................. 1035.1.2 PCI Express* to PCI-X* Bridge (Bm:D0:F3)........................................... 1045.1.3 PCI Express* Downstream Ports (Bp:D0:F0; Bp:D1:F0).......................... 1165.1.4 I/OxAPIC Devices (Bm:D0:F1). ........................................................... 1215.1.5 Flow Control ..................................................................................... 124

5.2 PCI Express* Root Ports (D28:F0,F1,F2,F3) ........................................................ 1255.2.1 Interrupt Generation .......................................................................... 1255.2.2 Power Management ........................................................................... 1265.2.3 SERR# Generation............................................................................. 127


5.2.4 Hot-Plug ...........................................................................................1275.3 PCI-to-PCI Bridge (D30:F0)...............................................................................129

5.3.1 PCI Bus Interface...............................................................................1295.3.2 PCI Bridge as an Initiator ....................................................................1295.3.3 Parity Error Detection and Generation...................................................1315.3.4 PCIRST#...........................................................................................1325.3.5 PCI-to-PCI Bridge Model .....................................................................1325.3.6 IDSEL to Device Number Mapping ........................................................1325.3.7 Standard PCI Bus Configuration Mechanism...........................................132

5.4 Integrated LAN Controller and SERDES/Kumeran Interface....................................1335.4.1 Integrated LAN Controller ...................................................................1335.4.2 Packet Reception and Transmission ......................................................1355.4.3 Buffer and Descriptor Structure............................................................1355.4.4 LAN Controller PCI Express* Bus Interface ............................................1355.4.5 Wake-Up ..........................................................................................1405.4.6 CSMA/CD Unit ...................................................................................1445.4.7 802.1q VLAN Support .........................................................................1455.4.8 EEPROM Interface ..............................................................................1465.4.9 Serial Flash Interface..........................................................................1465.4.10 Intel 631xESB/632xESB I/O Controller Hub MAC-PHY Interconnection.....1485.4.11 LAN Disabling ....................................................................................149

5.5 Board Management Controller (BMC)..................................................................1515.5.1 Management Microcontroller System Theory of Operation ........................1515.5.2 Feature List.......................................................................................1515.5.3 Memory Sub-System ..........................................................................1525.5.4 Instruction Cache and Data Cache........................................................1535.5.5 External Interfaces.............................................................................1535.5.6 Memory Host DMA .............................................................................1605.5.7 Cryptography Module .........................................................................161

5.6 LPC Bridge (with System and Management Functions) (D31:F0).............................1625.6.1 LPC Interface ....................................................................................162

5.7 DMA Operation (D31:F0) ..................................................................................1665.7.1 Channel Priority .................................................................................1675.7.2 Address Compatibility Mode.................................................................1685.7.3 Summary of DMA Transfer Sizes ..........................................................1685.7.4 Autoinitialize .....................................................................................1695.7.5 Software Commands ..........................................................................170

5.8 LPC DMA ........................................................................................................1705.8.1 Asserting DMA Requests .....................................................................1705.8.2 Abandoning DMA Requests ..................................................................1715.8.3 General Flow of DMA Transfers ............................................................1715.8.4 Terminal Count..................................................................................1725.8.5 Verify Mode.......................................................................................1725.8.6 DMA Request De-Assertion..................................................................1725.8.7 SYNC Field / LDRQ# Rules ..................................................................173

5.9 8254 Timers (D31:F0)......................................................................................1745.9.1 Timer Programming............................................................................1745.9.2 Reading from the Interval Timer ..........................................................175

5.10 8259 Interrupt Controllers (PIC) (D31:F0)...........................................................1765.10.1 Interrupt Handling .............................................................................1775.10.2 Initialization Command Words (ICWx) ..................................................1795.10.3 Operation Command Words (OCW).......................................................1805.10.4 Modes of Operation ............................................................................1805.10.5 Masking Interrupts .............................................................................1825.10.6 Steering PCI Interrupts.......................................................................183

5.11 Advanced Programmable Interrupt Controller (APIC) (D31:F0)...............................183


5.11.1 Interrupt Handling ............................................................................. 1835.11.2 Interrupt Mapping.............................................................................. 1835.11.3 PCI/PCI Express* Message-Based Interrupts ......................................... 1845.11.4 System Bus Interrupt Delivery ............................................................ 185

5.12 Serial Interrupt (D31:F0) ................................................................................. 1875.12.1 Start Frame ...................................................................................... 1875.12.2 Data Frames ..................................................................................... 1875.12.3 Stop Frame....................................................................................... 1885.12.4 Specific Interrupts Not Supported by way of SERIRQ .............................. 1885.12.5 Data Frame Format............................................................................ 188

5.13 Real Time Clock (D31:F0)................................................................................. 1895.13.1 Update Cycles ................................................................................... 1905.13.2 Interrupts......................................................................................... 1905.13.3 Lockable RAM Ranges ........................................................................ 1905.13.4 Century Rollover ............................................................................... 1905.13.5 Clearing Battery-Backed RTC RAM ....................................................... 191

5.14 Processor Interface (D31:F0) ............................................................................ 1925.14.1 Processor Interface Signals ................................................................. 1925.14.2 Dual-Processor Issues ........................................................................ 195

5.15 Power Management (D31:F0) ........................................................................... 1955.15.1 Features........................................................................................... 1955.15.2 Intel 631xESB/632xESB I/O Controller Hub and System Power States .... 1965.15.3 System Power Planes ......................................................................... 1985.15.4 SMI#/SCI Generation......................................................................... 1985.15.5 Dynamic Processor Clock Control ......................................................... 2005.15.6 Sleep States ..................................................................................... 2015.15.7 Thermal Management ........................................................................ 2045.15.8 Event Input Signals and Their Usage .................................................... 2055.15.9 ALT Access Mode ............................................................................... 2085.15.10 System Power Supplies, Planes, and Signals.......................................... 2115.15.11 Clock Generators ............................................................................... 2135.15.12 Legacy Power Management Theory of Operation .................................... 213

5.16 System Management (D31:F0).......................................................................... 2135.16.1 Theory of Operation ........................................................................... 2145.16.2 Heartbeat and Event Reporting by way of SMBUS .................................. 217

5.17 IDE Controller (D31:F1) ................................................................................... 2215.17.1 PIO Transfers.................................................................................... 2215.17.2 Bus Master Function........................................................................... 2235.17.3 Ultra ATA/100/66/33 Protocol ............................................................. 2265.17.4 Ultra ATA/33/66/100 Timing ............................................................... 2275.17.5 IDE Swap Bay ................................................................................... 2275.17.6 SMI Trapping .................................................................................... 228

5.18 SATA Host Controller (D31:F2).......................................................................... 2285.18.1 Legacy Operation .............................................................................. 2285.18.2 AHCI Operation ................................................................................. 231

5.19 High-Precision Event Timers ............................................................................. 2355.19.1 Timer Accuracy ................................................................................. 2365.19.2 Interrupt Mapping.............................................................................. 2365.19.3 Periodic Versus Non-Periodic Modes ..................................................... 2365.19.4 Enabling the Timers ........................................................................... 2375.19.5 Interrupt Levels ................................................................................ 2375.19.6 Handling Interrupts............................................................................ 2375.19.7 Issues Related to 64-Bit Timers with 32-Bit Processors ........................... 238

5.20 USB UHCI Host Controllers (D29:F0, F1, F2, and F3)............................................ 2385.20.1 Data Structures in Main Memory.......................................................... 2385.20.2 Data Transfers to/from Main Memory ................................................... 238


5.20.3 Data Encoding and Bit Stuffing ............................................................2395.20.4 Bus Protocol ......................................................................................2395.20.5 Packet Formats..................................................................................2405.20.6 USB Interrupts ..................................................................................2405.20.7 USB Power Management .....................................................................2425.20.8 USB Legacy Keyboard Operation ..........................................................243

5.21 USB EHCI Host Controller (D29:F7)....................................................................2465.21.1 EHC Initialization ...............................................................................2465.21.2 Data Structures in Main Memory ..........................................................2475.21.3 USB 2.0 Enhanced Host Controller DMA ................................................2475.21.4 Data Encoding and Bit Stuffing ............................................................2475.21.5 Packet Formats..................................................................................2475.21.6 USB 2.0 Interrupts and Error Conditions ...............................................2475.21.7 USB 2.0 Power Management................................................................2485.21.8 Interaction with UHCI Host Controllers ..................................................2505.21.9 USB 2.0 Legacy Keyboard Operation.....................................................2525.21.10 USB 2.0 Based Debug Port ..................................................................252

5.22 SMBus............................................................................................................2575.22.1 SMBus Controller (D31:F3)..................................................................2575.22.2 SMBus Slave Interface in PCI Express to PCI-X Bridge.............................269

5.23 AC97 Controller (Audio D31:F5, Modem D31:F6).................................................2765.23.1 PCI Power Management ......................................................................2785.23.2 AC-Link Overview ..............................................................................2795.23.3 AC-Link Low Power Mode ....................................................................2825.23.4 AC97 Cold Reset ...............................................................................2835.23.5 AC97 Warm Reset .............................................................................2835.23.6 Hardware Assist to Determine ACZ_SDIN Used Per Codec .......................284

5.24 Intel High Definition Audio Controller Overview .................................................284

6 Electrical Characteristics........................................................................................287

7 Component Ballout.................................................................................................3037.1 Intel 631xESB/632xESB I/O Controller Hub Ballout ............................................303

8 Signal Lists ............................................................................................................3078.1 Intel 631xESB/632xESB I/O Controller Hub Signal List (Sorted by Signal Name) ....3078.2 Intel 631xESB/632xESB I/O Controller Hub Signal List (Sorted by Ball Number).....323

9 Mechanical Specifications ......................................................................................339

10 Testability..............................................................................................................34310.1 JTAG Test Mode Description ..............................................................................34310.2 XOR Chain Test Mode Description ......................................................................344

10.2.1 XOR Chain Testability Algorithm Example ..............................................34510.3 XOR Chain Tables ............................................................................................345

11 Register and Memory Mapping ...............................................................................35111.1 Register Nomenclature and Access Attributes ......................................................35111.2 PCI Devices and Functions ................................................................................35211.3 PCI Configuration Map ......................................................................................35311.4 I/O Map..........................................................................................................353

11.4.1 Fixed I/O Address Ranges ...................................................................35311.4.2 Variable I/O Decode Ranges ................................................................355

11.5 Memory Map ...................................................................................................356

12 Chipset Configuration Registers .............................................................................35912.1 Chipset Configuration Registers (Memory Space) .................................................359

12.1.1 VCH Virtual Channel Capability Header Register...................................36112.1.2 VCAP1 Virtual Channel Capability #1 Register .....................................36112.1.3 VCAP2 Virtual Channel Capability #2 Register .....................................361


12.1.4 PVC Port Virtual Channel Control Register .......................................... 36212.1.5 PVS Port Virtual Channel Status Register............................................ 36212.1.6 V0CAP Virtual Channel 0 Resource Capability Register ......................... 36212.1.7 V0CTL Virtual Channel 0 Resource Control Register ............................. 36212.1.8 V0STS Virtual Channel 0 Resource Status Register .............................. 36312.1.9 V1CAP Virtual Channel 1 Resource Capability Register ......................... 36312.1.10 V1CTL Virtual Channel 1 Resource Control Register ............................. 36412.1.11 V1STS Virtual Channel 1 Resource Status Register .............................. 36412.1.12 PAT[0-F] Port Arbitration Table Register............................................. 36412.1.13 UES Uncorrectable Error Status Register ............................................ 36512.1.14 UEM Uncorrectable Error Mask Register.............................................. 36512.1.15 UEV Uncorrectable Error Severity Register.......................................... 36612.1.16 CES Correctable Error Status Register ............................................... 36612.1.17 CEM Correctable Error Mask Register ................................................. 36612.1.18 AECC Advanced Error Capabilities and Control Register ........................ 36712.1.19 RES Root Error Status Register ......................................................... 36712.1.20 ESID Error Source Identification Register ........................................... 36712.1.21 RCTCL Root Complex Topology Capabilities List Register ...................... 36812.1.22 ESD Element Self Description Register ............................................... 36812.1.23 ULD Upstream Link Descriptor Register.............................................. 36812.1.24 ULBA Upstream Link Base Address Register........................................ 36812.1.25 RP0D Root Port 0 Descriptor Register ................................................ 36912.1.26 RP0BA Root Port 0 Base Address Register .......................................... 36912.1.27 RP1D Root Port 1 Descriptor Register ................................................ 36912.1.28 RP1BA Root Port 1 Base Address Register .......................................... 37012.1.29 RP2D Root Port 2 Descriptor Register ................................................ 37012.1.30 RP2BA Root Port 2 Base Address Register .......................................... 37012.1.31 RP3D Root Port 3 Descriptor Register ................................................ 37112.1.32 RP3BA Root Port 3 Base Address Register .......................................... 37112.1.33 AZD High Definition Audio Descriptor Register .................................... 37112.1.34 AZBA High Definition Audio Base Address Register .............................. 37212.1.35 ILCL Internal Link Capabilities List Register ........................................ 37212.1.36 LCAP Link Capabilities Register ......................................................... 37212.1.37 LCTL Link Control Register ............................................................... 37312.1.38 LSTS Link Status Register ................................................................ 37312.1.39 VPCAP Private Virtual Channel Resource Capability Register.................. 37312.1.40 VPCTL Private Virtual Channel Resource Control Register...................... 37412.1.41 VPSTS Private Virtual Channel Resource Status Register ...................... 37412.1.42 VPR Private Virtual Channel Routing Register ...................................... 37412.1.43 L3A Level 3 Backbone Arbiter Configuration Register ........................... 37512.1.44 L2A Level 2 Backbone Arbiter Configuration Register ........................... 37512.1.45 L1A Level 1 Backbone Arbiter Configuration Register ........................... 37612.1.46 DA Downstream Arbiter Configuration Register ................................... 37612.1.47 UNRL Upstream Non-posted Request Limits Register ........................... 37712.1.48 UMR Upstream Minimum Reserved Register........................................ 37812.1.49 QL Queue Limits Register................................................................. 37812.1.50 GBC Generic Backbone Configuration Register .................................... 37912.1.51 RPC Root Port Configuration Register................................................. 38012.1.52 BAC Bandwidth Allocation Configuration Register................................. 38012.1.53 AS Arbiter Status Register................................................................ 38112.1.54 TRSR Trap Status Register ............................................................... 38112.1.55 TRCR Trapped Cycle Register............................................................ 38212.1.56 TWDR Trapped Write Data Register ................................................... 38212.1.57 IOTRn I/O Trap Register (0-3) .......................................................... 38212.1.58 TCTL TCO Configuration Register ...................................................... 38312.1.59 D31IP Device 31 Interrupt Pin Register .............................................. 384


12.1.60 D30IP Device 30 Interrupt Pin Register ..............................................38412.1.61 D29IP Device 29 Interrupt Pin Register ..............................................38512.1.62 D28IP Device 28 Interrupt Pin Register ..............................................38612.1.63 D27IP Device 27 Interrupt Pin Register ..............................................38612.1.64 D31IR Device 31 Interrupt Route Register ..........................................38712.1.65 D30IR Device 30 Interrupt Route Register ..........................................38812.1.66 D29IR Device 29 Interrupt Route Register ..........................................38912.1.67 D28IR Device 28 Interrupt Route Register ..........................................39012.1.68 D27IR Device 27 Interrupt Route Register ..........................................39112.1.69 OIC Other Interrupt Control Register..................................................39212.1.70 RC RTC Configuration Register ..........................................................39212.1.71 HPTC High Precision Timer Configuration Register................................39212.1.72 GCS General Control and Status Register............................................39312.1.73 BUC Backed Up Control Register........................................................39412.1.74 FD Function Disable Register.............................................................39512.1.75 CG Clock Gating ..............................................................................396

13 PCI Express* Bridge, Switch, and Endpoints Registers(Bm:D0:F0/F1/F3, Bp:D0:F0, Bp:D1:F0, Bp:D2:F0) ................................................39713.1 PCI Configuration Registers...............................................................................39713.2 Memory-Mapped Registers ................................................................................39813.3 PCI Express* Switch, Upstream/Downstream Port

Registers (Bm:D0:F0,Bp:D0:F0,Bp:D1:F0,Bp:D2:F0) ...........................................39813.3.1 Configuration Registers.......................................................................398

13.4 PCI Express* Switch, Upstream/Downstream Port(Bm:D0:F0,Bp:D0:F0,Bp:D1:F0,Bp:D2:F0) Enhanced...........................................42413.4.1 Configuration Registers.......................................................................424

13.5 I/OxAPIC Interrupt Controller Registers (Bm:D0:F1).............................................42913.5.1 PCI Configuration Space Registers........................................................42913.5.2 I/OxAPIC Direct Memory Space Registers ..............................................44113.5.3 Indirect Memory Space Registers .........................................................442

13.6 PCI Express* to PCI-X* Bridges (Bm:D0:F3) .......................................................44513.6.1 Configuration Registers.......................................................................445

13.7 PCI Express* to PCI-X* Bridges (Bm:D0:F3) Enhanced .........................................47513.7.1 Configuration Registers.......................................................................475

13.8 Hot-Plug Controller Registers.............................................................................48513.8.1 Memory-Mapped Registers ..................................................................48513.8.2 Offset 24h 40h: Logical Slot Registers (LSR) 1 to 6 ..............................490

14 Intel High Definition Audio Controller Registers (D27:F0) ....................................49514.1 Intel High Definition Audio PCI Configuration Space

(High Definition Audio D27:F0) .......................................................................49514.1.1 VID Vendor Identification Register

(High Definition Audio Controller D27:F0) ...........................................49614.1.2 DID Device Identification Register

(High Definition Audio Controller D27:F0) ...........................................49714.1.3 PCICMD PCI Command Register

(High Definition Audio Controller D27:F0) ...........................................49714.1.4 PCISTS PCI Status Register

(High Definition Audio Controller D27:F0) ...........................................49814.1.5 RID Revision Identification Register

(High Definition Audio Controller D27:F0) ...........................................49814.1.6 PI Programming Interface Register

(High Definition Audio Controller D27:F0) ...........................................49814.1.7 SCC Sub Class Code Register

(High Definition Audio Controller D27:F0) ...........................................49914.1.8 BCC Base Class Code Register

(High Definition Audio Controller D27:F0) ...........................................499


14.1.9 CLS Cache Line Size Register(High Definition Audio Controller D27:F0)........................................... 499

14.1.10 LT Latency Timer Register(High Definition Audio Controller D27:F0)........................................... 499

14.1.11 HEADTYP Header Type Register(High Definition Audio Controller D27:F0)........................................... 499

14.1.12 AZBARL High Definition Audio Lower Base AddressRegister (High Definition Audio Controller D27:F0) .............................. 500

14.1.13 AZBARU Intel High Definition Audio Upper Base AddressRegister (High Definition Audio Controller D27:F0) .............................. 500

14.1.14 SVID Subsystem Vendor Identification Register (High Definition Audio Controller D27:F0)........................................... 500

14.1.15 SID Subsystem Identification Register (High Definition Audio Controller D27:F0)........................................... 500

14.1.16 CAPPTR Capabilities Pointer Register (Audio D27:F0) ........................ 50114.1.17 INTLN Interrupt Line Register

(High Definition Audio Controller D27:F0)........................................... 50114.1.18 INTPN Interrupt Pin Register

(High Definition Audio Controller D27:F0)........................................... 50114.1.19 AZCTL Intel High Definition Audio Control Register

(High Definition Audio Controller D27:F0)........................................... 50214.1.20 TCSEL Traffic Class Select Register

(High Definition Audio Controller D27:F0)........................................... 50214.1.21 PID PCI Power Management Capability ID Register

(High Definition Audio Controller D27:F0)........................................... 50314.1.22 PC Power Management Capabilities Register

(High Definition Audio Controller D27:F0)........................................... 50314.1.23 PCS Power Management Control and Status Register

(High Definition Audio Controller D27:F0)........................................... 50314.1.24 MID MSI Capability ID Register

(High Definition Audio Controller D27:F0)........................................... 50414.1.25 MMC MSI Message Control Register

(High Definition Audio Controller D27:F0)........................................... 50414.1.26 MMLA MSI Message Lower Address Register

(High Definition Audio Controller D27:F0)........................................... 50514.1.27 MMUA MSI Message Upper Address Register

(High Definition Audio Controller D27:F0)........................................... 50514.1.28 MMD MSI Message Data Register

(High Definition Audio Controller D27:F0)........................................... 50514.1.29 PXID PCI Express Capability ID Register

(High Definition Audio Controller D27:F0)........................................... 50514.1.30 PXC PCI Express Capabilities Register

(High Definition Audio Controller D27:F0)........................................... 50514.1.31 DEVCAP Device Capabilities Register

(High Definition Audio Controller D27:F0)........................................... 50614.1.32 DEVC Device Control Register

(High Definition Audio Controller D27:F0)........................................... 50614.1.33 DEVS Device Status Register

(High Definition Audio Controller D27:F0)........................................... 50714.1.34 VCCAP Virtual Channel Enhanced Capability Header

(High Definition Audio Controller D27:F0)........................................... 50714.1.35 PVCCAP1 Port VC Capability Register 1

(High Definition Audio Controller D27:F0)........................................... 50714.1.36 PVCCAP2 Port VC Capability Register 2

(High Definition Audio Controller D27:F0)........................................... 50814.1.37 PVCCLT Port VC Control Register

(High Definition Audio Controller D27:F0)........................................... 50814.1.38 PVCSTS Port VC Status Register

(High Definition Audio Controller D27:F0)........................................... 508


14.1.39 VC0CAP VC0 Resource Capability Register(High Definition Audio Controller D27:F0) ...........................................508

14.1.40 VC0CTL VC0 Resource Control Register(High Definition Audio Controller D27:F0) ...........................................509

14.1.41 VC0STS VC0 Resource Status Register(High Definition Audio Controller D27:F0) ...........................................509

14.1.42 VCiCAP VCi Resource Capability Register(High Definition Audio Controller D27:F0) ...........................................509

14.1.43 VCiCTL VCi Resource Control Register(High Definition Audio Controller D27:F0) ...........................................510

14.1.44 VCiSTS VCi Resource Status Register(High Definition Audio Controller D27:F0) ...........................................510

14.1.45 RCCAP Root Complex Link Declaration EnhancedCapability Header Register (High Definition Audio Controller D27:F0) .....510

14.1.46 ESD Element Self Description Register(High Definition Audio Controller D27:F0) ...........................................511

14.1.47 L1DESC Link 1 Description Register(High Definition Audio Controller D27:F0) ...........................................511

14.1.48 L1ADDL Link 1 Lower Address Register(High Definition Audio Controller D27:F0) ...........................................511

14.1.49 L1ADDU Link 1 Upper Address Register(High Definition Audio Controller D27:F0) ...........................................511

14.2 Intel High Definition Audio Memory Mapped Configuration Registers (High Definition Audio D27:F0) .......................................................................51214.2.1 GCAP Global Capabilities Register

(High Definition Audio Controller D27:F0) ...........................................51514.2.2 VMIN Minor Version Register

(High Definition Audio Controller D27:F0) ...........................................51514.2.3 VMAJ Major Version Register

(High Definition Audio Controller D27:F0) ...........................................51514.2.4 OUTPAY Output Payload Capability Register

(High Definition Audio Controller D27:F0) ...........................................51614.2.5 INPAY Input Payload Capability Register

(High Definition Audio Controller D27:F0) ...........................................51614.2.6 GCTL Global Control Register

(High Definition Audio Controller D27:F0) ...........................................51614.2.7 WAKEEN Wake Enable Register

(High Definition Audio Controller D27:F0) ...........................................51714.2.8 STATESTS State Change Status Register

(High Definition Audio Controller D27:F0) ...........................................51814.2.9 GSTS Global Status Register

(High Definition Audio Controller D27:F0) ...........................................51814.2.10 INTCTL Interrupt Control Register

(High Definition Audio Controller D27:F0) ...........................................51814.2.11 INTSTS Interrupt Status Register

(High Definition Audio Controller D27:F0)51914.2.12 WALCLK Wall Clock Counter Register

(High Definition Audio Controller D27:F0) ...........................................52014.2.13 SSYNC Stream Synchronization Register

(High Definition Audio Controller D27:F0) ...........................................52014.2.14 CORBLBASE CORB Lower Base Address Register

(High Definition Audio Controller D27:F0) ...........................................52014.2.15 CORBUBASE CORB Upper Base Address Register

(High Definition Audio Controller D27:F0) ...........................................52114.2.16 CORBRP CORB Read Pointer Register

(High Definition Audio Controller D27:F0) ...........................................52114.2.17 CORBCTL CORB Control Register

(High Definition Audio Controller D27:F0) ...........................................521


14.2.18 CORBST CORB Status Register (High Definition Audio Controller D27:F0)........................................... 522

14.2.19 CORBSIZE CORB Size Register (High Definition Audio Controller D27:F0)........................................... 522

14.2.20 RIRBLBASE RIRB Lower Base Address Register (High Definition Audio Controller D27:F0)........................................... 522

14.2.21 RIRBUBASE RIRB Upper Base Address Register (High Definition Audio Controller D27:F0)........................................... 522

14.2.22 RIRBWP RIRB Write Pointer Register (High Definition Audio Controller D27:F0)........................................... 523

14.2.23 RINTCNT Response Interrupt Count Register (High Definition Audio Controller D27:F0)........................................... 523

14.2.24 RIRBCTL RIRB Control Register (High Definition Audio Controller D27:F0)........................................... 524

14.2.25 RIRBSTS RIRB Status Register (High Definition Audio Controller D27:F0)........................................... 524

14.2.26 RIRBSIZE RIRB Size Register (High Definition Audio Controller D27:F0)........................................... 524

14.2.27 IC Immediate Command Register (High Definition Audio Controller D27:F0)........................................... 525

14.2.28 IR Immediate Response Register (High Definition Audio Controller D27:F0)........................................... 525

14.2.29 IRS Immediate Command Status Register (High Definition Audio Controller D27:F0)........................................... 525

14.2.30 DPLBASE DMA Position Lower Base Address Register (High Definition Audio Controller D27:F0)........................................... 526

14.2.31 DPUBASE DMA Position Upper Base Address Register (High Definition Audio Controller D27:F0)........................................... 526

14.2.32 SDCTL Stream Descriptor Control Register (High Definition Audio Controller D27:F0)........................................... 527

14.2.33 SDSTS Stream Descriptor Status Register (High Definition Audio Controller D27:F0)........................................... 528

14.2.34 SDLPIB Stream Descriptor Link Position in BufferRegister (High Definition Audio Controller D27:F0) .............................. 529

14.2.35 SDCBL Stream Descriptor Cyclic Buffer Length Register (High Definition Audio Controller D27:F0)........................................... 529

14.2.36 SDLVI Stream Descriptor Last Valid Index Register (High Definition Audio Controller D27:F0)........................................... 530

14.2.37 SDFIFOW Stream Descriptor FIFO Watermark Register(High Definition Audio Controller D27:F0)........................................... 530

14.2.38 SDFIFOS Stream Descriptor FIFO Size Register (High Definition Audio Controller D27:F0)........................................... 531

14.2.39 SDFMT Stream Descriptor Format Register (High Definition Audio Controller D27:F0)........................................... 532

14.2.40 SDBDPL Stream Descriptor Buffer Descriptor List Pointer Lower Base Address Register (High Definition Audio Controller D27:F0)........................................... 533

14.2.41 SDBDPU Stream Descriptor Buffer Descriptor List Pointer Upper Base Address Register (High Definition Audio Controller D27:F0)........................................... 533

15 PCI Express* Configuration Registers.................................................................... 53515.1 PCI Express* Configuration Registers (PCI Express D28:F0/F1/F2/F3) ................. 535

15.1.1 VID Vendor Identification Register (PCI Express D28:F0/F1/F2/F3) ........................................................ 537

15.1.2 DID Device Identification Register (PCI Express D28:F0/F1/F2/F3) ........................................................ 538

15.1.3 PCICMD PCI Command Register(PCI Express D28:F0/F1/F2/F3) ........................................................ 538


15.1.4 PCISTS PCI Status Register (PCI Express D28:F0/F1/F2/F3) ........................................................539

15.1.5 RID Revision Identification Register (PCI Express D28:F0/F1/F2/F3) ........................................................539

15.1.6 PI Programming Interface Register (PCI Express D28:F0/F1/F2/F3) ........................................................540

15.1.7 SCC Sub Class Code Register (PCI Express D28:F0/F1/F2/F3) ........................................................540

15.1.8 BCC Base Class Code Register (PCI Express D28:F0/F1/F2/F3) ........................................................540

15.1.9 CLS Cache Line Size Register (PCI Express D28:F0/F1/F2/F3) ........................................................540

15.1.10 PLT Primary Latency Timer Register (PCI Express D28:F0/F1/F2/F3) ........................................................540

15.1.11 HEADTYP Header Type Register (PCI Express D28:F0/F1/F2/F3) ........................................................541

15.1.12 BNUM Bus Number Register (PCI Express D28:F0/F1/F2/F3) ........................................................541

15.1.13 IOBL I/O Base and Limit Register (PCI Express D28:F0/F1/F2/F3) ........................................................541

15.1.14 SSTS Secondary Status Register (PCI Express D28:F0/F1/F2/F3) ........................................................542

15.1.15 MBL Memory Base and Limit Register (PCI Express D28:F0/F1/F2/F3) ........................................................542

15.1.16 PMBL Prefetchable Memory Base and Limit Register (PCI Express D28:F0/F1/F2/F3) ........................................................543

15.1.17 PMBU32 Prefetchable Memory Base Upper 32 BitsRegister (PCI Express D28:F0/F1/F2/F3) ............................................543

15.1.18 PMLU32 Prefetchable Memory Limit Upper 32 BitsRegister (PCI Express D28:F0/F1/F2/F3) ............................................543

15.1.19 CAPP Capabilities List Pointer Register (PCI Express D28:F0/F1/F2/F3) ........................................................543

15.1.20 INTR Interrupt Information Register(PCI Express D28:F0/F1/F2/F3) ........................................................544

15.1.21 BCTRL Bridge Control Register (PCI Express D28:F0/F1/F2/F3) ........................................................544

15.1.22 CLIST Capabilities List Register (PCI Express D28:F0/F1/F2/F3) ........................................................545

15.1.23 XCAP PCI Express Capabilities Register (PCI Express D28:F0/F1/F2/F3) ........................................................545

15.1.24 DCAP Device Capabilities Register (PCI Express D28:F0/F1/F2/F3) ........................................................545

15.1.25 DCTL Device Control Register (PCI Express D28:F0/F1/F2/F3) ........................................................546

15.1.26 DSTS Device Status Register (PCI Express D28:F0/F1/F2/F3) ........................................................547

15.1.27 LCAP Link Capabilities Register (PCI Express D28:F0/F1/F2/F3) ........................................................547

15.1.28 LCTL Link Control Register (PCI Express D28:F0/F1/F2/F3) ........................................................548

15.1.29 LSTS Link Status Register (PCI Express D28:F0/F1/F2/F3) .................54915.1.30 SLCAP Slot Capabilities Register

(PCI Express D28:F0/F1/F2/F3) ........................................................54915.1.31 SLCTL Slot Control Register

(PCI Express D28:F0/F1/F2/F3) ........................................................55015.1.32 SLSTS Slot Status Register

(PCI Express D28:F0/F1/F2/F3) ........................................................55115.1.33 RCTL Root Control Register

(PCI Express D28:F0/F1/F2/F3) ........................................................551


15.1.34 RSTS Root Status Register (PCI Express D28:F0/F1/F2/F3) ........................................................ 552

15.1.35 MID Message Signaled Interrupt Identifiers Register (PCI Express D28:F0/F1/F2/F3) ........................................................ 552

15.1.36 MC Message Signaled Interrupt Message Control Register(PCI Express D28:F0/F1/F2/F3) ........................................................ 552

15.1.37 MA Message Signaled Interrupt Message AddressRegister (PCI Express D28:F0/F1/F2/F3)............................................ 553

15.1.38 MD Message Signaled Interrupt Message Data Register(PCI Express D28:F0/F1/F2/F3) ........................................................ 553

15.1.39 SVCAP Subsystem Vendor Capability Register(PCI Express D28:F0/F1/F2/F3) ........................................................ 553

15.1.40 SVID Subsystem Vendor Identification Register (PCI Express D28:F0/F1/F2/F3) ........................................................ 553

15.1.41 PMCAP Power Management Capability Register (PCI Express D28:F0/F1/F2/F3) ........................................................ 554

15.1.42 PMC PCI Power Management Capabilities Register (PCI Express D28:F0/F1/F2/F3) ........................................................ 554

15.1.43 PMCS PCI Power Management Control and StatusRegister (PCI Express D28:F0/F1/F2/F3)............................................ 554

15.1.44 MPC Miscellaneous Port Configuration Register (PCI Express D28:F0/F1/F2/F3) ........................................................ 555

15.1.45 SMSCS SMI/SCI Status Register (PCI Express D28:F0/F1/F2/F3) ........................................................ 556

15.1.46 RWC Resume Well Control Register (PCI Express D28:F0/F1/F2/F3) ........................................................ 556

15.1.47 VCH Virtual Channel Capability Header Register (PCI Express D28:F0/F1/F2/F3) ........................................................ 556

15.1.48 VCAP1 Virtual Channel Capability 1 Register (PCI Express D28:F0/F1/F2/F3) ........................................................ 557

15.1.49 VCAP2 Virtual Channel Capability 2 Register (PCI Express D28:F0/F1/F2/F3) ........................................................ 557

15.1.50 PVC Port Virtual Channel Control Register (PCI Express D28:F0/F1/F2/F3) ........................................................ 557

15.1.51 PVS Port Virtual Channel Status Register (PCI Express D28:F0/F1/F2/F3) ........................................................ 558

15.1.52 V0CAP Virtual Channel 0 Resource Capability Register (PCI Express D28:F0/F1/F2/F3) ........................................................ 558

15.1.53 V0CTL Virtual Channel 0 Resource Control Register (PCI Express D28:F0/F1/F2/F3) ........................................................ 558

15.1.54 V0STS Virtual Channel 0 Resource Status Register (PCI Express D28:F0/F1/F2/F3) ........................................................ 559

15.1.55 V1CAP Virtual Channel 1 Resource Capability Register (PCI Express D28:F0/F1/F2/F3) ........................................................ 559

15.1.56 V1CTL Virtual Channel 1 Resource Control Register (PCI Express D28:F0/F1/F2/F3) ........................................................ 560

15.1.57 V1STS Virtual Channel 1 Resource Status Register (PCI Express D28:F0/F1/F2/F3) ........................................................ 560

15.1.58 UES Uncorrectable Error Status Register (PCI Express D28:F0/F1/F2/F3) ........................................................ 560

15.1.59 UEM Uncorrectable Error Mask (PCI Express D28:F0/F1/F2/F3) ........................................................ 561

15.1.60 UEV Uncorrectable Error Severity (PCI Express D28:F0/F1/F2/F3) ........................................................ 562

15.1.61 CES Correctable Error Status Register (PCI Express D28:F0/F1/F2/F3) ........................................................ 563

15.1.62 CEM Correctable Error Mask Register (PCI Express D28:F0/F1/F2/F3) ........................................................ 563


15.1.63 AECC Advanced Error Capabilities and Control Register(PCI Express D28:F0/F1/F2/F3) ........................................................563

15.1.64 RES Root Error Status Register (PCI Express D28:F0/F1/F2/F3) ........................................................564

15.1.65 RCTCL Root Complex Topology Capability List Register(PCI Express D28:F0/F1/F2/F3) ........................................................564

15.1.66 ESD Element Self Description Register (PCI Express D28:F0/F1/F2/F3) ........................................................564

15.1.67 ULD Upstream Link Description Register (PCI Express D28:F0/F1/F2/F3) ........................................................565

15.1.68 ULBA Upstream Link Base Address Register (PCI Express D28:F0/F1/F2/F3) ........................................................565

16 UHCI Controllers Registers ....................................................................................56716.1 PCI Configuration Registers (USB D29:F0/F1/F2/F3) ..........................................567

16.1.1 VID Vendor Identification Register (USB D29:F0/F1/F2/F3) ................56816.1.2 DID Device Identification Register (USB D29:F0/F1/F2/F3).................56816.1.3 PCICMD PCI Command Register (USB D29:F0/F1/F2/F3) ...................56816.1.4 PCISTS PCI Status Register (USB D29:F0/F1/F2/F3) .........................56916.1.5 RID Revision Identification Register (USB D29:F0/F1/F2/F3) ..............56916.1.6 PI Programming Interface Register (USB D29:F0/F1/F2/F3) ...............57016.1.7 SCC Sub Class Code Register (USB D29:F0/F1/F2/F3) .......................57016.1.8 BCC Base Class Code Register (USB D29:F0/F1/F2/F3)......................57016.1.9 MLT Master Latency Timer Register (USB D29:F0/F1/F2/F3)...............57016.1.10 HEADTYP Header Type Register (USB D29:F0/F1/F2/F3) ....................57016.1.11 BASE Base Address Register (USB D29:F0/F1/F2/F3) ........................57116.1.12 SVID Subsystem Vendor Identification Register

(USB D29:F0/F1/F2/F3) ...................................................................57116.1.13 SID Subsystem Identification Register (USB D29:F0/F1/F2/F3)...........57216.1.14 INT_LN Interrupt Line Register (USB D29:F0/F1/F2/F3) .....................57216.1.15 INT_PN Interrupt Pin Register (USB D29:F0/F1/F2/F3) ......................57216.1.16 USB_RELNUM Serial Bus Release Number

Register USB D29:F0/F1/F2/F3) ........................................................57216.1.17 USB_LEGKEY USB Legacy Keyboard/Mouse Control

Register (USB D29:F0/F1/F2/F3) .......................................................57316.1.18 USB_RES USB Resume Enable Register (USB D29:F0/F1/F2/F3) .........57416.1.19 CWP Core Well Policy Register (USB D29:F0/F1/F2/F3)......................574

16.2 USB I/O Registers............................................................................................57516.2.1 USBCMD USB Command Register ......................................................57516.2.2 USBSTS USB Status Register ............................................................57816.2.3 USBINTR USB Interrupt Enable Register .............................................57816.2.4 FRNUM Frame Number Register ........................................................57916.2.5 FRBASEADD Frame List Base Address Register ....................................57916.2.6 SOFMOD Start of Frame Modify Register.............................................58016.2.7 PORTSC[0,1] Port Status and Control Register ....................................580

17 EHCI Controller Registers (D29:F7) .......................................................................58317.1 USB EHCI Configuration Registers

(USB EHCI D29:F7).......................................................................................58317.1.1 VID Vendor Identification Register

(USB EHCI D29:F7) .........................................................................58417.1.2 DID Device Identification Register

(USB EHCI D29:F7) .........................................................................58417.1.3 PCICMD PCI Command Register

(USB EHCI D29:F7) .........................................................................58417.1.4 PCISTS PCI Status Register

(USB EHCI D29:F7) .........................................................................58517.1.5 RID Revision Identification Register

(USB EHCI D29:F7) .........................................................................586


17.1.6 PI Programming Interface Register (USB EHCI D29:F7)......................................................................... 586

17.1.7 SCC Sub Class Code Register (USB EHCI D29:F7)......................................................................... 586

17.1.8 BCC Base Class Code Register (USB EHCI D29:F7)......................................................................... 586

17.1.9 PMLT Primary Master Latency Timer Register (USB EHCI D29:F7)......................................................................... 587

17.1.10 MEM_BASE Memory Base Address Register (USB EHCI D29:F7)......................................................................... 587

17.1.11 SVID USB EHCI Subsystem Vendor ID Register (USB EHCI D29:F7)......................................................................... 587

17.1.12 SID USB EHCI Subsystem ID Register (USB EHCI D29:F7)......................................................................... 587

17.1.13 CAP_PTR Capabilities Pointer Register (USB EHCI D29:F7)......................................................................... 588

17.1.14 INT_LN Interrupt Line Register (USB EHCI D29:F7)......................................................................... 588

17.1.15 INT_PN Interrupt Pin Register (USB EHCI D29:F7)......................................................................... 588

17.1.16 PWR_CAPID PCI Power Management Capability IDRegister (USB EHCI D29:F7) ............................................................ 588

17.1.17 NXT_PTR1 Next Item Pointer #1 Register (USB EHCI D29:F7)......................................................................... 589

17.1.18 PWR_CAP Power Management Capabilities Register (USB EHCI D29:F7)......................................................................... 589

17.1.19 PWR_CNTL_STS Power Management Control/StatusRegister (USB EHCI D29:F7) ............................................................ 590

17.1.20 DEBUG_CAPID Debug Port Capability ID Register (USB EHCI D29:F7)......................................................................... 590

17.1.21 NXT_PTR2 Next Item Pointer #2 Register (USB EHCI D29:F7)......................................................................... 590

17.1.22 DEBUG_BASE Debug Port Base Offset Register (USB EHCI D29:F7)......................................................................... 591

17.1.23 USB_RELNUM USB Release Number Register (USB EHCI D29:F7)......................................................................... 591

17.1.24 FL_ADJ Frame Length Adjustment Register (USB EHCI D29:F7)......................................................................... 591

17.1.25 PWAKE_CAP Port Wake Capability Register (USB EHCI D29:F7)......................................................................... 592

17.1.26 LEG_EXT_CAP USB EHCI Legacy Support ExtendedCapability Register (USB EHCI D29:F7).............................................. 593

17.1.27 LEG_EXT_CS USB EHCI Legacy Support ExtendedControl / Status Register (USB EHCI D29:F7) ..................................... 593

17.1.28 SPECIAL_SMI Intel Specific USB 2.0 SMI Register (USB EHCI D29:F7)......................................................................... 595

17.1.29 ACCESS_CNTL Access Control Register (USB EHCI D29:F7)......................................................................... 596

17.2 Memory-Mapped I/O Registers .......................................................................... 59617.2.1 Host Controller Capability Registers ..................................................... 59617.2.2 Host Controller Operational Registers ................................................... 59817.2.3 USB 2.0-Based Debug Port Register ..................................................... 609

18 PCI-to-PCI Bridge Registers (D30:F0) ................................................................... 61318.1 PCI Configuration Registers (D30:F0)................................................................. 613

18.1.1 VID Vendor Identification Register (PCI-PCI D30:F0) ........................ 61418.1.2 DID Device Identification Register (PCI-PCI D30:F0) ......................... 61418.1.3 PCICMD PCI Command (PCI-PCI D30:F0) ........................................ 61418.1.4 PSTS PCI Status Register (PCI-PCI D30:F0) ..................................... 615


18.1.5 RID Revision Identification Register (PCI-PCI D30:F0) .......................61718.1.6 CC Class Code Register (PCI-PCI D30:F0) ........................................61718.1.7 PMLT Primary Master Latency Timer Register

(PCI-PCI D30:F0) ............................................................................61718.1.8 HEADTYP Header Type Register (PCI-PCI D30:F0).............................61818.1.9 BNUM Bus Number Register (PCI-PCI D30:F0)..................................61818.1.10 SMLT Secondary Master Latency Timer Register

(PCI-PCI D30:F0) ............................................................................61818.1.11 IOBASE_LIMIT I/O Base and Limit Register

(PCI-PCI D30:F0) ............................................................................61918.1.12 SECSTS Secondary Status Register (PCI-PCI D30:F0)........................61918.1.13 MEMBASE_LIMIT Memory Base and Limit Register

(PCI-PCI D30:F0) ............................................................................62018.1.14 PREF_MEM_BASE_LIMIT Prefetchable Memory Base

and Limit Register (PCI-PCI D30:F0)..................................................62018.1.15 PMBU32 Prefetchable Memory Base Upper 32 Bits

Register (PCI-PCI D30:F0)................................................................62118.1.16 PMLU32 Prefetchable Memory Limit Upper 32 Bits

Register (PCI-PCI D30:F0)................................................................62118.1.17 CAPP Capability List Pointer Register (PCI-PCI D30:F0) ......................62118.1.18 INTR Interrupt Information Register (PCI-PCI D30:F0) ......................62118.1.19 BCTRL Bridge Control Register (PCI-PCI D30:F0) ..............................62118.1.20 SPDH Secondary PCI Device Hiding Register

(PCI-PCI D30:F0) ............................................................................62318.1.21 DTC Delayed Transaction Control Register

(PCI-PCI D30:F0) ............................................................................62318.1.22 BPS Bridge Proprietary Status Register

(PCI-PCI D30:F0) ............................................................................62418.1.23 BPC Bridge Policy Configuration Register

(PCI-PCI D30:F0) ............................................................................62518.1.24 SVCAP Subsystem Vendor Capability Register

(PCI-PCI D30:F0) ............................................................................62518.1.25 SVID Subsystem Vendor IDs Register (PCI-PCI D30:F0) ....................625

19 AC97 Audio Controller Registers (D30:F2) ............................................................62719.1 AC97 Audio PCI Configuration Space

(Audio D30:F2).............................................................................................62719.1.1 VID Vendor Identification Register (Audio D30:F2) ............................62819.1.2 DID Device Identification Register (Audio D30:F2) ............................62819.1.3 PCICMD PCI Command Register (Audio D30:F2) ...............................62819.1.4 PCISTS PCI Status Register (Audio D30:F2) .....................................62919.1.6 PI Programming Interface Register (Audio D30:F2) ...........................63019.1.7 SCC Sub Class Code Register (Audio D30:F2) ...................................63019.1.8 BCC Base Class Code Register (Audio D30:F2)..................................63019.1.9 HEADTYP Header Type Register (Audio D30:F2)................................63019.1.10 NAMBAR Native Audio Mixer Base Address Register

(Audio D30:F2) ...............................................................................63119.1.11 NABMBAR Native Audio Bus Mastering Base Address

Register (Audio D30:F2)...................................................................63119.1.12 MMBAR Mixer Base Address Register (Audio D30:F2).........................63219.1.13 MBBAR Bus Master Base Address Register

(Audio D30:F2) ...............................................................................63219.1.14 SVID Subsystem Vendor Identification Register

(Audio D30:F2) ...............................................................................63319.1.15 SID Subsystem Identification Register (Audio D30:F2) ......................63319.1.16 CAP_PTR Capabilities Pointer Register (Audio D30:F2) .......................63319.1.18 INT_PN Interrupt Pin Register (Audio D30:F2) ..................................634


19.1.19 PCID Programmable Codec Identification Register(Audio D30:F2) .............................................................................. 634

19.1.21 PID PCI Power Management Capability IdentificationRegister (Audio D30:F2) .................................................................. 635

19.1.22 PC Power Management Capabilities Register (Audio D30:F2) .............................................................................. 635

19.1.23 PCS Power Management Control and Status Register(Audio D30:F2) .............................................................................. 636

19.2 AC97 Audio I/O Space (D30:F2) ....................................................................... 63619.2.1 X_BDBAR Buffer Descriptor Base Address Register

(Audio D30:F2) .............................................................................. 63919.2.2 X_CIV Current Index Value Register (Audio D30:F2) ......................... 64019.2.3 X_LVI Last Valid Index Register (Audio D30:F2) ............................... 64019.2.6 X_PIV Prefetched Index Value Register (Audio D30:F2) ..................... 64219.2.9 GLOB_STA Global Status Register (Audio D30:F2) ............................ 64519.2.10 CAS Codec Access Semaphore Register (Audio D30:F2)..................... 64719.2.11 SDM SDATA_IN Map Register (Audio D30:F2) .................................. 647

20 AC97 Modem Controller Registers (D30:F3).......................................................... 64920.1 AC97 Modem PCI Configuration Space (D30:F3) ................................................. 649

20.1.1 VID Vendor Identification Register (Modem D30:F3) ......................... 65020.1.2 DID Device Identification Register (Modem D30:F3).......................... 65020.1.3 PCICMD PCI Command Register (Modem D30:F3) ............................ 65020.1.5 RID Revision Identification Register (Modem D30:F3) ....................... 65120.1.7 SCC Sub Class Code Register (Modem D30:F3) ................................ 65220.1.8 BCC Base Class Code Register (Modem D30:F3) ............................... 65220.1.9 HEADTYP Header Type Register (Modem D30:F3) ............................. 65220.1.10 MMBAR Modem Mixer Base Address Register

(Modem D30:F3) ............................................................................ 65220.1.11 MBAR Modem Base Address Register (Modem D30:F3)...................... 65320.1.12 SVID Subsystem Vendor Identification Register

(Modem D30:F3) ............................................................................ 65320.1.14 CAP_PTR Capabilities Pointer Register (Modem D30:F3) .................... 65420.1.15 INT_LN Interrupt Line Register (Modem D30:F3) .............................. 65420.1.16 INT_PIN Interrupt Pin Register (Modem D30:F3) .............................. 65420.1.17 PID PCI Power Management Capability Identification

Register (Modem D30:F3) ................................................................ 65520.1.18 PC Power Management Capabilities Register

(Modem D30:F3) ............................................................................ 65520.1.19 PCS Power Management Control and Status Register

(Modem D30:F3) ............................................................................ 65520.2 AC97 Modem I/O Space (D30:F3) ..................................................................... 656

20.2.1 X_BDBAR Buffer Descriptor List Base Address Register(Modem D30:F3) ............................................................................ 658

20.2.2 X_CIV Current Index Value Register (Modem D30:F3)....................... 65820.2.3 X_LVI Last Valid Index Register (Modem D30:F3)............................. 65820.2.4 X_SR Status Register (Modem D30:F3) ........................................... 65920.2.5 X_PICB Position in Current Buffer Register

(Modem D30:F3) ............................................................................ 66020.2.6 X_PIV Prefetch Index Value Register

(Modem D30:F3) ............................................................................ 66020.2.7 X_CR Control Register (Modem D30:F3).......................................... 66020.2.8 GLOB_CNT Global Control Register (Modem D30:F3) ........................ 66120.2.9 GLOB_STA Global Status Register (Modem D30:F3) .......................... 66220.2.10 CAS Codec Access Semaphore Register

(Modem D30:F3) ............................................................................ 664

21 LPC Interface Bridge Registers (D31:F0) ............................................................... 665


21.1 PCI Configuration Registers (LPC I/F D31:F0) ...................................................66521.1.1 VID Vendor Identification Register (LPC I/F D31:F0)..........................66621.1.2 DID Device Identification Register (LPC I/F D31:F0) ..........................66621.1.3 PCICMD PCI COMMAND Register (LPC I/F D31:F0) ............................66621.1.4 PCISTS PCI Status Register (LPC I/F D31:F0) ...................................66721.1.5 RID Revision Identification Register (LPC I/F D31:F0) ........................66721.1.6 PI Programming Interface Register (LPC I/F D31:F0) .........................66821.1.7 SCC Sub Class Code Register (LPC I/F D31:F0).................................66821.1.8 BCC Base Class Code Register (LPC I/F D31:F0) ...............................66821.1.9 PLT Primary Latency Timer Register (LPC I/F D31:F0) .......................66821.1.10 HEADTYP Header Type Register (LPC I/F D31:F0) .............................66821.1.11 SS Sub System Identifiers Register (LPC I/F D31:F0) ........................66821.1.12 PMBASE ACPI Base Address Register (LPC I/F D31:F0) ......................66921.1.13 ACPI_CNTL ACPI Control Register (LPC I/F D31:F0)...........................66921.1.14 GPIOBASE GPIO Base Address Register (LPC I/F D31:F0).................67021.1.15 GC GPIO Control Register (LPC I/F D31:F0)......................................67021.1.16 PIRQ[n]_ROUT PIRQ[A,B,C,D] Routing Control Register

(LPC I/F D31:F0).............................................................................67021.1.17 SIRQ_CNTL Serial IRQ Control Register

(LPC I/F D31:F0).............................................................................67121.1.18 PIRQ[n]_ROUT PIRQ[E,F,G,H] Routing Control Register

(LPC I/F D31:F0).............................................................................67121.1.19 LPC_I/O_DEC I/O Decode Ranges Register

(LPC I/F D31:F0).............................................................................67221.1.20 LPC_EN LPC I/F Enables Register (LPC I/F D31:F0) ...........................67221.1.21 GEN1_DEC LPC I/F Generic Decode Range 1 Register

(LPC I/F D31:F0).............................................................................67321.1.22 GEN2_DEC LPC I/F Generic Decode Range 2 Register

(LPC I/F D31:F0).............................................................................67421.1.23 FWH_SEL1 Firmware Hub Select 1 Register

(LPC I/F D31:F0).............................................................................67421.1.24 FWH_SEL2 Firmware Hub Select 2 Register

(LPC I/F D31:F0).............................................................................67521.1.25 FWH_DEC_EN1 Firmware Hub Decode Enable Register

(LPC I/F D31:F0).............................................................................67521.1.26 BIOS_CNTL BIOS Control Register

(LPC I/F D31:F0).............................................................................67721.1.27 RCBA Root Complex Base Address Register

(LPC I/F D31:F0).............................................................................67721.2 DMA I/O Registers (LPC I/F D31:F0)................................................................677

21.2.1 DMABASE_CA DMA Base and Current Address Registers (LPC I/F D31:F0) ...............................................................679

21.2.2 DMABASE_CC DMA Base and Current Count Registers(LPC I/F D31:F0).............................................................................679

21.2.3 DMAMEM_LP DMA Memory Low Page Registers (LPC I/F D31:F0).............................................................................680

21.2.4 DMACMD DMA Command Register (LPC I/F D31:F0)..........................68021.2.5 DMASTA DMA Status Register (LPC I/F D31:F0)................................68121.2.6 DMA_WRSMSK DMA Write Single Mask Register

(LPC I/F D31:F0).............................................................................68121.2.7 DMACH_MODE DMA Channel Mode Register

(LPC I/F D31:F0).............................................................................68221.2.8 DMA Clear Byte Pointer Register (LPC I/F D31:F0) ...............................68221.2.9 DMA Master Clear Register (LPC I/F D31:F0).......................................68321.2.10 DMA_CLMSK DMA Clear Mask Register (LPC I/F D31:F0)....................68321.2.11 DMA_WRMSK DMA Write All Mask Register

(LPC I/F D31:F0).............................................................................68321.3 Timer I/O Registers (LPC I/F D31:F0) ..............................................................683


21.3.1 TCW Timer Control Word Register (LPC I/F D31:F0).......................... 68421.3.2 SBYTE_FMT Interval Timer Status Byte Format Register

(LPC I/F D31:F0) ............................................................................ 68521.3.3 Counter Access Ports Register (LPC I/F D31:F0).................................. 686

21.4 8259 Interrupt Controller (PIC) Registers (LPC I/F D31:F0) .......................................................................................... 68621.4.1 Interrupt Controller I/O MAP (LPC I/F D31:F0).................................... 68621.4.2 ICW1 Initialization Command Word 1 Register

(LPC I/F D31:F0) ............................................................................ 68721.4.3 ICW2 Initialization Command Word 2 Register

(LPC I/F D31:F0) ............................................................................ 68821.4.4 ICW3 Master Controller Initialization Command

Word 3 Register (LPC I/F D31:F0) ..................................................... 68821.4.5 ICW3 Slave Controller Initialization Command

Word 3 Register (LPC I/F D31:F0) ..................................................... 68921.4.6 ICW4 Initialization Command Word 4 Register

(LPC I/F D31:F0) ............................................................................ 68921.4.7 OCW1 Operational Control Word 1 (Interrupt Mask)

Register (LPC I/F D31:F0) ................................................................ 68921.4.8 OCW2 Operational Control Word 2 Register

(LPC I/F D31:F0) ............................................................................ 69021.4.9 OCW3 Operational Control Word 3 Register

(LPC I/F D31:F0) ............................................................................ 69021.4.10 ELCR1 Master Controller Edge/Level Triggered Register

(LPC I/F D31:F0) ............................................................................ 69121.4.11 ELCR2 Slave Controller Edge/Level Triggered Register

(LPC I/F D31:F0) ............................................................................ 69221.5 Advanced Programmable Interrupt Controller (APIC)(D31:F0) ............................... 692

21.5.1 APIC Register Map (LPC I/F D31:F0).................................................. 69221.5.2 IND Index Register (LPC I/F D31:F0) .............................................. 69321.5.3 DAT Window Register (LPC I/F D31:F0)........................................... 69321.5.4 EOIR EOI Register (LPC I/F D31:F0) ............................................... 69321.5.5 ID Identification Register (LPC I/F D31:F0)...................................... 69421.5.6 VER Version Register (LPC I/F D31:F0) ........................................... 69421.5.7 REDIR_TBL Redirection Table (LPC I/F D31:F0) ................................ 695

21.6 Real Time Clock Registers (LPC I/F D31:F0) ..................................................... 69621.6.1 I/O Register Address Map (LPC I/F D31:F0)........................................ 69621.6.2 Indexed Registers (LPC I/F D31:F0) .................................................. 697

21.7 Processor Interface Registers (LPC I/F D31:F0) ................................................ 70021.7.1 NMI_SC NMI Status and Control Register

(LPC I/F D31:F0) ............................................................................ 70021.7.2 NMI_EN NMI Enable (and Real Time Clock Index)

Register (LPC I/F D31:F0) ................................................................ 70121.7.3 PORT92 Fast A20 and Init Register (LPC I/F D31:F0) ........................ 70121.7.4 COPROC_ERR Coprocessor Error Register

(LPC I/F D31:F0) ............................................................................ 70221.7.5 RST_CNT Reset Control Register (LPC I/F D31:F0)............................ 702

21.8 Power Management Registers (PM D31:F0) ...................................................... 70221.8.1 Power Management PCI Configuration Registers

(PM D31:F0) .................................................................................. 70221.8.2 Power Management I/O Registers ........................................................ 708

21.9 System Management

Intel 631xESB/632xESB I/O Controller Hub€¦ · · 2015-09-25standalone microcontroller with...

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