Integrated Circuits & Systems - UFSCguntzel/ine5442/slides/CSI-lecture-6...Lecture 6 CMOS...
Transcript of Integrated Circuits & Systems - UFSCguntzel/ine5442/slides/CSI-lecture-6...Lecture 6 CMOS...
Lecture 6 CMOS Fabrication Process & Design Rules
Prof. José Luís Güntzel [email protected]
Integrated Circuits & Systems INE 5442
Federal University of Santa Catarina Center for Technology
Computer Science & Electronics Engineering
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.2
N-channel (or NMOS) transistor
P-channel (or PMOS) transistor
Polysilicon (poly)
N well
Layout for CMOS Inverter (typical P substrate 0.35 µm tech.)
Active areas
P implant (drain & source)
N implant (drain & source)
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.3
NMOS transistor PMOS transistor
Polysilicon (poly)
N well
Layout for CMOS Inverter
P implant (drain & source)
N implant (drain & source)
Active area & P implant (well contact)
Active area & P implant
(substrate contact)
Active areas
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.4
NMOS transistor PMOS transistor
Polysilicon
Metal 1
Contact holes
Layout for CMOS Inverter
Metal 2
Via 1
Gnd Vdd
Gnd Vdd
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.5
NMOS transistor PMOS transistor
Layout for CMOS Inverter To study the CMOS process steps, we will disregard substrate and well contacts
Poly
N well P implant
(drain & source)
N implant (drain & source)
Gnd Vdd
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.6
NMOS transistor PMOS transistor Layout vs. AA’ Cross on Fabricated Structure
N well Field oxide
Transistor gate (poly)
P substrate
N implant
Transistor gate (poly)
Field oxide Field oxide
Gate (thin) oxide
Gate (thin) oxide P implant
Metal 1 Metal 2
A A’
Isolation oxide
N.B.: oxide = SiO2
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.7
N Well Creation
P substrate
Silicon oxide (SiO2)
Thickness of substrate is between 0.5 and 1.0 mm
A thin layer (“film”) of oxide (SiO2), typically with 10nm, is deposited through dry oxidation (which is slow, but allows for a good thickness control)
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.8
N Well Creation
P substrate
Silicon oxide (SiO2)
Silicon nitride (Si3N4)
A thicker layer (“film”) of “sacrificial” silicon nitride (Si3N4) is deposited through Plasma CVD (Chemical Vapor Deposition)
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.9
N Well Creation
P substrate
Silicon oxide (SiO2)
Silicon nitride (Si3N4)
Photolithography using N well mask: 1. Spin deposition of photoresist (~1µm) 2. Wafer is put in oven to dry photoresist 3. Wafer surface is exposed to UV light through N well optical mask
Optical mask with N well pattern (Negative) photoresist
UV light
“N well layer” (pattern)
A A’
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.10
N Well Creation
P substrate
Silicon oxide (SiO2)
Silicon nitride (Si3N4)
Photolithography using N well mask: 4. Unexposed photoresist is removed by using organic solvent 5. Wafer is “soft baked” at low temperature to hard remaining photoresist
Remaining photoresist
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.11
N Well Creation
P substrate
Silicon oxide (SiO2)
Silicon nitride (Si3N4)
Nitride is selectively removed by plasma etching (photoresist serves as coat)
Remaining photoresist
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.12
N Well Creation
P substrate
Silicon oxide (SiO2)
Silicon nitride (Si3N4)
Remaining photoresist
Nitride is selectively removed by plasma etching (photoresist serves as coat)
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.13
N Well Creation
P substrate
Silicon oxide (SiO2)
Silicon nitride (Si3N4)
Remaining photoresist is removed with a mixture of acids
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.14
N Well Creation
P substrate
Silicon oxide (SiO2)
Silicon nitride (Si3N4)
N well is formed by ion implantation: • Nitride is used as protecting coat
• Ions traverse oxide film
Ion implantation (N-type dopant)
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.15
N Well Creation
P substrate
Silicon oxide (SiO2)
Silicon nitride (Si3N4)
N well is formed by ion implantation: • Nitride is used as protecting coat • Ions traverse oxide film
N well
Ion implantation (N-type dopant)
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.16
N Well Creation
P substrate
Silicon oxide (SiO2)
Silicon nitride (Si3N4)
N well
Nitride is selectively removed by plasma etching
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.17
N Well Creation
P substrate
N well
Oxide is removed by using Hydrofluoric acid (HF) The wafer is cleaned (SDR - spin, rinse and dry with nitrogen)
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.18
Field Oxide Growth
P substrate
N well
There are two types of regions ion wafer surface: • Active area (where transistors are)
• Field area (must isolate transistors)
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.19
Field Oxide Growth
P substrate
N well
Silicon oxide (SiO2)
Silicon nitride (Si3N4)
After oxide and nitride deposition (similar to N well creation step), photolithography is performed with an optical mask containing the negative of active area pattern.
optical mask with negative pattern of active area
UV light
“Active area” layer (pattern)
A A’
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.20
Field Oxide Growth
P substrate
N well
Silicon oxide (SiO2)
Silicon nitride (Si3N4)
Wet oxidation is used to grow a thick layer of oxide, that will serve as isolation between transistors
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.21
Field Oxide Growth
P substrate
N well
Silicon oxide (SiO2)
Silicon nitride (Si3N4)
Wet oxidation is used to grow a thick layer of oxide (with a few hundreds of nanometers), that will serve as isolation between transistors
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.22
Field Oxide Growth
P substrate
N well
Nitride is selectively removed by plasma etching Oxide is removed by using Hydrofluoric acid (HF) The wafer is cleaned (SDR - spin, rinse and dry with nitrogen)
“Field oxide”
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.23
Field Oxide Growth
P substrate
N well
Nitride is selectively removed by plasma etching Oxide is removed by using Hydrofluoric acid (HF) The wafer is cleaned (SDR - spin, rinse and dry with nitrogen)
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.24
Gate Oxide Formation
P substrate
N well
Wafer surface is submitted to dry oxidation to grow a thin film of oxide (~100 Angstrom), referred to as “gate oxide”
“Gate oxide”
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.25
Polysilicon Deposition
P substrate
N well
Poly is deposited by CVD process using silane gas
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.26
Polysilicon Deposition
P substrate
N well
Transistor gate pattern pattern is “printed” on wafer surface by using photolithography.
optical mask with negative pattern of poly
UV light
“Poly” layer (pattern)
A A’
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.27
Polysilicon Deposition
P substrate
N well
UV light
“Poly” layer (pattern)
Transistor gate pattern pattern is “printed” on wafer surface by using photolithography.
A A’
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.28
Polysilicon Deposition
P substrate
N well
Non-exposed poly is selectively removed by etching. The photoresist serves as coating.
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.29
Polysilicon Deposition
P substrate
N well
Non-exposed poly is selectively removed by etching
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.30
Polysilicon Deposition
P substrate
N well
Non-exposed thin oxide is selectively removed by etching
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.31
Polysilicon Deposition
P substrate
N well
Non-exposed thin oxide is selectively removed by etching
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.32
PMOS Transistor Drain and Source Creation
P substrate
N well
P implant pattern is “printed” on wafer surface by using photolithography.
Optical mask with P implant pattern
UV light
“P implant” layer (pattern)
A A’
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.33
PMOS Transistor Drain and Source Creation
P substrate
N well
P implant pattern is “printed” on wafer surface by using photolithography.
Optical mask with P implant pattern
UV light
“P implant” layer (pattern)
A A’
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.34
PMOS Transistor Drain and Source Creation
P substrate
N well
P-type dopants are implanted through ion implantation. Photoresist serves as coating
Ion implantation (P-type dopant)
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.35
PMOS Transistor Drain and Source Creation
P substrate
N well
P-type dopants are implanted through ion implantation. Photoresist serves as coating
Ion implantation (P-type dopant)
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.36
PMOS Transistor Drain and Source Creation
P substrate
N well
Remaining photoresist is removed with a mixture of acids
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.37
PMOS Transistor Drain and Source Creation
P substrate
N well
Remaining photoresist is removed with a mixture of acids
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.38
NMOS Transistor Drain and Source Creation
P substrate
N well
N implant pattern is “printed” on wafer surface by using photolithography.
“N implant” layer (pattern)
Optical mask with N implant pattern
UV light A A’
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.39
NMOS Transistor Drain and Source Creation
P substrate
N well
N implant pattern is “printed” on wafer surface by using photolithography.
“N implant” layer (pattern)
Optical mask with N implant pattern
UV light A A’
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.40
NMOS Transistor Drain and Source Creation
P substrate
N well
N-type dopants are implanted through ion implantation Photoresist serves as coating
Ion implantation (N-type dopant)
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.41
NMOS Transistor Drain and Source Creation
P substrate
N well
N-type dopants are implanted through ion implantation Photoresist serves as coating
Ion implantation (N-type dopant)
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.42
NMOS Transistor Drain and Source Creation
P substrate
N well
Remaining photoresist is removed with a mixture of acids
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.43
NMOS Transistor Drain and Source Creation
P substrate
N well
Remaining photoresist is removed with a mixture of acids
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.44
Isolation Oxide Deposition
P substrate
N well
A thick film of oxide is deposited through CVD
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.45
Contact Wholes Opening
P substrate
N well
Contact holes are “printed” on wafer surface by using photolithography.
“Contact” layer (pattern)
Optical mask with contacts pattern
UV light A A’
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.46
Contact Wholes Opening
P substrate
N well
Contact holes are “printed” on wafer surface by using photolithography.
“Contact” layer (pattern)
Optical mask with contacts pattern
UV light A A’
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.47
Contact Wholes Opening
P substrate
N well
Contact holes are dug on isolation oxide through etching
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.48
Contact Wholes Opening
P substrate
N well
Contact holes are dug on isolation oxide through etching
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.49
Contact Wholes Opening
P substrate
N well
Remaining photoresist is removed
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.50
Contact Wholes Opening
P substrate
N well
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.51
Metal 1 Deposition
P substrate
N well
Metal 1 is deposited through sputtering
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.52
Metal 1 Deposition
P substrate
N well
Undesired metal 1 is removed, leaving only desired connections
“Metal 1” layer (pattern)
Optical mask with metal 1 pattern
UV light A A’
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.53
Metal 1 Deposition
P substrate
N well
Undesired metal 1 is removed, leaving only desired connections
“Metal 1” layer (pattern)
Optical mask with metal 1 pattern
A A’ UV light
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.54
Metal 1 Deposition
P substrate
N well
Undesired metal 1 is removed through etching
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.55
Metal 1 Deposition
P substrate
N well
Undesired metal 1 is removed through etching
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.56
Metal 1 Deposition
P substrate
N well
Photoresist is removed
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.57
P substrate
N well
Isolation Oxide Deposition
Another thick film of oxide is deposited through CVD to isolate metal 1 from metal 2
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.58
P substrate
N well
Similarly to metal 1 deposition
Metal 2 Deposition
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.59
NMOS transistor PMOS transistor Layout vs. AA’ Cross on Fabricated Structure
N well
P substrate
A A’
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.60
Conexões em cobre 0,11µm IBM
Fonte: Rabaey; Chandrakasan; Nikolic, 2003
Metal Layers in a Contemporary Technology
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.61
Dual-Well Trench-Isolated CMOS Process (Current)
Source: Rabaey; Chandrakasan; Nikolic, 2003
Epitaxial layer: Single-crystal film grown on silicon surface with controlled impurities, that can have fewer defects than native wafer surface.
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.62
Final Result
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.63
CMOS Process Layers Layer Color
N Well Gray Active Area Green N+ implant (N+ select) Yellow P+ implant (P+ select) Orange Polysilicon Red Metal 1 Medium blue Metal 2 Light blue Contact to drain/source Black Contract to polysilicon Black Via Light Gray
Colors may vary according to Foundry/technology/layout editor
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.64
W
L
1
1: mínima extensão da porta (poli) fora da área ativa
2: mínima extensão do implante fora da área ativa
2
L
1
W
2
3
4
3: mínima distância entre implante N e implante P
4: mínima distância entre implante N (área ativa) e poço N
Fonte: Fernanda Kastensmidt, EMicro2005
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.65
1: mínima largura de metal 1 2: mínima distância entre metal 1 3: mínima largura de metal 2 4: mínima distância entre metal 2 5: mínima largura do contado 6: mínima extensão de metal 1
para fora do contato 7: mínima distância entre contatos 8: mínima largura de via 9: mínima extensão de metal 2
para fora da via 10: mínima extensão de metal 1
para fora da via
1
2
3
4
5 6
7
8 9
10
Fonte: Fernanda Kastensmidt, EMicro2005
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.66
A
A B
B
Conectando Transistores em Série
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.67
A
A B
B
Conectando Transistores em Série
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.68
A B
X Y
X=Y se A=1 E B=1
A B
X Y
Conectando Transistores em Série
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.69
A A B B
X
Y
Conectando Transistores em Paralelo
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.70
X
A B
X
Y A B
X
Y
Problema: capacitância da “difusão” é muito grande!
Conectando Transistores em Paralelo
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.71
Solução: usar metal para conexões, sempre que possível!
X=Y se A=1 OU B=1
A B
X
Y A B
X
Y
Conectando Transistores em Paralelo
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.72
Dois Transistores em Série em Tecnol. 350nm
0,4µm
Lmin = 0.35µm
minimum contact spacing =0,4µm
0,45µm
0,4µm b
b
0,4µm
Lmin = 0.35µm
0,45µm
0,4µm
0,4µm a
b
b
0,4µm a
0,4µm
0,4µm
a=0,3µm (minimum diffusion contact to gate spacing) b=0,15µm (minimum diffusion enclosure to contact)
Two transistors in series with wider chanels (asuming typical 0.35 µm CMOS Design Rules)
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.73
in out
A Typical 350nm CMOS Inverter
0,4µm
0,4µm b
b
0,4µm
0,4µm
0,4µm b
b
Vdd
Gnd
PMOS: W=Wmin=0.35µm L=1.5 µm
NMOS: W=Wmin=0.35µm L=0.7 µm
in out
a=0,3µm (minimum diffusion contact to gate spacing)
b=0,15µm (minimum diffusion enclosure to contact)
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.74
in out
V DD
GND
in out
Another Inverter Layout
Polysilicon to connect PMOS to NMOS gate
Metal 1 to connect PMOS and NMOS drains
A given layout for a logic gate is referred to as “cell”
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.75
A
S
V DD
GND
B
A S
B
A B
Vdd
2-Input NAND Cell
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.76
A
V DD
GND
B
S
A
S
B
A
B
Vdd
2-Input NOR Cell
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.77
Standard Cells
in
Out
V DD
GND
A
V DD
GND
B
S
A
S
V DD
GND
B
Circuit layout is assembled by using pre-designed cell layouts made available in a library (“cell library”)
inversor nor2 nand2 ...
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.78
Standard Cell-Based Circuit Structure
Cells laid out in strips
VCC
GND
cells
roteamento sobre os transistores, em M2, M3, ...
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.79
Standard Cell-Based Circuit Structure
CMOS Fabrication Process & Design Rules
Lecture 6 – 2012/2 Prof. José Luís Güntzel
INE/CTC/UFSC Integrated Circuits and Systems Slide 6.80
References
1. RABAEY, J; CHANDRAKASAN, A.; NIKOLIC, B. Digital Integrated Circuits: a design perspective. 2nd Edition. Prentice Hall, 2003. ISBN: 0-13-090996-3.
2. JAEGER, Richard C. “Introduction to Microelectronic Fabrication” 2nd Edition. (Modular Series on Solid State Devices, Vol V), Prentice Hall, 2002.
3. REIS, Ricardo.(Organizador.) Concepção de Circuitos Integrados. Porto Alegre: Sagra-Luzzatto/UFRGS, 2002. 2a edição. Cap. 3. ISBN 85-241-0625-5