Int. J. Elec&Electr.Eng&Telecoms. 2012 Anjana R and Ajay ... · biased keeper, Sleepy keeper, BSIM...

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Int. J. Elec&Electr.Eng&Telecoms. 2012 Anjana R and Ajay Kumar Somkuwar, 2012

MINIMIZING THE SUB THRESHOLDLEAKAGE FOR HIGH PERFORMANCE CMOSCIRCUITS USING NOVEL STACKED SLEEP

TRANSISTOR TECHNIQUE

Anjana R1* and Ajay Kumar Somkuwar2

This paper presents a technique for minimizing sub threshold leakage current using stackedsleep technique. Comparison is made with conventional CMOS, Sleepy stack, Forced stack,Sleepy keeper and the proposed body biased keeper which were analyzed using BSIM 4 model.The proposed technique dissipates lesser static power and lesser delay product compared tothe previous technique. An improvement of 1.2X was observed in static power dissipation incomparison with conventional approach, thus maintaining the state of art of the logic in thedigital circuit.

Keywords: Sub threshold leakage, Conventional CMOS, Sleepy stack, Forced stack, Bodybiased keeper, Sleepy keeper, BSIM 4

INTRODUCTIONWith ever increasing in high speedcomputation and battery operated devices likelaptops, tablet, palmtops, note books etc.,power consumption has become majorconcern in very large scale integration (VLSI)systems. Also power consumption is majorconcern in deep sub micron technologies.According to Moore’s law “number oftransistor increases exponentially double everytwo years” (Borkar, 2001; and Srivastava etal., 1998). Thus shrinkage in size and addition

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Int. J. Elec&Electr.Eng&Telecoms. 2012

1 Department of Electronics and Communication, Laxmi Institute of Technology, Sarigam, Gujarat.2 Department of Electonics and Communication, MANIT, Bhopal, MP.

Research Paper

*Corresponding Author: Anjana R,[email protected]

of large function in an integrated circuit givesmore power dissipation. Power consumptionin VLSI circuits includes static (or leakage)and dynamic power dissipation, short circuitpower dissipation. Switching power whichincludes both short circuit and dynamic poweris consumed when the charging anddischarging of the capacitance takes place.Leakage power is due sub threshold leakageand reverse biased diode.

Thus total power consumed by the circuit isgiven by,

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Ptotal

= Pdynamic

+ Pshort-circuit

+ Pleakage

...(1)

Thus, the leakage power becomes the keyto low power design. Leakage power isdissipated when the transistor is in standbymode or in sleep mode. Even though transistoris in stable state, it produces small leakagecurrent at the junctions and also reverse biaseddiode is the major contributor of this leakagecurrent (Figure 1).

Figure 1: Components of Leakage Power

Source: Rabaey (1996)

This paper thus concentrates on reducingthe leakage power at the dynamic node byplacing the body biased keeper. By thisapproach 1.2X power dissipation wasobserved in comparison with previousapproaches.

RELATED WORKIn this section the previously appliedtechniques for sub threshold reduction arebriefed.

A. Conventional CMOS Technique (Mutoh S et al., 1995)

Figure 2 shows the block diagram ofconventional CMOS logic. In this approach,Pull up network is designed using PMOStransistors and Pull down network is designedusing NMOS transistors. PMOS/NMOS arerepresented in parallel/series for product and

sum term. PMOS is connected to power supplyand NMOS is connected to ground.

Figure 2: Conventional CMOS Technique

Source: Mutoh S et al. (1995)

B. Sleep Transistor technique (Powell et al., 2000; and Park et al., 2004)

Figure 3 shows the block diagram of sleeptransistor technique. A sleep PMOS transistoris placed between power supply V

dd and the

pull up network. Similarly sleep NMOStransistor is placed between ground and pulldown network. The sleep transistors functionin such a way that they are turned on duringthe active mode and turned off during the sleep/in active mode. This technique reduces the subthreshold leakage by isolating the gates frompower supply and ground. Hence thistechnique is also termed as state destructivetechnique as there is loss in the present statelogic.

Figure 3: Sleep Transistor Technique

Source: Powell et al. (xxxx) and Park et al. (2004)

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C. Forced Stack Technique (Narendra et al., 2001)

Figure 4 shows the block diagram of stackapproach. In this approach, the circuit isdivided and stacked into two half width of thetotal transistor size. When these are stackedtogether, the simultaneously turn on and off.Thus reducing the sub threshold leakagecurrent. But the overall delay of the circuitincreases as the number of transistorincreases.

Figure 4: Forced Stack Technique

Source: Narendra et al. (2001)

D. Sleepy Stack Technique (Park, 2005; and Kao and Chandra- kasan, 2001)

Figure 5 shows the block diagram of sleepystack approach. It combines sleep transistorand stack technique. Hence they are called assleep transistor technique. Here the sleepPMOS is placed parallel to pull up network andsleep NMOS is placed parallel to pull downnetwork. The sleep transistors action are sameas in sleep transistor technique. Since sleeptransistors are always on in active mode thereis current flow in the circuit and hence hasfaster switching time than stack approach.Here high Vth transistors are used as sleep

transistors. As high Vth transistors are usedleakage is substancially reduced.

Figure 5: Sleepy Stack Technique

Source: Park (2005) and Kao and Chandrakasan (2001)

E. Sleepy Keeper Technique (Se Hun Kim and Mooney, 2006)

Figure 6 shows the block diagram of sleepykeeper technique. It is the improved versionof sleep approach. In this technique, anadditional high V

t NMOS transitor is added in

parallel with sleep PMOS transistor and highVt NMOS is added in parallel with sleepPMOS. In sleep mode, sleep transistors areis cut off state. So, when sleep signal isasserted, the high V

t NMOS transistor

connected in parallel with the sleep PMOS

Figure 6: Sleepy Keeper Technique

Source: Se Hun Kim and Mooney (2006)

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transistor is the only source of Vdd to the pullupnetwork and the high V

t PMOS transistor

connected in parallel with the sleep NMOStransistor provides the path to connect thepulldown network with the ground. Thus themajor advantage of this approach is it reducesthe leakage power thereby maintaining thelogic state of the circuit.

METHODOLOGYIn this paper, we present stacked sleeptransistor technique. In this sleep transistor wasgetting stacked, which reduces the leakagecurrent to great extent. This technique uses twostacked sleep transistors in power supply railsand two stacked sleep transistor in ground.Thus leakage reduction takes place in twosteps. Firstly, due to stack effect of sleeptransistor and secondly due to sleep transistoritself. It is well known fact that NMOS are notefficient in passing the power supply. But inthis technique, stacked sleep transistor usespmos in the power supply and NMOS in theground for maintaining exact logic state of thecircuit (Figure 6).

Figure 6: Proposed StackedSleep Approach

Let us maintain the value of logic 1 in sleepmode. During standby mode, sleep = 0 andsleep bar = 1 is asserted. The stacked sleepapproach uses this pmos to get connected topower supply and nmos to be connected theground. This is the reason why the pmos/nmosis placed in parallel to the sleep transistor.When in sleep mode this pmos is the onlysource of power supply to pull up network.

Let us now maintain the value of logic 0 inthe sleep mode. During this mode, sleep = 1and sleep bar = 0 is asserted. The stackedsleep trannsistor uses this logic 0 output tomaintain the nmos transistor connected toground ad maintain the logic state equal tologic 0 at the output. Thus when in sleep modenmos transistor, is the only source of groundto pull down network as the sleep transistorare turned on.

SIMULATION RESULTSMicrowind EDA tool was used for the layoutand the simulation of two input NAND gate wasdone using BSIM 4 MOSFET model in 1.2 nmtechnology. Performance characteristics suchas static power dissipation, dynamic powerdissipation, propagation delay and powerdelay products in static and dynamicconditions were observed using conventionalCMOS, Stack, Sleep and Sleepy keepertechniques at a temperature of 27 0C and aSupply voltage, VDD of 1.2 V.

The threshold voltage of MOS transistorincreases with increase in its channel lengthmodulation. So the channel length of highthreshold transistor and sleep transistor wasmaintained larger than low threshold transistor

in stacked sleep approach. The probable input

combinations are shown in table 1.

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Table 1: Combination of Input Vector

a b Sleep ~Sleep

0 0 0 1

0 0 1 0

0 1 0 1

0 1 1 0

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 0

The minimum leakage was found during theinitial state when the input vectors aremaintained at logic 0. The static powerdissipation is calculated as the average ofpower dissipation for all the input vectorcombination. The dynamic power dissipationwas calculated by applying the clock signalsto the input at the temperature of 270C.

Figure 8: Waveformwith Input Vector(1,0,1)

Figure 9: Waveformwith Input Vector(1,1,0)

PERFORMANCE COMPARISONComparitive analysis is done on NAND2 as thebenchmark circuit. Static power dissipation ofthe NAND2 gate was 0.048 W using theconventional CMOS technique while only 0.032W static power was dissipated using theStacked sleep technique. Figures 11 and 12shows the comparision among different logicsfor static and dynamic power consumption.

Figure 11: Static and DynamicPower Consumption

Po

we

r in

Mic

ro W

att

Figure 10: Layout of aTwo Input NAND Gate

Waveforms for input vector combinations isshown in the Figure 8 and 9. Figure 10 shownthe layout of two input nand gate.

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Figure 12: Static and DynamicPower Delay Product

Po

wer

in

E-1

9

Static power delay product of conventionallogic gate and the proposed technique is foundto be 0.4304 x 10-19 J and 0.42 x 10-19 Jrespectively.

CONCLUSIONPerformance characteristics such as staticpower dissipation, dynamic power dissipation,power, delay, power delay product wasanalyzed for the conventional CMOS logic,stack, sleeper, sleepy stack, sleepy keeperwith the proposed stacked sleep approach in1.2 nm technology. By experimental result itwas found that there was 1.2 X improvementin the power dissipation with the stackedsleeper technique.

REFERENCES1. Borkar S (2001), “Low Power Design

Challenges for the Decade”, Proceedingsof the IEEE/ACM Design AutomationConference, pp. 293-296, June.

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Solid-State Circuits, Vol. 27, No. 4, pp.473-484.

3. Deepaksubramanyan B S and Nunez A(2007), “Analysis of Sub thresholdLeakage Reduction in CMOS DigitalCircuits”, Proceedings of the 13th NASASymposium on VLSI Design, Post Falls,Idaho, USA, June 5-6, pp. 1-8.

4. Johnson M, Somasekhar D, Chiou L-Yand Roy K (2002), “Leakage Control withEfficient Use of Transistor Stacks inSingle Threshold CMOS”, IEEETransactions on VLSI Systems, Vol. 10,No. 1, pp. 1-5.

5. Kao J and Chandrakasan A (2001),“MTCMOS sequential circuits”, Proc. OfEuropean Solid-State Circuits Conf.,September, pp. 332-335.

6. M S Islam et al. (2010), “Dual StackMethod: A Novel Approach to LowLeakage and Speed Power ProductVLSI Design”, Proc. ICECE2010, 18-20December, pp. 89-92, Dhaka, Bangladesh.

7. Mutoh S et al. (1995), “1-V Power SupplyHigh-speed Digital Circuit Technologywith Multi threshold-Voltage CMOS”,IEEE Journal of Solid-State Circuits, Vol.30, No. 8, pp. 847-854.

8. Narendra S S, Borkar V D, Antoniadis Dand Chandrakasan A (2001), “Scaling ofStack Effect and its Application forLeakage Reduction”, Proceedings of148 the International Symposium onLow Power Electronics and Design,August, pp. 195-200.

9. Nittaranjan Karmakar, Mehdi Z Sadi, Md.Khorshed Alam and Islam1 M S (2009),

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“A Novel Dual Sleep Approach to LowLeakage and Area Efficient VLSIDesign”, IEEE-RSM Proc., Kota Bahru,Malaysia.

10. Nose K and Sakurai T (2000), “Analysisand Future Trend of Short-Circuit Power”,IEEE Transactions on Computer-AidedDesign of Integrated Circuits andSystems, Vol. 19, No. 9, pp. 1023-1030.

11. Pal P K, Rathore R S, Rana A K and SainiG (2010), “New low-power techniques:Leakage Feedback with Stack & SleepStack with Keeper”, InternationalConference on Computer andCommunication Technology (ICCCT),pp. 296-301.

12. Park J (2005), “Sleepy Stack: a NewApproach to Low Power VLSI andMemory,” Ph.D. Dissertation, School ofElectrical and Computer Engineering,Georgia Institute of Technology, 2005,[Online], available http://etd.gatech.edu/theses.

13. Park J C, Mooney III V J andPfeiffenberger P (2004), “Sleepy StackReduction of Leakage Power”,Proceeding of the InternationalWorkshop on Power and Timing

Modeling, Optimization and Simulation,September, pp. 148-158.

14. Powell M, Yang S-H, Falsafi B, Roy K andVijaykumar T N (2000), “Gated-Vdd: ACircuit Technique to Reduce Leakage inDeep submicron Cache Memories”,International Symposium on Low PowerElectronics and Design, July, pp. 90-95.

15. Rabaey J (1996), Digital IntegratedCircuits: A Design Prospective, Prentice-Hall, Englewood Cliffs, NJ.

16. Se Hun Kim and Mooney V J (2006),“Sleepy Keeper: a New Approach to Low-leakage Power VLSI Design”Proceeding of the 2006 IFIPInternational Conference on Very LargeScale Integration, October, pp. 367-372.

17. Srivastava P, Pua A and Welch L (1998),“Issues in the Design of Domino LogicCircuits”, Proceedings of the IEEE GreatLakes Symposium on VLSI, February,pp. 108-112.

18. Vincent J and Mooney III (xxxx), “SleepyKeeper: A New Approach to Low-leakage Power VLSI Design”, School ofElectrical and Computer Engineering,Georgia Institute of Technology, Atlanta,GA USA.

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