INSTRUCTOR'S MANUAL SOFTWARE AND HARDWARE · PDF file2 1 INTRODUCTION Software and Hardware...

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))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))INSTRUCTOR'S MANUAL

SOFTWARE AND HARDWARE ENGINEERING:

MOTOROLA M68HC12 )))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))Q

1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2 COURSE ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

3 DETAILED COURSE PLAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5 LABORATORY EXERCISES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6MC68HC12 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7MC68HC12 Program Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Addressing and Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Hexadecimal and Binary Memory Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Binary Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Structured Assembly Language Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Structured Program Design and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Parallel Ports I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Interrupts I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Interrupts II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3 SOLUTIONS TO CHAPTER PROBLEMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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1 INTRODUCTION

Software and Hardware Engineering: Motorola M68HC12, together withMicrocontrollers and Microcomputers: Principles of Software and Hardware Engineering, isdesigned to give the student a fundamental understanding of microcontroller-based systems. Thematerial is aimed at the sophomore, junior or senior level Electrical Engineering, ElectricalEngineering Technology, Computer Engineering, or Computer Science student taking a first coursein microcomputers. Prerequisites are a digital logic course and a first course in a programminglanguage.

This text is a successor to Software and Hardware Engineering: Motorola M68HC11and, like that text, its overall objective is to provide an introduction to the architecture and designof hardware and software for the Motorola M68HC12. Although Software and HardwareEngineering: Motorola M68HC12 is designed to accompany a text explaining the generalprinciples of software and hardware engineering, it can stand alone as a reference for M68HC12users. It gives many programming and hardware interfacing examples that will enable students tobecome accomplished software and hardware designers. Of course, no one should expect tobecome an expert in using the M68HC12 in a single course.

Two major members of M68HC12 family, the MC68HC812A4 and the MC68HC912B32,are described in detail. We also compare features of the M68HC12 with the M68HC12 for thosestudents and engineers familiar with that microcontroller.

In addition to covering the features common to all members of the M68HC12 family ofmicrocontrollers, advanced features are discussed. These include the memory expansioncapabilities of the MC68HC812A4 in Chapter 9 and the pulse-width modulator of theMC68HC912B32 in Chapter 10. The enhanced Serial Communications Interface (SCI) and SerialPeripheral Interface (SPI) are discussed in Chapter 11 and the analog-to-digital converter inChapter 12. The fuzzy logic instruction set is covered in Chapter 13 with an example programshowing a general-purpose inference engine. Chapter 14 describes the Background DebugTM

module and other debugging features of the M68HC12 family. Chapter 15 describes advancedarchitectures of the M68HC12.

2 COURSE ORGANIZATION

The overall objective for this text and Microcomputers/Microcontrollers: Principles ofSoftware and Hardware Engineering is to provide an introduction to the architecture and designof microcomputer/microcontroller hardware and software. We do not aim to make our studentsexperts in using the M68HC12 microcontroller.

The introductory chapter in Microcomputers/Microcontrollers: Principles of Softwareand Hardware Engineering explains the concepts of a stored program computer. A plausibledesign is created, and while the result doesn't answer all the questions students might have abouthow a computer is designed, nor is it very practical, it does give them a fundamental understandingabout how a computer works. We want to dispel the mystery but we don't want to have too manydetails to obscure the relevant issues.

The resources of the M68HC12 used in the laboratory are then explored with side trips toexplain some important issues. Our goal is to be able to begin laboratory exercises while teachingother concepts. To do this, we introduce the basic hardware registers, the ALU, and the conditioncodes. The explanation of the condition codes register allows us to discuss binary codes and

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coding. Even though students have learned about binary codes in their introductory logic courses,a review is beneficial. Special attention is paid to codes used for arithmetic and how the variouscodes affect the operation of the condition code register.

By this time (at least in our course) the students are starting the concurrent laboratory andneed to know how to program the computer. We point out that learning the instruction set of aprocessor involves knowing what the hardware resources are, what addressing modes have beenimplemented, and what general categories of instructions are available. A general discussion onaddressing is provided with specific examples from the processor and instruction set being used inthe laboratory.

The mechanics of using an assembler are then presented in enough detail that the studentscan assemble and run small programs in the laboratory. The complete instruction set for theprocessor used is covered, at least in instruction categories. It is sufficient to lead the studentsthrough examples of using various instructions, particularly those with different addressing modes.

By now the students are able to write, assemble, download, and run simple programs in thelaboratory. Their experience will show the need for debugging tools. We discuss debugging toolsin general in Microcomputers/Microcontrollers: Principles of Software and HardwareEngineering but the bulk of the information the students need is in Software and HardwareEngineering: Motorola M68HC12 where the debugging monitor supplied by Motorola with theirEVB system is discussed. In courses where other debugging software or hardware is used,instructors can supplement this chapter with their own information.

A large portion of the cost of developing any microcomputer system is the software. A keychapter in Microcomputer/Microcontroller Software and Hardware Engineering is dedicated tosoftware design. The basic elements of software design are presented and the differences betweendesign methodologies and design tools are discussed. Top down design is presented and pseudo-code, probably the most widely used design tool, is promoted. This should reinforce softwaredesign concepts students receive in a previous course. The students are shown how to usestructured programming principles in assembly language. The design of software modules, withattention paid to reducing interaction between modules, is also presented.

Bus architectures and interfaces between external devices and a CPU are then discussed. Asynchronous bus transfer handshaking is covered. The basic input/output capabilities of theM68HC12 are discussed with laboratory exercises giving the students practical experience.

After programmed input and output is covered, the need for interrupts and real timeoperations can be discussed. Various forms of interrupt processing are covered in chapter 8 ofMicrocomputer/Microcontroller Software and Hardware Engineering and the specific detailsnecessary for the students to attempt interrupt processing on the M68HC12 in the laboratory arecovered in chapter 8.

By now the students understand the reason for memory (to store a program and data). Wediscuss the different types of memory, ROM and RAM, and why a system has both. Memoryinterfaces and timing signals are presented. Software and Hardware Engineering: MotorolaM68HC12 chapter 9 shows the memory types available in the M68HC12.

Many engineers have a terrible time with serial interfaces, especially the RS-232C"standard", because they don't understand why all the signals in the standard interface are there. One has to understand that the handshaking signals were developed for half-duplex communicationchannels. Once these concepts are understood, and that two different types of devices have thesame name for different signals, the serial interface problem becomes much easier. Chapter 10 inMicrocomputer/Microcontroller Software and Hardware Engineering provides completecoverage of serial interfaces. Interface cables for various RS-232C devices are shown and other

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common interface standards such as RS-422, RS-423, and RS-485 are defined. The M68HC12has two different types of serial interfaces. Each in covered in detail in chapter 11.

The use of timers and the importance of real time events are then covered. The M68HC12has an especially powerful timer section which students can use in their laboratories.

I generally conclude my course with a discussion of the concepts of A/D conversion and itscompanion, D/A conversion. Chapter 11 in Microcomputer/Microcontroller Software andHardware Engineering and chapter 12 in this text discuss and show examples of A/D conversion.

Software and Hardware Engineering: Motorola M68HC12 includes chapters on fuzzylogic (chapter 13) and the powerful debugging features of the M68HC12 family (chapter 14 andAppendix A). I never get time to cover these but I hope you will.

3 DETAILED COURSE PLAN

The following detailed course plan shows how to closely integrate the two texts. In thereading assignments shown, "M" denotes Microcomputer/Microcontrollers: Principles ofSoftware and Hardware Engineering, and "S" Software and Hardware Engineering: MotorolaM68HC12.Lecture Number: 1 Topic: M68HC12 Instruction setTopic: Introduction and the picoprocessor Reading Assignment: S4Reading Assignment: M1, M2.1-M2.3

Lecture Number: 2; 3 Topic: CASM AssemblerTopic: The picoprocessor Reading Assignment: S3, M5.1-M5.2Reading Assignment: M2.4; M2.5-M2.8

Lecture Number: 3 Topic: Assembly language programmingTopic: Registers and condition codes. Reading Assignment: S6.1-S6.2, M4.5-M4.6Reading Assignment: S2.1-S2.3, M3.1-M3.2,MA.1 Lecture Number: 13

Lecture Number: 4 Reading Assignment: M5.9-5.10, S5Topic: The condition code register.Reading Assignment: M3.5-M3.7 Lecture Number: 14

Lecture Number: 5 Reading Assignment: M5.3-M5.7Topic: Memory architectures and addressingmodes Lecture Number: 15Reading Assignment: M4.1-M4.4 Topic: Top down design.

Lecture Number: 6Topic: Addressing modes with M68HC12 Lecture Number: 16examples. Topic: Structured programming.Reading Assignment: M4.4, S2.6 Reading Assignment: M6.9

Lecture Number: 7; 8; 9 Lecture Number: 17; 18

Lecture Number: 10; 11

Lecture Number: 12

Topic: Debugging and testing.

Topic: Code location.

Reading Assignment: M6.1-M6.7

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Topic: Assembly language structured forms. Topic: Interrupt service routinesReading Assignment: S6.2 Reading Assignment: M8.8-M8.10

Lecture Number: 19 Lecture Number: 30Topic: Module design. Topic: M68HC12 interrupt service routinesReading Assignment: M6.12-M6.14 Reading Assignment: S8.11

Lecture Number: 20 Lecture Number: 31Topic: Introduction to parallel I/O Topic: Introduction to memory, RAM andReading Assignment: M7.1-M7.2 ROM

Lecture Number: 21Topic: I/O timing and address decoding Lecture Number: 32Reading Assignment: M7.3-M7.3 Topic: Memory timing diagrams

Lecture Number: 22Topic: M68HC12 I/O Lecture Number: 33Reading Assignment: S7.1-7.5 Topic: M68HC12 memory

Lecture Number: 23Topic: I/O handshaking Lecture Number: 34Reading Assignment: M7.4, S7.8-7.9 Topic: M68HC12 timer

Lecture Number: 24Topic: I/O synchronization Lecture Number: 35Reading Assignment: M7.4, S7.8-7.9 Topic: M68HC12 timer interrupts

Lecture Number: 25Topic: Simple I/O devices Lecture Number: 36; 37Reading Assignment: M7.6-M7.9 Topic: Serial I/O

Lecture Number: 26Topic: Introduction to interrupts Lecture Number: 38Reading Assignment: M8.1-M8.5 Topic: M68HC12 serial I/O

Lecture Number: 27Topic: Interrupt priorities and introduction to Lecture Number: 39M68HC12 interrupts Topic: Analog I/OReading Assignment: M8.6-M8.7, S8.1-S8.3 Reading Assignment: M11.1-11.7

Lecture Number: 28 Lecture Number: 40Topic: M68HC12 parallel I/O interrupts Topic: M68HC12 analog-to-digital converterReading Assignment: S8.4-S8.7 Reading Assignment: S12.1-S12.8

Lecture Number: 29



Reading Assignment: S9.1-9.7




Reading Assignment: S11.1-S11.4

5 LABORATORY EXERCISES

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Over the years a number of laboratory exercises have been developed. Here are a few,and you will find a growing collection of others for the M68HC12 and M68HC11 processors onthe web at http://www.coe.montana.edu/ee/cady/books/profs.htm.

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MC68HC12 Introduction

References: Software and Hardware Engineering: Motorola M68HC12 chapter 5,

Pre-Lab: Read Chapter 5: Debug-12 Monitor and Debugger

1. Using the Debug-12 Monitor, assemble the following program to be at $0800. (Note: Typea period <.> to get out of the ASM mode.) After it is in and you have checked that it is OK,run the program by typing G 800.

Enter in ASM Whats in MemoryProgram Comment ASM 800LDAB ': Load ASCII code for : LDAB #$3A 0800: c6 3aLDX $FE04 Load the vector for putchar LDX $FE04 0802: fe fe 04JSR 0,X Print what's in B on terminal JSR 0,X 0805: 15 00LDX $FE02 Load the vector for getchar LDX $FE02 0807: FE FE 02JSR 0,X Get a new character in B JSR 0,X 080a: 15 00LDAA #5 Initialize loop counter LDAA #5 080c: 86 05

LOOP PSHA Save the counter on stack PSHA 080e: 36LDX $FE04 Load the vector for putchar LDX $FE04 080f: fe fe 04JSR 0,X Print it on terminal JSR 0,X 0812: 15 00PULA Retrieve the counter PULA 0814: 32DECA Decrement loop counter DECA 0815: 43BNE LOOP If counter <> 0, repeat BNE $80e 0816: 26 f6SWI Return to the monitor SWI 0818: 3f

<.>1.1 What does this program do?1.2 Change the ":" prompt to a "$".1.3 Change the loop counter so it prints exactly 15 of them.

2 Using elements of this program and other monitor utility routines, write, assemble anddemonstrate a program which conforms to the following design:

+)))))))))))))))))))))))))))))))))))), *Input character from the keyboard * .))))))))))))))))0)))))))))))))))))))- +))))))))))2))))))))))))), *Add 1 to the character * .))))))))))0)))))))))))))- +)))2))))))))), *Print +1= * .)))0)))))))))- +))))))))))))))))))2)))))))))))))))))))))))), *Print the character to which 1 was added * .))))))))))))))))))0))))))))))))))))))))))))- +))))2))))))))), *End program * .))))))))))))))-

Example. If you had entered the character A, the program display should show A+1=B. Demonstrate the program to your lab instructor.

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MC68HC12 Program Debugging

1 Pre-Lab:Read Chapter S-5.3.

2 Using the D-Bug12 Monitor, assemble the following program at $4000. After you haveentered it, trace through it one step at a time. Explain to your lab instructor what you seeon the screen. In particular, explain what is happening to the condition code register ateach step.What’s in Memory Enter in ASM 4000 CE4000 LDX #$4000 4003 C602 LDAB #$02 4005 A600 LDAA 0,X 4007 08 INX 4008 53 DECB 4009 26FA BNE $4005 400B 3F SWI

3 Assemble the following program. The program is to allow you to enter a character fromthe keyboard and to print the hexadecimal code used by the computer to represent thatcharacter. For example, if you type A after starting the program the display should showA=41. It doesn't do it. Why not? Fix it so it does. Demonstrate to your lab instructor.

Operation Operand CommentLDX $FE02 ; Get a character using getcharJSR 0,X PSHA ; Save the character on the stackLDAB #$3C ; Load ASCII code for =LDX $FE04 ; Print it using putcharJSR 0,X PULA ; Get the character back from the stackLDX $FE18 ; Print its hex code using out2hexJSR 0,XLDAB #$0D : Load ASCII code for carriage returnLDX $FE04 ; and print itJSR 0,X LDAB #$0A ; Load ASCII code for line feedJSR 0,X ; and print itSWI

4 Using elements of this program and other monitor utility routines, modify the program toprint A = $41 or B = $42, etc. (including the spaces in front and back of the =).

5 Extra Credit: Modify the program so that it continues until the user types the Esc (escape)key..

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Addressing and CASM12 Introduction

References: Chapters 3 and 5 in Software and Hardware Engineering: M68HC12

1 Pre-Lab: Create a source file (ASCII text file) that reproduces your program from part 4 of Lab 2. Come to lab with this on your floppy disk. Read chapter S3 to see how to properly formatthis file for the CASM12 assembler.

2 Use the D-Bug12 Monitor ASM command to enter the following program at $4000.

ldab #$10ldab $10ldx #$4000ldab 7,xldx $4000ldab 7,xnopswi

Demonstrate and explain to your lab instructor what is going on at each program step.

You are to write a memo report explaining, for each line of code in (2), what addressingmode is employed and what the results were for each instruction. The memo is due nextweek. Use the Informative Memo Style (see the web page<http://www.coe.montana.edu/ee/commhtml.htm> for an example of this type of report.)

3 Following the DOWNLOADING AN S19 FILE TO THE EVB instructions in the EE371LABORATORY PROCEDURES handout, download the file lab3bug.s19 from thec:\ee371 directory. This program is to print out Good Job! five times on the screen (usingthe D-Bug printf monitor routine) and then quit. It doesn’t do it. You can see what it doesby typing in G 4100 to run the program. Fix the program making use of breakpoints,tracing, and ASM.

4 Use the CASM12 cross-assembler to assemble the source program that you prepared as thepre-lab, upload it to the EVB and demonstrate it to your instructor.

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Addressing and Arithmetic

1 Pre-Lab: Come to the lab with a source file program prepared for the program specified in2.

2 Create the following program

a. Locate the program at $4000 using:PROG: EQU $4000

ORG PROG...(Write your program op codes etc here)...

b. You are to set up 4 data buffers of 14 bytes each. Use the EQU, ORG, DB and DSassembler directives to initialize data in BUF1 and BUF2 and allocate storage for BUF3and BUF4 as shown. Use the labels BUF1 - BUF4 and refer to them in your program.BUF1LOC: EQU $4100BUF2LOC: EQU $4110BUF3LOC: EQU $4120BUF4LOC: EQU $4140

ORG BUF1LOCBUF1: DB $45,$45,$33,$37,$31,$20,$69,$73,$20,$66,$75,$6E,$21,$7F

ORG BUF2LOCBUF2: DB $02,$2D,$32,$2A,$43,$00,$01,$FC,$42,$BA,$CC,$F5,$44,$01

ORG BUF3LOCBUF3: DS $0e

ORG BUF4LOCBUF4: DS !14

The program is to:c. Add each bytes in BUF1 with the corresponding byte in BUF2 and store the result in BUF3.d. Exclusive-OR each byte in BUF3 with $20 and store the results in BUF4.

Extra credit. After you have completed the program required for 2, add the capability toprint out the contents of the four buffers in hexadecimal. Each of the four buffers should beprinted like this, with a label (BUF1: etc) followed by the hex display of the 14 bytes ineach buffer.

BUF1:$45,$45,$33,$37,$31,$20,$69,$73,$20,$66,$75,$6E,$21,$7FBUF2:$02,$2D,$32,$2A,$43,$00,$01,$FC,$42,$BA,$CC,$F5,$44,$01BUF3: ...(contents of BUF3)...BUF4: ...(contents of BUF4)...

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Hexadecimal and Binary Memory Display

1 Pre-Lab: Review Chapter S5.3 - Monitor Utility Routines. Come to the lab with a sourcefile ready to do the following programming assignment.

2 In the previous lab you programmed the M68HC12 to fill some data buffers and then to addand exclusive-OR the data. You are now to take that program and add the followingfeatures.a. Locate BUF1 and BUF2 contiguously in a constant data area in the EVB. That is,

BUF1 should immediately follow the program code and BUF2 should immediatelyfollow BUF1 in the EVB pseudo-ROM. To do this, eliminate the BUF1LOC andBUF2LOC equates and the associated ORGs. Locate BUF3 and BUF4 contiguouslyin the RAM data area in the EVB. BUF3 should be immediately followed byBUF4. To do this, equate BUF3LOC to $5000 and delete the BUF4LOC equateand ORG.

b. Initialize all data locations in BUF3 and BUF4 to zero each time the program is run. Be prepared to demonstrate that you are doing this.

c. Do the arithmetic and exclusive-OR just as you did in the last Lab.d. Output the string "BUF1:" followed by the bytes in BUF1 as hex values, i.e., if

memory contains 01000101 01000101 ..., the display should be BUF1: 45 45 ... (note the space between the values).You must print all data values from BUF1

e. Output a carriage return, line feed to the screen.f. Output the string "BUF2:" followed by the bytes in BUF2 to the screen just like in

24. Do the same for BUF3 and BUF4.g. Output another carriage return, line feed.h. Output the string "The binary values in BUF4 are:" followed by a carriage return,

line feed.i. Output the first 5 bytes in BUF4 in the format

$Hex_Value = %Binary_Value$Hex_Value = %Binary_Value...Where Hex_Value is the hexadecimal display of the data in BUF4 andBinary_Value is a binary display. Each of the five data locations should be on aseparate line.

A typical output would look like this:BUF1: 45 45 33 37 31 20 69 73 20 66 75 6E 21 7FBUF2: 02 2D 32 2A 43 00 01 FC 42 BA CC F5 44 01BUF3: 47 72 65 61 74 20 6A 6F 62 20 41 63 65 80BUF4: 67 52 45 41 54 00 4A 4F 42 00 61 43 45 A0

The binary values in BUF4 are:$67 = %01100111 (First byte in BUF4)$52 = %01010010 (Second byte in BUF4)$45 = %01000101 (etc)...

3 Extra Credit. Assume the code for the numbers in BUF4 is unsigned binary. Add thefollowing printout to the program.

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The decimal values in BUF4 are:$67 = 103$52 = 82$45 = 69

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Binary Arithmetic

1 This program will be similar to the previous lab where you will add together each memorylocation in BUF1 with the corresponding location in BUF2 and save the result in BUF3. There is no BUF4. Each buffer is 13 bytes long and contains the following data:10

BUF1: DB $FF,$FF,$01,$70,$7F,$80,$80,$81,$C0,$C0,$FF,$00,$01BUF2: DB $01,$02,$01,$0D,$01,$01,$80,$81,$C0,$BF,$FE,$FE,$FE

BUF1 and BUF2 are to be located in the pseudo-ROM and BUF3 is to be located in thedata ram area of the EVB.

For each addition, your program is to print out the two data values being added and thesum. If as a result of the addition an unsigned binary overflow occurs, print out themessage Unsigned overflow occurred. If as a result of the addition a two's complementoverflow occurred, print out the message Two's-complement overflow occurred. If bothtypes of overflow occur, both message should be printed. For example, when adding thefirst two bytes, you should display:

$FF + $01 = $00 Unsigned overflow occurred

Each addition should be printed on a new line.

(Hint: You will have to save the condition code register after the addition so you can printthe error messages. There are a couple of ways to do this. You can push and pull it or youcan use the transfer register instruction TFR C,A and TFR A,C to transfer into and out ofthe A register.)

2 Extra credit: Add two additional lines printed out for each addition that show theequivalent addition in decimal assuming first, unsigned binary code, and second two's-complement binary code. For example, the printout for the first addition would show:

$FF + $01 = $00 Unsigned overflow occurred255 + 1 = 0 Unsigned addition-1 + 1 = 0 Two's-complement addition

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Structured Assembly Language Programming

1 Pre-Lab: Review Chapter S6.2 - Structured Assembly Language Programming. Come tothe lab with a source file ready to do basically the same program that you did for Lab 5EXCEPT:

You are to write STRUCTURED ASSEMBLY LANGUAGE CODE to implement thefollowing design. You MUST implement this design and you MUST use structured code. You may use subroutines as needed or wanted. You may add more design comments andother comments if you wish but you may not change the design in any substantial way.

A source file with the following pseudo code design comments is as follows:

; Pseudo code design ; Output CR, LF; Initialize counter1 to number of bytes ; Initialize Counter1=5; DO (add and XOR the bytes in the bufs) ; DO (Output 5 bytes in hex and binary); Get value from BUF1 ; Get data from BUF4; Add value from BUF2 ; Output $ and the hex data value; Store sum in BUF3 ; Output " = %"; XOR sum ; Initialize Counter2=8; Store in BUF4 ; DO (Output the binary value); ENDO ; IF MSB of data = 1; WHILE (Counter1 != 0) ; THEN Print "1"; Output "BUF1: " ; ELSE Print "0"; Output BUF1's data and CR, LF ; Shift data left; Output "BUF2: " ; ENDO; Output BUF2's data and CR, LF ; WHILE (Counter2 != 0); Output "BUF3: " ; Output CR, LF; Output BUF3's data and CR, LF ; ENDO; Output "BUF4: " ; WHILE (Counter1 != 0); Output BUF4's data and CR, LF ; Return to monitor; Output "The binary values in BUF4 are:"

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Structured Program Design and Implementation

1. Pre-Lab: Do a top down design for the program specified below. You and your lab partnerare to work together to produce a fully structured design using structured programming andpseudocode. The design must have at least one WHILE-DO or DO-WHILE and at least one IF-THEN-ELSE. You should carry the design to a level where you can easily convert the design to aprogram. This design is to be a file and each line is to be used as a comment in your program. Show your design to the lab instructor BEFORE you start coding the problem.

2. Implement the design using structured assembly language code. Write an assemblylanguage program using ONLY structured code.

The Program

Prompt the user to enter a character. Use a prompt that is informative and tells the userwhat you want. After the user has entered the character, print it out in the following format: (Assume the user has typed the z key.)

The character you entered was: zIts ASCII code is:Hexadecimal: $7A (Print the hex representation for the character the user typed.)Binary: %01111010 (Binary representation for the character.)

Continue the above until the user types the ESC character. When the ESC character is printed,instead of printing out the information shown above, the program must display the following:

The character you entered was: <Esc>We now return you to your regularly scheduled program.

and then return to the B-Bug12 monitor.

You are to use a subroutine to print out the binary code. The byte to be printed will beinput to the subroutine in the A register. The subroutine must not alter any registers including thecondition code register. Nothing is returned to the calling program.

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Parallel Ports I/O

1 The I/O board attached to the EVB has a set of 8-switches attached to Port J and 8-LEDsattached to Port H. You may read from the switches by loading from Port J and write to theLEDs by storing to Port H.

LED Display:The LEDs are attached to port H through a 74LS373 octal latch with tri-state output. PortH is used for the 8-bit output (and a zero written to the port turns the LED on). Port F, bit-6 must be asserted high to latch the data. The tri-state output is permanently enabled. Isuggest you write a subroutine to enable the LEDs using the following design:

; Set the data direction register DDRH so all bits on Port H are output; Set bit-6 in data direction register DDRF so bit-6 is an output; Assert bit-6 in Port F high to allow the LED output latch to follow ; the data on Port H.

To display data on the LED, you must first complement the byte to display and then outputto Port H. Write a subroutine to do that.Switch Port:The switches are input to Port J through a 74LS244 octal tri-state buffer. At reset, Port Jwill be configured as an input but it is a good idea to initialize it to be an input anyway. Port S bit-2 is used for the output enable and must be asserted low when reading from theswitches. I suggest you write a subroutine to enable the switch port using the followingdesign:

; Set the data direction register DDRJ so all bits on Port J are input; Set bit-2 in data direction register DDRS so bit-2 is an output.

To input data from the switch, Write a subroutine to assert Port S bit-2 low to enable thebuffer, read the data from Port J and then deassert Port S bit-2. (You may need a shortdelay (NOP) after asserting bit-2 and before reading the data.)Here are the equates for the registers you will be using. See chapter S7 (page 202, 205-206) for more informationPORTH: EQU $0024DDRH: EQU $0025PORTF: EQU $0030DDRF: EQU $0032PORTS: EQU $00D6DDRS: EQU $00D7PORTJ: EQU $0028

2 Write an assembly language program to do the following: ; Initialize all I/O; DO; Input a value from the switches; IF the value is different from the last one displayed; THEN ; Display the value on the LEDs; Print carriage return, line feed; Print "The switches are set to: $xx (where xx is the 2 digit hex value)

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; ENDDO; WHILE the switches are not set to %00000000; Print carriage return, line feed

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Interrupts I

1 Enter the IRQEX2.ASM program shown below and demonstrate that it works. Because theIRQ input is asserted when the signal is low (the switch pressed), the test program shouldprint out the message continuously when the switch is pressed.

2 Modify IRQEX2.ASM so that the message is printed out once and only once each time theswitch is pressed. Hint: You will need to change only one line of code in IRQEX2.ASMto do this.

3 Port J-7 is connected to the SDB switch on the I/O board. Write an assembly languageinterrupt program that uses the key wakeup feature of Port J. Refer to S233-S242 forinformation.

The program is to perform to the following specifications:

Foreground Job: When an interrupt is not being serviced, your foreground job is tocontinuously get a characters from the keyboard and then display them on the screen. Itshould do this forever or until the RESET switch is pressed (whichever comes first).

Background Job: The background job, or interrupt service routine, is to be entered whenthe SDB switch is pressed. Every time the switch is pressed the following message is tobe printed on the display:carriage-return linefeed SDB switch pressed carriage-return linefeed

A requirement of the routine is that this message is to be printed once, and only once, eachtime the SDB switch is pressed. The message is to be printed when the switch is pressed,not when it is released.

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; Sample listing to initialize interrupt vectors; in a system WITH a Dbug-12 Monitor; irqex2.asm; EE371 Fall 1999; Memory map equatesROM: EQU $4000RAM: EQU $6000STACK: EQU $8000; IRQ system equatesINTCR: EQU $1e ; Interrupt control regIRQEN: EQU %01000000 ; IRQ enable bit; D-bug12 monitor equates SetVec: EQU $fe1aPrintf: EQU $fe06IRQNUM: EQU !25 ; IRQ num for SetVect;

org ROMlds #STACK

; Initialize rest of machine including; any interrupt system details.; Initialize the D-Bug12 monitor interrupt vector

ldd #IRQISR ; Get adr of ISR pshd ; Stack for SetVecldd #IRQNUM ; Get the numberjsr [SetVec,pcr]puld ; Clean up stack

; Enable the IRQ interruptbset INTCR,IRQEN

; Unmask interruptscli

; The main process is a loop which runs; forever.; DOloop:; yada, yada, yada; WHILE (forever)

bra loop;***************************************; Here are the interrupt service routinesIRQISR:; blah, blah, blah, whatever; Print a test message

ldd #irqmesjsr [printf,pcr]rti ; Special return

;***************************************irqmes: DB "External IRQ detected "

DB 0d,0a,00

.nolist

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Interrupts II

1 It is my fervant and lasting hope that you will actually do a structured design for thefollowing program. If you do you will get it done much faster than if you don't.

2 Write a program that has a foreground job that does no processing other than to monitor thePort J, bit-0 toggle switch to see if a rocket launch is to proceed. When the switch input isone, the foreground job is to allow the countdown for launching a rocket. The countdownis to be produced by an interrupt service routine described in (a) below. If the Port J-0switch is changed to zero, the countdown sequence is to hold at its present count and thenresume when the switch is changed back to one. After the countdown reaches Blast Off! asdescribed in (a), return to the D-Bug12 monitor. If the SDB switch (Port J, bit-7) ispressed at any time, the launch is to be aborted and control returned to the D-Bug12monitor as described in (b).

There are to be two interrupt service routines.

a. Using the timer overflow flag to generate 1 second timing intervals, write an interruptservice routine that prints out the launch countdown from 10 to 0. The countdown is to beprinted on the screen and should decrement every second (or as close to a second as youcan get). Each digit is to be on a new line. When zero is reached, the display is to showBlast Off! instead of zero. (Note that the countdown is to start only after the user sets thebit-0 switch to one. Once the countdown starts, it continues until it reaches Blast Off!unless Port J-0 is zero putting the countdown into a hold or the user presses the SDBswitch.)

b. Port J-7 is connected to the SDB switch on the I/O board. Write an interrupt serviceroutine that uses the key wakeup feature of Port J so that when the switch is pressed thelaunch sequence is aborted and the message **** LAUNCH ABORTED **** is printedon the screen. After this, control is to be returned to the D-Bug12 monitor. You must notreturn to the monitor directly from the interrupt routine. You must return to the foregroundjob and then exit.

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3 SOLUTIONS TO CHAPTER PROBLEMS

SOLUTIONS TO CHAPTER 2 PROBLEMS

2.1 Which of the M68HC12 ports is used for the A/D converter inputs? Port E2.2 Which of the M68HC12 ports is used with serial I/O? Port S2.3 Draw the programmer's model for the M68HC12.

+))))))))))))))0)))))))))))))),*7 A 0*7 B 0 *.))))))))))))))2))))))))))))))-

or+))))))))))))))))))))))))))))),*15 D 0 *.)))))))))))))))))))))))))))))-+))))))))))))))))))))))))))))),*15 X 0 *.)))))))))))))))))))))))))))))-+))))))))))))))))))))))))))))),*15 Y 0 *.)))))))))))))))))))))))))))))-+))))))))))))))))))))))))))))),*15 S 0 *.)))))))))))))))))))))))))))))-

2.4 Which bits in the M68HC12 condition code register may be tested with conditionalbranching instructions? The negative, zero, two's-complement overflow and carry bitsmay be tested by conditional branch instructions.

2.5 Calculate the effective address for each of the following examples of indexedaddressing.a. X = $5000

LDAA 0,X EA = $5000b. Y = $5000

STAA $10,Y EA = $5010c. X = $500D

LDAA $25,X EA = $50322.6 Describe the following M68HC12 addressing modes:

Immediate, Direct, Extended, Indexed, Indexed-in direct, Inherent, Relative

Immediate: The data for the instruction immediately follows the op code. Immediateaddressing is used for constants known at the time the program is assembled.

Direct: Direct addressing uses an 8-bit address to directly access a location in the first256 bytes of memory.

Extended: Extended addressing uses a 16-bit address to access a memory locationanywhere in the 64 Kbyte address space.

Indexed: Indexed addressing generates the effective address by adding a 8-bit, straight-binary offset (specified by the instruction) to the contents of the IX or IY registers.

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A 16-bit address is the result.Indexed-Indirect: This mode uses indexed addressing to find the address of the memory

location which contains the address of the data.Inherent: Inherent addressing means the instruction itself specifies where the operand is

located.Relative: Relative addressing is used for branch instructions. An 8-bit, two's-

complement offset specified by the instruction is added to the contents of theprogram counter.

2.7 Discuss the relative advantages and disadvantages of direct and extended addressing.Direct addressing uses only 8 bits to specify the address of the memory data andthus is faster and uses less memory than extended addressing. Its disadvantage isthat only 256 memory locations can be addressed. Extended addressing requires 3bytes for the instruction and address and thus takes longer to execute and requiresmore memory. Extended addressing can access the whole 64 Kbyte address space.

2.8 Discuss the relative advantages and disadvantages of extended and indexed addressing.Indexed addressing can be a two byte instruction. Thus it is faster and uses lessmemory than extended addressing. Its major advantage is that the address of thedata can be determined at run-time and the index register can be incremented anddecremented to step through tables of data.

2.9 What is in the following CPU registers after a system reset?A, B, CCR, Stack Pointer

A, B = unknown. In the CCR, the I, X and S bits are set and the rest of the bits areunknown. The stack pointer is unknown.

2.10 Discuss how the CPU fetches the first operation code of the first instruction to beexecuted following a system reset.

After the system reset, the CPU fetches the address of the first op code to beexecuted from $FFFE:$FFFF.


3.1 Give four ways to specify each of the following constants.a. The ASCII character X.

'X', "X", $58, !88, %01011000, Q01011000b. The ASCII character x.

'x', "x", $78, !120, %01111000,Q01111000c. 10010

!100, $64, %01100100, Q01100100d. 6416

!100, $64, %01100100, Q011001003.2 Give the symbol used when specifying a constant in the following bases:

hexadecimal - $, decimal - !, binary - %, ASCII - ' ' or " "3.3 What assembler pseudo-operation is used to allocate memory for data variables? DS

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3.4 What assembler pseudo-operation is used to define strings of ASCII characters? DB3.5 What assembler pseudo-operation is used to define byte constants in ROM memory?

DB3.6 What assembler pseudo-operation is used to set the assembler's location counter? ORG3.7 How are data storage areas located when using the CASM assembler?

By using ORG pseudo-operations 3.8 Your hardware designer tells you that the microcontroller will have ROM located at

addresses $E000 to $FFFF and RAM at $0800 to $0FFF. Show how to inform theassembler so that it locates its code and data areas properly.

ORG $E000The program and constant definitions follow this.

ORG $0800The variable data allocations follow this.

3.9 Give the addressing mode and the effective address for each of the followinginstructions:

Mode Effective AddressLDAA #5 Immediate The contents of the program counter after the opcode has

been fetchedLDAA $5 Direct $0005LDAA $5,X Indexed The contents of the X register plus 5STAA $081A Extended $081A


4.1 You be the assembler. Assemble the following source code just as the CASM12assembler would do it.

cprb1ans.asm Assembled with CASM 04/09/1998 21:12 PAGE 1

0000 1 COUNT: EQU !7 0000 2 MAX: EQU !10 0000 3 ROM: EQU $F000 0000 4 RAM: EQU $0800 F000 5 ORG ROM F000 8607 6 ldaa #COUNT F002 8B0A 7 adda #MAX F004 7A0800 8 staa DATA F007 3F 9 swi 0800 10 ORG RAM 0800 11 DATA DS 1

4.2 In the program above, what addressing mode is used for the ldaa instruction? Immediate4.3 In the program above, what addressing mode is used for the staa instruction? Extended

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4.4 What is in memory location $0800 before the program runs?Unknown. The DS reserves a memory byte. It does not initialize it.

4.5 For each of the following questions, assume the memory display of the M68HC12shows:

5000 B0 53 05 2B 36 89 00 FF FE 80 91 3E 77 AB 8F 7F

Give the results after each of the following instructions are executed.a. LDAA $5000 A = $B0, NZVC = 100-b. Assume X = $5000

LDAA 0,X A = $B0, NZVC = 100-c. Assume X = $5000

LDAA 6,X A = $00, NZVC = 010-4.6 Use the contents of memory shown in problem 4.5 and give the results of the following

instructions.a. LDX $5000 X = $B053b. LDY $5002 Y = $052Bc. LDX $5003

PSHXPULD X = $2B36, A = $2B, B = $36

d. LDD $5000LDX $5002XGDX D = $052B, X = $B053

e. Assume X = $5000LDD $0A,X D = $913E

4.7 Use the contents of memory shown in problem 4.5 and give the results of the followinginstructions.a. SP = $5005

PULA A = $89, SP = $5006b. SP = $5005

PULA A = $89PULB B = $00

c. SP = $5005PSHAPSHB SP = $5003

d. SP = $500APULAPSHB A = $91, SP = $500A

4.8 Why do store instructions not use the immediate addressing mode?The data for an immediate instruction immediately follows the opcode andprograms are usually stored in ROM. Therefore, one cannot store data in ROM atrun-time.

4.9 Use the contents of memory shown in problem 4.5 and give the results of the followinginstructions.a. Assume X = $5000

BSET 0,X,$0F ($5000) = $BFb. Assume X = $5000

BSET 6,X,$AA EA = $5006, (EA) = $AAc. Assume X = $5007

BCLR 0,X,$AA ($5007) = $55d. Assume Y = $5000

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BCLR 0,Y,$FF ($5000) = $004.10 Assume A = $C9 and the NZVC bits are 1001. Give the result in A and the NZVC bits

for each of the following instructions.a. LSLA A = $92, NZVC = 1001b. LSRA A = $64, NZVC = 0011c. ASLA A = $92, NZVC = 1001d. ASRA A = $E4, NZVC = 1001e. ROLA A = $93, NZVC = 1001f. RORA A = $E4, NZVC = 1001

4.11 The ASLx instructions have the same operation codes as the LSLx instructions. Why?Both shift a 0 into the least significant bit and shift the most significant bit into thecarry bit.

4.12 Use the contents of memory shown in problem 4.5 and give the results of the followinginstructions.a. LDAA $5003

LDAB $5004ABA A = $61, B = $36, NZVC = 0000

b. LDX $5000LDAB $5007LEAX B,X X = $B152, NZVC = ----

c. LDAB $5009ADDB $500A B = $11, NZVC = 0011

d. Assume X = $5000LDAA 9,XADDA $0A,X A = $11, NZVC = 0011

e. Assume X = $5000LDAA 9,XSUBA $0A,X A = $EF, NZVC = 1001

f. LDAA $5000LDAB $5001ABAADCA $5002 A = $09, NZVC = 0000


NEGA A = $00, NZVC = 0100b. LDAA $5007

NEGA A = $01, NZVC = 0001c. NEG $5009 ($5009) = $80, NZVC = 1011d. LDAA $5006

COMA A = $FF, NZVC = 1001e. LDAA $5007

COMA A = $00, NZVC = 0101f. COM $5009 ($5009) = $7F, NZVC = 0001

4.14 After an addition, the carry bit in a status register indicates that a 2's complementoverflow has occurred - false.

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4.15 The following straight binary addition was done in the M68HC12. What is the binaryresult and what are the N, Z, V, and C flags?

010101110110011010111101 N=1, Z=0, V=1, C=0

4.16 Assume the following M68HC12 code is executed in sequence. Give the hexadecimalresult in each of the registers after each instruction is executed.

A B N Z V Cldaa #$4A 4A__ xxxx 0 0 0 -ldab #$D3 4A__ D3__ 0 0 0 -aba 1D__ D3__ 0 0 0 1adca #$70 8E__ D3__ 1 0 1 0

4.17 Use the contents of memory shown in problem 4.5 and give the results of the followinginstructions.

LDAA $5002ADDA $5004 A = $3BDAA A = $41


ORAA $5003 A = $2F, NZVC = 000-b. LDAA $5002

EORA $5003 A = $2E, NZVC = 000-c. LDAA $500D

ANDA $500E A = $8B, NZVC = 100-d. LDAB $5002

COMB B = $FA, NZVC = 10014.19 Use the contents of memory shown in problem 4.5 and give the results of the following

instructions.a. LDAA $5000

CMPA $5001 A = $B0, NZVC = 0010b. TST $5006 NZVC = 0100c. TST $5007 NZVC = 1000

4.20 Assume A = $00 and memory location DATA = $B0. A CMPA DATA instruction isexecuted followed by a conditional branch. For each of the conditional branchinstructions in the table, indicate by yes or no if you expect the branch to be taken.BGE BLE BGT BLT BEQ BNEyes no yes no no yesBHS BLS BHI BLOno yes no yes

4.21 Assume A = $05 and memory location DATA = $22. A CMPA DATA instruction isexecuted followed by a conditional branch. For each of the conditional branchinstructions in the table, indicate by yes or no if you expect the branch to be taken.BGE BLE BGT BLT BEQ BNEno yes no yes no yesBHS BLS BHI BLOno yes no yes

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4.22 Assume A = $56 and memory location DATA = $22. A CMPA DATA instruction isexecuted followed by a conditional branch. For each of the conditional branchinstructions in the table, indicate by yes or no if you expect the branch to be taken.BGE BLE BGT BLT BEQ BNEyes no yes no no yesBHS BLS BHI BLOyes no yes no

4.23 Assume A = $22 and memory location DATA = $22. A CMPA DATA instruction isexecuted followed by a conditional branch. For each of the conditional branchinstructions in the table, indicate by yes or no if you expect the branch to be taken.BGE BLE BGT BLT BEQ BNEyes yes no no yes noBHS BLS BHI BLOyes yes no no

4.24 Briefly describe what each of the following instructions do. These are separateinstructions, not a program.

COMA 1's Complement the A registerCBA Compare A to B = (A)-(B) and set flagsCMPB 10,X Compare B to memory (B)-(M) where the address of memory is 10

plus the contents of the X registerTSTB Test the B register for zero; modifies the N and Z flagsBRN Branch neverSWI Software interrupt. Used as a breakpoint in the EVB monitorBITA $80 Tests if the A register is $80; modifies N and Z and resets VBCC LOOP Branch carry clear to LOOP; take the branch if C=0, otherwise

continue with the next instructionXGDX Exchange the D register with XLSR $5000 Logical shift right the contents of memory location $5000NEGB Two's-complement the B register

4.25 Draw a memory map showing the contents of the stack expected after the program inExample 4-13 is executed. What value do you expect in the A register after thesubroutine adds all the data?

9F4: 08 Return 9FA: 06 Data9F5: 14 Address 9FB: 05 "9F6: 0A Data 9FC: 04 "9F7: 09 " 9FD: 03 "9F8: 08 " 9FE: 02 "9F9: 07 " 9FF: 01 "

A = $37


5.1 You downloaded an S-record file to the EVB and the D-Bug12 Monitor responds withthe message "Invalid Command". What went wrong?

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You probably forgot to start the download with the LOAD command.5.2 What sequence of keystrokes would you use to put the hexadecimal data 11, 22, 33, 44

into memory locations $5000-$5003?MM 5000<Enter>11<CR>22<CR>33<CR>44<CR>.<Enter>

5.3 Write a short D-Bug12 assembler (ASM) code segment showing how to use the D-Bug12 Monitor utility routine putchar to print the letter A on the terminal.

ldab #$41ldx $FE04jsr 0,xswi

5.4 Write a short CASM12 code segment showing how to use the D-Bug12 Monitor utilityroutine putchar to print a $ on the terminal.putchar: EQU $FE04

ldab #'$' ; Load ASCII code for $ldx putcharjsr 0,xswi

5.5 Write a short D-Bug12 assembler (ASM) code segment showing how to use the D-Bug12 Monitor utility routine printf to print a null-terminated string starting at $5000.

ldd #$5000ldx $FE06jsr 0,xswi

5.6 Write a short CASM12 code segment showing how to use the D-Bug12 Monitor utilityroutine printf.printf: EQU $FE06NULL: EQU 0MESG: DB "Hello World",NULL

ldd #MESGldx printfjsr 0,xswi

5.7 How does the D-Bug12 monitor know when to stop printing characters in the printfroutine?

The printf routine prints characters until it finds a null ($00) character.5.8 Write a short D-Bug12 assembler (ASM) code segment showing how to use the D-

Bug12 Monitor utility routine out4hex assuming the data to be printed is at $5000.ldd $5000ldx $FE18jsr 0,xswi

5.9 What command is used to set a breakpoint at $4016?BR 4016

5.10 What command is used to clear all breakpoints?NOBR

5.11 What command is used to display what breakpoints are currently set?BR

5.12 What command is used to set register A to $AA?A AA

5.13 What command is used to display memory locations $5000 to $502FMD 5000 5020

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6.1 For each of the logic statements, give the appropriate M68HC12 code to set thecondition code register and to branch to the ELSE part of an IF-THEN-ELSE. AssumeP and Q are 8-bit, unsigned numbers in memory locations P and Q.a. ; IF P >= Q

ldaa Pcmpa Qblo ELSE_PART

b. ; IF Q > Pldaa Qcmpa Pbls ELSE_PART

c. ; IF P = Qldaa Pcmpa Qbne ELSE_PART

6.2 For each of the logic statements, give the appropriate M68HC12 code to set thecondition code register and to branch to the ELSE part of an IF-THEN-ELSE. AssumeP and Q are 8-bit, signed numbers in memory locations P and Q.a. ; IF P >= Q

ldaa Pcmpa Qblt ELSE_PART

b. ; IF Q > Pldaa Qcmpa Pble ELSE_PART

c. ; IF P = Qldaa Pcmpa Qbne ELSE_PART

6.3 For each of the logic statements, give the appropriate M68HC12 code to set thecondition code register and to branch to the ELSE part of an IF-THEN-ELSE. Assume P, Q and R are 8-bit, signed numbers in memory locations P, Q and R.a. ; IF P + Q >= 1

ldaa Padda Qcmpa #1blt ELSE_PART

b. ; IF Q > P - Rldaa Qadda Rcmpa P ; Q + R > P?ble ELSE_PART

c. ; IF (P > R ) OR (Q < R) ldaa Pcmpa Rbgt THEN_PARTldaa Qcmpa Rbge ELSE_PART

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d. ; IF (P > R) AND (Q < R)ldaa Pcmpa Rble ELSE_PARTldaa Qcmpa Rbge ELSE_PART

6.4 Write M68HC12 assembly language code for the following pseudocode designassuming K1, K2, and K3 are 8-bit, signed or unsigned, numbers in memory locationsK1, K2, and K3. Assume memory has been allocated for these data.

s6-4ansc.asm Assembled with CASM 12/08/1998 21:14 PAGE 1

1 ; WHILE K1 does not equal $0d 2 while_start: 0000 B6001C 3 ldaa K1 0003 810D 4 cmpa #$0d 0005 2715 5 beq end_while 6 ; DO 7 ; IF K2 = K3 0007 B6001D 8 ldaa K2 000A B1001E 9 cmpa K3 000D 2608 10 bne else_part 11 ; THEN 12 ; K1 = K1 + 1 000F 72001C 13 inc K1 14 ; K2 = K2 - 1 0012 73001D 15 dec K2 0015 2003 16 bra end_if 17 ; ELSE 18 else_part: 19 ; K1 = K1 -1 0017 73001C 20 dec K1 21 ; ENDIF K2 = K3 22 end_if: 23 ; ENDO 24 ; ENDOWHILE 001A 20E4 25 bra while_start 26 end_while: 27 28 ; Data variables 001C 29 K1: DS 1 001D 30 K2: DS 1 001E 31 K3: DS 1

6.5 Write a section of M68HC12 code to implement the design given below where K1 andK2 are unsigned 8-bit numbers in memory locations K1 and K2.


1 ; IF K1 < K2 0000 B60012 2 ldaa K1 0003 B10013 3 cmpa K2 0006 2405 4 bhs Else_Part 5 ; THEN K2=K1 0008 7A0013 6 staa K2 000B 2005 7 bra Endif 8 ; ELSE K1=64 9 Else_Part: 000D 8664 10 ldaa #!64 000F 7A0012 11 staa K1

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12 Endif: 13 ; ENDIF K1 < K2 0012 14 K1: DS 1 0013 15 K2: DS 1

6.6 Write a section of M68HC12 code to implement the design given below where K1, K2and K3 are signed 8-bit integer numbers stored at memory locations K1, K2 and K3.


1 ; WHILE K1 < K2 2 While_Start: 0000 B60023 3 ldaa K1 0003 B10024 4 cmpa K2 0006 2C1B 5 bge End_While 6 ; DO 7 ; IF K3 > K2 0008 B60025 8 ldaa K3 000B B10024 9 cmpa K2 000E 2F08 10 ble Else_Part 11 ; THEN K2 = K1 0010 B60023 12 ldaa K1 0013 7A0024 13 staa K2 0016 2006 14 bra End_If 15 ; ELSE K2 = K3 16 Else_Part: 0018 B60025 17 ldaa K3 001B 7A0024 18 staa K2 19 End_If: 20 ; ENDIF K3 > K2 21 ; K1 = K1 + 1 001E 720023 22 inc K1 23 ; ENDO 0021 20DD 24 bra While_Start 25 26 End_While: 27 ; ENDWHILE K1 < K2 28 ; Data allocation 0023 29 K1: DS 1 0024 30 K2: DS 1 0025 31 K3: DS 1

6.7 For problem 6.6, assume K1=1, K2=3 and K3= -2. How many times should the codepass through the loop and what are the final values of K1, K2 and K3?

One pass through the loop; final values are K1=2, K2= -2, and K3= -2;

6.8 Write structured M68HC12 code for the following design:IF A1 = B1 THEN WHILE C1 < D1 DO Decrement D1 A1 = 2 * A1 ENDO ENDWHILE C1 < D1 ELSE A1 = 2 * B1ENDIF A1 = B1Assume that A1, B1, C1, and D1 are 16-bit unsigned-binary numbers and that memory

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has been allocated in the program by the following code:A1: DS 2B1: DS 2C1: DS 2D1: DS 2Assume A1, B1, C1 and D1 are initialized to some value in some other part of theprogram.


1 ; IF A1 = B1 0000 FC002D 2 ldd A1 0003 BC002F 3 cpd B1 0006 261C 4 bne else_part 5 ; THEN 6 ; WHILE C1 < D1 7 while_start: 0008 FC0031 8 ldd C1 000B BC0033 9 cpd D1 000E 2412 10 bhs end_while 11 ; DO 12 ; Decrement D1 0010 FE0033 13 ldx D1 0013 09 14 dex 0014 7E0033 15 stx D1 16 ; A1 = 2 * A1 0017 FC002D 17 ldd A1 001A F3002D 18 addd A1 ; Double it 001D 7C002D 19 std A1 20 ; ENDO 21 ; ENDWHILE C1 < D1 0020 20E6 22 bra while_start 23 end_while: 0022 2009 24 bra end_if 25 ; ELSE 26 else_part: 27 ; A1 = 2 * B1 0024 FC002F 28 ldd B1 0027 F3002F 29 addd B1 002A 7C002D 30 std A1 31 ; ENDIF A1 = B1 32 end_if: 002D 33 A1: DS 2 002F 34 B1: DS 2 0031 35 C1: DS 2 0033 36 D1: DS 2

6.9 For problem 6.8, assume A=2, B=2, C=3, and D=6. What final values do you expectafter the code has been executed? A=16, B=2, C=3, D=3.

6.10 For the program in Example 6-11, how does the assembler evaluate the expressionDATA2-DATA1. What is it's value. Why does one use an expression here instead ofjust putting in a defined (equated) constant value?

DATA2-DATA1 = 4. You use an expression to let the assembler calculate thesize of the buffer. That way, if the number of bytes in DATA1 changes, theprogram automatically changes when it is reassembled.

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6.11 For the program in Example 6-11, what is printed on the screen when the program isexecuted?

STAa carriage-return, line-feed.6.12 Why are JSR instructions used to branch to the D-Bug12 Monitor subroutines rather than

BSR instructions?BSR instructions are relative addressing and the monitor subroutines are morethan 127 bytes away. So a JSR instruction that uses extended addressing must beused.

6.13 For the program in Example 6-12, how many bytes are reserved for "data" in the RAM. How many bytes of stack are used by the program?

NUMCHR+3 = 6. The program uses two bytes of the stack each time it jumps to amonitor subroutine plus whatever the routine uses.

6.14 How does the D-Bug12 Monitor know when to stop printing characters in the printfroutines?

An NULL character ($00) signifies the end of the string to be printed.6.15 Write a routine using the putchar() monitor subroutine to output characters to the

terminal. Assume the register X points to the start of the string to be output and thestring is terminated by the ASCII EOT character.

6.16 Write a routine that outputs the character in A. The routine is to check for unprintableASCII characters (codes $00-$1F, $7F-$FF). If one of these characters occurs, printthe "#" character.

6.17 A 16-bit number is in sequential memory positions DATA1 and DATA1+1 with themost significant byte in DATA1. Write an M68HC12 code segment to store thenegative of this 16-bit number in DATA2 and DATA2+1.


7.1 What levels must be on the BKGD, MODA and MODB pins at &R&E&S&E&T to place theM68HC12 into normal-expanded mode? (1 0 1)

Into normal single-chip mode? (1 0 0)7.2 Give the data register addresses for Port A, B, C, H, and J.

PORTA = $0000, PORTB = $0001, PORTC = $0004, PORTH = $0024, PORTJ =$0028

7.3 How do you control the direction of the bidirectional bits in the M68HC12 I/O ports. Each of the bidirectional data ports has a data direction register. Writing a one to abit in the DDR enables that bit to be an output.

7.4 Design an output circuit with 8 LEDs connected to Port B. The LEDs are to be on whenbits in a byte stored in location DATA1 are 1's. Show the hardware and softwarerequired.

7.5 Design an input circuit to input the states of eight switches to the M68HC12.

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8.1 When the I bit in the condition code register is set to 1, interrupts are: B. disabled.

8.2 Interrupts are masked when you get to the interrupt service routine - true.8.3 In the M68HC12 interrupt service routine, you MUST unmask interrupts with the CLI

instruction before returning - false.8.4 How are interrupts unmasked if the CLI instruction is not executed in the interrupt

service routine?When the condition code register is pulled from the stack by the RTI instruction,the I bit is cleared.

8.5 How many bytes are pushed onto the stack when the M68HC12 processes an interruptrequest? 9

8.6 Which instruction is used to globally unmask interrupts? CLI8.7 Which instruction is used to globally mask interrupts? SEI8.8 What address does the M68HC12 use to find the address of your interrupt service

routine for a timer overflow? $FFDE:FFDF8.9 Assume a dedicated application system (no D-Bug12 Monitor) with ROM at $E000-

$FFFF and RAM at $0800 - $0BFF. Show how to initialize the interrupt vectors for the&I&R&Q and Timer Channel 1 interrupts. Assume IRQISR and TC1ISR are labels on therespective interrupt service routines.

prb8_9c.asm Assembled with CASM 01/25/1998 21:45 PAGE 1

0000 1 TC1VEC: EQU $FFEC ; TC1 Vector location 0000 2 IRQVEC: EQU $FFF2 ; IRQ Vector location 0000 3 PROG: EQU $E000 ; Program location 4 ; E000 5 ORG PROG 6 ; E000 A7 7 TC1ISR: nop ; TC1 ISR E001 0B 8 rti 9 ; E002 A7 10 IRQISR: nop ; IRQ ISR E003 0B 11 rti 12 ; Locate the vectors FFEC 13 ORG TC1VEC FFEC E000 14 DW TC1ISR FFF2 15 ORG IRQVEC FFF2 E002 16 DW IRQISR

8.10 Repeat problem 8.9 but assume your code is to be run on a system with a D-Bug12Monitor. Show the code that is necessary to vector the M68HC12 to the correctinterrupt service routines.


0000 1 TC1NUM: EQU !22 ; User Vector Number for TC1 0000 2 IRQNUM: EQU !25 ; User Vector Number for IRQ 0000 3 SetVec: EQU $FE1A ; D-Bug12 SetUserVector 0000 4 PROG: EQU $0800 ; Program location 0000 5 STACK: EQU $0A00 ; Stack location

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6 ; 0800 7 ORG PROG 0800 CF0A00 8 lds #STACK 9 ; 10 ; Initialize the vector for TC1 0803 CC081C 11 ldd #TC1ISR ; Get the address of the ISR 0806 3B 12 pshd ; Put on the stack 0807 CC0016 13 ldd #TC1NUM 080A 15FBF60C 14 jsr [SetVec,pcr] 15 ; Initialize the vector for IRQ 080E CC081E 16 ldd #IRQISR ; Get the address of the ISR 0811 3B 17 pshd ; Put on the stack 0812 CC0019 18 ldd #IRQNUM 0815 15FBF601 19 jsr [SetVec,pcr] 0819 1B84 20 leas 4,sp ; Clean up stack 21 ; - - - 081B 3F 22 swi 081C A7 23 TC1ISR: nop ; TC1 ISR 081D 0B 24 rti 25 ; 081E A7 26 IRQISR: nop ; IRQ ISR 081F 0B 27 rti

8.11 For the interrupt service routine in Example 8-10, where would you put a breakpoint tofind out if you are getting to the interrupt service routine.

Set a breakpoint at the first instruction in the ISR.8.12 Assume you have written a program similar to Example 8-10 where the bell is to beep

whenever you assert Port H, bit-0. When you run the program, instead of beeping once,the bell beeps continuously, much to the annoyance of your lab partners and supervisor. What has gone wrong?

The programmer has not reset the key wakeup flag properly in the interruptservice routine.

8.13 Write a complete M68HC12 program in assembly language for an interrupt occurring onthe external IRQ source. The interrupt vector is to be at $FFF2:FFF3. When theinterrupt occurs the ISR is to increment an 8-bit memory location "COUNT" startingfrom $00. The foreground job is to be a spin loop "SPIN BRA SPIN". Assume:1. The D-Bug12 monitor is not installed.2. Code is to be located in ROM at $E000.3. RAM is available between $0800 and $0BFF


0000 1 PROG: EQU $E000 ; Program Location 0000 2 STACK: EQU $0A00 ; Stack Location 0000 3 RAM: EQU $0800 ; RAM Location 0000 4 IRQVEC: EQU $FFF2 ; IRQ Vector Location 0000 5 IRQEN: EQU %01000000 ; IRQ Enable Bit 0000 6 INTCR: EQU $1e ; Interrupt Control Register 7 ; Allocate Data Area 0800 8 ORG RAM 0800 01 9 Count: DB 1 10 ; E000 11 ORG PROG E000 CF0A00 12 lds #STACK ; Initialize stack pointer 13 ; Initialize memory counter = 0

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E003 790800 14 clr Count 15 ; Enable the IRQ interrupt E006 4C1E40 16 bset INTCR,IRQEN 17 ; Unmask interrupts E009 10EF 18 cli 19 ; Foreground job is a spin loop E00B 20FE 20 spin: bra spin 21 ; 22 ; Interrupt Service Routine E00D 720800 23 ISR: inc Count ; No overflow detection E010 0B 24 rti 25 ; Initialize the vector for IRQ FFF2 26 ORG IRQVEC FFF2 E00D 27 DW ISR

8.14 What is the priority order of interrupts in the M68HC12.See the list of interrupt vector assignments in Table 8-4.

8.15 How can the priority order of interrupts be changed?The HPRIO register contains eight bits which can allow any of the interruptsources to be promoted to the top of the hierarchical order. The priority can onlybe changed when the interrupts are masked (I-bit = 1).

8.16 The Timer Channel 3 interrupt and the Real Time Interrupt happen to occursimultaneously. Which is serviced first?

The Real Time Interrupt is service first unless the Timer Channel 3 has beenpromoted to the highest position by reprogramming the HPRIO register.

8.17 What is the SWI instruction and what does it do?SWI is a software interrupt instruction. It is a single byte and CPU treats it as ifan interrupt has occurred. All registers are pushed onto the stack and theprocessor fetches a vector from $FFF6:FFF7.

8.18 What instructions can be used to reduce power consumption when waiting for aninterrupt to occur?

WAI and STOP.8.19 Define interrupt latency.

Interrupt latency is the time delay between the interrupt request and when theinterrupt service routine is entered.

8.20 What are the components of interrupt latency?Interrupt latency is comprised of the following:1) The time to complete executing the current instruction. 2) The time to push the registers onto the stack.3) The time to fetch the vector and transfer to the interrupt service routine.In addition, if the processor is in another ISR with interrupts masked, the latencyis increased by the time required to complete the ISR and unmask the interrupts.

8.21 Show how to modify the code in Example 8-4 to have the ISR service all interruptsgenerated by any of the four key wakeup bits.

; Interrupt Service routineISR:; Service all interrupts that have been generated.; Check each one in turn

ldaa KWIFJ ; Get the flags; IF bit-0

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bita #BIT0beq Chk_1

; THEN DO the bit-0 ISR; . . .; IF bit-1Chk_1: ldaa KWIFJ ; Get the flags

bita #BIT1beq Chk_2


bita #BIT2beq Chk_3


bita #BIT3beq Done

; THEN DO the bit-3 ISR; . . .;Done:; Now reset all flags that have been set

ldaa KWIFJstaa KWIFJrti ; Return to interrupted prog


9.1 On reset, the RAM in the MC68HC812A4 is mapped to $0800 and the 512 byte registerblock to $0000. The locations of these can be changed. Describe how this is done.

The INITRM ($0010) and INITRG ($0011) can be programmed with the mostsignificant byte of the new address. This can be done only once in your program.

9.2 What registers are used to remap the data RAM, EEPROM, and control registers?The INITRM ($0010), INITEE ($0012) and INITRG ($0011) registers.

9.3 What is the default memory location of EEPROM in the MC68HC812A4? $1000-$1FFF in expanded mode systems and $F000-$FFFF in single-chipsystems.

9.4 What is the default memory location of the Flash EEPROM in the MC68HC912B32 insingle-chip mode? In expanded mode?

$8000-$FFFF single-chip mode and $0000-$7FFF (although disabled) inexpanded-modes.

9.5 What are the three methods that can erase EEPROM?Byte erase, row erase, bulk erase.

9.6 How does the M68HC12 generate the 19 volts needed to program the EEPROM?A charge pump is used to generate the EEPROM programming voltage. The

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program turns the charge pump on and then must wait at least 10 ms for theprogramming to be completed.


10.1 What is wrong with the following code to get the 16-bit value of the TCNT register?LDAA $84 Get the high byteLDAB $85 Get the low byteIf the TCNT register is incrementing at each M-clock cycle, the low byte will havechanged during the time the high byte is being read.

10.2 What is wrong with the following code to get the 16-bit value of the TCNT register?LDAB $85 Get the low byteLDAA $84 Get the high byteIf the TCNT register is incrementing at each M-clock cycle, by the time you getthrough reading the low byte, it may have overflowed, causing the high byte to beincremented by one.

10.3 How should you read the 16-bit TCNT value?LDD $84 Latches the 16-bit data from the TCNT register so the value is

stable.10.4 How is the TCNT clock prescaler programmed?

Bits PR2, PR1 and PR0 in the TMSK2 register may be set by the programmer.10.5 Give the name of the bit, the name of the register that it is in, the register's address, which

bit, and the default or reset state of the bit for each of the following:a. What bit indicates that the timer has overflowed?

Timer overflow flag, TOF, in the TFLG2 register at $8F, bit-7; the reset state is 0.b. What bit enables the timer overflow interrupts?

TOI in the TMSK2 register at $8D, bit-7. The default state is interrupts disabled.c. What bits are used to prescale the timer clock?

PR2, PR1 and PR0, in the TMSK2 register at $8D, bits 2, 1 and 0. The default stateis 000 to divide by 1.

10.6 When is the timer overflow flag set? When the TCNT register rolls over from $FFFF to $0000.

10.7 How is the timer overflow flag reset?By the software writing a one to bit-7 of TFLG2 register.

10.8 What timing resolution can be achieved with the output compare?1 M-clock cycle times the prescaler value in TMSK2.

10.9 Give the name of the bit, the name of the register that it is in, the register's address, whichbit, and the default or reset state of the bit for each of the following:a. What bit indicates that a comparison has been made on Output Compare 2?

C2F, in the TFLG1 register at $8E, bit 2. The reset state is 0.b. What bit enables the Output Compare 2 interrupt?

C2I, in the TMSK1 register at $8C, bit 2. The reset state is interrupts disabled.c. What bits are used to set the Output Compare 3 I/O pin high on a successful

comparison?OM3 and OL3 in the TCTL2 register at $89, bits 7 and 6. The reset state is for thetimer to be disconnected from the output pin.

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10.10 Write a small section of code to set the Output Compare 2 I/O pin to toggle on everycomparison.

ldaa #%00010000 ; Set OM2, OL2 to 01staa $89 ; Write to TCTL2 register

10.11 Write a small section of code to enable Output Compare 1 to set bits PT7, PT6 and PT5to one on the next successful comparison.

ldaa #%11100000 ; Set bits 7,6,5 highstaa $83 ; Write the Output Compare data register OC7Dstaa $82 ; Enable bits 7, 6, and 5 in OC7M mask reg

10.12 What two registers control which data bits are output when the Output Compare 7 flag isset?

The Output Compare 7 Data (OC7D) register located at $83 and the OutputCompare 7 Mask (OC7M) register located at $82.

10.13 How does the programmer select the active edge for Input Capture 2?Timer Control Register 4 (TCTL4) at $8B contains bits to select the edge used forthe input capture. Bits 5 and 4 control the edge for IC2 by the following truth table:

EDG2B EDG2A Edge 0 0 Capture Disabled 0 1 Capture on rising edges only 1 0 Capture on falling edges only 1 1 Capture on any edge, rising or falling

10.14 Write a short section of code demonstrating how to reset the Input Capture 2 Flag C2F.ldaa #%00000100 ; C2F positionstaa $8E ; Write to TFLG1

10.15 Write a short section of code demonstrating how to enable the Input Capture 1 interrupts.ldaa #%00000010 ; C1I positionstaa $8C ;Write to TMSK1

10.16 Write a short section of code demonstrating how to enable the real time interrupt and toset the nominal rate to 16.384 ms assuming a 8 MHz M-clock.

bset $14,#%00000101 ; Set RTR2, RTR0 in RTICTLbclr $14,#%00000010 ; Clear RTR1 in RTICTLbset $15,#%10000000 ; Write to RTIFLG to reset real

; time interrupt flagbset $14,#%10000000 ; Write to RTICTL to enable real

; time interrupts10.17 Write a short section of code demonstrating how to reset the COP timer.

ldaa #$55 ; Arm patternstaa $17 ; Write to COPRST registerldaa #$AA ; Reset patternstaa $17 ; Write to COPRST register

10.18 Write a short section of code demonstrating how to enable the Pulse Accumulator as anevent counter counting rising edges.

bset $A0,#%01010000 ; Set PAEN and PEDGE in PACTLbclr $A0,#%00100000 ; Clear PAMOD in PACTL

10.19 Write a short section of code demonstrating how to enable the Pulse Accumulator as agated time accumulator with a high level enable accumulation.

bset $A0,x %01100000 ; Set PAEN and PAMOD in PACTLbclr $A0,x %00010000 ; Clear PEDGE in PACTL

10.20 What bit in what register must be set to enable the Pulse Accumulator Input Edgeinterrupt?

PAI, bit-0 in PACTL, $A0 must be set.

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11.1 For the SCI0, give the name of the bit, the name of the register it is in, the register'saddress, which bit, and the default or reset state of the bit for each of the following:a. What bit enables the SCI0 transmitter?

TE, in the SC0CR2 register at $C3, bit-3; the transmitter is disabled on reset.b. What bit enables the SCI0 receiver?

RE, in the SC0CR2 register at $C3, bit-2; the receiver is disabled on reset.c. What bit determines how many data bits are sent?

M (mode), in SC0CR1 at $C2, bit-4; the default is 1 start, 8 data and 1 stop bit.d. What bit can the user test to see if the last character has cleared the transmit data

buffer?TDRE, in the SC0SR1 at $C4, bit-7; the default is that the buffer is empty.

e. What bit can the user test to see if a new character has been received?RDRF, in the SC0SR1 at $C4, bit-5; the default is that the register is not full.

f. What bit is used to indicate the software is not reading data from the SC0DRL fastenough?OR, in SC0SR1 at $C4, bit-3; no overrun by default.

g. What bit is an indication that the communication channel is noisy?NF, in SC0SR1 at $C4, bit-2; default is no noise.

h. What bit is an indication that the sending and receiving baud rates may not beidentical?FE, in SC0SR1 at $C4, bit-1; default to no framing error.

11.2 For the SCI0, give the name of the bit, the name of the register it is in, the register'saddress, which bit, and the default or reset state of the bit for each of the following:a. What bit enables an interrupt when the transmit buffer is empty?

TIE, in the SC0CR2 register at $C3, bit-7; TDRE interrupts are disabled.b. What bit enables an interrupt when the transmitter has completely emptied its

serial shift register?TCIE, in the SC0CR2 at $C3, bit-6; transmit complete interrupts are disabled.

c. What bit enables interrupts by the SCI0 receiver?RIE, in the SC0CR2 at $C3, bit-5; receiver interrupts are disabled.

11.3 What SCI0 receiver conditions can generate an interrupt?Receive data register full, receiver overrun, idle line detect.

11.4 What different status information do the SCI0 status bits TDRE and TC give?TDRE indicates that the last character has been transferred from the SC0DRLtransmit register to the output shift register. TC, transmission complete, indicatesthat the last character has been shifted out of the shift register.

11.5 Give the meanings of the following mnemonics.TDRE - Transmit Data Register EmptyTC - Transmission CompleteRDRF - Receive Data Register FullOR - (Receiver) OverRunFE - Framing Error

11.6 What is the M68HC12 I/O address for the SC0BDH register? $C0

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11.7 What is the value used to initialize the SCI0 for 4800 baud assuming an E-clock = 8.0MHz? 10410

11.8 Which port and which bits are the serial communications interface (SCI0) transmittedand received data? Port S, Pins 1 (TxD) and 0 (RxD)

11.9 For the SPI, give the name of the bit, the name of the register it is in, the register'saddress, which bit, and the default or reset state of the bit for each of the following:a. What bit enables the SPI?

SPE, in the SP0CR1 register at $D0, bit-6; the default state is SPI disabled.b. What bit selects the master or slave mode?

MSTR, in the SP0CR1 register at $D0, bit-4; SPI configured as a slave.c. What bits select the data transfer rate?

SPR2, SPR1, SPR0, in the SP0BR register at $D2, bit-2, -1, -0; the reset state is000.

d. What bit is the Master Output/Slave Input?MOSI, Port S, $D6, bit-5; the default is to act as Port S, bit-5.

e. What bit is the Master Input/Slave Output?MISO, Port S, $D6, bit-4; the default is to act as Port S, bit-4.

11.10 For the SPI, give the name of the bit, the name of the register it is in, the register'saddress, which bit, and the default or reset state of the bit for each of the following:a. What bit indicates the SPI has completely sent the last data?

SPIF, SP0SR at $D3, bit-7; default state is reset.b. What bit indicates an error has occurred when new data has been written to the

output register before the old data has cleared?WCOL, SP0SR at $D3, bit-6; default is reset.

c. What bit is set to enable SPI interrupts?SPIE, SP0CR1 at $D0, bit-7; interrupts are disabled.

11.11 How does the SPI differ from the SCI?The SPI is a synchronous serial port. Data bits are transferred from a master to aslave when the master generates a SCK signal. Data rates can be much higherwith this system than with the SCI.

11.12 How does a slave station SPI send data to the master station?The slave station shifts data to the master as the master is shift data to the slave. All data transfer is controlled by the master SCK signal.

11.13 What do the following mnemonics mean in the operation of the SPI?&S&S - Slave select; SCK - SPI Clock; MOSI - Master Out, Slave In; MOMI -Master Out, Master IN; MISO - Master In, Slave Out; SISO - Slave In, Slave Out;SPIE - SPI Interrupt Enable; SPE - SPI System Enable; MSTR - Master/slaveMode Select


12-1 How is the A/D powered up?By writing a 1 to the ADPU bit in the ATDCTL2 register.

12-2 How long must the program delay before using the A/D after powering it up?At least 100 µs.

12-3 The A/D is programmed to convert a sequence of four channels in continuousconversion mode. What is the maximum frequency signal on PAD0 that can be

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converted without aliasing (ignore aperture time effects, assume the final sample time istwo ATD clocks and the ATD clock is 2 MHz).

The conversion time for any one channel is 18 ATD clock periods giving the totalsequence conversion time of 72 clocks = 36 µs. Thus the sampling frequency forany one channel is 27.78 kHz and the Nyquist frequency is 13.89 kHz.

12-4 The analog input ranges from 1 volt to 4 volts.a. What should V and V be? V = 4V, V = 1 V.RH RL RH RL

b. What is the resolution? 3 V/256 = 11.72 mVc. The analog result register shows $56. What is the analog voltage?

$56 = 86 . The input voltage is 86*11.72 mV + V = 1.007 V + 1.000 V = 2.00710 RL

V.12-5 The analog input is 0 to 5 volts and V = 5, V = 0. The A/D reading is $24. What isRH RL

the analog input voltage?$24 = 36 . The resolution is 5 V/256 = 19.5 mV, therefore the input voltage is10

36*19.5 mV = 0.70 V.12-6 The following bytes are written to the ATDCTL to initiate the conversion. Give the

channels expected in the A/D result registers ADR0H - ADR7H.Byte ADR0 ADR1 ADR2 ADR3 ADR4 ADR5 ADR6 ADR700000000 PAD0 PAD0 PAD0 PAD0 ---- ---- ---- ----00000100 PAD4 PAD4 PAD4 PAD4 ---- ---- ---- ----00010000 PAD0 PAD1 PAD2 PAD3 ---- ---- ---- ----00010100 PAD4 PAD5 PAD6 PAD7 ---- ---- ---- ----01010000 PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD701001100 V V V V V V V VRH RH RH RH RH RH RH RH


13-1 Using table-lookup (instead of a fuzzy logic system), how many bytes would be neededfor the table in a system with three inputs with 8-bit resolution on each input and oneoutput with 8-bits resolution?

256 x 256 x 256 = 16,777,21613-2 Referring to Figure 13-4, for what temperature or temperatures are the expressions

'temperature is cold' and 'temperature is warm' true to the same degree?$78 to $88

13-3 Sketch graphical representations of the following input membership functions...a) LOW FCB $20,$60,$08,$10 ;pt1,pt2,slope1,slope2b) MID FCB $60,$A0,$10,$0B ;pt1,pt2,slope1,slope2c) HI FCB $A0,$E0,$0B,$08 ;pt1,pt2,slope1,slope2

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Problem 13-3.

13-4 What is the maximum number of rules that would be needed in a fuzzy logic system thathas three inputs with three labels each? How many fuzzy inputs would there be in such asystem and how many bytes of RAM would that require?

There are a maximum of 3 x 3 x 3 = 27 rules. Each of the three inputs has threelabels so there are nine fuzzy inputs and these require nine bytes of storage.

13-5 For the fuzzy logic system in Example 13-4, how many bytes of memory in theknowledge base did it take for all 25 rules?

There are five bytes for each rule plus the Rule_end separator = 126 bytes.13-6 In Figure 13-9, how many rules would be active if temperature was $C0 and pressure

was $90? Which rule(s) would be active?Four rules are active; [19], [20], [24], [25]

13-7 Using Figure 13-11, what value should be in FanSpeed if temperature is $B0 andpressure is $38?

$58

Fan Speed' $00($80%$00($00%$00($00%$00($00%$00($00$80%$00%$00%$00%$00

Fan Speed'$00$80

'$00

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13-8 Manually perform the defuzzification computation for the system in Example 13-4 if thetemperature is $60 and pressure is $20.

Using Figure 13-8, the fuzzified inputs are:Cold = 0, Cool = $FF, Normal = 00, Warm = 00, Hot = 00VeryLo = $80, Low = $80, Med = 00, High = 00, VeryHi = 00Using a rule matrix like Table 13-3 we can complete a rule evaluation table likeTable 13-4:

Rule evaluation

Rule Fuzzy Input #1 Fuzzy Input #2 Min(#1:#2) Output Max(Min:Current)Current Fuzzy New Fuzzy Output

1 Cold=$00 VeryLo=$80 $00 Stop=$00 Stop=$002 Cold=$00 Low=$80 $00 Stop=$00 Stop=$003 Cold=$00 Medium=$00 $00 Stop=$00 Stop=$004 Cold=$00 High=$00 $00 Stop=$00 Stop=$005 Cold=$00 VeryHi=$00 $00 Stop=$00 Stop=$00

6 Cool=$FF VeryLo=$80 $80 Stop=$00 Stop=$807 Cool=$FF Low=$80 $80 Stop=$80 Stop=$808 Cool=$FF Medium=$00 $00 Slow=$00 Slow=$009 Cool=$FF High=$00 $00 Slow=$00 Slow=$0010 Cool=$FF VeryHi=$00 $00 Slow=$00 Slow=$00

11 Normal=$00 VeryLo=$80 $00 Slow=$00 Slow=$0012 Normal=$00 Low=$80 $00 Slow=$00 Slow=$0013 Normal=$00 Medium=$00 $00 Mid=$00 Mid=$0014 Normal=$00 High=$00 $00 Mid=$00 Mid=$0015 Normal=$00 VeryHi=$00 $00 Mid=$00 Mid=$00

16 Warm=$00 VeryLo=$80 $00 Slow=$00 Slow=$0017 Warm=$00 Low=$80 $00 Mid=$00 Mid=$0018 Warm=$00 Medium=$00 $00 Fast=$00 Fast=$0019 Warm=$00 High=$00 $00 Fast=$00 Fast=$0020 Warm=$00 VeryHi=$00 $00 Fast=$00 Fast=$00

21 Hot=$00 VeryLo=$80 $00 Mid=$00 Mid=$0022 Hot=$00 Low=$80 $00 Fast=$00 Fast=$0023 Hot=$00 Medium=$00 $00 Fast=$00 Fast=$0024 Hot=$00 High=$00 $00 FullOn=$00 FullOn=$0025 Hot=$00 VeryHi=$00 $00 FullOn=$00 FullOn=$00

From this we see the fuzzy outputs are:Stop = $80, Slow = 00, Mid = 00, Fast = 00, FullOn = 00

Using Figure 13-10 and equation (13.1) we calculate:

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Problem 14-1.

Problem 14-3.

This can be checked by using Figure 13-11.13-9 How many bytes of program space are used for the executable portion of the fuzzy logic

program in Example 13-4?!52


14-1 This is the waveform for one bit time in a BDM communication.Which direction is data being transferred (host-to-target or target-to-host)?

From the target HC12 to the host pod.14-2 Looking at the waveform in problem 14-1, what causes the portion of the waveform

labeled [1]? The portion labeled [2]?[1] is a slow RC rise because neither the host nor the pod is driving the BKGD pinat this time. [2] is the fast rising edge caused by the target-driven speedup pulse.

14-3 This is the waveform for a BDM command. What is the command?

READ_BD_BYTE from address $FF01. The data is $C0 (low half of $E4C0)14-4 Looking at the waveform in problem 14-3, what is the portion labeled [3] for?

This delay allows the target BDM to find a free bus cycle and complete the readso the host pod can read the data from the target HC12.

14-5 Draw an approximate waveform for a BDM command to write $81 to address $08F1.

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Problem 14-5.

14-6 Where are each of the user registers CCR, D, X, Y, SP, and PC saved while thebackground debug mode is active?

CCR is saved in the BDM register CCRSAV at $FF06 in the BDM map, D issaved in CPU temporary register TMP3, X, Y, and SP are not explicitly saved butthey do not change because the BDM firmware avoids using these registers, PC issaved in CPU temporary register TMP2.

14-7 Suppose a target application system is connected to a BDM pod. Which of the followingtypes of memory could be programmed using the BDM interface?a) an external 256 Kbyte RAM (in an MC68HC812A4 based system)b) 32 Kbyte on-chip flash EEPROM (in an MC68HC912B32 based system)c) on-chip EEPROMd) all of the abovee) b and c

d) All of the above. BDM can see any memory locations the CPU can see.14-8 The following state information was captured in an MC68HC12 system.

**************************************Label> ADDR DATA &&L&S&T&RB R&/ W Base > Hex Hex Binary Binary

001 0801 55AA 1 0**************************************What took place during this cycle?

&&L&S&T&RB:R/W:A0 = 1:0:1 (RW-TYP = WLH) This is a misaligned write of$AA55 to address $0801 in the on-chip RAM.

Use the following logic analyzer state listing to answer questions 14-9 through 14-14.**************************************Label> ADDR DATA RW_TYP PER PEF Base > Hex Hex Symbol Symbol Symbol

1 0822 7E09 R16 ALL sev ????/???? ????/???? ????/???? 2 7E09 7E09 R8L LAT sod 0822/7E09 ????/???? ????/???? 3 0824 01C6 R16 ALL ????/???? 0822/7E09 ????/???? 4____0826 64FD R16______ALD____sev__????/???? 0824/01C6 0822/7E09 5 0901 7698 WLH W LAT 0822 7E0901 STX $0901 6 7698 7698 R8H O-f (write $9876 to $0901) 7____0828 0800 R16_P____ALL____sod__ 8____082A 7D19 R16_P____ALD____sod__0825 C664 LDAB #$64 (100) 9 0800 8602 R16 R ALD 0827 FD0800 LDY $0800 10 082C 01CE R16 O-P (read $8602 from $0800) 11____082E 6000 R16_P____ALD sev__

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12 1901 1986 W8L Wh LAT 082A 7D1901 STY $1901 13 1902 0202 W8H Wl (write $8602 to $1901,1902) 14 0202 0202 R8H O-f 15____0830 CD61 R16_P____ALL____int__ 16 FFEC FF4E R16 V ALD Begin processing interrupt 17 09FE 082D W16 S LAT (vector $FF4E fetched from $FFEC) 18 FF4E 05FB R16 P (this is the Timer Ch.1 vector) 19 09FC 8602 W16 S ALD 20 09FA 9876 W16 S 21 FF50 F89A R16 P 22 09F8 6402 W16 S ALD 23 09F7 0988 W8L s 24____FF52 05FB R16_P___________sev__**************************************

14-9 Beginning from state 001, reconstruct the internal pipe activity until you reach the startof an identifiable instruction. What is the address, opcode, and disassembledinstruction?

Address=$0822, opcode=$7E, instruction= STX $090114-10 Which state numbers correspond to the execution of the disassembled instruction?

States 5, 6, and 714-11 There is a STY $1901 instruction in states 12-15. The instruction set documentation

says this instruction should take 3 cycles. Why did it take 4 cycles?The write was a misaligned write to an external address so it had to be split intotwo adjacent 8-bit writes.

14-12 Which state corresponds to a misaligned write to the on-chip RAM? What value waswritten, and to what address?

State 5, $9876 was written to $0901. The WLH mnemonic tells you it was amisaligned write to on-chip RAM, or you could have disassembled the instructionand noted that $901 is an odd address in the on-chip RAM.

14-13 An interrupt is serviced after state 15, what caused this interrupt?The interrupt was caused by timer channel 1 because the vector address was$FFEC

14-14 Find an O-f cycle and an O-P cycle in the state listing.States 6 and 14 are O-f cycles, state 10 is an O-P cycle

14-15 How is the tagging function enabled in the MC68HC12?By the serial BDM command TAG_GO.

14-16 Which tagging mode would you set, using a BDM debug pod, for the followingsituations? State the 3-bit value you would write to BKEN1:BKEN0:BKPM for eachcase.a) To break on any write to address $0945 or $0946b) To break just before executing the instruction at $0822c) To repair a program error at $8110 in on-chip ROMd) To break if the value $55 is written to port T

a) Dual address BDM (int) BKEN1:BKEN0:BKPM = 1:1:0 There are twoaddresses so a dual address mode is needed. R/W is needed in the breakpointspecification so the tagging mechanism can’t be used.b) Dual address BDM (tag) BKEN1:BKEN0:BKPM = 1:1:1 The taggingmechanism is needed since you want to break just before an instruction. Dualaddress BDM is called for because the problem statement said you have a BDM

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debug pod connected which implies you are doing debug through BDM.c) Dual address SWI (tag) BKEN1:BKEN0:BKPM = 0:1:x You don’t want amode that takes you to active background when you are doing program patches.d) Full address/data breakpoint (int) BKEN1:BKEN0:BKPM = 1:0:x This is theonly mode that allows you to match a data value.

14-17 What value would you write to BRKCT0:BRKCT1 to establish a breakpoint for a writeof $80 to PORTB (address $0001)?

BKCTL0:BKCTL1 = $805214-18 Which breakpoint type(s) require a valid user stack?

a) SWI-based software breakpointsb) BGND-based software breakpointsc) Hardware breakpointsd) All of the abovee) None of the above

a) Of the types listed, only the SWI-based software breakpoint requires a validuser stack.

14-19 What values would be written to all six registers in the breakpoint module to establishbreakpoints for the instructions at $820 and $843?

BKCTL0:BKCTL1 = $EC40 or: BKCTL0:BKCTL1 = $EC40BRKDH:BRKDL = $0843 BRKDH:BRKDL = $0820BRKAH:BRKAL = $0820 BRKAH:BRKAL = $0843

14-20 What is the breakpoint condition that is set by writing the following values to thebreakpoint registers?BRKCT0 = $80BRKCT1 = $72BRKAH = $09BRKAL = $FEBRKDH = $34BRKDL = $12

Full address/data breakpoint (int); compare all 16 bits of data, R/W=0 (write);data to match is $3412; address to match is $09FE. Break at the next instructionboundary after a write of $3421 to address $09FE.

Copyright 2000 Oxford University Press

INSTRUCTOR'S MANUAL SOFTWARE AND HARDWARE · PDF file2 1 INTRODUCTION Software and Hardware...

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