CMPT 250 Computer Architecture

Instructor: Yuzhuang Huyhu1@cs.sfu.ca

Final

August 7, 2009

7:00pm - 10:pm

HCC1700

I/O Interface UnitsPeripherals are often eletro-mechanical devices whose

manner of operation is different from that of the CPU and memory.

The data-transfer rate of peripherals is usually different from the clock rate of the CPU.

Data codes and formats in peripherals differ from the word format in the CPU.

The operating modes of peripherals differ from each other.

I/O bus and interface

Modes of Transfer

Data transfer under program control.

Interrupt-initiated data transfer.

Direct memory access transfer.

Program-Controlled Transfer

Interrupt-Initiated Transfer

SP <- SP – 1 Decrement stack pointerM[SP] <- PC Store return address on stackSP <- SP – 1 Decrement stack pointerM[SP] <- PSR Store processor status word

on stackEI <- 0 Reset enable-interrupt flip-

flopINTACK <- 1 Enable interrupt

acknowledgePC <- IVAD Transfer interrupt vector

address to PC, go to fetch phase

Final

August 7, 2009

7:00pm - 10:pm

HCC1700

Sequential Circuit Design

Design from ASM

processor

status

control pts

SEQ

CTRL PTSSELECTORExternal

control inputs

Data in Data out

Clock

VHDL

Write some VHDL codes.

Processes in VHDL.

Pipeline

Execution of the instructions in each stage.

Hazards.Find data and control hazards.Avoid data and control hazards.

Insert NOP Change the order of the instructions Other methods

Data hazardsConsider the following instructions

1. MOV R1, R5

2. ADD R2, R1, R6

3. ADD R3, R1, R2

IF DOF EX WB

IF DOF EX WB

IF DOF EX WB

1 2 3 4 5

Mov R1, R5Add R2, R1, R6Add R3, R1, R2

Cache Memory32 bit address, 1024 KB cache, 4 word line,

two way associative cache

Question: how many bits in tag and index?

tag index block byte

Overall picture

THANKS!