Instruction Set Architecture of 8085 Microprocessor ... · Prepared by Mr.S.Sayeekumar , AP/ EEE ,...
Transcript of Instruction Set Architecture of 8085 Microprocessor ... · Prepared by Mr.S.Sayeekumar , AP/ EEE ,...
Prepared by Mr.S.Sayeekumar , AP/ EEE , RMD ENGINEERING COLLEGE
Instruction Set Architecture of 8085 Microprocessor
Instruction Formats in 8085 Microprocessor :
1-BYTE INSTRUCTION : 2-BYTE INSTRUCTION : 3-BYTE INSTRUCTION :
DATA TRANSFER INSTRUCTIONS
Instruction
Name
RTL representation Explanation Illustration
MVI r, data(8)
r data(8) r – A,B,C,D,E,H,L
Move the mentioned 8-bit data
into a mentioned
register
MVI B , 08H B08H
Now B-register holds the 8-bit data 08H
MOV rd , rs
rd rs where rd or rs - A,B,C,D,E,H,L
Move the contents of
source register (rs)
into a destination register (rd)
MOV H,A Let A = 98H
Now H-register will have the contents of A-register (i.e. 98H)
LDA addr(16
)
A [Addr(16)] Load the contents of given 16-bit
memory location
into 8-bit accumulato
r
Let Addr(16) = 5645H Let [Addr(16)] = 67H
Then LDA 5645H A 67H
LHLD addr(16
)
L[Addr(16)] H[Addr(16) + 1]
Contents of given
memory
Let Addr(16) = 6547H [6547H] = 35H [6548H] = 48H
8-bit OPCODE 8-bit DATA or I/O PORT ADDRESS
8-bit DATA or Lower Byte of Memory location or I/O port Address
8-bit DATA or Higher Byte of Memory location or I/O port Address
8-bit OPCODE
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location will be loaded
into L-register and contents of subsequent
memory location will be moved
into H-register
Then LHLD 6547H L35H H48H
STAX rp [rp]A rp – BC ,DE
Contents of A-register are copied
into the 16-bit memory
location mentioned
in the register pair
Let BC = 8756H Let A = 0FH
Then STAX B Now the memory location 8756H
contains 0FH
XCHG H↔D , L↔ E Contents of HL register
pair are swapped with DE register
pair.
Let HL = ABCDH (i.e. H = AB , L = CD)
DE = B678H (i.e. D = B6 , E = 78)
Then XCHG HL = B678H
(i.e. H = B6 , L =78) DE = ABCDH
(i.e. D = AB , E = CD)
ARITHMETIC and LOGICAL OPERATIONS (or DATA MANIPULATION OPERATIONS)
ARITHMETIC OPERATIONS
ADD r AA+r r – A,B,C,D,E,H,L
Add the contents of accumulator and given register and
store the result in the accumulato
r
Let A = 06H B = 08H
Then ADD B A 06H + 08H
A 0EH
ADI data(8)
AA+data(8)
Add the contents of accumulator and given 8-bit data and store
Let A= 03H Data(8) = 08H Then ADI 08H A 03H + 08H
A0BH
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the result in the
accumulator
ADC r AA+r+Cy r – A,B,C,D,E,H,L
Add the contents of accumulato
r , given register and
carry and store the
result in the accumulato
r
Let C = 20H A = 50H CY = 1
Then ADC C A 50H + 20H + 1
A 71H
ACI data(8)
A A+ data(8) + Cy Add the contents of accumulator , given 8-
bit data and carry and store the result in
accumulator
Let A =30H Data(8) = 20H
CY = 1 Then ACI 20H
A 30H + 20H + 1 A51H
DAD rp HL HL + rp rp – BC , DE ,HL , SP
Add the 16-bit contents
of HL register pair with given
register pair and store
the result in HL register
pair.
Let DE = 1020H HL = 2050H Then DAD D
HL 2050H + 1020H HL 3070H
i.e. H = 30 H , L = 70H
SUB M AA-M M is memory location given by the contents
of HL register pair
Subtract the 8-bit
contents of Accumulator and given
Memory location
and store the result in accumulato
r
Let HL = 1020H Let [1020H] = 10H
A = 50H Then SUB M
A 50H – 10H A40H
SBI data(8)
AA-data(8)-CY Subtract the
Let A = 50H , data(8) = 20H , CY = 1 Then SBI 20H
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contents of accumulator , given 8-
bit data and carry and store the result in
accumulator
A 50H – 20H – 1 A 2FH
DAA A(BCD) A(Binary) Adjust the contents of accumulato
r into a packed BCD
number
Let A = 39H , C = 12H Then ADD C
A4BH Now DAA
Since the lower nibble is > 9 [ie. In 4B H , 4 is higher nibble and B is lower nibble] ,
add 0110 (06H) to it. Therefore A 51[BCD]
INR r r r + 1 r – A,B,C,D,E,H,L
Increment the content of specified register by
1.
Let B = 10H Then INR B B B + 1 B 10 + 1
B11H
DCX rp rp rp – 1 rp BC , DE , HL , SP
Decrement the
contents of given
register pair by 1
Let DE = 1020H Then DCX D DE101FH
LOGIC OPERATIONS
ANA r A A ^ r Logically AND the
contents of accumulator and given register and
store the result in
accumulator
Let A = AAH B = 0FH
Then ANA B A AAH ^ 0FH
A 0AH
ORA M A A ∨ M M is memory location given by the contents
of HL register pair
Logically OR the
contents of accumulator and given
memory location
and store
Let A = 55H , HL = 2050H [2050H] = B3H Then ORA M
A 55H ∨ B3H A F7H
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the result in accumulato
r
XRI data(8)
A A ⊕ data(8) Logically XOR the
contents of accumulator and given 8-bit data and store
the result in accumulato
r
Let A = B3H Data (8) = 39H Then XRI 39H
A B3H ⊕ 39H A 8AH
CMP r A – r Compare the
contents of accumulator and given
register. Compare
operation is similar to
subtraction operation
but result is not stored
in accumulato
r. CARRY FLAG is set according
to the result of
comparison.
When A ≥ r , CY = 0
When A < r , CY = 1
Let A = B8H D = B9H
Then CMP D CY = 1
Since A < D.
STC CY 1 Set Carry bit of FLAG
REGISTER = 1
Let CY = 0 Then STC
CY1
CMA A�̅� One’s complemen
t the contents of accumulato
Let A = 88H Then CMA A 77H
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r and store the result in accumulato
r. 1’s
complement of binary number is
obtained by replacing all 0s by 1s and all 1s by 0s
of the original number
RLC CY
D7
D6
D5
D4
D3
D2
D1
D0
RLC
D7
D6
D5
D4
D3
D2
D1
D0
D7
Rotate the contents of accumulator left by one position. D7 is placed in CY and D0
Let A = 57H and CY = 1
CY
D7
D6
D5
D4
D3
D2
D1
D0
1 0 1 0 1 0 1 1 1
Then RLC
CY
D7
D6
D5
D4
D3
D2
D1
D0
0 1 0 1 0 1 1 1 0
Now A AEH
RAR D7
D6
D5
D4
D3
D2
D1
D0
CY
RAR
CY
D7
D6
D5
D4
D3
D2
D1
D0
Rotate the contents of accumulato
r right by one
position. D0 is placed in CY and CY is
placed in D7.
Let A = A3H and CY=0
D7
D6
D5
D4
D3
D2
D1
D0
CY
1 0 1 0 0 0 1 1 0
Then RAR
CY
D7
D6
D5
D4
D3
D2
D1
D0
0 1 0 1 0 0 0 1 1
Now A 51H
STACK OPERATIONS
PUSH rp SP SP – 1 , (SP) rpH SP SP – 1 , (SP) rpL
Stack pointer
contents decremented by 1 and
in that stack location higher
order byte of register
pair is stored.
Let SP = 2000H , DE = 1050H Then PUSH D
SPSP-1 SP 2000H – 1
SP 1FFFH [1FFFH]10H
SPSP-1 SP 1FFFH – 1
SP1FFEH [1FFEh] 50H
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Again the stack
pointer contents is
decremented by 1 and
in that stack location
lower order byte of
register pair is stored.
POP PSW
Flag Register (SP) , SP + 1 A (SP) , SP + 1
Lower order byte in
given stack location
written into FLAG
register and SP is
incremented by 1. Higher
order byte in
subsequent memory location
written into accumulator and SP is
again incremente
d by 1.
Let SP = 2000H , (2000H) = 30H , (2001H) = 50H
Then POP PSW Flag Register 30H
SPSP + 1 = 2000H + 1 = 2001H Accumulator 50H
SP SP + 1= 2001H + 1 = 2002H
SPHL SPHL Contents of HL register are copied into STACK
pointer
Let HL = 2500H Then SPHL
SP 2500H
BRANCH OPERATIONS
Jcond addr(16
)
If condition true , PC addr(16) Conditions are the individual bits of FLAG register. These instructions take decision based on whether they are set or reset.
If the condition in
the instruction
is true , then branch
to the
Instruction Code
Description Condition for RET
JC Jump on CY CY=1
JNC Jump on No CY
CY = 0
JP Jump on Positive
S = 0
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specified address
JM Jump On Minus
S = 1
JPE Jump on Parity Even
P = 1
JPO Jump on Parity Odd
P = 0
JZ Jump on Zero
Z = 1
JNZ Jump on Not Zero
Z = 0
Let CY = 1 Let PC = 4200H 4200H JC 2000H
[JC instruction is in address 4200H] After execution
PC = 2000H
CALL addr(16
)
(SP-1) PCH (SP-2) PCL
SP SP-2 PC addr(16)
Pushes the current PC contents
onto stack and loads the given address onto PC.
This instruction transfers program
control to subprogram
or subroutine
Let at address 6000H the CALL instruction be present. Therefore PC =
6000H Let SP = 3000H
Then 6000H CALL 2000H (2FFFH) 60H (2FFEH) 00H
SP 2FFEH PC 2000H
R conditio
n
If condition True PCL(SP) PCH (SP+1) SP SP + 2
This instruction pops the
return address
[ADDRESS OF THE
INSTRUCTION NEXT TO
CALL INSTRUCTION IN MAIN PROGRAM] and loads
the
Instruction Code
Description Condition for RET
RC Return on CY
CY=1
RNC Return on No CY
CY = 0
RP Return On Positive
S = 0
RM Return On Minus
S = 1
RPE Return on Parity Even
P = 1
RPO Return on Parity Odd
P = 0
RZ Return on Z = 1
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program with the return
address.
Zero
RNZ Return on Not Zero
Z = 0
Let SP = 27FDH and S = 1 (27FDH) 00H (27FEH) 62H
Then RP PCL 00H PCH 62H SP 27FFH
PCHL PCHL Load the contents of HL register
pair into Program Counter
Let HL = 6000H Then PCHL
PC 6000H
RST n (SP-1) PCH (SP-2) PCL
SP SP-2 PC(n × 8) in hex
This instruction transfers to
vector address.
The vector address is calculated
by multiplying
the RST number by
8.
Instruction Code Vector Address
RST 0 0 × 8 = 0000H
RST 1 1 × 8 = 0008H
RST 2 2 × 8 = 0010H
RST 3 3 × 8 = 0018H
RST 4 4 × 8 = 0020H
RST 5 5 × 8 = 0028H
RST 6 6 × 8 = 0030H
RST 7 7 × 8 = 0038H
Let SP = 3000H Let PC =2000H
2000H RST 6 Then
(2FFFH) 20H (2FFEH) 00H
SP 2FFDH PC 0030H
INPUT/OUTPUT PORT INSTRUCTIONS
IN addr(8)
A [addr(8)] Copies the data from
the specified input port
address into accumulato
r
Let Port address = 80H [80H] = 81H Then IN 80H
A 81H
OUT addr(8)
A [addr(8)] Copies the data from
the accumulato
r into
Let A = 40H Port Address = 50H
Then OUT 50H [50H] 40H
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specified output port
MACHINE CONTROL INSTRUCTIONS
EI IE FF1 INTERRUPT ENABLE
FLIP-FLOP is SET. This
instruction enables the interrupts.
--
NOP No Operation is Performed - --
SIM SOD
SOE
X RST 7.5
MSE
M 7.5
M6.5
M5.5
SOD – Serial Output Data [ 1 or 0] SOE – Serial Output Enable = 0 [Disable] ,
1[Enable] RST 7.5 = 1 , Reset RST 7.5 Flip-Flop
MSE – Mask Set Enable. This bit must be 1 for making D2-D0 active
M7.5 = 1 , Mask RST 7.5 interrupt M6.5 = 1 , Mask RST 6.5 interrupt
M5.5 = 1 , Mask 5.5 interrupt
This instruction
enables and disables the interrupts and also
enable and disable serial
output communica
tion
--
Addressing Modes of 8085 Microprocessor :
Addressing Mode – It is the way of specifying data or a memory address in a instruction. Different types of addressing modes of 8085 microprocessor are as follows :
Immediate addressing mode – 8-bit or 16-bit data directly specified in the instruction Eg. MVI B, 45H [ 8-bit data 45H is moved into B-register] LXI B , 4531H [ 16-bit data 4531H is moved into BC register pair. Higher order byte (i.e. 45H) is moved into B-register and Lower order byte (i.e. 31H) is moved into C-register. Register addressing mode – 8-bit data is specified through a register and 16-bit data is specified through a register pair in the instruction. Eg. MOV A,B [Move the 8-bit data in B-register to A-register] ADD B [Add the 8-bits in B-register and A-register and store the result in A-register] Direct addressing mode – 8-bit port address or 16-bit memory address is directly specified in the instruction. Eg. LDA 2050H – Load (Write) the contents of memory location 2050H into accumulator. IN 35H – Load (Write) the contents of port location 35H into accumulator Register Indirect addressing mode – 16-bit memory address is specified by means of register pair in the instruction. Eg. LDAX B(Move the 8-bit contents of memory location stored in BC register pair to accumulator)
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MOV A,M (Move the 8-bit contents of memory location stored in HL register pair to accumulator) Implicit or Implied addressing mode – Accumulator is the only register and is specified as part of the instruction. Eg. CMA – 1’s complement the contents of accumulator and store the result in the accumulator RRC – Rotate the contents of accumulator in the RIGHT direction.
Time Delay Generation Using Instructions :
Microprocessor takes fixed time for executing instructions , since it is driven by a constant frequency clock. This makes it possible to generate time delay between two events. The TIME DELAYS GENERATED BY REPEATED EXECUTION OF GROUP OF INNSTRUCTION IS CALLED SOFTWARE DELAY. TIME DELAY USING NOP INSTRUCTION : NOP instructions takes 4 T-states to execute. Therefore by executing a NOP instruction between two instructions .
1 T-state = 1
𝑂𝑝𝑒𝑟𝑎𝑡𝑖𝑛𝑔 𝐹𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦 𝑜𝑓 8085 𝑚𝑖𝑐𝑟𝑜𝑝𝑟𝑜𝑐𝑒𝑠𝑠𝑜𝑟
TIME DELAY USING COUNTERS : 8-BIT COUNTERS : [SUITABLE FOR SMALL DELAYS] INSTRUCTION NUMBER OF T-STATES MVI C , COUNT 7 T-STATES BACK : DCR C 4 T-STATES JNZ BACK 10/7 T-STATES Two values are specified for JNZ instruction : 7 T-states when condition is not met and 10 T-states when condition is met. There are (COUNT – 1) passes through the LOOP .The NUMBER OF T-STATES WHILE COUNT ≠ 0 IS (COUNT – 1) × (4 + 10). On the last pass the condition is met and loop is terminated. The NUMBER OF T-STATES NOW ELAPSED IS 4+7= 11 T-STATES. ∴ TOTAL T-STATES TO EXECUTE THE GIVEN PROGRAM = 7 + (COUNT-1)×14 + 11. FOR AN 8-BIT COUNTER MAXIMUM VALUE IS FFH(i.e. 25510 ) = 7 + (255-1)×14 + 11 × 0.5 μs = 1787 μs. 16-BIT COUNTER : [SUITABLE FOR LARGE DELAYS] INSTRUCTION NUMBER OF T-STATES LXI B , COUNT 10 T-STATES BACK : DCX B 6 T-STATES MOV A,C 4 T-STATES ORA B 4 T-STATES JNZ BACK 10/7 T-STATES In this program , the instructions within the LOOP (i.e. from DCR to JNZ) execute to count stored in BC register pair. There are (COUNT – 1) passes through the LOOP. The NUMBER of T-STATES WHILE COUNT ≠ 0 IS (COUNT – 1) × (6+4+4+10). On the last pass the condition is met and loop is terminated. THE NUMBER OF T-STATES NOW ELAPSED IS 6+4+4+7 = 21 T-STATES ∴ TOTAL T-STATES TO EXECUTE THE GIVEN PROGRAM = 10 + (COUNT-1)×24 + 21.
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FOR AN 8-BIT COUNTER MAXIMUM VALUE IS FFFFH(i.e. 6553510 ) = 7 + (65535-1)×24 + 21 × 0.5 μs= 0.7864 sec.
TIME DELAY USING NESTED LOOPS : INSTRUCTION NUMBER OF T-STATES MVI B , MULTIPLIER COUNT 7 T-STATES START: MVI C , DELAY COUNT 7 T-STATES BACK: DCR C 4 T-STATES JNZ BACK 10 / 7 T-STATES DCR B 4 T-STATES JNZ START 10/7 T-STATES
There are (DELAY COUNT – 1) passes through the INNER LOOP. The NUMBER of T-STATES while DELAY COUNT ≠ 0 IS 7+ (DELAY COUNT – 1) × (4+10). On the last pass the condition is met and the loop is terminated. THE NUMBER OF T-STATES NOW ELAPSED IS 4+7 = 11. ∴ TOTAL NUMBER OF T-STATES TO EXECUTE THE INNER LOOP = 7 + (DELAY COUNT – 1) × 14 + 11.
There are (MULTIPLIER COUNT – 1) passes through the OUTER LOOP. THE NUMBER OF T-STATES WHILE MULTIPLIER COUNT≠ 0 IS (MULTIPLIER COUNT – 1) × (TINNER + 4 + 10). On the last pass the condition is met and the loop is terminated . THE NUMBER OF T-STATES NOW ELAPSED IS 4 + 7 = 11.
∴ TOTAL NUMBER OF T-STATES TO EXECUTE THE OUTER LOOP =(MULTIPLIER COUNT – 1)× (TINNER +4 + 10) + 11. For Delay COUNT = 65H (10110) and Multiplier Count = 51H (8110) TINNER = 7 + (101-1) × 14 + 11 = 1418 TOUTER = [(81 – 1)×(1418+14)+11]×0.5μs = 57.29 ms.
Programming Using 8085 ISA : Write a 8085 ALP to divide a 8-bit number by another 8-bit number and store the remainder and quotient in 4252H and 4253H respectively.
LXI H , 4250H MOV A,M Load the Dividend or Numerator in Accumulator INX H MOV B,M Load the Divisor or Denominator in B-register MVI C, 00H Initialize Remainder LOOP2: CMP B JC LOOP 1 When Dividend is less than divisor , SUB B INR C JMP LOOP2 LOOP1: STA 4252H Store the Dividend or Numerator as the remainder MOV A,C STA 4253H The Quotient is 00.(i.e. Quotient does’nt exist when Dividend is less than divisor) HLT
For example when 9 is divided by 4 , the quotient is 2 and the remainder is 1. Whereas when 4 is divided by 9 , the quotient is 0 and the remainder is 4 , as the 4 is < 9
Write a 8085 ALP to solve the following : Z = 2X + Y where X and Y are stored in memory locations 4200H and 4201H . The value of Z should be stored in 4202H(Lower nibble) and 4203H(Higher nibble).
LXI H , 4200H
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MOV A,M Load accumulator with X [X is in memory location 4200H] INX H MOV B,M Load B-register with Y [Y is in memory location 4201H] ADD A Add the contents of accumulator twice [i.e. obtain 2X] ADD B Add 2X with Y and store the sum in accumulator. STA 4202H MOV A,M ANI 0FH Store the lower order nibble of the resultin accumulator (2X + Y) in 4202H MOV M , A MOV A,M ANI 0FH INX H Store the higher order nibble of the result in the accumulator (2X + Y) in 4203H MOV M,A
Write a ALP to sort numbers in the ascending order.
MVI B , 05H Initialize Counter 1 LOOP3: MVI C , 05H Initialize Counter 2 LXI H , 3000H LOOP2: MOV A,M Move the number from memory location 3000H into accumulator INX H CMP M Compare the contents of memory location 3000H and 3001H JC LOOP1 Don’t swap the numbers if number in memory location 3000H is less than number in memory location 3001H JZ LOOP1 Don’t swap the numbers if number in memory location 3000H is equal to the number in memory location 3001H. MOV D,M MOV M,A If number in memory location 3000H is greater than number in memory location 3001H , swap DCX H them. MOV M,D INX H Increment the memory location for subsequent comparisons to take place. LOOP1: DCR C JNZ LOOP2 For each comparison of subsequent memory locations , decrement counter 2 DCR B JNZ LOOP3 After completion of sorting of 5 elements , decrement counter 1 HLT
The 5 elements will be properly sorted in ascending order only after 5 iterations of sorting. This is taken care by the counter B-register
Stack and Subroutine :
A SUBROUTINE is a group of instructions that will be used repeatedly in different locations of a program.
A SUBROUTINE usually exist separately from a MAIN PROGRAM.
Two 8085 instructions for dealing with SUBROUTINE : CALL and RET instructions
CALL instruction transfers the program control from CALLING ROUTINE to CALLED ROUTINE whereas RET instruction transfers the program control from CALLED ROUTINE to CALLING ROUTINE.
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To explain how stack is affected while calling a SUBROUTINE program , we illustrate it using CALL and RET
instructions. In the above diagram , when the instruction “CALL 4000H” is fetched , the microprocessor or microcontroller understands that 4000H is the starting address of SUBROUTINE. It then places higher and lower order bytes of subroutine address onto W and Z registers , pushes the RETURN ADDRESS [Address after the CALL instruction in the main program] onto STACK and loads the SUBROUTINE ADDRESS from WZ register pair into PC.
The RET instruction takes the contents of two memory locations at the TOP of STACK and uses them as the RETURN
ADDRESS.
The number of PUSH and POP instructions used in a SUBROUTINE must be the same , otherwise RET instruction will POP wrong RETURN ADDRESS.
Data is passed to a subroutine through registers. There are two ways of passing DATAs to SUBROUTINE : (i) CALL BY REFERENCE , wherein CALLING PROGRAM stores a VALUE in a register and the SUBROUTINE access it and modifies it and sends it back to the CALLING PROGRAM. (ii) CALL BY VALUE , wherein the SUBROUTINE stores the DATA in the REGISTERS onto a STACK location after entry into it and RESTORES those data before exiting from it.