Input/Output Pins, Ports & Circuits

By

S. Shanthini

III-CSE

• As we know Microprocessor doesn't have inbuilt Input/output ports.

• It must add an additional chip to interface with the external circuitry/devices.

• This disadvantage is overcome by the Microcontroller 8051.

• MC 8051 has inbuilt I/O ports/circuits.

• This helps the MC 8051 to connect with the external devices/memory etc..

SNSCE/ III-CSE/ 8051-I/O Ports and Circuits 2

Pin Description of the 8051

1234567891011121314151617181920

4039383736353433323130292827262524232221

P1.0P1.1P1.2P1.3P1.4P1.5P1.6P1.7RST

(RXD)P3.0(TXD)P3.1

(INT0)P3.2 (INT1)P3.3

(T0)P3.4(T1)P3.5

(WR)P3.6(RD)P3.7

XTAL2XTAL1GND

Vcc P0.0(AD0)P0.1(AD1)P0.2(AD2)P0.3(AD3)P0.4(AD4)P0.5(AD5)P0.6(AD6)P0.7(AD7) EA/VPP ALE/PROG

PSEN P2.7(A15)P2.6(A14)P2.5(A13)P2.4(A12)P2.3(A11)P2.2(A10)P2.1(A9)P2.0(A8)

8051

SNSCE/ III-CSE/ 8051-I/O Ports and Circuits 3

Pin details of MC 8051

The Microcontroller 8051 has 40 Pins.

I/O Port 0I/O Port 1I/O Port 2I/O Port 3

Pins 32-37Pins 1-8Pins 21-28Pins 10-17

Pin 40 - Vcc Pin 20 - GndPin 19 & 18 – XTAL1 & XTAL2Pin 9 – ResetPin 31 – EA (External Access)Pin 29 – PSEN ( Program Store Enable)Pin 30 – ALE (Address Latch Enable)

SNSCE/ III-CSE/ 8051-I/O Ports and Circuits 4

• Vcc（pin 40）：

–Vcc provides supply voltage to the chip.

–The voltage source is +5V.

• GND（pin 20）：ground

• XTAL1 and XTAL2（pins 19,18）

SNSCE/ III-CSE/ 8051-I/O Ports and Circuits 5

• RST（pin 9）：reset

– It is an input pin and is active high（normally low）.

• The high pulse must be high at least 2 machine cycles.

– It is a power-on reset.

• Upon applying a high pulse to RST, the

microcontroller will reset and all values in registers

will be lost.

• Reset values of some 8051 registers

SNSCE/ III-CSE/ 8051-I/O Ports and Circuits 6

RESET Value of Some 8051 Registers:

Register Reset Value

PC 0000

ACC 0000

B 0000

PSW 0000

SP 0007

DPTR 0000

RAM are all zero.SNSCE/ III-CSE/ 8051-I/O Ports and Circuits 7

• /EA（pin 31）：external access

– There is no on-chip ROM in 8031 and 8032 .

– The /EA pin is connected to GND to indicate the code is

stored externally.

– /PSEN ＆ ALE are used for external ROM.

– For 8051, /EA pin is connected to Vcc.

– “/” means active low.

• /PSEN（pin 29）：program store enable

– This is an output pin and is connected to the OE pin of the

ROM.

SNSCE/ III-CSE/ 8051-I/O Ports and Circuits 8

• ALE（pin 30）：address latch enable

– It is an output pin and is active high.

– 8051 port 0 provides both address and data.

– The ALE pin is used for de-multiplexing the addressand data by connecting to the G pin of the 74LS373latch.

• I/O port pins

– The four ports P0, P1, P2, and P3.

– Each port uses 8 pins.

– All I/O pins are bi-directional.SNSCE/ III-CSE/ 8051-I/O Ports and Circuits 9

• The 8051 has four I/O ports

– Port 0 （pins 32-39）：P0（P0.0～P0.7）– Port 1（pins 1-8） ：P1（P1.0～P1.7）– Port 2（pins 21-28）：P2（P2.0～P2.7）– Port 3（pins 10-17）：P3（P3.0～P3.7）– Each port has 8 pins.

• Named P0.X （X=0,1,...,7）, P1.X, P2.X, P3.X

• Ex：P0.0 is the bit 0（LSB）of P0

• Ex：P0.7 is the bit 7（MSB）of P0

• These 8 bits form a byte.

• Each port can be used as input or output (bi-direction).

SNSCE/ III-CSE/ 8051-I/O Ports and Circuits 10

PortPin Circuit

SNSCE/ III-CSE/ 8051-I/O Ports and Circuits 11

Port 0 :-• When used as input,a ‘1’ must be written to

corresponding port latch

• Used as an output,’0’ must be be programmed

• Logic ‘1’ in address bit will turn Upper FET on & lower FET off

• After address has formed & latched into External circuitry by ALE pulse,the External Bus is turned ON

• Port 0 now reads data from External Memory

• Port 0 pins can be accessed by address P0.0,P0.1,….,P0.7

• It can also be addressed as AD0,AD1,…….AD7

SNSCE/ III-CSE/ 8051-I/O Ports and Circuits 12

Port 0 with Pull-Up Resistors

SNSCE/ III-CSE/ 8051-I/O Ports and Circuits 13

Port 1 :-

• Port 1 pins have no Dual functions

• If used as input a ‘1’ is written to latch which turns upper FET on

• Used as output,lower FET is On & the Pullup is Off

• Output latch is directly connected to gate of Lower FET

• Port 1 can be accessed as P1.0,P1.1,. . . . .P1.7

SNSCE/ III-CSE/ 8051-I/O Ports and Circuits 14

Port 2 :-

• It can be used as i/p or o/p which is similar in operation of Port 1

• The alternate use of port 2 is to supply a high-order address byte in conjunction with port 0 low-order byte to address external memory

• Port 2 latches remain stable when External Memory is addressed

• It can be accessed as P2.0,P2.1,. . . . . ,P2.7

SNSCE/ III-CSE/ 8051-I/O Ports and Circuits 15

Port 3 :-

• It is similar to port 1,but has alternate Uses

• Each pin may be individually Programmed as I/O or for alternate Functions as shown

Pin Alternate Use SFR

P3.0-RXD Serial data input SBUF

P3.1-TXD Serial data Output SBUF

P3.2-INT0 External interrupt 0 TCON.1

P3.3-INT1 External interrupt 1 TCON.3

P3.4-T0 External timer 0 input TMOD

P3.5-T1 External timer 1 input TMOD

P3.6-WR External Memory Write Pulse -

P3.7-RD External Memory Read Pulse -

SNSCE/ III-CSE/ 8051-I/O Ports and Circuits 16

Writing “1” to Output Pin P1.XVcc

Load(L1)

Read latch

Read pin

Write to latch

Internal CPU

bus

M1

D Q

P1.X

Clk Q

8051 IC

2. output pin isVcc

P1.X

pin

1. write a 1 to the pin1

0 output 1

TB1

TB2

SNSCE/ III-CSE/ 8051-I/O Ports and Circuits 17

Writing “0” to Output Pin P1.XVcc

Load(L1)

Read latch

Read pin

Write to latch

Internal CPU

bus

M1

D Q

P1.X

Clk Q

8051 IC

2. output pin isground

P1.X

pin

1. write a 0 to the pin0

1 output 0

TB1

TB2

SNSCE/ III-CSE/ 8051-I/O Ports and Circuits 18

Reading “High” at Input Pin

Vcc

Load(L1)

Read latch

Write to latch

Internal CPU bus

M1

P1.X pinD Q

P1.X

Clk Q

8051 IC

2. MOVA,P1

external pin=High1. write a 1 to the pin MOV

P1,#0FFH

1

0

Read pin

3. Read pin=1 Read latch=0

Write to latch=1

1

TB1

TB2

SNSCE/ III-CSE/ 8051-I/O Ports and Circuits 19

Reading “Low” at Input Pin

Vcc

Load(L1)

Read latch

Write to latch

Internal CPU bus

M1

P1.X pinD Q

P1.X

Clk Q

8051 IC

2. MOVA,P1

external pin=Low1. write a 1 to the pin

MOV P1,#0FFH

1

0

Read pin

3. Read pin=1 Read latch=0

Write to latch=1

0

TB1

TB2

SNSCE/ III-CSE/ 8051-I/O Ports and Circuits 20