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IQ switch scheduling

Pag. 1

Input Queued routers/switches

Andrea BiancoTelecommunication Network Group

QoS Issues in Telecommunication Networks - 1Andrea Bianco – TNG group - Politecnico di Torino

Telecommunication Network [email protected]

http://www.telematica.polito.it/

The Internet is a mesh of routers

core router


access router

enterprise router


Pag. 2

The Internet is a mesh of routers• Access router:

– high number of ports at low speed (kbps/Mbps)– several access protocols (modem ADSL cable)several access protocols (modem, ADSL, cable)

• Enterprise router:– medium number of ports at high speed (Mbps)– several services (IP classification, filtering)

C t


• Core router:– moderate number of ports at very high speed

(Mbps/Gbps)– very high throughput

Faster and faster• Need for high performance routers

– to accommodate the bandwidth demands for new users and new services

– to support QoS– to reduce costs

• Moore’s law (electronic packet processing power) is too slow with respect to the increase


power) is too slow with respect to the increase in link speed

• The bottleneck is memory speed


Pag. 3

Single packet processing

• The time to process one packet is becoming shorter and shortershorter and shorter

• Worst case: 40-Byte packets (ACKs)• 3.2 µs at 100 Mbps• 320 ns at 1 Gps• 32 ns at 10 Gps• 3 2 ns at 100 Gbps


• 3.2 ns at 100 Gbps• 320 ps at 1Tbps

CP CP

Hardware architecture

S F

LC

LC

LC

LC

CP

S F

IP

IP

IP

IP

CP

OP

OP

OP

OP


O

physical structure logical structure


Pag. 4

Hardware architecture: main elements

• Line cards– support input/output transmissions– store packets– adapt packets to the internal format of the switching fabric– support data link protocols– classify packets– schedule packets

t it


– support security • Switching fabric

– transfers packets from input ports to output ports

Hardware architecture: main elements

• Control processor/network processor– runs routing protocolsg p– computes routing tables– manages the overall system

• Forwarding engines


– compute the packet destination (lookup)– inspect packet headers– rewrite packet headers


Pag. 5

control forwarding forwarding

Interconnections among main elements - I

switching fabric

processor engine engine


line card line card1 N

Interconnections among main elements - II

control

processor

switching fabric

processor


line card &forwarding engine

1

line card &forwarding engine

N


Pag. 6

Cell switch (fabric) ORM1ISMpackets cells cells packets

Cell-based synchronous routers

ORMN

1

N

ISM


• ISM: Input-Segmentation Module

• ORM: Output-Reassembly Module

• Packet: variable-size data unit

• Cell: fixed-size data unit

Switching fabric• Our assumptions:

– Bufferless• to reduce internal hardware complexity

– Non-blocking• it is always possible to transfer in parallel from input to

output ports any non-conflicting set of cells



Pag. 7

Switching fabric• Examples:

– BusesSh d

123pu

ts

– Shared memory – Crossbar – Multi-stage

• rearrangeable Clos network • Benes network • Batcher-Banyan network (self-routing)

Buffered cross bars (not considered)

34

1 2 3 4outputs

inp


– Buffered cross-bars (not considered)• Switching constraints

– at most one cell for each input and for each output can be transferred

Generic switching architecture

Output 1

switching fabricInput 1

Input N Output N

Sin

Sin

Sout

Sout


input queues output queues


Pag. 8

Speedup• The speedup (increase in speed with respect

to line speed) determines switch performance:p ) p– Sin = reading speed from input queues– Sout = writing speed to output queues

• The speedup is also a technological constraint


• Maximum speedup factor:– S = max(Sin, Sout)

Switches with queues at outputs• OQ (Output Queued)• The switching fabric is able

to transfer to any output all 1 1Nλto transfer to any output all cells received in one time slot

• 100% throughput • Optimal average delay• Speedup N with respect to

line speed is required in NxNN N

λi λo=Nλi

Nλi


p qswitching fabric speed and in output port memory access


Pag. 9

Switches with queues at inputs• IQ (Input Queued) • Advantages: 1 1

– Switching fabrics and memories less costly

• No speedup required in the switching fabric

• Memory access speed equal to line speedS d 1

1 1

N N


• Speedup=1

– Only viable solution for very high speed devices

NxNN

1 1

IQ switches• Two problems:

– Define scheduling algorithms to avoid output 1 1

N N

algorithms to avoid output contention

• Select in each time slot data to be transmitted from inputs to outputs

• Constraint: in each time slot– At most 1 data from each

input (no speeedup in reading)


NxNN Nreading)

– At most 1 data to each output (no speedup in writing because no memory is available)


Pag. 10

IQ switches• Two problems:

– Memory architecture:• If using FIFO queues, HoL

(Head of the Line) blocking• If choosing cyan packet from

queue N, the red packet in queue 1 is blocked by the cyan packet which is at the head of queue 1 even if red

t t t N i f

1 1

N


output port N is free• For uniform unicast traffic

throughput limited to 58.6%NxN

N N

Memory architecture

• To avoid HoL blocking phenomenum, a more complex memory architecture is needed

• Two possible solutions:– p-window queueing

VOQ (Vi t l O t t Q i )


– VOQ (Virtual Output Queueing)


Pag. 11

p=3

Memory architecture• p-window queueing:

– p is the window size1 1

N

– The first p cells of each queue are considered for scheduling

– Higher complexity• Scheduler deals with pN

cells


NxNN N• Non FIFO queues

– HoL blocking reduced, completely eliminated only for P→∞

1

Memory architecture• VOQ (virtual output

queueing)1 1

N

N

1

– At each input data are stored in separate queues according to data destination (N queues for each input)

– N2 queues in total


NxNN N

N

– Eliminates HoL blocking and it permits to achieve 100% throughput with a proper scheduling algorithm


Pag. 12

Scheduling problem modelling• Problem to be solved

by the scheduling can be represented using a

• An edge i→j exist if there is at least a data at input i willing to reach

1

2

1

2

be represented using a bipartite graph

at input i willing to reach output j

• Edges may be weighted• Weight

– Binary– Queue length


3

N

3

N

g– HoL cell age or waiting

time– Other metrics

Scheduling problem modeling• The scheduling algorithm tries to determine, in each

time slot, a matching over the bipartite graphs.

1

2

1

2

1

2

1

2

• Select at most N edges with constraints– At most one edge for each input– At most one edge for each output


3

N

3

N

3

N

3

N

Graph G Matching M


Pag. 13

• Another possible representation is based on a (Request Matrix RM), which stores the information related to data transfer request

Scheduling problem modeling

transfer request

INPU

0: no data from input to output

1: at least one data from inputto output (may be weighted)


• Matching it is a permutation matrix i.e., a matrix such that the row and column sum is at most equal to 1

T

OUTPUT

to output (may be weighted)

Scheduling in IQ switches• Request Matrix • Permutation matrix

3 5 0 02 0 0 44 5 0 00 0 8 2

0 1 0 00 0 0 11 0 0 00 0 1 0



Pag. 14

Traffic description• Aij(n) = 1 if a packet arrives at time n at input i,

with destination reachable through output jg p j• λij = E[Aij(n)]• An arrival process is admissible if:

– ∑i λij < 1– ∑j λij < 1


∑j λij• no input and no output are overloaded on average• OQ switches exhibit finite delays only for admissible traffic

• Traffic matrix: Λ = [λij ]

Traffic scenarios• Uniform traffic

– Bernoulli i.i.d. arrivalsl t tb d i th ⎥

⎥⎤

⎢⎢⎡

11111111

ρ– usual testbed in the literature

• “easy to schedule”

• Diagonal traffic– Bernoulli i.i.d arrivals

⎥⎤

⎢⎡ 0012

⎥⎥⎥

⎦⎢⎢⎢

⎣

=Λ

111111111111

Nρ


– critical to schedule, since only two matchings are good

⎥⎥⎥⎥

⎦⎢⎢⎢⎢

⎣

=Λ

200112000120

3ρ


Pag. 15

Traffic scenarios• LogDiagonal traffic

– Bernoulli i.i.d. arrivals ⎥⎥⎤

⎢⎢⎡

24811248

ρ– more critical than

uniform, less than diagonal traffic

⎥⎥⎥

⎦⎢⎢⎢

⎣

−=Λ

8124481212 N

ρ


Scheduling policies: objective• Let us consider a NxN IQ• Denote by i the input port index and by j the output port

index• Goal: assuming infinite buffer size, transfer any admissible

traffic pattern with no losses• Solutions are known

– If traffic pattern is known in advance• TDM of Birkhoff von Neumann algorithm

– For admissible unknown traffic patterMaximum Weight Matching


• Maximum Weight Matching• Maximum Size Matching

• Several heuristics are proposed for unknown traffic pattern– iSLIP, iLQF, iOCF, 2DRR (WFA), MUCS, RPA, and many others


Pag. 16

Scheduling uniform known traffic

• A number of algorithms give 100% throughput when traffic is uniform – For example:

• TDM and a few variants• iSLIP (see later)

Example of a TDM schedule for a 4x4 switch


Example of a TDM schedule for a 4x4 switch

Birkhoff - von Neumann theorem• Any doubly stochastic matrix Λ can be

expressed as convex combination of t ti t ipermutation matrices πn:

Λ = ∑n an πn

with


• with– an≥0– ∑n an =1


Pag. 17

Scheduling non-uniform known traffic

• Thanks to the Birkhoff - von Neumann theorem

• If the traffic is known and admissible, 100% throughput can be achieved by a TDM scheme using:– for a fraction of time a1 matching M1 (π1)


for a fraction of time a1 matching M1 (π1)– for a fraction of time a2 matching M2 (π2)– for a fraction of time ak matching Mk (π3)

MSM: Maximum Size Matching• MSM maximizes the number of data

transferred in a single time slot, i.e. select the i b f dmaximum number of edges

– Instantaneous throughput maximization.• Asymptotic computational complexity is

O(N2.5)• Non optimal algorithm


Non optimal algorithm– Some admissible traffic pattern cannot be

scheduled, i.e. it does not always achieve 100% throughput.


Pag. 18

MSM: exampleO1 O2 O3

I1 λ 0 0I 0 λ 0

I1

I2

O1

O2I2 0 λ 0

I3 λ λ 0 λ=0.5

I2

I3

O2

O3

I1 O1 I1 O1 I1 O1

Three MSM are possible in overload, i.e. when all queues are full


I2

I3

O2

O3

I2

I3

O2

O3

I2

I3

O2

O3

When the first matching is chosen, the maximum throughput cannot be achieved

MWM: Maximum Weight Matching• A weight is associated with each edge• The MWM, among all possible N! matchings,

selects the one with the highest weight (sum of edge metrics)

I1 O1 I1 O1 I1 O11

20

MWMMSM


I2

I3

O2

O3

I2

I3

O2

O3

I2

I3

O2

O3

1

1


Pag. 19

MWM: Maximum Weight Matching• MWM does not maximize instantaneous throughput (worse

than MSM)It was demonstrated that a MWM algorithm• It was demonstrated that a MWM algorithm– in IQ switches with VOQ architecture– under admissible traffic– with infinite queue size– when using as weight either the queue length or the age of the HoL

data

achieves100% throughput


achieves100% throughput • Asymptotic computational complexity O(N3)• With finite queue size, it behaves similarly to MSM• Problems with delays and possible starvation

MSM algorithm• Start from the bipartite graph• Add a source and a sink node, respectivelyAdd a source and a sink node, respectively

connected to all inputs and all outputs• Execute a flow maximization algorithm

– Flow augmentation path

I1 O1


I1

I2

I3

O1

O2

O3

source sink


Pag. 20

MSM algorithm• Operates on the residual capacity graph• Select at random a path connecting source

to sink

source sink Flow 1


• Residue graph:

source sink

MSM algorithm

• Residue graph:

source sink Flow 2


source sink


Pag. 21

MSM algorithm

so rce sink Flow 3

• Residue graph:

source sink Flow 3


• Algorithm terminates when there are no more admissible paths among source and sink

source sink

MSM algorithm• Final solution obtained by summing the flows

obtained ineach step

• Algorithms never backtracks to modify a choice

source sink


choice• Problems:

– Successive iterations cannot be made parallell– Not suitable to hardware implementation


Pag. 22

Uniform traffic• MWM and MSM behave almost identically

100Uniform Traffic

MWM

10

Mea

n de

lay

MWM MSM


10.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

M

Normalized Load

Diagonal traffic• MSM yields much longer delays than MWM at medium/high loads

1000Diagonal Traffic

MWM

100

Mea

n de

lay

MWM MSM


1

10

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

M

Normalized Load


Pag. 23

Practical solutions• Need to define heuristics

– with reasonable complexity– that can be implemented in hardware

• Any scheduling algorithm defines three aspects:– A method to compute the weights to be associated with

each edge (metric):• Approximate MSM

– Binary (queue occupancy)


Binary (queue occupancy)• Approximate MWM

– Queue length (it is an indication of the fact that the queue, which is associated with an input/output pair, is suffering)

– Age of HoL data– Interface load– Ad hoc metrics to select critical edges/nodes

Practical solutions– ...– A heuristic algorithm to determine a matching– A contention resolution algorithm among edges

with the same metric:• round-robin (initial choice state dependent)• sequential search (initial choice non state dependent)• random



Pag. 24

i-SLIP• Iterative algorithm• It defines a heuristic algorithm which g

determines, with a proper number of iterations, a maximal size matching (i.e., a matching that cannot be further extended with other edges selection)Metric is the queue occupancy


• Metric is the queue occupancy• To solve contentions, it exploits an arbiter for

each input and for each output

i-SLIP• In each iteration, three phases can be

identified:– Request: each unmatched input sends a request– Request: each unmatched input sends a request

to every output for which it has a cell– Grant: each unmatched output that has received

requests, sends a grant to one of the requesting inputs.

• Contentions solved by a round robin mechanism


Contentions solved by a round robin mechanism.– Accept: if an unmatched input receives grants, it

selects an output and becomes matched to it • Contentions solved by a round robin mechanism


Pag. 25

i-SLIP: counters• Each input (output) has a pointer associated with

to solve contentions• The output pointer is incremented, modulo N, by

one unit beyond the index of the input to which the grant was issued

• The input pointer is incremented, modulo N, by one unit beyond the index of the output from


one unit beyond the index of the output from which an accept was received

i-SLIP: properties• For uniform overload the bipartite graph is

a full mesh the higher the number of alternatives the easier is to determine aalternatives, the easier is to determine a good matching. iSLlP degenerates to a TDM scheme ES:

I

I1

O

O11,2,3,4 1,2,3,4

• All outputs grant


I2

I3

I4

O2

O3

O4

1,2,3,4

1,2,3,4

1,2,3,4

1,2,3,4

1,2,3,4

1,2,3,4

p ginput 1

• Input 1 accepts output 1


Pag. 26

i-SLIP: properties

I

I1

O

O1• IT 1

For one iteration unsatisfactoryI2

I3

I4

O2

O3

O4

y

I1 O1

• IT 2I1 O11,2,3,4 1,2,3,4


I4 O4

I2I3

O2

O3

1,2,3,4

1,2,3,4

1,2,3,4

1,2,3,4

1,2,3,4

1,2,3,4

I2

I3

I4

O2

O3

O4

i-SLIP: properties• At the end:

• IT N

I O4

I2

I1

I3

O2

O1

O3

1,2,3,4

1,2,3,4

1 2 3 4

1,2,3,4

1,2,3,4

1 2 3 4

• IT N

I2

I1

I3

I

O2

O1

O3

O

1,2,3,41,2,3,4


• A maximum (implies maximal) matching is obtained after N iterations

I4 O41,2,3,4 1,2,3,4 I4 O4


Pag. 27

i-SLIP: propertiesIn the following steps, pointers are staggered one iteration is enough to obtain a maximum matching

I O1 2 3 4• Step 2

I O

I2

I1

I3I4

O2

O1

O3

O4

1,2,3,4

1,2,3,4

1,2,3,4

1,2,3,4

1,2,3,4

1,2,3,4

1,2,3,4

1,2,3,4

I2

I1

I3I4

O2

O1

O3

O4• Step 3


I2

I1

I3I4

O2

O1

O3

O4

1,2,3,4

1,2,3,4

1,2,3,4

1,2,3,4

I2

I1

I3I4

O2

O1

O3

O4

1,2,3,4

1,2,3,4

1,2,3,4

1,2,3,4

i-SLIP: properties• Each iteration has a computational complexity of O(N2),

but it can be easily made parallel• Worst case in one iteration: 1 edge is selected• Worst case in one iteration: 1 edge is selected• When executing N iterations, the matching is maximal

(depends on the choice made but cannot be extended) however, the computational complexity is O(N3)

• Experimental results show that log2N iterations are in general enough to obtain good performance


g g g p• Performance drops if pointers are badly synchronized• iSLIP was implemented on a single chip in the Cisco

12000 router


Pag. 28

iSLIP: extensions• Use the same heuristic algorithm (3-phase) but with

different metrics– Queue length iLQFQueue length iLQF– HoL cell age iOCF

• Input send requests containing the weight • Contentions are solved using the weight first, only

for equal weights the choice is random• Does not exploit pointer synchronization to obtain

good performance rather the edge weight


good performance, rather the edge weight • OCF has better delay properties (never starves

data), but the increase in complexity is significant and makes the algorithm practically unfeasible

2DRR: Two Dimensional Round Robin

• Operates on the request matrix• Extension of the WFA (Wave Front Arbiter), very

easily implementable in hardwareeasily implementable in hardware• Definitions

– Generalized diagonal is a set of N elements of a matrix NxN such that two elements do not belong to the same row or column

• A set of N diagonal is said to be covering if each element of the matrix belongs to one and only one


g ydiagonal

• In each time slot, the algorithm goes through N iterations


Pag. 29


• At the beginning, all links (input-output connections) are enabledAt h it ti i li d di l i• At each iteration, a given generalized diagonal is chosen– Only enabled links may be selected if the are covered by

the elements belonging to the chosen diagonal • If a link from input i to output j is selected, all

requests issued by i or sent to j are disabled for the


current time slot (cannot be chosen in the matching)• In N iterations, all N generalized diagonal are

considered and the request matrix is fully covered

2DRR: example

1 0 1 10 1 0 1 1010

1101IT 1

10101101

IT 2

0 1 0 11 1 0 10 0 1 0

0001

010010111010

1101IT 3

010010111010

IT 41101

RM=


010010000010

010010111010

010010111010


Pag. 30


• At each time slot, a different covering set of generalized diagonal is chosen, to improve fairness– Indeed, edges covered to the first diagonal chosen are

more likely selected– Round robin over different sets of covering diagonal and

round robin on each element in the set• Emulates a MSM

Not easy to extend to other metrics


• Not easy to extend to other metrics• Asymptotic computational complexity O(N2)

MUCS: Matrics Unit Cell Scheduler• Information on queue status are concentrated

on a request matrix A (NxN)q ( )• Starting from A, the weight matrix W is

computed• The matching is computed on the basis of W• Elements aij of A are non-negative integers


jthat indicate the priority to be assigned to the edge connecting input i to output j


Pag. 31

MUCS: Matrics Unit Cell Scheduler

• 3 possible values can be associated with each aij:ij– QoS priority: aij is inversely proportional to the

minimum Maximum Cell Transfer Delay in queue storing packets from i to j

– Binary priority: aij=1 if there is at least a packet in the queue storing packets from i to jQ l th i it i th f th


– Queue length priority: aij is the occupancy of the queueu storing packets from i to j

• Weights wij are computed starting from aij

MUCS: Matrics Unit Cell Scheduler• At step n, the reduced request matrix An is defined,

whose size Mn is decreasing (Mn+1< Mn)At each iteration the follo ing steps are e ec ted• At each iteration, the following steps are executed:– Compute the weight matrix from matrix An:

⎪

⎪⎨

⎧ ≠+ aifwca

wra

w ijij

ij

ij

ij

ij

0


⎪⎩ otherwisej

0

∑=

=nM

jijij awr

1∑=

=nM

iijij awc

1


Pag. 32

MUCS: Matrics Unit Cell Scheduler– Select the edge i→j associated with the largest value of wij

Once edges are selected, the reduced matrix An+1 is computed taking into account all elements in A belongingcomputed, taking into account all elements in A belonging to rows and columns not selected in previous iterations

– the algorithm ends when all elements in A were considered

• It is a greedy algorithm• Asymptotic computational complexity is O(N3)


• Asymptotic computational complexity is O(N3)• Good performance, but implemented using analog

components

RPA: Reservation with Preemption and Acknowledgment

• It is a heuristic algorithm based on two phases:– Reservation (possibly preemptive) – Acknowledgment

• Inputs keep an urgency metric Xij associated with each queue

• Inputs operate on a reservation vector RES which stores reservations made by inputs in each time slot

• Reservation vector RES has N elements; each element refers to a different output port and contains– Urgency


g y– Input port index

• Initially, at each round: Urgj = 0, ∀ j

Urg1,In1 Urg2,In2 Urg3,In3 UrgN,InN

Out 1 Out 2 Out 3 Out N

RES


Pag. 33

RPA: reservation phase• Input ports access vector RES sequentially, according to a

pre-defined order• The first input makes a greedy selection, choosing the output g y g

corresponding to the maximum urgency • The input following in the pre-defined order chooses the

output that maximizes the difference among queue urgency and RES vector urgencies– Input i computes Wj = Xij – Urgj for all j– finds j* such that Wj* = max{ Wj }– if Wj* > 0,

⇒ reserve output j* and set Urg =X possibly overwriting the previous


⇒ reserve output j and set Urgj*=Xij*, possibly overwriting the previous reservation

– It may pre-empt an already existing request if this choice maximizes the global urgency (may not select its maximum urgency)

• The reservation phase ends when all ports made their reservation

RPA: acknowledgment phase• Reservation vector RES is again processed by all

inputs, in the same order followed during the reservation phase

• Each input checks if its reservation was cancelled :– If NOT: input gets access to the reserved output– If YES: the input cannot gain access to the previously

reserved output; however, it may select another output among available (not reserved) outputs Note that since


among available (not reserved) outputs. Note that, since the number of inputs is normally equal to the number of outputs, if some reservations were cancelled, some outputs are surely available


Pag. 34

RPA features• Good performance

– Sum of the weights selected is at least half of the weights transferred by MWMtransferred by MWM

• Different urgency metrics may be chosen, making the algorithm very flexible– Strict priority among multiple classes may be enforced– Standard urgency is queue length

• No iterations are required


q• Asymptotic computational complexity O(N2)• Cannot be made parallel, since a sequential access

is fundamental

Uniform traffic• Comparison between MWM, iSLIP, iLQF, RPA

1000Uniform Traffic

100

1000

ean

dela

y

MWMiSLIP iLQF RPA


1

10

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

M

Normalized Load


Pag. 35

LogDiagonal traffic• iSLIP saturates close to 84% throughput

100000LogDiagonal Traffic

1000

10000

100000

ean

dela

y

MWMiSLIP iLQFRPA


1

10

100

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Me

Normalized Load

Diagonal traffic• RPA achieves 98% throughput, iLQF 87%, iSLIP 83%

100000Diagonal Traffic

100

1000

10000

100000

ean

dela

y

MWMiSLIP iLQF RPA


1

10

100

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Me

Normalized Load


Pag. 36

Issues in IQ switches• Signalling:

– Signalling bandwidth required to transfer weights from i h ll b i ifi i hinputs to the controller may be significant with respect to the available bandwidth in the switching fabric

– The more complex the adopted metric, the larger the signalling bandwidth required

– Differential signalling may be adopted• Multiple classes:


Multiple classes:– Given K classes, first the VOQ architecture must be

extended, by using KN queues at each input– Scheduling algorithms must be extended to support

priorities

Issues in IQ switches• QoS (fair queueing):

– Scheduling for QoS (need to serve the most urgent k ) h diffi l i i i h h h d lipacket) has a difficult interaction with the scheduling to

transfer data from inputs to outputs– Need to balance performance and fairness– No ideal optimal solution known

• Frame scheduling:Operate on a frame of length F slot and compute a


– Operate on a frame of length F slot, and compute a schedule on the frame and not on a slot by slot basis

– Scheduling algorithm executes only at frame boundaries– Relatively easy to provide QoS guarantees for each input-

output pair– Delay increases at low loads


Pag. 37

Issues in IQ switches• Variable packet length support

– May introduce packet scheduling instead of cell y p gscheduling

• Packets transferred as trains of cells– An edge is selected when the first cell of a packet arrives

and is kept in all the following matchings until the last cell of the packet is transferred

– It avoids reassembly machines at outputs


It avoids reassembly machines at outputs– Same throughput guarantees– Packet delay may be larger or shorter

• Depends on packet length distribution

Issues in IQ switches• Multicast:

– 2N possible different multicast flows– May be treated as unicast through input port replicationMay be treated as unicast through input port replication

(often named multicopy) • At each input a number of copies equal to the packet fanout are

created, for the proper outputs, and inserted in the proper VOQ– Speedup required– Increases the instantaneous input load– May lead to low throuhgput (unable to sustain a single broadcast

flow)– Scheduling for multicast must be defined to exploit


Scheduling for multicast must be defined to exploit switching fabric multicast capabilities

• Balance fanout splitting and no-fanout splitting• Often a single FIFO for multicast is proposed (HoL blocking, less

critical with respect to unicast)• Critical traffic patterns when few inputs are active


Pag. 38

Example of a critical traffic pattern


Issues in IQ switches– MC-VOQ architecture

• 2N separate queues at each input• Best possible solution (no HoL blocking)• Best possible solution (no HoL blocking)

– An optimal scheduling was defined (only theoretically)– Implies re-enqueueing and out-of-sequence

• However, admissible traffic pattern exist that cannot be scheduled in an IQ switch regardless of the queue architecture and of the scheduling algorithm

• Scalability problemN b f


– Number of queues– Scheduling algorithm

– Manage a finite number of queues• CIOQ switches (a moderate speedup helps a lot)


Pag. 39

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