Initial Performance Results of the APS P0 (Transverse Bunch-to-Bunch) Feedback System N. DiMonte#,...
1
Initial Performance Results of the APS P0 (Transverse Bunch-to-Bunch) Feedback System N. DiMonte#, C.-Y. Yao, Argonne National Laboratory, Argonne, IL 60439, U.S.A. Functional block of the FPGA 1.Storage Ring @ 352MHz, (2.84ns) 2.Bunches/buckets = 1296 3.ADC sampling rate 88MHz (11.36ns) a.Samples a ¼ of the buckets. b.324 buckets can be enabled. 4.Storage Ring turn rate = 271.6kHz (3.68s) 5.X & Y inputs use 14-bit A/D 6.Sum & Aux use 12-bit A/D Average FPGA readings of the monopulse receiver output. The FPGA is set to sample at a fixed time relative to the revolution clock to sample for 4096 samples. Standard deviation of the readings of the monopulse receiver output. Same condition. Low value of standard deviation indicates a real beam bunch. Abstract The Advanced Photon Source electron beam exhibits transverse instability when a large amount of charge is present in a single bunch. The P0 feedback system stabilizes the transverse motion of the beam under these circumstances. The initial requirement was to stabilize a single bunch of electrons in the horizontal plane. By implementing the stabilizer in an FPGA and using the parallel processing capabilities provided by this hardware, it is possible to stabilize 324 bunches per turn in both the horizontal and vertical planes. The stabilizer consists of 648 32-tap finite impulse response filters. This paper discusses the challenges in achieving this performance and some issues in interfacing to a Coldfire IOC running RTEMS. Initial test results of the system response are presented. 32-tap Finite Infinite Response Filter for one channel. ADC DAC Programmable 32tap FIR Bucket Control Programmable Delay #0, 4, 8, …1296 Total = 324 X plane To Amp ADC DAC Programmable 32tap FIR Bucket Control Programmable Delay Y plane To Amp Scope PLL x 2 = 88 MHz P0 Sync & Control 44 MHz Clk P0 Clk Clk Sum APS Event Receiver Inhibit Ctl Event Signal Coldfire CPU Network Serial FPGA Code (Flash) Flash Port Bucket Select 855 Hz to 109 kHz Aux FIR Memory block (1 of 4) The memory block in conjunction with the 32-tap FIR filter is used for 324 buckets per channel, a total of 648 filters. Each element is 18-bits wide. The computation speed for all 648 filters is approximately 6109 multiply-accumulate operations per second. *Work supported by U.S. Department of Energy, Office of Science, Office of Basic Energy Sciences, under Contract No. DE- AC02-06CH11357. #[email protected] Data & coefficien t inputs. Scope waveform of the Input stripline sum signal to the monopulse receiver. Beam bunches are at the high amplitude locations. The monopulse receiver takes a 1ns pulse and expands it to 100ns, hence the 24 bucket limit. 24 bucket mode. a) 153.4ns between bunches b) 100ns output pulse from monopulse receiver. 153ns 100ns FPGA scope data for 24 bucket mode. Six of the 24 buckets are visible to the left, upper peaks of the waveform indicates a valid bucket. Each data point is an average of 4096 samples for a selected bucket. This test is verifying that the FPGA can distinguish selected buckets, which is about 13.5 samples apart. [(1296/24)/4=13.5] 320 bucket out of 1296 are shown. Every other 4 th bucket can be scanned (4x80=320). A diagram of the FPGA-based transverse bunch-to-bunch feedback system. Since the DAC is transformer-coupled, a test was performed to characterize the output. The FPGA was programmed with 162 buckets at positive full- scale and 162 buckets at negative full-scale. This produced a 271.6 kHz square wave signal using all 324 buckets. The figure to the right shows this pattern and the effects of the transformer-coupled output. Results: The monopulse receiver was the last component installed for this system at the end of August ’07. Test are just now being conducted with limited beam time. Some of the tests for the input section have been shown in this poster, with the monopulse receiver being a critical part of the system. The output circuit, including the amplifiers are currently being tested with the step-function being discussed here. The FPGA is proving that it can sample the buckets correctly with the monopulse receiver. However, more tests are needed before the output of the FIR filters are connected to the output circuit. This system is now integrated into the storage ring, so caution is being exercised. Response of FPGA output with a step-function drive.
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Transcript of Initial Performance Results of the APS P0 (Transverse Bunch-to-Bunch) Feedback System N. DiMonte#,...
Initial Performance Results of the APS P0 (Transverse Bunch-to-Bunch) Feedback SystemN. DiMonte#, C.-Y. Yao, Argonne National Laboratory, Argonne, IL 60439, U.S.A.
Functional block of the FPGA
1. Storage Ring @ 352MHz, (2.84ns)2. Bunches/buckets = 12963. ADC sampling rate 88MHz (11.36ns)
a. Samples a ¼ of the buckets.b. 324 buckets can be enabled.
4. Storage Ring turn rate = 271.6kHz (3.68s)5. X & Y inputs use 14-bit A/D6. Sum & Aux use 12-bit A/D
Average FPGA readings of the monopulse receiver output. The FPGA is set to sample at a fixed time relative to the revolution clock to sample for 4096 samples.
Standard deviation of the readings of the monopulse receiver output. Same condition. Low value of standard deviation indicates a real beam bunch.
Abstract The Advanced Photon Source electron beam exhibits transverse instability when a large amount of charge is present in a single bunch. The P0 feedback system stabilizes the transverse motion of the beam under these circumstances. The initial requirement was to stabilize a single bunch of electrons in the horizontal plane. By implementing the stabilizer in an FPGA and using the parallel processing capabilities provided by this hardware, it is possible to stabilize 324 bunches per turn in both the horizontal and vertical planes. The stabilizer consists of 648 32-tap finite impulse response filters. This paper discusses the challenges in achieving this performance and some issues in interfacing to a Coldfire IOC running RTEMS. Initial test results of the system response are presented.
32-tap Finite Infinite Response Filterfor one channel.
ADC DACProgrammable
32tap FIRBucketControl
ProgrammableDelay
#0, 4, 8, …1296Total = 324
X plane To Amp
ADC DACProgrammable
32tap FIRBucketControl
ProgrammableDelay
Y plane To Amp
Scope
PLLx 2 =
88 MHz
P0 Sync&
Control
44 MHz Clk
P0
Clk
Clk
Sum
APSEvent
Receiver
Inhibit Ctl
Event Signal
Coldfire CPU
Network
Serial
FPGA Code(Flash)
FlashPort
Bucket Select
855 Hz to109 kHz
AuxFIR Memory block (1 of 4)
The memory block in conjunction withthe 32-tap FIR filter is used for 324buckets per channel, a total of 648 filters. Each element is 18-bits wide. The computation speed for all 648 filters is approximately 6109 multiply-accumulate operations per second.
*Work supported by U.S. Department of Energy, Office of Science, Office of Basic Energy Sciences, under Contract No. DE-AC02-06CH11357.#[email protected]
Data &
coefficient
inputs.
Scope waveform of the Input stripline sum signal to the monopulse receiver. Beam bunches are at the high amplitude locations. The monopulse receiver takes a 1ns pulse and expands it to 100ns, hence the 24 bucket limit.
24 bucket mode.a) 153.4ns between bunchesb) 100ns output pulse frommonopulse receiver.
153ns
100ns
FPGA scope data for 24 bucket mode. Six of the 24 buckets are visible to the left, upper peaks of the waveform indicates a valid bucket. Each data point is an average of 4096 samples for a selected bucket. This test is verifying that the FPGA can distinguish selected buckets, which is about 13.5 samples apart. [(1296/24)/4=13.5]
320 bucket out of 1296 are shown. Every other 4th bucket can be scanned (4x80=320).
A diagram of the FPGA-based transverse bunch-to-bunchfeedback system.
Since the DAC is transformer-coupled, a test was performed to characterize the output. The FPGA was programmed with 162 buckets at positive full-scale and 162 buckets at negative full-scale. This produced a 271.6 kHz square wave signal using all 324 buckets. The figure to the right shows this pattern and the effects of the transformer-coupled output.
Results:
The monopulse receiver was the last component installed for this system at the end of August ’07. Test are just now being conducted with limited beam time. Some of the tests for the input section have been shown in this poster, with the monopulse receiver being a critical part of the system. The output circuit, including the amplifiers are currently being tested with the step-function being discussed here. The FPGA is proving that it can sample the buckets correctly with the monopulse receiver.
However, more tests are needed before the output of the FIR filters are connected to the output circuit. This system is now integrated into the storage ring, so caution is being exercised.
Response of FPGA output with a step-function drive.
