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Current, Delay, and Power Analysis of Subrnicron CMOS Circuits

Anas Hamoui

(B-Eng., 1996)

Department of Electncal and Computer Engineering

McGill University, Montréal

July 1998

A thesis submitted to the Faculty of Graduate Studies and Research

in partial fulfillment of the requiremenü for the degree of

Master of Engineering

O Anas A. Hamoui, 1998

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Abstract

An analytical model for computing the supply current, delay, and power of a submicron

CMOS inverter is presented. The effect of the Miller capacitance is also modeled.

A modified version of the n-th power Iaw MOSFET model [25] is proposed and used to

relate the terminal voltages to the drain current in submicron transistors.

By first computing definable reference points on the output voltage waveforrn and

then using linear approximations through these points to find the actual points of interest,

the desired speed and accuracy of the inverter model is achieved. The most important part

of the analysis is a three-step process for computing the time and output voltage when the

short-circuit transistor changes its mode of operation. The time and output voltage when

the charging/discharging current reaches its maximum are also calculated and then used to

evaluate the propagation delay and characterize the output voltage waveforrn.

The model, implemented in MATLAB, has been validated with a wide range of

inverters under various conditions of input transition time and capacitive load: it can predict

the delay, peak supply current, and power dissipation to within a few percent of ELDO

simulation results, while offering about two orders of magnitude gains in CPU time over

ELDO sirnulator. Hence, its use in CAD tools supporting low power design is justified.

Résumé

Un modèle analytique pour calculer le courant d'alimentation, le retard, et la dissipation de

puissance dans un inverseur submicronique de CMOS est présenté. L'effet de la capacité

de Miller est également modelé. Une version modifiée du modèle de transistor MOSFET

basé sur la loi d'ordre n ('n-th Power Law MOSFET Model') [25] est proposée et utilisée

pour associer les tensions terminales au courant de drain dans les transistors

su bmicroniques.

En calculant des points de référence définis sur la forme de la tension de sortie et

puis utilisant des approximations linéaires par ces points pour trouver les exacts points

d'intérêt, la rapidité et la précision désirées pour le modèle d'inverseur ont pu être réalisées.

La partie la plus importante de l'analyse est un procédé en trois étapes pour calculer le

temps et la tension de sortie quand le transistor de court-circuit change son mode de

fonctionnement. Le temps et la tension de sortie quand le courant de charge/décharge

atteint son maximum sont également calculés et puis utilisés pour évaluer le retard et pour

caractériser la forme de la tension de sortie.

Le modèle, mis en application dans MATLAB, a été validé avec un éventail

d'inverseurs dans de diverses conditions de temps de transition du signal d'entrée et de

capacité de chargement: i! peut prévoir le retard, le courant d'alimentation maximal, et la

dissipation de puissance à quelques pour cent près des résultats de simulation dTELDO, tout

en offrant un gain en temps de calcul informatisé d'environ deux ordres de grandeur par

rapport au simulateur ELDO. Par conséquent, son utilisation dans des outils de DAO

supportant la conception à faibIe puissance est justifiée.

Acknowledgment

For the past two years, 1 was lucky to be working under the supervision of a great

person: Prof. Nicholas Rumin. 1 would like to deeply thank him for his constant

encouragement and help, his knowledge and vision. his enthusiasm and pragmatism, .... his

exceptional character. 1 will remain grateful to him for having offered me the opportunity

to join the Microelectronics and Computer Systems (MACS) Lab. at McGill University.

1 would Iike to acknowledge the Natural Sciences and Engineering Research Council

of Canada (NSERC) for providing the financial support which allowed me to pursue my

graduate studies. 1 would like to also acknowledge the Canadian Microelectronics

Corporation (CMC) for providing the equipments, tools, and technical support, and

thank its staff for being so helpful.

1 would like to thank Northern Telecom (NORTEL) for giving us access to their

technology files and to the MISNAN MOSFET model. 1 am particularly grateful to

Mr. Farag Fattouh (NORTEL) for his constant help and encouragement, and his kindness.

1 would like to also thank Dr. Stan Tarasewicz (NORTEL) and Dr. Kenneth Wagner

(S3 Inc.) for the interesting and useful discussions 1 had with them.

1 would like to thank Prof. Gordon Roberts for his advice and recornmendation, and

for the many fruitful talks 1 had with him. 1 am also thankful to a dedicated system

adrninistrator, Mr. Jacek Slaboszewicz, for working hard to maintain an efficient

computing environment. Furthemore, 1 greatly appreciate al1 the help 1 received from

the supporting staff at the Department of Electrical and Computer Engineering,

McGill University.

iii

1 am grateful to my MACS Lab. mates for making our lab. an enjoyable and

simulating place to work, and for always k i n g willing to help. In particular, 1 would like

to thank: John Abcarius, Benoit Dufort, Mourad El-Garnal, Adel Fakhry, Choon-Haw

Leong, Vincent Leung, Loai Louis, Victor Tyan, and Victor Zia for their friendship.

Many of them taught me lots of small things that it would have taken me ages to find out

by myself, and for that 1 am grateful. Our soccer games and jogs will always remain in my

During the ups and downs of the last months of writing, the encouragements of

Anas Zahabi, Dima & Raghid Berchaili, and Amer Omar were of great help. 1 would like

to deeply thank them for that and for their friendship. 1 also greatly appreciated the cheerful

words from Mrs. Lydia Rumin.

My special thanks go to my teacher, Prof. Moustafa Ghannarn (IMEC, Belgium and

Kuwait University), who introduced me to the world of microelectronics and taught me al1

its basics. 1 will remain grateful to him for al1 his help and advice.

1 am indebted to my relatives and friends in Syna for their love and support.

1 am particularly obligated to my grandmother, Wasfieh, to my aunts, Hiyam and Nijah,

and to my late uncle, Zouheir Al-Tinawi, for their profound kindness and unrelenting

support. AI1 1 can Say is Sh~ikran.

To my mother, Samiha. To my father, Adnan. To my sister, Rima. To them, 1 owe all.

No words can really describe my appreciation and gratitude to them for k i n g there for me,

afways and unconditionally. Their love and understanding can never be repaid.

To my parents, Samiha and Adnan,

To my sister, Rima,

with love and admiration.

Table of Contents

Abstract .............................................................................................................................. i

. . Résumé .................... ... ............ ... .............................................................................. i i

... Acknowledgment ............................................................................................................. i i i

............................................................................................................. Table of Contents .-v

*..

List of Figures ................................................................................................................. viii

List of Tables ..................................................................................................................... xi

............................................................................................... Chapter 1 Introduction 1

1 . 1 Motivation ........................................................................................................ I

1.2 Thesis Overview ............................................................................................... 3

.................................................................. Chapter 2 Submicron MOSFET Mode1 .S

........................................................................... 2.1 Square-Law MOSFET Model 6

2.2 Short-Channel Effects ....................................................................................... 8

2.2.1 Hot-Carrier Effects ............................................................................. 8

2.2.2 Threshold-Voltage Variations ............................................................... 13

.................................................. 2.3 Modified n-th Power Law MOSFET Mode1 17

................................................... 2.4 Effective Threshold Voltage .. ...................... 21

2.5 MOSFET Mode1 Parameters ......................................................................... 25

2.5.1 Parameter Extraction ............................................................................ 26

....................................................................... 2 S.2 Parameter Optimization 28

.................................................................................................. 2.5.3 Results 33

Chapter 3 Inverter Delay and Power Models ......................................................... 36

3.1 The CMOS Inverter ........................................................................................ 36

........................................................................................... 3.2 Literature Review 41

3.2.1 a-power Law MOSFET Mode1 ........................................................... 41

3.2.2 Review of Inverter Delay Models ...................................................... 42

3.2.3 Review of Inverter Power Models ....................................................... 44

3.3 Nomenclature .................................................................. ... ...................... 46

3.4 Inverter DeIay Mode1 ...................................................................................... 47

3.5 Inverter Power Model ..................................................................................... 48

3.6 MOSFET Capacitance Modeling .................................................................... 54

Chapter 4 Inverter Current Model ........................................

4.1 Nomenclature ........ ... ................................................................................... 61

4.2 Discharging Inverter (Rising Input) .......................................................... 62

.......................................................... 4.2.1 Minimum Short-Circuit Current 63

4.2.2 Maximum Short-Circuit Current ........................................................ 64

........................................................... 4.2.3 Maximum Discharging Current 70

................................................................... 4.3 Charging Inverter (Falling Input) 72

4.3.1 Peak Power-Supply Current ................................................................ 72

........................................................................... Chapter 5 Results and Conclusion 74

5.1 Resuits .................................................................................................--.......... 74

5.1.1 Delay .................................................................................................... 74

5 - 1 2 Peak Power-Supply Current ................................................................ 78

................................................................................ 5.1 -3 Power Dissipation 81

............................................................................................ 5.1.4 CPU Time 82

........................................................................................... 5.2 Mode1 Limitations 83

...................................................................................................... 5.3 Conclusion 84

.................................................................................................................... Bibliography 85

vii

List of Figures

2.1 Effect of the longitudinal electric field on the average driR velocity of the carriers in the

MOSFET surface channel 1161 [18]. ....................................................................................... 8

2.2 Effect of the effective transverse electric field on the inversion layer mobility of carriers

....................................................................................... in the MOSFET channel [14] [23]. 11

2.3 Sketch of the dependence of the MOSFET threshold voltage, Vt, on (a) the effective

channel length, Le, (b) the drain-source voltage, VDs, in short-channel devices, and

................................................ (c) the effective channe1 width, W, [161[17]. (Not to scale) 14

2.4 (a) Cross section of an NMOSFET. The shaded areas near the source and the drain

indicate the regions of charge sharing where the gate-controlled depletion region overlaps

with the depletion regions of the source and drain p-n junctions. .................................... 15

2.4 (b) NMOSFET cross-section perpendicular to the source-drain direction. The portions of

the gate-controlled depletion region that are neglected in the one-dimensional theory for

V, (graduai charnel approximation) are indicated by the shaded areas. ......................... 15

2.5 Extraction of the MOSFET effective threshold voltage Vt, from the ID versus 1 VGSI characteristic a t ] VDS 1 = 1% VDD. AMOS transistor with L = Lmi, and W = 4W,, is used.

[The characteristics shown correspond to the SV 0 . 8 p BiCMOS technology of NORTEL's

................................................................................................................ BATMOS process] 24

viii

Selection of fitting points on the measured ID-VDs characteristics of the MOSFET

(with VGS as a parameter and Vss = 0 ) for the extraction of the MOSFET mode1

.......................................................................................................................... parameters. 26

MOSFET ID-VDs characteristics: (-) measured, (-) modified n-th power law MOSFET

model. To demonstrate the validity of the optimized set of model parameters over the full

range of transistor widths used in circuit design, the characteristics of an MOS device

with L = Lmi, and (a) W = Wb, (b) W = 20W- are plotted. [The characteristics shown

correspond to the 5V 0 . 8 ~ BiCMOS technology of NORTE& BATMOS process where

Lm, = 0 . 8 ~ and W,, = 1.4pm] ........................................................................................ 35

CMOS inverter circuit with the parasitic capacitances of the MOS transistors rnodeied

explicitly. in circuit diagram (a), COp and Co, include the input capacitances of the fanout

gates while the load capacitance, CLoad, accounts for the interconnect capacitances.

In the equivalent circuit model (b), the effective inverter load, CL, groups the NMOS and

PMOS drain-bulk junction capacitances, the input capacitances of the driven gates, and

the intercomect capacitances. ............................................................................................ 37

CMOS inverter circuit: (a) discharging inverter (rising input), (b) charging inverter

...................................................................................................................... (falling input). 39

Linear approximation of the output voltage wavefonn for a discharging inverter

(rising input). The output voltage transition can be fully characterized by the tangent line

to the output voltage waveform a t time hm, when the discharging current, in, reaches its

...................................................... ..........*.....**....*................................ maximum.. ....... 47

Piecewise linear approximation of the short-circuit current, ip, used to compute the

short-circuit energy dissipation for the case of a discharging inverter (rising input) ...... 52

Lumped model for the parasitic capacitances of an MOS transistor (the source and bulk

terminals are at the same potential: Vsb = 0 ) ..................................................................... 54

Piecewise linear approximations of the discharging current in (-) and the short-circuit

current ip (-1, used in step 2 of the derivation of the maximum short-circuit current for

a discharging inverter (rising input) ................................................................................... 67

Delay plot versus loading capacitance with input transition time, Ti, as a parameter.

A minimum size CMOS inverter (W, = Wp = 1.4p.m) is used. ........................... ... ......... 75

5.2 Delay plot versus loading capacitance with input transition time, Ti, as a parameter.

A very large CMOS inverter (W, = Wp = 2Opm) is used .................................................... 76

5.3 Delay plot versus input transition time for several ratios of transistor sues, Wfi.

A CMOS inverter (W, = 4 p ) driving a loading capacitance of (a) Cload = 0.2pF and

(b) Cload = 1pF is used .......................................................................................................... 77

5.4 Plot of the peak power-supply current versus: (a) input transition time Ti (for

Cload = 0.44pF) and (b) loading capacitance Cload (at Ti = 0.5nsec) for several ratios of

transistor sizes, W f l o A CMOS inverter with W, = 1 0 p is used. ............................... 79

List of Tables

Effective threshold voltages of the NMOS and PMOS transistors in the 5V 0 . 8 ~

BiCMOS technology of NORTEL's BATMOS process ........................................................ 23

Optimized parameters for the modified n-th power law model of the MOS transistors in

the 5V 0 . 8 ~ BiCMOS technology of NORTEL's BATMOS process. ............................... 34

Approximation of the MOSFET gate intrinsic capacitances [12]. .................................... 55

Definition of the model parameters for the MOSFET gate extrinsic (overlap)

........................................................................................................................ capacitances. 57

Definition of the model parameters for the MOSFET drain-bulk junction capacitance. 59

Peak power-supply current, its time of occurrence, and the corresponding output voltage.

The results computed using the proposed anaiytical model are compared with ELDO

simulation results for different CMOS inverters (with transistor widths W, and Wp),

under various conditions of input transition time, Ti, and loading capacitance, Cload. ..-80

Short-circuit energy dissipation and total dynamic energy dissipation per switching

event. The results cornputed using the proposed anaiytical model are compared with

ELDO simulation results for different CMOS inverters (with transistor widths

W, and Wp), under various conditions of input transition time, Ti, and loading

capacitance, Cload. ................................................................................................................ 81

Introduction

To set the scene for this thesis, it is appropriate to begin by briefly outlining the importance

of the topic addressed in this work and the need for a CMOS inverter model. A description

of the thesis structure then follows.

1.1 MOTIVATION

The growth of portable information technologies is resulting in a pressing demand for

reduced power dissipation in VLSI circuits. With today's deep su6micron technologies, the

weight and size of portable devices are directly determined by the batteries used to power

the electronic circuits. Even when power is available for nonportable applications, the

design for low power remains a critical issue [1][2]: the continuing increase in the clock

frequency, switching activity, density, and size of VLSI chips has been accompanied by a

considerable increase in power consumption and heat dissipation, thereby making it

difficult to provide adequate cooling and toughening the packaging constraints. The

packaging cost is actually becoming a key price factor for an integrated circuit (IC), to the

extent of precluding some products from the market cornpetition [3]. Thus, there is a

growing need for providing IC designers with accurate power estimation tools.

Another major issue for digital design verification is the estimation of critical path delays

in large VLSI systems. Furthemore, for reiiability design, the peak supply current values

are needed to properly size the power and signal lines in order to avoid electromigration

failures and IR-drop problems [4].

Chapter 1 Introduction 1.1 Motivation

Existing circuit sirnulators, such as SPICE, consume too much CPU time to be

practical other than for small circuits with a few hundred transistors. Therefore, computer-

aided design (CAD) tools must include efficient techniques for the rapid, yet accurate

enough, estimation of delay, power, and maximum currents in digital ICs, thereby

minimizing the logic design time while allowing designers to efficiently explore a wide

variety of circuit and logic architectures and better utilize the design space.

Full CMOS remains the most widely used VLSI circuit design technoiogy because it

altows a simple implementation of reliable digital circuits with good noise margins and

ideally no static (dc) power consumption. A number of methods for computing the delay

and/or power dissipation in ClMOS digital circuits has been recently presented.

These techniques, reviewed in detail in Chapter 3, apply to the CMOS inverter in particular.

The focus on developing an analytical mode1 specifically for the inverter stems from the

following:

Any complex CMOS gate can be simp1y replaced by its worst-case equivalent

inverter. Using these inverters to sirnulate a given signal path yieIds its worst-case

delay, which is required to determine the critical paths in a VLSI systern.

The design of dock buffers, bus network (data, control, and address buses) and

U 0 drivers in a digital VLSI chip relies on inverters. Ensuring well-defined and

well-behaved clocks and minimizing clock skews remain critical factors in

determining system performance, hence the persisting need for precisely estimating

the delays over the clock distribution network. In addition, the power consumption

of the clock generation and distribution network constitutes the dominant part of the

total chip power because clocks typically switch at the highest frequency and must

be distributed across the entire chip: clock power in a CMOS VLSI chip can be as

high as twice the logic power when using static logic and about three times for

dynamic Iogic [5]. For example, in the DEC Alpha microprocessor [6] , the clocking

system together with the control network and the WO drivers consume 4095, 15%

and 10% of the chip power, respectively, while the execution units and the memory

caches only contribute the remaining 35%.

Chapter 1 Introduction 1.2 Thesis Ovewbw

A number of efficient transistor-level techniques for reducing CMOS logic gates to

equivalent inverters are available [7]. Thus, by deveioping a delay/power model for

the CMOS inverter, any CMOS logic circuit can be analyzed.

1.2 THESIS OVERVIEW

In this thesis, an analytical model for computing the supply current, deiay, and power of a

su bmicron CMOS inverter is presented. The effect of the input-to-output coupling

capacitance (Miller capacitance) is also modeled. A rnodified version of the n-th power law

MOSFET mode1 [25] is proposed and used to relate the terminal voltages to the drain

current in submicron transistors.

By first computing definable reference points on the output voltage waveform and

then using linear approximations through these points to find the actual points of interest,

the desired speed and accuracy of the inverter model is achieved. Furthemore, the model

is comprehensive: it cornputes the maximum currents in addition to both the delay and

power, and the same model is used regardless of whether the input-voltage switching

transe

wide

tion is fast or slow.

Chapter 2 begins by describing the short-channel effects which are neglected in the

y-used square-iaw MOSFET model but must be accounted for when analyzing

submicron transistors. A modified version of the n-th power law MOSFET model [25],

suitable for fast analysis of submicron MOSFET circuits, is then proposed. The algorithm

developed to optimize the model parameters, so that the MOSFET model can describe most

accurately the transistor electrical characteristics over the full range of device dimensions

used in circuit design, is presented in Section 2.5.

Chapter 1 Introduction 1.2 7'hesis Owrview

To facilitate the presentation, the inverter model proposed in this thesis is divided into

3 sub-modeis: - Delay model: computes the propagation delay and characterize the output voltage

waveform. - Power model: computes the power dissipation.

Current model: computes the peak short-circuit and chargingdischarging current

values, their time of occurrence, and the corresponding output voltages.

In Chapter 3, the CMOS inverter circuit and the associated parasitic capacitances,

which must be accounted for in the delay and power calculations, are introduced. A detailed

literature review of techniques for computing the delay and/or power in CMOS inverters

fol lows. The delay and power models are then presented. These models are based on values

computed using the current model, hence the sirnplicity of the delay and power analysis.

The current model is derived in Chapter 4. The most important part of the analysis is

a three-step process for computing the time and output voltage when the short-circuit

transistor changes its mode of operation. These values are used to calculate the peak

short-circuit current and the corresponding short-circuit energy dissipation (in the power

model). The time and output voltage when the chargingldischarging current reaches its

maximum are also calculated. These values are needed to compute the peak power-supply

current and are also used to evaluate the propagation deIay and characterize the output

voltage waveform (in the delay model).

The proposed model, implemented in MATLAB, has been tested with a wide range

of inverters designed in the 5V 0.8pm BiCMOS technology of NORTEL'S BATMOS

process. Various switching conditions of input transition time and capacitive load were

considered. To validate the model, the delay, peak supply current, and power dissipation

computed using the model are compared with the 'exact' values obtained by simulating the

analyzed circuits in ELDO simulator [40] using NORTEL'S MISNAN MOSFET model

[20]. The results are presented in Chapter 5. Before concluding this thesis, the possible

limitations of the proposed inverter model are discussed.

Subrnicron MOSFET Mode1

Using the simple square-law MOSFET mdel to relate the terminal voltagcs to the drain

current in submicron devices is no longer valid because it neglects the short-channel

effects. At the same time, accurate models for short-channel MOSFETs involve a large

number of parameters and are therefore not suitable for quick analysis. Hence, for fast

analysis of submicron MOSFET circuits, a simple, yet reasonably accurate, MOSFET

engineering rnodel must be derived. To achieve this goal, a modified version of the n-th

power law MOSFET model suggested by Sakurai [25] is proposed.

This chapter begins by surnmarizing the basic assumptions in the derivation of the

square-law MOSFET model followed by a detailed description of the short-channel effects

which must be accounted for when analyzing submicron devices. The modified n-th power

law MOSFET mode1 is then presented. Section 2.4 discusses how an effective threshold

voltage, corresponding to the gate voltage below which the MOSFET can be considered

off, is selected. To characterize a given MOS process technology, the model parameters in

the modified n-th power law MOSFET equations must first be extracted, then optimized for

the MOSFET equations to most accurately describe the transistor electrical characteristics

over the full range of device dimensions used in circuit design. An optimization atgorithm

was developed for this purpose and implemented in MATLAB [39]. The extraction and

optimization procedures for the MOSFET model parameters are presented in Section 2.5.

Finally, the limitations of the modified n-th power law MOSFET model, which must be

carefully taken into account when optimizing the model parameters, are discussed.

Chapter 2 Submicron MOSFET M o d c l 2.1 Square-Law MOSFET M a k l

In this chapter, al1 MOSFET drain current equations correspond to an enhancement-

mode NMOS device with its drain current defined as flowing from drain to source. For an

enhancement-mode PMOS device where the positive current flow is assumed to be in the

source to drain direction, the same equations are used but with the polarity of al! terminal

voltages reversed and the threshold voltage V I exchanged with IV,I .

In the square-law MOSFET model, the transistor drain current is expressed as [ 1 1 ] [ 13][19]

where

(Linear Region) (2- 1 )

(Saruration Region) (2.2)

and VDs, VGS, and V,, are the drain-source, gate-source, and source-bulk voltages,

respectively. L, and W, are the effective channel length and width, respective

V, denotes the threshold voltage while )i models the channel-length modulation effect.

is the effective mobility of the carriers in the channel, and

is the gate-oxide capacitance per unit area, with E,, and t,, being the permittivity and

thickness of the gate oxide, respectively.

Chapter 2 Submicmn MOSFET Mode1 2.1 Squamiaw MOSFET M e 1

The effective channel length and width are defined as

where L and W are the drawn channel length and width, respectively. XL and XW are,

respectively, the gate length and width correction to account for masking and etching

effects. LD is the laterat diffusion into the channel from the source/drain diffusion region

while WD is the sideways diffusion into the channel from the bulk along the width,

The square-law model equations were derived for a long-channel MOSFET where

the following two approximations are valid:

Gradual-channel approximation: The charge density under the gate is assumed

to be completely controlled by the electric field perpendicular to the channel,

thereby permitting a one-dimensional analysis dong the channel. Hence, the

current flow within the conducting channel is taken to be almost exclusively in

the source-drain direction [ 171 [ 161.

Constant mobility of carriers in the channel: The channel current is assumed to

be carried entirely by a charge drift with constant mobility.

As the device dimensions shrink into the submicron range, the channel length

becomes comparable to other device geornetries (such as the depth of the source/drain

islands and the width of the source/drain p-n junctions). This results in a breakdown of

assumptions used in the long-channel analysis, in an enhancement of certain effects

neglected in long-channel devices, and in the occurrence of totally new phenornena [19].

Consequently, the operation of the actual MOSFET is seen to deviate substantially from the

derived square-law equations. The effects resulting in departures from long-channel

behavior are referred to as short-channel effects (or small-geometry effects).

Ch8ptef 2 Submicron MOSFET Mode1

2.2 Short-Channel Effects

2.2.1 Hot-Carrier Effects

In the analysis of the long-channel MOSFET, the average carrier drift velocity was

assumed to be directly proportional to the electric field along the channel. independent of

the magnitude of that field:

where the effective carrier mobility p. in the channel is taken to be constant. However,

when the electric field along the channel reaches a critical value Es,, . the velocity that the

carriers can attain in the MOSFET surface channel tends to saturate as iltustrated in

Figure 2.1. This limit occurs near the mean thermal velocity (-10'' pdsec in Si) and

represents the point at which added energy imparted by the field is transferred to the iattice

rather than increasing the carrier velocity 1181.

<- v =

l / M E

(dope = p = constant)

Es,, = 1.5

Longitudinal Electric Field W l ~ m )

Figure 2.1 Effect of the longitudinal electric field on the average drift veiocity of the carriers

in the MOSFET surface channei [16] [18].

Chapler 2 Submicnrn MOSCET Mo&/ 2.2 Short-Chan~I E-s

At 300K. the average carrier drift velocity attains its maximum value of v, (- 10' ' pm/sec) when the accelerating electric field reaches -1 -5 Vlpm for electrons in a p-type

silicon and -10 V/pm for holes in an n-type silicon. Thus, for exampie, in an NMOS device

with a channel length L = lpm, a 2V drop between drain and source is enough for the

velocity of the camers in the NMOSFET surface channel to reach the saturation point.

Therefore, the velocity saturation effect can no longer be neglected in the analysis of

submicron devices.

To see the impact of velocity saturation on the MOSFET 1-V characteristics, assume

that the carrier drift velocity v dong the channel is related to the longitudinal electric field

E through the piecewise-linear model

Then, a simple expression for the MOSFET current which takes into account the velocity

saturation effect can be obtained:

(2. IO)

V,,,, is the drain-source voltage at which the average carrier drift velocity saturates. In

this model, current saturation in the MOSFET is assumed to occur when the electric field

at the drain reaclies the saturation field Es,, [17].

Chapter 2 Submicron MOSCET Mode! 2.2 Short-Channe! E î k t s

An expression for the factor K, which models the velocity saturation effect. can be obtained

by equating the relations for b in equations (2.10) and (2.1 1) at Vos = Vossor. The value

of K depends on the MOS technology and increases with ( V G s V , ) , though it may be

regarded as constant under certain conditions [23]. For devices with finite channel Iength

and operating under practicd bias conditions, it is found that O < K < 1 .

By comparing equations (2.10) to (2.13) with equations (2.1) to (2.4) in which

velocity saturation effect is neglected, it can be observed that velocity saturation has three

main effects on the MOSFEIT characteristics:

ID,,, is significantly reduced.

ID,,, exhibits an almost linear dependence on (VcsVr) in contrast with the

square-law dependence in long-channel devices. Therefore, the current drive

capability of short-channel devices is less sensitive to changes in the operating

voltage.

VDSsRl is reduced. thereby extending the saturation region of a short-channel

device as compared to a long-channel transistor.

Mobility Degradation

The velocity of carriers dong the MOSFET channel is also a function of the transverse

electric field, the field component normal to the channel. As the transverse electric field

increases with increasing applied gate voltage, the amount of scattering at the Si-SiO2

interface is enhanced, thereby reducing the ease of carrier motion dong the channel. Le. the

carrier mobility. Figure 2.2 shows how the electron mobility decreases as the transverse

electric filed in the inversion layer of an NMOS transistor increases [23].

Chapter 2 Submicron MOSFfT Model

1

O 100 Effective Transverse Electric Field

(V/prn)

Figure 2.2 Effect of the effective transverse electric field on the inversion layer mobility of

carriers in the MOSFET channel [141[231.

A first-order empirical mode1 for the carrier mobility in the channel is given by [15]

car 1 + @ - ( V , - V , ) Es

where po is the low-field mobility, Es is the surface electric field in the channel at the Si-

SiO, interface, &, is the permittivity of silicon, and VG and Vc are the gate and channel

voltages, respectively. The coefficient 0. typically between IO-^ and IO-' pmN, is an

empirical parameter that depends weakly on the MOS technology. Note that as device

dimensions are scaled down, the oxide thickness is reduced and the dependence of the

carrier mobility on the transverse electric fietd becomes increasingly significant.

Furtherrnore, in long-channel devices, it was reasonable to assume the channel depth

and the carrier charge density in the channel to be uniform from source to drain.

Accordingly, using an effective carrier mobitity dong the channel did not introduce a

significant error. However, for submicron devices, the variation in carrier mobility (the

change in V, in equation (2.14)) in going down the channel from source to drain can no

longer be negiected.

Chapter 2 Submicron MOSFET Mo&/ 22 Short-Channel EIlbcts

Ballistic Transport

The carrier drift velocity between source and drain is the net result of the numerous

scattering events that the carriers in the MOSFET surface channel experience when an

electnc field is applied. provided the channel length L is much larger than the average

distance between scattering events A. However, if a submicron MOSFET is built with

L < A, then a large percentage of the carriers would then travel between source and drain

without experiencing a single scattering event. This is referred to as ballistic transport.

Thus. in deep subrnicron devices. ballistic effects make the carrier velocity a non-local

function of the electric field, rendering the description of the carrier velocity in the channel

an even harder task.

It is interesting to note that ballistic transport is of practical importance because it

could lead to superfast devices: Not limited by scattering, the effective average velocity of

carriers traversing the channel would exceed the mean thermal velocity. This is referred to

as velocity overshoot [19].

Oxide Charging ('Hot Etechon' Effect)

Under normal bias conditions, the electric field strength near the drain region can become

high enough for the channel electrons and the electrons entering the drain-substrate

depletion region to gain sufficient energy to surmount the Si-SiO2 surface barrier and enter

the gate oxide. Neutra1 centers in the oxide trap some of the injected electrons, thereby

causing a charge build up within the oxide and, therefore, a change in the threshold voltage

[19]. Typically, the V , of NMOS transistors will increase while the V , of PMOS devices

will decrease. Furthemore, 'hot' electrons entering the oxide Iayer may induce a leakage

gate current and an excessive substrate current [15]. Because oxide charging is cumulative

over time, the hot-electron effect can lead to a long-term reliability problem: after a circuit

is used for a certain time, its performance will start degrading.

Chapter 2 Submicmn MOSFET Modcl 2.2 Short-Chanm! Eilbcts

For an electron to become hot, an electric field of at least 1V/pm is necessary.

Although, oxide charging does occur in long-channei transistors, its effect in short-channel

MOSFETs is much more pronounced as a result of

the electric field strengths k ing much larger in submicron devices as

compared to long-channel transistors. This is because, while the device

dimensions are being continually scaled down, the supply and operating

voltages are kept constant or reduced by much smaller factors.

a larger percentage of the gate oxide region k ing affected by the hot electron

phenornenon in submicron devices. This is because the electnc field levels are

high over a larger portion of the channel, and, in addition, the ratio of channel

length to drain-junciion depletion width is smaller.

2.2.2 Threshold-Voltage Variations

In a long-channel MOSFET, the threshold voltage V , is assumed to be a function of only

the MOS technology and the applied body bias (source-bulk voltage) V S B :

where V l o is the threshold voltage at VsB = O , y is the body-effect coefficient, and OF is

the potential difference between the electrostatic potential and the Fermi potential inside

the substrate under thermal equilibriumt [11][19].

1 t In an NMOS transistor: y = -A-; and O F - VTln - c,, , G: 1

wherc q is the electronic charge. is the perrnittivity of Si, VT is the thermal voltage. ni is the

intrinsic crirrier concentration, and NA is the substnte doping.

Chapter 2 Submicron MOSFET Mdel 22 Short-ChanneI E f f e t s

(a) Short-Length

Effect

(b) Drain-Induced (c ) Narrow- Width

Barrier Lowering Effoct

Figure 2.3 Sketch of the dependence of the MOSFET threshold voltage, V,, on

(a) the effective channel length, Le, (b) the drain-source voltage, VDS, in short-channel

devices, and (cl the effective channel width, We [161[171. mot to scale)

As the device dimensions shrink into the pm-range, the variations of V, as a function

of L , W , and V,, can no longer be neglected. Hence, besides varying over time (as a result

of oxide charginp). Vlo is no longer constant over a11 NMOS/PMOS transistors in a given

integrated circuit implemented in a submicron MOS technology.

Short-Length Effect

In enhancement-mode short-channel devices. 1 V,I is found to monotonically decrease with

decreasing channel length L, as illustrated in Figure 2.3 (a) [16][17].

Before an inversion layer or channel forms in a MOSFET, the substrate region under

the gate must be first depleted from majority carriers [19]. For long-channel transistors, the

value of IV,I is predicted using the gradual-channel approximation (based on a one-

dimensional theory) which assumes that al1 the depletion-region charge beneath the gate

originates from the electric field lines normal to the gate. This ignores the depletion regions

of the source and drain p-n junctions, as illustrated in Figure 2.4 (a).

Chapter 2 Submicron MOSFEf M d 1 22 Short-Channd Eflbcts

As the device dimensions are scaled down into the pm-range, the channel length

becomes comparable to the depletion-region width at the sourceldrain p-n junctions,

rendering the contribution of these junctions in depleting the region beneath the gate no

longer negligible. Consequently, as L decreases, less gate charge is required to invert the

channel because a larger percentage of the depletion-region charge under the gate is

balanced by the sourceldrain p-n junctions and, therefore. 1 V,I decreases.

Figure 2.4 (a) Cross section of an NMOSFET. The shaded areas near the source and the

drain indicate the regions of charge sharing where the gate-controlled depletion region

overlaps with the depletion regions of the source and drain p-n junctions.

depletion-rc&n boundary

p-substnte 1

Figure 2.4 (b) NMOSFET cross-section perpendicdar to the source-drain direction. The

portions of the gate-controlled depletion region that are neglected in the one-dimensional

theory for Vt (gradua1 channel approximation) are indicated by the shaded areas.

Chepter 2 Submicmn MOSFET Modsl

As the drain-source (drain-bulk) voltage increases, the width of the drain-junction

depletion region increases. Therefore, a phenornenon similar to the short-length effect on

IV,I occiirs in submicron MOSFETs where IV,I decreases with increasing IVDd, as

illustrated in Figure 2.3 (b). This effect is referred to as drain-induced barrier lowering

(DIBL) [ I 71. DIBL renders the threshold voltage a function of the transistor operating

voltage.

Narrow- Wüith Effect

In enhancement-mode narrow-channel devices, IV,I is found to monotonically increase

with decreasing channel width W, as illustrated in Figure 2.3 (c) [16][17].

Referring to the cross-section view of the MOSFET in Figure 2.4 (b), the gate-

controlled depletion region extends beyond either side of the gate width W. The assumption

of a one-dimensional theory (graduai-channel approximation) for V , in the analysis of

wide-width transistors ignores the gate-induced space charge in these lateral regions.

In submicron MOS technologies, narrow-width transistors can be built with channel

width W comparable to the depletion layer width xd at the silicon surface beneath the gate.

In these narrow-channel devices, the gate-controlled charge on either side of the gate width

is no Ionger negligible as compared to the charge directly beneath the W-width of the gate.

Consequently, as W decreases, more gate charge is required to invert the channel because

a larger percentage of the gate-induced space charge is Iost in fringing fields, and, therefore,

1 V,I increases [ l5][19].

Chapter 2 Submicmn MOSFET M d 1 23 Modifksd *th Povrnsr Law MOSFm Modd

2.3 Modified n-th Power Law MOSFET Model

Several deep subrnicron MOSFET models, such as NORTEL's MISNAN [20] and the

Berkeiey S hort-channel IGFET Model (BSIM3v3) [22], have been reported in the literature

and implemented in circuit simulators such as ELDO [40] and HSPICE [42]. These models

are accurate, continuousi, scalable, and physically-based, but involve a large number of

parameters (67 parameters in the BSIMl [21]) and are therefore not suitable for fast

analytical treatment of MOSFET circuits. Furtherrnore, it is difficult to develop an intuitive

understanding of the device elecuical behavior from such a list of model parameters- On

the other hand, the simple long-channel square-law model is not valid for submicron

devices mainly because it neglects the velocity saturation and mobility degradation effects.

A desirable model for the fast analysis of integrated circuits based on submicron

MOSFETs has the fol lowing properties:

- simple (involves a small nrimber of parameters)

@ reasonably accurate (approxitnates the velocity saturation and tnobility

degradation effects)

does not require computationaly expensive procedures to extract the model

parameters

Several such 'engineering' models for short-channel MOSFETs have been suggested

[23] [X] [25]. In particular, the n-th power law modei, proposed by Sakurai and Newton in

[25] and [26]. offers a simple, yet accurate enough, empiricai model for the MOSFET drain

current.

+ i.e. the same defining relationships are used over the full range of openting modes and conditions.

Chapter 2 Submicron MOSFET Mode1 2.3 Moâiîïuâ n-th Powr Law MOSFET Mo&/

The corresponding equations are Iisted below for easier reference:

VDs 5 V,,,, (Linear Region):

V,, 2 VDss,, (Satrtration Region):

where

L, and W , are, respectively, the effective channel length and width, as defined in

equations (2.6) and (2.7). V, denotes a threshold voltage while k = ho + k, V,, models

the channel-iength modulation effect. The technology-dependent constants n, ml K, and B

describe the short-channel effects in an empirical manner. The MOSFET region of

operation is determined by the drain-source saturation voltage V,,,, . Note that with 1

j z = 2 , m = 1 , K = 1 . and B = ?uCo,, and assuming kVDS = O in the linear region,

the model equations reduce to the square-law 1-V relations in equations (2.1) to (2.4).

The n-th power law MOSFET model assumes that the threshold voltage V , is a

function of only the MOS technology and the applied body bias Vs, as given in equation

(2.15) and rewritten below for easier reference:

Thus, it neglects the V, dependence on L , W, and VDs, illustrated in Figure 2.3. However,

for a given MOS process technology, the mode1 should be capable of accurately

Chapter 2 Submicron MOSET Mode1 2.3 Modifisd n-th Pomr iaw MOSFET Mo&/

representing the MOSFET electrical characteristics over the full range of device

dimensions used in circuit design with a single set of model parameters

{ V,,, A,, 12, B, rn, K) . Therefore, Vto in equation (2.15) must be expressed as a function

of L , W. and V,,.

To model the threshold-voItage variations due to short-length and narrow-width

effects. we propose the following expression for V t o :

where V,,,, denotes a zero body-bias threshold voltage for wide-channel transistors and the

empirical factor f describes the dependence of Vto on L and W. Note that, since alrnost

al1 the MOSFETs in a digital circuit are designed at the minimum channel length, the

dependence of the threshold voltage on L is of minor significance compared to its variation

with W, especially for transistor widths close to the minimum channel width available in

the MOS technology used.

In characterizing a given MOS process technology, the 1-V characteristics of a

nuinber of transistors with different channel dimensions wiil be used to optimize V,,, over

al1 V, , between O and VDD for various Vcs values (as discussed in section 2.5).

Therefore, although V,,, is assumed to be independent of VDs, the DIBL effect is still

irnplicitly accounted for to some extent by extracting a threshold voltage value optimized

over the full range of operating VD,-voltages.

The n-th power law MOSFET mode1 does not give a good approximation for the

drain current in the near- and sub-threshold regions 1251. However, the errors that this

introduces in the calculation of the delay and power using the inverter model proposed in

this thesis turn out to be acceptable.

Chapter 2 Submicron MOSFET Mode1 2.3 Moüifieû n-th Power Law MOSFET Modbl

In summary, the modified n-th power law MOSFET model used to calculate the drain

current is:

* VDs < VDSs,, (Linear Region):

- I rD, 2 V,,,, (Saturation Region):

ID = iDsat ( + vDs)

w here

and V,,, V,,, and VsB are the drain-source, gate-source, and source-bulk voltages,

respectively. L, and W , are, respectively, the effective channel length and width, as

defined in equations (2.6) and (2.7).

The above model equations correspond to an enhancement-mode NMOS device with its

drain current defined as flowing from drain to source. For an enhancement-mode PMOS

Chapter 2 Submicmn MOSFET Modcl 2.4 EIIective fhreshold Y o m

device, where the positive current flow is assumed to be in the source to drain direction, the

same equations are used but with the polarity of al1 terminai voltages reversed, and the

threshold voltage V , replaced with 1 V,I . In the following chapters, the subscripts n and p

will be used in conjunction with the above currents, voltages, and model parameters to

associate these quantities to the NMOS or PMOS device in the CMOS inverter circuit,

respectively.

Consequently, a given MOS process technology can be fully characterized by

extracting the set of seven empirical parameten { V,, f , ho, n, B. rn, K} , for Vs, = 0.

The mode1 parameter extraction and optimization procedure (a one-time process) is

described in Section 2.5.

The circuits analyzed in this thesis are designed in the SV 0.8pm BiCMOS

technology of NORTEL's BATMOS process and simulated in ELDO using NORTEL's

MISNAN -MOSET model. The modified n-th power law MOSFET model parameters

{ VI,$., f . A,, n, B. m, K} are extracted and optimized to fit the measured 1-V characteristics

of the NMOS and PMOS transistors. VaIidation of the inverter model proposed in this

thesis is achieved by comparing the delay and power computed using the model with the

'exact' values obtained by simulating the analyzed circuit.

2.4 Effective Threshold Voltage

The threshold voltage, V, , is defined as the gate-source voltage, V,, . needed to induce a

strongly inverted channel under the gate, thus providing ample carriers for conduction

between the source and drain of the MOS transistor. It is based on a desire to model the

MOSFET as an ideal switch with an on-state (1 VGs1 > 1 Vrl ) where a significant drain

current I D is allowed to pas , and an off-state ( 1 VGSI < 1 V,I ) where I D = O . However, for

1 VGsl c 1 VrI , the MOS transistor is still conducting, though at small drain current levels.

This is referred to as subthreshold conduction. In fact, the transition from the on- to off-

state is not abrupt, but rather gradual.

Chapter 2 Submicron MOSFET Model 2.4 Effective Threshold Voltage

In the presence of a weakly inverted channel (Le. for 1 VGsl < V , ), the MOSFET?

drain and source terminals together with the oppositely doped channel-region in between

form a lateral parasitic bipolar junction transistor. In a long-channel device, V,, drops

alrnost entirely across the drain-channel junction and the component of the channel electric

field parallel to the Si-SiO2 interface is negligible. Thus, the subthreshold drain current is

dominated by carrier diffusion Cjust as for the collector current in a long-base BJT) and

drops exponentially with VGS at a rate almost independent of VDs [16]. However, in a

short-channei device, the mechanism responsible for the subthreshold conduction is quite

different because the channel length is now comparable to the width of the drain depletion

region and, as a result, the potential gradient that the applied VDS voltage induces within

the weakly inverted channel is no longer negligible. Consequently, in a subrnicron

MOSFET, the subthreshold drain current is significantly influenced by the value of VDs * .

and drops with VGS at much lower rates as compared to a long-channel transistorn.

Now, the MOSFET drain current equations (2.2 1)-(2.27) are used in the proposed inverter

model to compute quantities Iike the peak inverter current, which correspond to strong

inversion. Since the n-th power law MOSFET model does not give a good approximation

for the drain current in the near- and sub-threshold regions anyway, the MOSFET model

parameters are optimized to best fit the ID-VDs charactenstics for values of VGS

significantly larger than the threshold voltage as it is normally defined. Consequently, the

empirical parameter V , in the MOSFET drain current equations takes a value significantly

different than the actual threshold voltage. On the other hand, the proposed inverter model

also requires a knowledge of the threshold voltage. Accordingly, an effective threshold

voltage V, , , which specifies more accurately the value of VGs below which the MOSFET

can be regarded as off ( I D = O ), must be determined.

5 Assumc an NMOS transistor.

F t As a rcference figure: the subthreshold drain current drops by about a factor of 10 for cvery 60 mV

reduction in VGs in practical long-channel NMOS deviccs (with VsB = 0) [SOI.

Chapter 2 Submicmn MOSFET Mode1 2.4 Eflsctive ïVueshold Vol-

The effective threshold voltage V,, is extracted from the I D venus lVcsl

characteristic of the MOSFET at 1 V,,I = 1 % V,, , where V,, is the supply voltage.

A relatively small drain-source voltage is used to ensure that the channel formed is uniform

(no pinch-off) and the transistor is essentially operating in its Iinear region. The intersection

of the tangent to the curve at the point of maximum slope with the VG,-axis gives the

effective threshold voltage V,, of the MOS transistor, as shown in Figure 2.5.

The effective threshold voltage V,, is assurned to be independent of the transistor

size, and is extracted for a representative MOSFET. The errors that this introduces in the

calculation of the power dissipation using the inverter mode1 proposed in this thesis turn

out to be acceptable. In Figure 2.5, a medium-size MOS device with L = Lmin and

W = 4 W,, was used. Lm, and W,, denote, respectively, the minimum channel length

and width defined by the design rules in the MOS process technology used.

The effective threshold voltages of the NMOS and PMOS transistors in the 5V O.8pm

BiClMOS technology of NORTEL's BATMOS process are given in Table 2.2.

Table 2.1 Effective threshold voltages of the NMOS and PMOS transistors in the SV 0 . 8 ~

BiCMOS technology of NORTEL's BATMOS process.

Chapter 2 Submicron MOSFET Modsl 2.4 EHective Threshold Voltage

Id vr. Vgs ciurictenrdc al V&YmV of NMOS (rinsutor (M.&nn,W17um)

I

Vcs 0

(a) NMOS transistor (L==û.8pm, W=7prn)

Id vr. Vsg ch.raciensoc et Vsd-MmV of PMOS Irrruislor (G0.Burn.W-7um)

(b) PMOS transistor (L=0.8pm, W=7pm)

Figure 2.5 Extraction of the MOSFET effective threshold voltage Vk from the ID versus

1 VGS 1 characteristic at 1 VDs ( = 1% VDD. A MOS transistor with L = L,, and W = 4W,, is

used. [The characteristics shown correspond to the 5V 0 . 8 ~ BiCMOS technology of

NORTEL's BATMOS process] .

Chapter 2 Submicmn MOSFET Mode1

2.5 MOSFET Mode1 Parameters

In the proposed inverter model, the modified n-th power law MOSFET equations were used

to relate the terminal voltages of each transistor to its drain current. Therefore, the resulting

delay and power expressions are in terms of the technology-dependent parameters

{ V,_, f, )co, n, B, m, K} . Hence, in order to apply the inverter model, these parameters

must be extracted for the technology in hand.

Accordingl y, the goal is to find the set of model parameters { V,,, f, ko, n, B, m, K )

that makes the modified n-th power law MOSFET equations fit best the measured 1-V

characteristics of the NMOS and PMOS transistors. A two-step procedure is followed for

that purpose. First, an initial estimate of these model parameters is found by solving simple

linear equations. Then, for the model to describe most accurately the MOSFET electncal

characteristics over the full range of device dimensions used in circuit design, an optimized

value of these parameters is computed using an optimization algorithm developed and

implemented in MATLAB.

A set of MOSFET model parameters is valid only for a small range of channel length.

Although the procedure described below is general, the model parameters were extracted

and optimized assuming al1 MOSFETs are designed at minimum channel length, Le.

L = L,,li,, which is a reasonable assumption for digital circuits. In general, two or three

sets of parameters may be enough in designing and analyzing a complete digital VLSI

circuit.

To characterize the SV 0.8pm BiCMOS technology of NORTEL's BATMOS

process, the model parameters { V,,,,, f, ho, n, B, m, K) were extracted by curve fitting the

1-V characteristics simulated in ELDO using NORTEL's MISNAN MOSFET model [20].

Measured 1-V characteristics were not used for two reasons: first, such data was not

available. Second, the inverter rnodel proposed in this thesis will be validated by comparing

the delay and power computed using the inverter model with the 'exact' values obtained by

simulating the analyzed circuit in ELDO using the MISNAN MOSFET model. Thus, any

Chapter 2 Submicron MOSFff Modd 2.5 MOSFET M d / Panmeters

discrepancy between the MISNAN model and the actuai MOSFET characteristic will not

get incfuded when assessing the accuracy of the inverter model. Accordingly, for the results

presented in the following analysis, the terms 'exact' and 'measured' are used to refer to

values obtained through circuit simulation with ELDO using NORTEL'S MISNAN

MOSFET model.

2.5.1 Parameter Extraction

An initial estimate of the MOSFET model parameters { VtW, f, &-,, n, B, m, K.) has to be

found for both the NMOS and PMOS transistors. The measured I D - V,, characteristics of

a medium size device with W = 4 W , , are used to extract these parameters (although any

other representative MOSFET width cm be selected). Recdl that Lm, and W,, denote

the minimum channel length and width, respectively, permitted in the MOS process

technology used.

VDS

Figure 2.6 Selection of fitting points on the measwed ID-VDs characteristics of the

MOSFET (with VGS as a parameter and VBS = 0 ) for the extraction of the MOSFET model

parameters.

Chapter 2 Submicmn MOSF€l M&e/ 2.5 MOSFET Modsl Pammetefs

The procedure followed to extract the initial set of MOSFET mode1 parameters is:

1. Assume V , , = V , , andf =O.then Vro = V,,-

2. From the saturation region of the measured I D - VDs characteristics of the

MOSFET with VGs as a parameter and V B , = O , select three fitting

points V G s V I I D ) v G s 2 D s 2 D ~ ) 9 a d (VGS3,VDS3 .ID3) with

VGSl = VGs2, as shown in Figure 2.6. Then, using equations (2.22) and

(2.23), we get:

3. From the linear region of the measured I D - VDs characteristics of the

MOSFET with Y,, as parameter and VBs = O , select two fitting points

(V,,, VDs,,I,,) and (VGSS, VDSS,ID5) , as illustrated in Figure 2.6. Then.

Chapter 2 Submicron MOSFEf Mode! 2.5 MOSFET Mode1 Panmeters

using equations (2.2 1 ) and (2.24), we get:

2.5.2 Parameter Optirnization

Since the delay and power expressions in the proposed inverter model are in terms of the

MOSFET model parameters { V,,,, f , ko, n, B, rn, K) , the accuracy of the invener model

will depend directly and to a large extent on these parameters. Therefore, after a set of

model parameters is extracted for each of the NMOS and PMOS transistors, it must be

optimized for the modified n-th power law MOSFET equations to describe most accurately

the eIectrica1 characteristics of the corresponding MOS device.

For a given MOS process technology, it is desired to accurately represent the

MOSFET electrical characteristics over the full range of device dimensions used in circuit

design with one set of model parameters ( V,,, f , Ao, n, B, rn, K 1 for both the NMOS and

PMOS transistors. Although the use of several sets of model parameters over specific

restricted ranges of transistor channel width would increase the accuracy of the MOSFET

model, in the interest of simplicity it was decided to work with only one set.

Chapter 2 Submicmn MOSF€T Mo&/ 2.5 MOSFET Mo&f Purametera

A set of w different MOSFETs with channel widths spanning the full range of device

dimensions used in circuit design are selected. The ID-V,, characteristic of each

MOSFET is measured at g different VGS values between VGsl and VDD, with

VGS, > Vrc. The goal is to optimize the set of MOSFET model parameters

{ V,,,., f , h,, n, B, m, K ) for the modified n-th power law MOSFET equations to fit best al1

these measured I D - VDs characteristics

The algorithm developed to optimize the set of MOSFET model parameters

{ V ,,,, f, Xo, n, B, m, K) is as follows:

1. Let the vector of MOSFET model parameters to be optimized be

- Hf - [w , . . . w,J = vector of w channel widths corresponding to

each of the transistors used in optimizing the

MOSFET mode1 parameters.

- VGs = [V,,, . . . vDD] = vector of g equally spaced

between VGSI and VDD, with

- VDs- [vDD/d ... v&] = vector of d equally spaced

between VDD/d and VDD .

where VDD is the supply voltage.

VGS values

V c s 1 ' v, -

V,, values

t The optimization algorithm outlined here applies to the modcl parameters of an NMOS device. The

srime algorithm is used to optimizc thc model panmetcrs of a PMOS transistor but with the terms

V,, and VGS intcrchanged with VsD and VSG, respectively.

Chapter 2 Submicron MOSFET Moôcl 2.5 MOSFET Mo&/ Panmeters

3. For a given MOSFET with channel width W i , the normalized error in the

MOSFET model at a particular point on the ID-VDs characteristic is

defined as:

where I ,,,,,,,,,,, is the exact drain current value obtained from the

measured ID - VDs characteristics of the MOSFET while ID,,dcI is the

drain current value computed using the modified n-th power law MOSFET L

model equations at VGS = V G S j and V,, = VDsk I.

4. The normalized error in the MOSFET model over an entire ID-VDs

characteristic with VGS = VGS, is then expressed as the sum-of-squares of

the error at each point on that particular characteristic for d different VDs

values:

- - 5. The normalized error vector E ( x ) is fomed as follows:

- - - E ( x ) = E ( x y I V i , V G S ) , i = 1 ,..., w and j = I ,..., g (2.39)

1

- - Thus, E ( x ) contains the normalized error in the MOSFET model for al1 g

1-V characteristics of each of the w different transistors considered in the

optimization.

t In this analysis, the i-th elemcnt of a given vector A is denoted by A , .

Chapter 2 Submicron MOSFET Mode1 2.5 MOSFET Mo&/ Pammeter8

6. The optimization problem can now be viewed as a nonlinear least-squares

problem:

find the vector x that will rninimize

Accordingly, the optimum set of MOSFET model parameters

{ IJ ,,'., f, A,, n, B, rn, K} corresponds to the solution X of the nonlinear

least-squares problem in equation (2.40). A starting guess for X is the

extracted set of MOSFET model pararneters obtained as outlined in

Section 2.5.1.

A MATLAB routine was written to compute the optimum set of MOSFET model

parameters { V , ,,, f, Ao, n, B, m, K } following the optimization algorithm outlined above.

The nonlinear ieast-squares problem in equation (2.40) was solved using the Gauss-

Newton method irnplemented in MATLAB [39]-

A trade-off exists between the computation time taken to optimize a set of MOSFET

model pararneters and the accuracy of these parameters. If, in the optimization process, a

larger set of MOSFETs with different channel widths is considered (i.e. w is increased),

additional measured 1-V characteristics for each of these MOSFETs is curve fiited

(i-e. g is increased), and more fitting points on each of these curves are used

(Le. d is increased), then a more accurate set of optimized model parameters will resuit.

However, the convergence time of the optimization routine will increase.

2.5 MOSFET M-1 Purametcm

Optimization Constraints

In optimizing the MOSFET model parameten, I D - VDS characteristics for VGS

values down to VGS are curve fitted. Since the n-th power law MOSFET model does not 1

give a good approximation for the drain current in the near- and sub-threshold regions, the

choice of VGSl has a very significant impact on the accuracy of MOSFET parameten and,

consequently, of the inverter mode1 proposed in this thesis.

On one hand, if VGS is chosen too close to V,, , the optimizer will be trying to curve 1

fit MOSFET equations to 1-V curves that these equations do not properly model to start

with, thereby leading to erroneous MOSFET model parameters. On the other hand, if VGS,

is chosen too far from V, , , the MOSFET equations will accurately fit the selected 1-V

characteristics but a large number of possible operating points will be excluded from the

optimization and, therefore, these equations will not properly model the transistor electricd

behavior over a sufficient range of operation. Consequently, a trade-off exists in selecting

VG SI . The value of VGs,, whose corresponding optimized MOSFET parameters will

enable the proposed inverter model to work most accurately, depends on the MOS process

technology used and must be determined experimentally.

The following experimental procedure was used to select VGS, :

i ) Assume VGS = 1 Z V , , . 1

i i ) Use the optimization routine to compute the corresponding set of MOSFET

model parameters.

i i i ) For a minimum size inverter with a fan out of 5 and an input voltage ramp

of transition time between 0.2511s and 2.5ns, compare the inverter delay

computed using the proposed inverter model with the 'exact' value

obtained by simuiating the inverter circuit.

25 MOSFET Mode1 Pammeters

iv) Repeat the above steps for larger VGsl values.

V) The set of MOSFET model parameters resulting in the most accurate delay

values is used to characterize the MOS technology.

In optimizing the MOSFET model parameten for the SV 0.8pm BiCMOS

technology of NORTEL's BATMOS process, it was found that curve fitting ID-VDs

characteristics for VGS values down to VGs, = 2V will result in the optimum set of

MOSFET model parameten with regard to the performance of the inverter model presented

in this thesis.

2.5.3 Results

The optimized parameters for the modified n-th power law model of the NMOS and

PMOS transistors in the 5V 0.8pm BiCMOS technology of NORTEL's BATMOS process

(where L,ni, = 0.8pm and W,,,, = 1.4pm ) are given in Table 2.2. The optimization was

perforrned for

In other words, the model parameters were optimized for the modified n-th power law

MOSFET equations to best fit the measured ID-VDs characteristics, down to

VGs = VGS, = 2 V , for a set of MOS transistors with channel widths of 2, 4, 8 and

16 W,, and a channel length of Lm,.

Chapter 2 Submicmn MOSFEt Mdel 2.5 MOSFET Modbl Parameters

To demonstrate the validity of the optimized set of model parameters over the full

range of transistor widrhs used in circuit design, the measured I D - VDS curves together

with the corresponding charcpcteristics computed using the modified n-th power law

MOSFET model are shown in Figure 2.7 for NMOS devices with channel width of W,,

( 1.4pm) and 20 W,, (28pm). These curves are plotted for different Vcs values between

1 V and 5V.

The failure of the model to reproduce the ID - V,, characteristics for VGS < I V was

anticipated (recall that V, , = 0.78V). Nevertheless, for V,, 2 2 V , the modified ndi-

power law MOSFET equations fit the measured I D - VDs curves to within 6% for both the

1.4pm- and 28pm-wide devices. For the MOS transistor with channel width W,,

(20 WnIi, ), the error over the characteristic corresponding to VGS = 1 .SV can get as large

as 18% ( 13%) at VDS = SV but does not exceed 8% (5%) for VDs voltages close to

V,,,, . Thus, the errors that this c m introduce in the calculation of the delay and power

using the inverter model presented in this thesis are negligible.

It is important to observe in Figure 2.7 how accurately the MOSFET model predicts

the value of VD,,, over al1 the VGs voltages. Since the peak currents in the CMOS

inverter occur when the corresponding transistor changes its region of operation (i.e. leaves

the linear region and enters saturation or vice-versa), a precise expression for VDSso, is

critical to accurately compute the inverter delay and power.

Table 2.2 Optimized parameters for the modified n-th power law mode1 of the MOS

transistors in the 5V 0 . 8 ~ BiCMOS technology of NORTEL'S BATMOS process.

J - ( ~ v ) '

0.0506

0.1042

NMOS

PMOS

K B

0.9369 3.77943-5

1.1789 1.923e-5

vh CV>

0.9792

1.1770

f

0.1488

0.0648

n

1.1937

1.1806

m

0.6678

0.7004

Figure 2.7 MOSFET ID-Vos characteristics: (-1 measured, (-) modified n-th power law

MOSFET model. To demonstrate the validity of the optimized set of model parameters over

the full range of transistor widths used in circuit design, the characteristics of an MOS device

with L = Lmin and (a) W = Wmin, <b) W = 20Wmin are plotted. m e characteristics s h o w

correspond to the 5V 0.8p.m BiCMOS tecbnology of NORTEL'S BATMOS process where

Lmi,=0.8pn and Wmi,= 1.4p.1111.

Inverter Delay and Power Modes

This chapter begins by introducing the CMOS inverter circuit and the associated parasitic

capacitances, which must be accounted for in the delay and power calculations. To simplify

the transient analysis of the CMOS circuit, these nonlinear voltage-dependent capacitances

are modeled by equivalent constant capacitances, as described in Section 3.6.

A detailed literature review of techniques for computing the delay andor power in CMOS

inverters is given in Section 3.2. For easier reference, the symbois used when describing

the inverter circuit are defined in Section 3.3. The delay and power modets are then

presented assuming that the peak short-circuit and charging/discharging current values,

their time of occurrence, and the corresponding output voltages are known.

This information is readily obtained using the inverter current model presented in

Chapter 4, hence the simplicity of the delay and power analysis.

3.1 The CMOS Inverter

The CMOS inverter circuit is depicted in Figure 3.1 (a), with the parasitic capacitancest of

the MOS transistors modeled explicitly:

- - -- -

.: The subscripts d. g. S. and b denote, rcspectively. the drain. gate, source, and bulk teminals of the MOS transistors,

rcsptxtively. while the subscripts n and p are used to asscziatc the capricitances to the NMOS or PMOS device ifi the

CMOS invener circuit, respectivcly.

Chepter 3 lnverter Oelsy and Power Modrsls 3.1 The C M InverUr

Note that the output capacitances, Con and Co,, . include the input (gaie) capacitances of,

respectively, the pull-down and pull-up groups in the fanout gates.

A load capacitance, Cl,,lrdi accounts for the effective interconnect capacitances.

When computing the voltage and currents at the output node, the equivalent inverter circuit

in Figure 3. l (b) cm simply be used, with the effective load capacitance defined as

Figure 3.1 CMOS inverter circuit with the parasitic capacitances of the MOS transistors

modeled explicitlp In circuit diagram (a), COp and Co, include the input capacitances of the

fanout gates while the load capacitance, Cload, accounts for the intercomect capacitances.

In the equivalent circuit mode1 (b), the effective inverter load, CL, gmups the NMOS and

PMOS drain-bulk junction capacitances, the input capacitances of the driven gates, and the

intercomect capacitances.

Chapter 3 Inverter h l a y and Power M-1s 3.1 7 7 ~ CMOS In wrîer

Thus, the effective inverter load CL includes the NMOS and PMOS drain-bulk junction

capacitances, the input capacitances of the driven gates, and the interconnect capacitances.

The gate capacitances, C,, . C,, . and Cpd , are lumped MOS capacitors that account

for the gate-to-channel capacitances and also include, respective1 y, the gate-to-bulk, gate-

to-source, and gate-to-drain overIap capacitances. Cdb is a lumped p-n junction capacitor

describing the drain-bulk junction capacitances. These MOSFET parasitic capacitances are

nonlinear voltage-dependent capaci tances whose exact mode1 ing is qui te complex.

Therefore, to simplify the delay and power calculations in the CMOS inverter circuit, these

capacitances are replaced by equivalent constant capacitances, as described in Section 3.6.

Consider the CMOS inverter circuits in Figure 3.2. If the input voltage, vi , is a rising

signal, the NMOS transistor will turn on (when q 2 V,,), thus discharging the load

capacitance. However. until the PMOS transistor tums off (when vi 2 VD, - 1 V,I ), a

conducting path persists between the power and ground rails, thereby reducing the effective

current available to discharge the load and resulting in supply-power consumption. For this

reason, ip is called the 'short-circuit' current in the case of a discharging inverter (rising

input). Similady, when the input voltage is a falling signal, the PMOS transistor is the

charging transistor and in is the short-circuit current.

With rising/falling input transitions, the gate-to-drain coupling capacitance (Miller

capacitance), CM, allows a current i , to fiow between the input and output nodes, causing

an overshoot/undershoot at the early part of the output voltage wavefonn: as vi starts

ris inglfalling from ground/ V,, , CL gets actualiy overcharged/discharged unti 1 the

NMOSPMOS transistor turns on, thereby creating a path to ground/VD, and eventually

dischargingkharging the load capacitance.

Chapter 3 lnverter Delay end Powcr ModsIs 3.1 nie CMOS lnwfter

The input voltage waveform is assumed to be a rising/falling ramp with transition

time T r / T J :

Sr 1 O l t l T , risinginput (discharginginverter): v j ( t ) = { vDD t 2 T ,

(3-5)

O l t l T f falli ng input (charging inverter): v i ( t ) =

t r T / (3 .4)

where sr = V D D / T r and s, = V D D / T f are the dopes of the rising and falling input voltage

ramps, respectively. This input wavefom approximation is widely accepted because of its

si mpIicity and effectiveness.

(a) Discharging lnverter (Rising Input) (b) Charging Inverter (Falling input)

Figure 3.2 CMOS inverter circuit: (a) discharging inverter (rising input), (b) charging

inverter (falling input).

Chap:er 3 Inverter Delay and Pow;hr Modsls 3.1 The CMOS In wrter

The differential equation describing the charging/discharging of the CMOS inverter

is obtained by writing Kirchoff s Current Law at the output node:

For the case of a rising input voltage ramp, the above equation reduces to

. . dv,, - - - - [ I I - l p + c,s, , for O 5 r 5 T , dr CL + CM

where c,,, = CM C L + ~ M '

The modified n-th power law MOSFET equations in (2.21)-(2.27), suitable for

submicron devices, are used to express the drain currents of the NMOS and PMOS

transistors in terms of their respective terminal voltages.

Chapter 3 Inverter Oslsy and Powr M o d e i s 3.2 Litemturs Review

3.2 Literature Review

In this section, we review some of the previous work on computing the dehy andor power

in a CMOS inverter with a capacitive load (Figure 3.2), using accurate transistor-level

rnodels. Since a nurnber of these techniques are based on the simple a-power law MOSFET

model [24], it is bnefly described below.

3.2.1 a-power Law MOSFET Mode1

Before introducing the n-th power law MOSFET model [25] (described in Section 2.3),

Sakurai and Newton proposed a simpler, but less accurate, a-power law model to account

for the velocity saturation effect in short-channel transistors [24]:

'Drur I D = - VDs , VDs 5 VDssu, (Linear Region) V ~ ~ s u r

I D = IDsur , VDs 2 VDssu, (Saturation Region) (3.10)

w here

The model is an extension of the long-channel square-la LW MOSFET model in the saturation

region, and is based on four parameters: V, (threshold voltage), a (velocity saturation

index), V,, (drain saturation voltage at V,, = V,,), and I D , (drain current at

V,, = V,, = V,, ). Hence, ID, and V,, must be extracted for each transistor size used.

In the linear region, the drain current is approximated by a linear function of VDs ,

rendering the model inadequate for investigating the behavior of transistors in this mode of

operation. Furthemore, the model does not account for the channel length modulation

effect.

Chapter 3 Inverter Dslsy and Power Models

3.2.2 Review of Inverter Delay Models

Delay evaluation in digital CMOS circuits has been the subject of research for a long time.

A number of techniques, involving various trade-offs between speed and accuracy, have

been presented in the literature.

In [24], an expression for the delay, based on the a-power law MOSFET model, was

derived, neglecting the short-circuit current and the effect o f the input-to-output

capacitance (Miller capacitance). Furthemore, it was assumed that, at v , = V D D / 2 ,

the input voltage ramp has reached its final value and the charging/discharging transistor is

operating in its linear region. Hence, the resulting delay equation is only valid for those

particular cases where the input ramp is fast compared to the output voltage transition

a n d o r the fanout is hight.

Embabi and Damodaran [27] presented an efficient technique to improve the

approximate delay time, calculated from the equation in [24], by accounting for the

short-circuit current through the complementary transistor. However, since the initial

approximate delay was derived for heavily-loaded inverters a n d o r fast input signals,

this method will result in a more accurate delay time only for those particular cases.

An extension of Sakurai's work [24] on delay modeling for the case of slow input

ramp and/or low fanout was proposed in [28], but still assuming negligible short-circuit

current. The inverter dc vol tage-transfer-characteristic was used for that purpose. The delay

was calculated from an empirical expression joining the two extreme points corresponding

to infinitely fast and infinitely slow input ramps. The curve fitting coefficients used depend

on the ratio of the transistor sizes and the inverter fanout, and must be reproduced by

mnning HSPICE simulations. Still, no clear definition is given to extract the critical

transition times used to distinguish a fast input transition (where Sakurai's mode1 is valid)

from a slow one (where the proposed equations must be used).

t A voltage transition at the input of a given invener may no longer be 'fast'. compiued to the output transition. if the

fanout is rcduced. Similarly. the load may no longer be 'large' if the invener is drivcn by slower input nmps.

Chapter 3 Inverter Dclsy and m e r Mm18 3.2 Litemtum Review

In [25], Sakurai and Newton denved another delay expression for the CMOS

inverter, but now based on the n-th power law MOSFET model. Both the short-circuit

current and the effect of the Miller capacitance were again neglected. Furthemore, it was

assumed that the output node starts k ing chargeddischarged only when the input voltage

ramp reaches V,,, , the logic threshold voltage. Vi,I , was defined as the input voltage

which makes v , = V , , / 2 and was derived assuming zero load and both transistors

saturated.

The diftërential equation describing the charging/discharging of the load capacitance

at the output node (equation (3.7)) was solved, in [29] and [30], for an input voltage ramp,

considering the current through both transistors and the effect of the Miller capacitance.

However, in [29] , the long-channel bulk-charge MOSFET model was used, with the

quadratic VDs-term in the drain current equation neglected. Furthemore, the derived

expressions for the output voltage response are in terms of the mathematical error function

(erf), and fitting methods are used to determine the empirical coefficients in the delay

equations. In [30], analytical expressions for the output voltage waveform are derived

based on the a-power law MOSFET model. However, the short-circuit current is

approximated by a linear function of time with the dope calculated by equating the exact

current in the linear region with the approximate one at t = t o / 2 , where t , is the time

when the short-circuit transistor turns off. Hence, in order to solve for the output voltage

equations and evaluate the delay, Taylor series expansions up to the second-order

coefficient were used for v, ,( t) and VDs,,,(t) around t = t , - t , , where r , is the time

when the chargingldischarging transistor turns on.

A different, more elaborate, approach was followed by Park and Soma [3 11 to predict

the output voltage waveform of a CMOS inverter at switching transitions: the inverter is

first transformed into a time-invariant linear system, and convolution theory is then used to

solve for the switching responses. However, a number of parameters, which depend on both

the geometry of the devices and the processing technology, must be extracted before the

inverter model can be applied.

Chapter 3 Inverter M y and Pbmr M u s 32 Uiemture Review

3.2.3 Review of Inverter Power Models

The total power consumption of a CMOS inverter can be calculated, readily and accurately,

provided its short-circuit component can be evaluated (as discussed later in Section 3.5).

Hence, the focus nas k e n on developing models for computing the short-circuit power

dissipation, P,,, in CMOS inverters.

In [32], a simple formula for P,, was derived based on the long-channel square-law

MOSFET model, assuming symmetrical inverters and zero load. Furthermore, the effect of

the Miller capacitance was neglected. This formuia was then extended to submicron

inverters in [24], by replacing the square-law MOSFET equations with the corresponding

a-power law equations.

Hedenstierna and Jeppson [33] derived a formula for Px based on the long-channel

square-law MOSFET model, considering the effect of the load capacitance. In their

analysis, an expression for the output voltage response was derived neglrcting the short-

circuit current, Isc, and then used to express I,, as a function of time. P,, is finally obtained

by integrating the resulting expression for 1,. Vemuru and Scheinberg [34][35] followed

the same analysis to derive a formula for Psc in submicron inverters, based on the a-power

law MOSFET model. Then, to get an analytical solution for the integral equation of P,,, the

time when the short-circuit transistor changes its mode of operation was assumed to occur

at t = 1, - r , , where t , and t , are, respectively, the times when the chargingldischarging

transistor turns on and the short-circuit transistor turns off. Consequently, the error in both

formu las is large for relatively slow input ramps and/or low fanouts, where the short-circuit

dissipation is no longer small compared to the total dynamic power dissipation.

The differential equation describing the charging/discharginp of the load capacitance

at the output node (equation (3.7)) was solved in [36] for an input voltage ramp, considering

the current through both transistors and the effect of the Miller capacitance. However, the

short-circuit current was represented by a piecewise linear function of time. Furthermore,

the maximum value of the short-circuit current was assumed to appear when the input

Chapter 3 Inverter Delay and Power ModsIs

voltage reaches V i n , , the logic threshold voltage. V i n , was evaluated using the expression

derived in [25], assuming zero load and both transistors saturated. The piecewise linear

approximation for the short-circuit current is then used to obtain P,,.

In 1381, an equivalent capacitance was defined for each power component and then

derived on the basis of the empirical delay macro-mode1 for the CMOS inverter presented

in [37] (where step responses are empirically corrected for actual input ramp transitions).

Furthemore, the effective input transition time is assumed to be defined through the step

response of the driving inverter, and the waveform of the short-circuit current is taken to

be symmetrical with respect to its maximum.

3.3 Nomenclature

The following parameters will be used when describing the discharging (rising input)

CMOS inverter in Figure 3.2:

Discharging current (drain current of the NMOS device)

Short-circuit current (drain current of the PMOS device)

Maximum value of the discharging current

Maximum value of the short-circuit cwrent

Minimum value of the short-circuit current

Slope of the rising input voltage ramp

Time variable

Time when the NMOS device tums on

Time when the discharging current reaches its maximum

Time when the NMOS device leaves saturation and enters the linear region

Time when the PMOS device turns off

Time when the PMOS device leaves the Iinear region and enters saturation

Transition time of the rising input voltage ramp

Input voltage waveform of the CMOS inverter

Output voltage waveform of the CMOS inverter

Power-supply voltage

Drain-source voltage of NMOS device

Gate-source voltage of NMOS device

Source-drain voltage of PMOS device

Source-gate voltage of PMOS device

Threshold voltage of NMOS device, in the modified n-th power law MOSFET model

Threshold voltage of PMOS device, in the modified n-th power law MOSFET model

Chapter 3 Inverter Dslay and Pbwcr Models

3.4 Inverter Delay Mode1

In a CMOS inverter circuit dnving a capacitive load, the output voltage transition can be

properly characterized by the tangent line to the output voltage waveform at the time when

the chargingldischarging current reaches it maximum. This is shown in Figure 3.3 for the

case of a discharging inverter (rising input).

Let t , , be the time when the discharging current reaches its maximum, and defïne

V ,,,, , = ~ , , ( t , ~ , ) . Expressions for r , , and V ,,, will be derived in Section 4.2.3, as part of

the inverter current model. The tangent iine to the output voltage waveform at t = t , , is

then

~ ' , ( f ) = Vonm + Sf,, ( f - f n m ) (3.13)

d where s,, Ezvoll - is computed using equation (3.8) (with the drain currents of both

- *nm

devices calculated based on their known terminal voltages).

. 104 Time (sec)

Figure 3.3 Linear approximation of the output voltage waveform for a discharging inverter

(rising input). The output voltage transition c m be fuily characterized by the tangent line to

the output voltage waveform at time t,, when the discharging current, in, reaches its

maximum.

Chapter 3 lnverîer Delay and Power Mdeîs 3.5 lnverter Power Mo&/

This lineanzed output voltage transition is now used to compute the propagation delay

(time between the 50% points of the input and output voltage waveforms) of the

discharging inverter:

The time at which the linearized output voltage transition starts falling and its

transition time are, respectively,

and

Thus, t,, and T,,, can now be used to fully characterize the falling voltage transition at the

input of the fanout pates.

The derivation of the propagation delay and the characteristics of the output voltage

transition for the case of a charging inverter (falling input) is symmetrical, and equivaient

results can be obtained by appropriate substitution in the derived equations.

3.5 Inverter Power Mode1

The power dissipation in a CMOS logic gate can be expressedt as

t assuming no glitches

Chapter 3 Inverter Delsy and Power M o d s I s 3.5 Inverter Power Modsl

The static component of the power consumption is due to the dc leakage current II,,,,,, . There are two types of MOSFET leakage currents: (1) a reverse-bias p-n junction current

between the drainfsource and the substrate; (2) a subthreshold current resulting from carrier

diffusion between the drain and the source when the gate-source voltage, IV,,I , is below

the threshold voltage, 1 V,I , but is still large enough to induce a weakly-inverted channel (as

opposed to a strongly-inverted channel, when 1 VGsl 2 1 V,I , where carrier drift is dominant

[16]). The leakage currents are determined primarily by the MOS processing technology

used. With the ongoing trend towards scaling down the minimum feature size and the

supply voltage in CMOS integrated-circuits, the subthreshold currents are growing due to

short-channel effects and scaled-down threshold voltages [8][9], thereby increasing the

power dissipation. However, the contribution of the static power component to the total

power consumption remains negligible in a well-designed CMOS logic circuit [IO].

The dynarnic component of the power consumption is due to the charging and discharging

of the load capacitances and to the switching transient currents. f denotes the clock

frequency while p is the switchirig probability o r activity factor at the output node

(i-e. the average number of output switching events per clock cycle). An output switching

event refers to the sequence of a low + high and a high + low output logic transition

(i.e. the full charging and discharging of the output node).

The dynamic energy consumed per output switching event is defined as

i swi&ïng evcnt

where i,, and V, , are the power-supply current and voltage, respectively.

For the CMOS inverter circuit in Figure 3.2, the dynamic energy dissipation is then

Chapter 3 Inverter Dulay end Power M M 8 3.5 Inverter Power Mode1

The first te*, C,V;, , represents the energy dissipation due to the charging and

discharging of the effective load capacitance, CL. On the 0 + VDD output voltage

transition. an energy c ~ v ~ , is drawn from the power supply, haif of which is stored in

CL and half is dissipated in the pull-up PMOS device. On the VDD + O output voltage

transition, no charge is drawn from the supp1y (other than the charge accounted for in Es, ).

However, the energy stored in CL is dissipated to ground via the pull-down NMOS device.

The second terrn, 2 c , , v~ , , is the energy dissipation due to the input-to-output coupling

capacitance, C , . A rising input results in a V,, 4 -VDD transition of the voltage across

C , and, consequently, a change in charge of 2 C,VDD. The charging current flows from

the input of the inverter (or power supply of the driving stage) to ground. The failing input

transition causes the same charging current to flow, but now from the power supply of the

inverter to the ground of the previous stage.

The short-circuit energy dissipation, Es,, is due to the direct-path current from supply to

..round when both the NMOS and PMOS devices are simultaneously onT: s

where

and

rire the short-circuit energy dissipations in the case of a charging and a discharging inverter,

respectively.

i It is intercsting to note that. if the MOS proccssing technology and the supply voltage used hrid V D D c V,, + IV,,,l . the short-circuit currents could bc eliminated becausc the NMOS and PMOS dcvices would not bc on

sirnultaneously for any value o f input voltage.

Consequently, the total power dissipation in the CMOS inverter circuit can be readily

calcuiated, from equations (3.17) and (3.19), provided the short-circuit energy dissipation

per switching event, Es,, can be evaluated. This requires solving the integral equations

in (3.21) and (3.22), a computationaly expensive procedure. At the same time, the total

power consumption is largely underestimated if its short-circuit component is neglected:

as shown in Chapter 5, the short-circuit energy can account for more that 35% of the total

dynamic energy dissipation. Furthemore, with the ongoing trend towards scaling down

the suppIy voltage and the minimum feature size in CMOS integrated-circuits, the

short-circuit current contribution to the total power dissipation is increasing.

A simple, yet accurate enough, approach for evaluating E,, is presented below.

Short-Cireuit Energy Dissipation

To evaluate E,, , one can approximate the short-circuit currents (in in the charging inverter

and i, in the discharging inverter) by piecewise linear functions of time. This is shown in

Figure 3.4 for the case of a discharging inverter (rising input).

With rising input transitions, the Miller capacitance, CM, allows a current flow frorn

the input to the output node, causing an overshoot at the early part of the output voltage

waveform and an initially negative flow (from the output node to the power suppiy) of the

short-circuit current. i,: as vi Stans rising, the load capacitance,CL, gets actually

overcharged until the NMOS transistor turns on, thereby creating a path to ground and

eventually discharging CL. Therefore, it is reasonable to assume that the short-circuit

current reaches its minimum value, I,,, , when the discharging NMOS transistor turns on

(when VGSn = V,,, ), at time r , r , .

Chapter 3 Inverter Dslay and Power Mode18 3.5 InveHer Powur Mockl

Let r,, be the time when the short-circuiting PMOS transistor leaves the linear region

and enters saturation. Simulation results have shown that, for the purpose of computing

E,,. . it is valid to assume that the short-circuit current reaches it maximum value, I,,,, ,

at t = r,, . Now, it is possible, in the case of very fast input trmsitions, that the PMOS

device actually turns off before entering saturation. This occurs if, by the time when the

PMOS transistor switches off (i-e. at t = t , ,) , the output voltage wavefonn has not yet

completed its overshoot and dropped below VDD - 1 V,I . In this case, t,, is simply assumed

equal to r,, . as discussed in Section 4.2.2.

Expressions for lPmi,, I ,,,, , and t,, will be derived in Chapter 4- as part of the

inverter current model.

Now. as discussed in Chapter 2, the value of the gate-source voltage lVGsl below

which the NMOSIPMOS transistor can be regarded as off (no drain current is flowing) is

more accurately specified by the corresponding effective threshold voltage, V,, , than by

the threshold voltage value, V,, used in the modified n-th power law MOSFET equations

in (2.2 1 )-(2.27).

Figure 3.4 Piecewise linear approximation of the short-circuit current, ip, used to compute

the short-circuit energy dissipation for the case of a discharging inverter (rising input).

Chapter 3 Inverïer lblay and Pomsr Moddr 3.5 Inverter Po- Mode1

Therefore, only for the purpose of evaluating E,,, the times when the transistors are

switched on or off are computed using the effective threshold voltages, Vrn, and V,,,

derived in Section 2.4. Thus, for the case of a discharging inverter,

and

Hence, from Figure 3.4, the short-circuit energy

discharging inverter (in equation (3.22)) can be expressed

dissipation for the case of a

as

The short-circuit energy dissipation for the case of a charging inverter (falling input), Es, - , , cari be derived in a sirnilar way.

Chapter 3 Inverter Delay and m r M M s 3.6 MOSFET Capachnce Mokbling

Figure 3.5 Lumped model for the parasitic capacitances of an MOS transistor (the source

and b d k terminais are at the same potential: Vsb = 0).

3.6 MOSFET Capacitance Modeling

MOSFETs exhibit a number of parasitic capacitances which must be accounted for in

ac and transient circuit analysis. Figure 3.5 iIlustrates a lumped model for the parasitic

capacitances of an MOS transistor. The gate capacitances C,, , Cg,, and Cg, are MOS

capaci tors that account for the gate-to-channel capacitances and also include, respective1 y,

the gate-to-bulk, gate-to-source, and gate-to-drain overlap capacitances. Cdb is a p-n

junction capacitor describing the drain-bulk junction capacitance.

The MOSFET parasitic capacitances are distributed, voltage-dependent, and

nonIinear, and their exact modeling is quite cornpiex. Therefore, to simplify the delay and

power caiculations in the proposed inverter mode], these capacitances are replaced by

equivalent constant capacitances, as described below. It is important to stress that the

accuracy of the inverter mode1 will depend directly and to a large extent on these constant

capac itances.

Chapter 3 lnverter Dslsy and Pbwsr Moddr 3.6 MOSFET Capaciîance Modbling

I - - - -

MOSFET Mode of Operation

- - - -

Table 3.1 Approximation of the MOSFET gate intrinsic capacitances [12].

' ~ ~ i n r

Gate Capacitances

The gate capacitances are expressed as the sum of their respective intrinsic and extrinsic

(overlap) capacitancesi:

= CGB,,, + CCB,,, (3.26)

CRS = Cmint + CcSx, (3.27)

C g d = CGD,, + CCD~,; (3.28)

Off

wg ~c,- c o x

The intrinsic capacitance is a fraction of the effective gate-oxide capacitance and

function of the MOSFET biasing voltages. A simple, yet accurate enough, approximation

of the intrinsic capacitance is

C i n r = WK L c Cox

where r is a constant over each MOSFET mode of operation.

Linear

0

-- - - - - - -

t The subscripts irir and exr stand for intrinsic and extrinsic. respectively.

Saturation

0

Chapter 3 lnverter Delay and Pmmr Mrrdels

The gate-oxide capacitance per unit area is given by

where E,,, and t,, are, respectively, the permittivity and thickness of the gate oxide.

L, is the effective channel length, as defined in equation (2.6), and

is the effective gate width, with W and XW being, respectively, the drawn channel width

and the gate width correction to account for masking and etching effects.

In tems of the accuracy of the transient anaIysis, the optimal set of values for r depends

on the MOS process technology used, and must therefore be extracted experimentally.

However, to keep the inverter model simple and general, the consenmtive estimates, given

in Table 3.1 1121, for the gate intrinsic capacitances were used.

The gate extrinsic capacitances, CG, , C,Sc-rr, and CGDcIr, account for the overlap CS1

of the gate over the bulk, source, and drain regions, respectively, and are computed as

folIows [4 1][42]:

=GS,,, = W , (LD Co, + CGFRS) = W, CGSO

c ~ s c . c r = Wp (LD C,,, + CGFRD) = W, C G D O

In the above equations, the model parameters for the gate extrinsic capacitances, defined in

Table 3.2. are characteristic of the MOS process technology used.

Chapter 3 lnverter Delay and Power M d l s 3.6 MOSFET Capaciîance Mothling

CPTS

WTGF

CGFRS

CGFRD

LD

CGBO

CGSO

CGDO

polysilicon-to-substrate capacitance, per unit area over the gate-to-field oxide transition at the edge of the gate

- -- -

width of the transition fkom gate oxïde to field oxide under the polysilicon, along the length edges of the gate

- -

gate-to-source fringing field capacitance, per unit gate width

gate-to-drain fringing field capacitance, per unit gate width - - ~ -

lateral diffusion into the channel from the source/drain diffusion region

gate-to-bulk overlap capacitance, per unit channel length

gate-to-source overlap capacitance, per unit gate width

gate-to-drain overlap capacitance, per unit gate width

Table 3.2 Definition of the mode1 parameters for the MOSFET gate extrinsic (overlap)

capacitances.

The depletion-layer (junction) capacitance C, of a p-n junction diode is function of the

reverse-bias voltage V, across the junction [ l I l :

where C j , is the junction capacitance at equilibrium (i.e. ai zero bias). V,, is the junction

built-in (contact) potential and ln is the junction grading coefficient ( m is f for an abrupt

p-n junction and for a linearly-graded one).

$ V , corresponds to the potential at the n-sidc of the junction with respect to the psidc. and is therefore positive for a

reverse-biased p-n junction.

Chapter 3 Inverter Delay and Power M&Is 3.6 MOSFEf Capacibnce Modeling

An equivalent constant capacitance, which sees the same change in charge as the

voltage-dependent junction capacitance for a change in the reverse-bias voltage from V , ,

to V r 7 , is then given by [ I l ]

Similarly, in the CMOS inverter circuit, the drain-bulk junction capacitances can be

rnodeled by constant capacitances which will force equivalent changes in charge for

transitions in the reverse-bias drain-bulk voltages between O and VDDt:

where

In the above equations, the model parameten for the MOSFET drain-bulk junction

capacitance, defined in Table 3.3, are characteristic of the MOS process technology used.

A, and Pd are. respectively. the area and periphery of the drain region. Note that C,, , CjI ,

and C j , represent the equivalent junction capacitances over the area of the drain region

(A,), dong the field-oxide periphery of the drain region ( P d - W,), and along the gate-

oxide periphery of the drain region ( W, ), respectively .

t where V D D is the supply voltage

Chapter 3 lnverîer Delay and Power A#-8 3.6 MOSFET Copacitance Mdeling

Table 3.3

capacitance.

bulk-junction built-in (contact) potential

zero-bias bulk-junction capacitance, per unit area over the drain region

zero-bias bulk-junction capacitance, per unit length along the field-oxide periphery (sidewail) of the drain region

zero-bias bulk-junction capacitance, per unit length along the gate-oxide periphery (gate-edge sidewall) of the drain region --

buik-junction grading coefficient for area component

bulk-junction grading coefficient for field-oxide periphery (sidewall) component

bulk-junction grading coefficient for gate-oxide periphery (gate-edge sidewall) component

De6nition of the mode1 parameters for the MOSFET drain-bulk junction

Inverter Current Mode1

In this chapter, the current mode1 for the CMOS inverter is presented. The inputs to the

mode1 are the transistor sizes, the input-voltage transition tirnes, and the capaciti ve loading.

The outputs are the peak values of the short-circuit and chargingldischarging currents, their

time of occurrence, and the corresponding output voltages. These data are required by the

delay and power models presented in Chapter 3. Furthennore, the peak values of the power-

supply current are needed to properly size the power and signal lines, in order to avoid

electromigration failures and IR-drop problems.

We first study the case of a discharging inverter (rising input). An expression for the

minimum short-circuit current is derived. Analytical techniques for computing rapidly and

accurately the times when the PMOS and NMOS transistors change their mode of operation

and the corresponding output voltages are presented. These values are used to calculate the

maximas of the short-circuit and the discharging currents. The symmetrical case of a

c harging inverter (falling input) is then discussed, and an expression for the peak value of

the power-supply current is derived. For easier reference, the syrnbols used when

describing the CMOS inverter circuit are listed at the beginning of this chapter.

Chapter 4 lnveder Current Mo&/

4.1 Nomenclature

The following parameters will be used when describing the discharging (rising input)

CMOS inverter in Figure 3.2:

Discharging current (drain current of the NMOS device)

Short-circuit current (drain current of the PMOS device)

Maximum value of the discharging current

Maximum value of the short-circuit current

Minimum value of the s hort-circuit current

Slope of the rising input voltage ramp

Time variable

Time when the NMOS device turns on

Time when the dischar,@g current reaches its maximum

Time when the NMOS device leaves saturation and enters the h e a r region

Time when the PMOS device turns off

Time when the PMOS device ieaves the linear region and enters saturation

Transition time of the rising input voltage ramp

Input voltage wavefonn of the CMOS inverter

Output voltage waveform of the CMOS inverter

Power-supply voltage

Drain-source voltage of NMOS device

Gate-source voltage of NMOS device

Source-drain voltage of PMOS device

Source-gate voltage of PMOS device

Threshold voltage of NMOS device, in the modified a-th power law MOSFET model

Threshold voltage of PMOS device, in the modified n-th power law MOSFET model

Chapter 4 Inverîer Cumnt M W 1

4.2 Discharging Inverter (Rising Input)

Consider the discharging inverter circuit in Figure 3.2. The input voltage waveform is

assumed to be a rising rarnp with transition time T , :

where sr = V D D / T , is the slope of the rising input rarnp. This input waveform

approximation is widely accepted because of its simplicity and effectiveness.

As vi rises, the NMOS and PMOS transistors are, respectively, tumed on and off

at times

and

The modified n-th power law MOSFET equations in (2.2 1)-(2.27). suitable for

submicron devices, are used to express the drain currents of the NMOS and PMOS

transistors in terms of their respective terminal voltages.

Chapter 4 Inverter Cumnt Mo&/ 4.2.1 Minimum Short-Cireuit Cumnt

4.2.1 Minimum Short-Circuit Current

With rising input transitions. the Miller capacitance, CM, allows a current flow frorn the

input to the output node, causing an overshoot in the early part of the output voltage

waveform and an initially negative fiow (from the output node to the power supply) of the

short-circuit current. i,: as vi starts rising, the load capacitance,C,, gets actually

overcharged until the NMOS transistor turns on, thereby creating a path to ground and

eventually discharging CL. Therefore, it is reasonable to assume that the short-circuit

current reaches it minimum value, IPmin, when the discharging NMOS transistor turns on,

i.e. at t = t,,, .

For O S t I t , , , the PMOS transistor is operating in its linear region while the NMOS

device is off (Le. i, = O ). Since V,,, = VDD - v , is very small during that time interval,

its quadratic terni in the PMOS drain current equation in (2.21)-(2.24) can be neglected.

Thus. the short-circuit current can be approximated by

where v i ( t ) is replaced by its value at t = t , , . Substituting i,, into equation (3.8) and

solving the resulting differeniial equation with the initial condition v,(O) = V,, yields an

approximation of the output voltage waveform during the time interval O I r I r , , :

Hence, the minimum value. Ip , , t in , of the short-circuit current is computed using the

PMOS drain current equation in (2.2 1)-(2.24) with V,,, = VDD - V, and

V,,, = V,, - Von, , where Von, = v , ( t , , ) is calculated from equation (4.5).

Chapter 4 Inverter Cumnt Mode1 4.2.2 Maximum Short-Circuit Cumnt

4.2.2 Maximum Short-Circuit Current

Let t , , be the time when the short-circuiting PMOS transistor leaves the linear region and

enters saturation, and define V,,, = v , ( t p , ) . The values t,, and VOpl need to be found

because:

1 ) in the power model, the short-circuit energy dissipation is computed assuming that

the maximum short-circuit current occurs at t = t,, .

2 ) v , ( t , , ) will be used (in Section 4.2.3) as an initial condition when solving the

differential equation (3.8) to determine the time when the discharging current

reaches its maximum. This time and the corresponding output voltage are needed to

evaluate the inverter delay and calculate the maximum discharging current.

Let r,, be the time when the NMOS device leaves saturation and enters the linear region.

S ince at vi = v , both the NMOS and PMOS transistors must be in saturation, the PMOS

device must enter saturation before the NMOS device leaves it. Therefore, we have

t,, - f,,",, , where t,,, = m i n o ,,,, t,,) -

The special case of t,, = t,, corresponds to very fast input ramps where the PMOS device

turns off before entering saturation. This occurs if vi reaches V,, - 1 V,I (switching the

P M O S transistor off) before the output voltage waveform has completed its overshoot and

v,, has dropped below V, , - 1 V,,I .

T o evaiuate t , , , a three-step approach is used: In the first step, the short-circuit

current is neglected, i-e. i, = O is assumed. An approximate expression for the output

voltage is then derived and used to compute 5,, an estimate of t,, , and the corresponding -

output voltage, V,, . In the second step, t , is used as a reference point in time.

The actual time. t , , required for the output voltage to drops to V,, is found by accounting

for the short-circuit current neglected in the first step. Now, [ t , , V,,] represents an actual

point on the output voltage waveform very close to t,, . Therefore, in the third step,

a linear approximation of the output voltage waveform through the point [ t , , V,,] is used

to compute t,, and V,,, . The denvation of this procedure is as follows.

Chapter 4 Inverter Cumnt Mu&/ 4.2.2 Maximum Short-Cimdt Current

Consider the time interval t, , 5 t 5 tnml . The PMOS transistor operates in its linear

region until time r,, , when it enters saturation. The NMOS device remains sanirated over

the entire time interval,

- Step 1:

Assume i, = O , i.e. neglect the short-circuit current. Furthemore, since t,, occurs at the

early stage of the falling output voltage and V,, = v, , the approximation

1 + A,, V,, = 1 + knV,, is used in the NMOS drain current equation.

The first-order differential equation (3.8). with in expressed in tems of its terminal

voltages using equations (2.2 1 )-(2.24) and with initial condition v,( tn )

solved to get an approximation for the output voltage wavefom during

t r i l l t l t n n t l :

= Von, , is now

the time interval

where cp,, = 1 w e n - 1 Bn (nn + I ) sr ( 1 + h , V , D ) .

C L + c,, Lm

If, in equation (4.6). v,(tP,) > V D D - 1 Vrpl , then the PMOS device will turn off before

entering saturation. In this case, t,, = t,, is used and the following steps are skipped.

The output voltage when the PMOS device changes its mode of operation is given by

Therefore, equations (4.7) and (4.6) can be combined at t = t,, and the resulting equation

can be solved for t , , using the bisection or the Newton-Raphson method

Since the short-circuit current was neglected in this analysis, the computed value, denoted

7, . is on1 y an approximation for t , , . The corresponding output voltage, v,!?,) = Y,, , is

calculated from equation (4.6).

Chapter 4 lnverter Cunent Mode/ 4.2.2 Maximum ShortlCircult Cumnt

Step 2: -

V,, would correspond to the output voltage at t = t , if the entire current in was available

to discharge the load capacitance (i.e. if i, = O). However, because the PMOS transistor

is on dunng the time interval t , , S r < tPo , the discharging path through the NMOS device

is also shared by the charge leaking from the power supply. Consequently, the effective

current available to discharge the load is only i, - i , . Therefore, for the output voltage to

actually drop to Vo, , the output node must be discharged by

where r, is the actual time required for the output voltage to drop to V,, .

Hence, defining

and

i t follows from equation (4.8) that

Here, Q,, represents the amount of charge which leaked from the power supply through

the short-circuiting PMOS transistor during the time interval t , , 5 t 52, . To compensate

for Q,, , the output node must be discharged by a net additional charge, QUdd, during the

time interval 7,s t i t , , thereby allowing the output voltage to actually drop to Vo,, .

Equation (4.1 1) will be used later to compute t , .

To compute Q,, and Q,, , one can represent the drain currents i , ( t ) and i , ,(t) by

piecewise linear functions of time, as shown in Figure 4.1.

Chaptcr 4 Inverter Current Modsl 4.2.2 Maximum Short-Circuit Current

Figure 4.1 Piecewise linear approximations of the discharging current in (-1 and the

short-circuit current ip (-1, used in step 2 of the derivation of the maximum short-circuit

current for a discharging inverter (rising input).

The minimum value, I,,, , of the short-circuit current was computed in Section 4.2.1. - -

The current values at t = 7 , . i , ( t y ) = 7~, and iP(7,) = I p y , are calculated from the NMOS

and PMOS drain current equations in (2.21)-(2.24) based on their respective terminal

voltages, with the approximation v,(;,) = V,, . For t 2 ?, , the drain currents are descnbed -

by linear functions of time with rates of change equal to those at t = t , :

Expressions for the derivatives in the above equations can be obtained by differentiating

the NMOS and PMOS drain current equations in (2.2 1)-(2.24). These derivatives are then

Chapter 4 lnverter Cuncnt Mode1 4.2.2 Maximum Short-Circuit Cunent

- d evaluated by substituting, in the derived expressions, t = t , and - dlvOIr = i ' which

Y computed using equation (3.8).

Consequently, defining

d Adi -(in - i p ) d t

and using Figure 4.1, we can write:

- 1 Q ( , ~ ~ = ( t u - t y ) Ai + - ( t q - I,)' Adi

2

( 7 ~ q 1. I - I p m j n r y ) where r , = - I P ~ - I ~ m i n

Hence, equating Q,, and QUd results in

Note that in 1271, Embabi and Damodaran computed ?50, the approximate time

corresponding to v,, = VDD/2, using an expression derived by Sakurai and Newton in

[24]. Then, they considered a similar approach to ours to improve j so . However, in their

case, the output voltage, whose corresponding time 750 is to be improved, was preset to a

fixed value of VDD/2. Therefore. the times when the NMOS and PMOS transistors change

their mode of operation (Le. t,, and t , , ) must be first determined to be able to compute

Q,, . To find t,, and t,,,, the output voltage waveform was assumed to fall linearly from -

V,, at t = t n l to VDD/2 at t = t50. which is a relatively large voltage excursion.

As a result, the nonlinear behavior of the transistors was not accurately modeled.

Chepter 4 Inverter Current Mode1 4-22 Maximum Short-Circuit Cunsnt

In our case, on the other hand, a reference point in time, 7,, is to be improved.

Since 7, was derïved to correspond to t,, for the case of i, = O (Le. neglecting the

short-circuit current), it is by definition smaller than the actual t , , . Therefore, the

mode of operation of both devices over the entire time interval t 5 t 5 is known:

the NMOS is in saturation and the PMOS is in the linear region. Hence, Q,, can be

simply computed (as described above), regardless of how the output voltage is changing.

It is important to re-emphasize that our goal here is to develop a technique to compute

r , , , f,, , and the corresponding output voltages rapidly and accurately. Then, the simple

delay and power models presented in Chapter 3 can be used.

Step 3:

Now. [ t y , VDy] represents an actual point on the output voltage waveform very close to

the desired point [ t , , , V,,,] . Therefore, one can approximate the output voltage waveforrn

near t,, by a linear function of time through [t, , V,,] :

d where s, =- - is computed using equation (3.8). with the drain currents of both d r v " l r = Y

devices calculated from equations (2.21)-(2.24) based on their known terminal voltages.

Therefore, equations (4.7) and (4.19) can be combined at t = t,, and the resulting equation

can be solved for t , using the bisection or the Newton-Raphson method.

Consequently, an improved value of t, , . which takes into account the short-circuit current,

is determined. The corresponding output voltage, V,,, = v , ( t , , ) , is then calculated from

equation (4.19).

Finally, the maximum value, I,,,, . of the short-circuit current is computed using

the PMOS drain current equation in (2.2 1)-(2.24), with V = V - t and

VSD, = V D D - Vop/ .

Chapter 4 Inverter Cumnt M&I 4.2.3 Maximum Discharging Cumnt

4.2.3 Maximum Discharging Current

The discharging current, i n , reaches its maximum when the NMOS transistor leaves

saturation and enters the linear region (at t = t,, ), but not later than the time when VGsn

attains its maximum value of VDD (at t = Tr ).

Let t , , be the time when the discharging current reaches its maximum.

Define r , , , = rnin(f,,, t,,) and t,,, = min(t,,, T , ) . Then, t,, m u t occur within one of

the following 2 time intervals:

Time interval 1 : t,,/ S t 5 tnIrl1

Both the PMOS and NMOS devices are operating in the saturation region.

Now. for t < t , , . V,, = v , ( t ) is larger than VsDp = V D D - V D , because v , ( t ) is a

falling signal and v , ( t , , ) is close to VDD/2. Thus, a possible simplifying assumption,

to be used in the drain current equations for the NMOS and PMOS devices, is:

1 +X,,V,,,= 1 +L,V, , and I +hpVsDpz 1 .

The first-order differential equation (3.8), with in and i, expressed in terms of their

terminal voltages using (2.21)-(2.24) and with initial condition v, ( t , , ) = V,,,, is now

solved to get an expression for the output voltage wavefonn during the time interval

t P [ 5 f s ~ n t d :

where cp,, = 1 W e n - 1 Bn ( n , + i ) sr ( l + x n v D ~ ) CL + C m Le,

Chapter 4 Inverter Cumnt Moâel 4.2.3 Maximum Discharging Current

The output voltage when the NMOS device changes its mode of operation is given by

Therefore, equations (4.21) and (4.20) can be combined at t = t,, and the resulting

equation can be solved for t,, , using the bisection orthe Newton-Raphson method.

If t,#, 5 t,, , then r ,,, = r,, . Othenvise, time interval 2 must be used to compute t,, .

Time interval 2: t,, 5 1 5 t,,?

The PMOS transistor tums off (i.e. i , = O ) while the NMOS device is still saturated.

The first-order differential equation (3.8), with in expressed in terms of its terminai

voltages using (2.2 1 )-(2.24) and with the initial condition v, ( tPo) calculated from equation

(4.20), is solved to get an expression for the output voltage waveform dunng the time

Therefore, equations (4.21) and (4.22) can be combined at t = t,, and the resulting

equation can be solved for t,, , using the bisection or the Newton-Raphson method.

If t,!, 5 T , , then t,, = t,,. Otherwise, t,, = 7,.

Consequently, Von, = v,(t,,) is calculated from equation (4.20) if r,, l t,, ,

and from equation (4.22) otherwise. The maximum value, I,v,,u,, of the discharging current

is cornputed using the NMOS drain current equation in (2.21)-(2.24), with VGSn = srtnm

and V ~ ~ t i = V ~ , r m -

Chapter 4 Invarter Cumnt Mode1 4.3.1 Pe8k Potwr-Suppfy Cunsnt

4.3 Charging Inverter (Falling Input)

The analysis for the case of a charging inverter (falling input) is symmetrical. In fact, the

theory and equations presented in Chapters 3 and 4 for the case of a discharging inverter

(rising input) will correspond to a charging inverter if the following interchanges are made:

TERMS: discharging t) charging

NMOS t) PMOS

rising t) falling

SUBSCRIFTS:

VOLTAGES:

4.3.1 Peak Power-Supply Current

Consider the CMOS inverter circuit in Figure 3.1 (a). The power-supply current is given by

where ce = C~ + + + Cloud '

Thus, the supply current is dominated by the PMOS drain current, i,. Therefore, it is

reasonable to assume that the absolute peak value of the supply current occurs in the case

of a charging inverter (falling input), when the charging current, i,, reaches its maximum.

Chapter 4 Inverter Current Mo&/ 4.3.1 Peak Povinr-Supply Cumnt

Let t,, be the time when the charging current reaches its maximum, and define

V,,, = v,,(t,,) . The values of t,, and V,,,, are computed using the inverter current

model. Assuming the input voltage wavefom to be a falling ramp with transition time Tf ,

the peak value of the supply current is then given by

The drain currents of the NMOS and PMOS devices at t = t,, are calculated from the

MOSFET equations (2.2 1)-(2.22), based on the their known terminal voltages. The values

of the parasitic capacitances are computed as described in Section 3.6.

Results and Conclusion

The proposed model, imptemented in MATLAB, has been tested with a wide range of

inverters designed in the 5V 0.8pm BiCMOS technology of NORTEL'S BATMOS

process. Various switching conditions of input transition time and capacitive load were

considered. To validate the model, the delay, peak supply current, and power dissipation

computed using the model are compared with the 'exact' values obtained by simulating the

analyzed circuits in ELDO simulator 1401 using NORTEL's MISNAN MOSFET mode1

[ml.

When describing the CMOS inverter circuits, Ti and CI,,d refer to, respectively, the

input transition time and the loading capacitance, while W , and W p are, respectively, the

channel widths of the NMOS and PMOS devices.

5.1 Results

5.1.1 Delay

In Figure 5.1, the delays computed using the analytical model are compared with those

produced by ELDO for a minimum size inverter (W, = W p = 1.4pm). In this

comparison, the delays for Cload = 15 + 1 0 fF are displayed with Ti as a parameter.

Then, to verify the validity of the model over a wide range of inverter sizes, the delays in

the case of a very large inverter (W, = W,, = 20pm) are compared in Figure 5.2 for

Cf,,d = 0.4 + 2 pF.

Chapter 5 Results and Conclusion

Ckuglng 1n-w r i ïh W n r W p l . 4 ~ ~ 1 : Oo4my (ns) v u C l o d (W) for TThO.Snm. Zn* i I

O 1 O 2 0 30 40 60 UI 7 0 80 BO 100

Loading capacitance, Clo,d [El

Dlichmrglnq Invrrtw wiîh WnrWprl Aum: D m I q (ns) v u C l d (W) for T-Snm. 2ns

I

Loading capacitance, Cload lfFl

- : ELDO simulation

Figure 5.1 Delay plot versus loading capacitance with input transition time, Ti, as a

parameter. A minimum size CMOS inverter (W, = Wp = 1.4p.m) is used.

Chapter 5 Results and Conclusion

0 1 1 0 2 0.4 0.6 0.8 1 1 2 1.4 1.1 1.8 2

Loading capacitance, Cload lpFl

- 0.2 0.4 0.6 o.. 1 t 2 1.4 1 .a 1 .m 2

Loading capacitance, Cload [PFI

- : ELDO simulation : Analytical mode1

Figure 5.2 Delay plot versus loading capacitance with input transition time, Ti, as a

parameter. A very large CMOS inverter (W, = Wp = 20p) is used.

Chapter 5 Results and Conclusion 5.1.1 Delay

Input transition time, Ti b e c 1

- : ELDO simulation

mrglng ïnwœir whk W&um, ChlpF: LM- (m) ws. T i (nr) fw W p d S W n . Wn. ZWn

1 Cload = lpF

0 3 1 1.6 2 26 3 1.S 4 4.S S

Input transition time, Ti [nsecl

Figure 5.3 Delay plot versus input transition time for several ratios of transistor sizes,

W P n . A CMOS inverter OK, = 4pm) driving a loading capacitance of (a) Cload = 0.2pF and

(b) Cload = 1pF is used.

Chapter 5 Results and Conclusion S. 1 .2 W k Pbwr-Supply Cunsnt

Furthermore, to demonstrate the accuracy of the mode1 over more possible switching

conditions, Ti is varied over the range 0.5 + 5 nsec and the corresponding delay is plotted

in Figure 5.3 for several values of W , / W, . Results frorn ELDO simulations are also given

for cornparison. For completeness, the test is performed, using a medium size inverter with

W , = 4 Pm, twice: first in the case of low fanout (Cloud = 0.2 pF in Figure 5.3(a)) and

then for a high fanout case (ClOad = 1 pF in Figure 5.3(b)).

The maximum error in the delay, computed using the analytical model, is less than

8% compared to ELDO simulation results for the broad range of transistor sizes, input

transition time, and capacitive load studied.

5.1.2 Peak Power-Supply Current

In Figure 5.4(a), the input transition time, Ti, is varied over the range 0.25 -t 4 nsec and

the corresponding peak supply current is plotted for several values of W , / W , . Results

from ELDO simulations are also given for comparison. The peak value of the supply

current is found to decrease with slower input transitions. Note how, in Figure 5.4(a), the

peak supply currents computed using the proposed model follow precisely the nonlinear

change (with input transition time) of the exact peak-supply-current curves produced by

ELDO.

To verify the validity of the model over various loading conditions, the peak supply

current for Cload = 0.25 + 3 pF is displayed in Figure 5.4(b) for several values of

W,/ W , l . Since the peak supply current is largest for fast input transitions, the test was

perfonned for Ti = 0.5 ns. ELDO simulation results are also plotted for comparison.

Furthermore, Table 5.1 compares the peak supply current, its time of occurrence, and

the corresponding output voltage computed using the analytical model with those produced

by ELDO. Results, given for different inverter sizes and under various conditions of input

transition time and loading capacitance, show an excellent agreement between these two.

Chapter 5 Results and Conclusion 5.1-2 Peak Powur-Supply Curren t

Inwwtu with WralOum. Cl-: Po& Cu- (mA) v r Ti (nr) for WprQ.SWn. Wn. ZWn

1

Input transition time, Ti Insecl

(a)

1nvmrî.r wlth WnalOum. TLO.Snr: Pmak S-îy C-nt (mA) vm. CI (pF) for Wpt0.SWn. Wn. 2Wn 1

I

0.5 1 0.5 1 1 .S 2 2 6 3

Loading capacitance, Cload [pF]

- : ELDO simulation : Analyticd mode1

Figure 5.4 Plot of the peak power-supply current versus: (a) input transition time Ti

(for Cload = 0.44pF) and (b) loading capacitance Cload (at Ti = 0.5nsec) for several ratios of

transistor sizes, W&. A CMOS inverter with W, = l O p m is used.

Chapter 5 Results and Conclusion 5.1.2 Pbak Pbrnsr-Supply C~nisnt

Over the wide range of transistor sizes, input transition time, and capacitive load is

considered, the maximum errors observed are 4% for the peak supply current and its time

of occurrence, and 6% for the corresponding output voltage.

Peak Supply Current Time Output Voltage

Table 5.1 Peak power-supply current, its time of occurrence, and the corresponding output

voltage. The results computed using the proposed analytical mode1 are compared with ELDO

simulation results for different CMOS inverters (with transistor widths W, and Wp), under

Wn

/.lm)

8

16

8

16

various conditions of input transition tirne, Ti, and loading capacitance, Cload.

Wp

(pn)

8 1

16

16

32

8

16

16

32

'load

(fF)

125

500

125

500

350

750

350

750

125

500

125 . 500

350

750

350

750

Analytical Model

1.16

1.48

1.75

2.75

2.57

2.91

3.89

5 .O2

0.99

1.37

1.48

2.13

2.13

2.58

3.19

3.91

ELDO Simulator

1.18

1.47

1.80

2.75

2.62

2.92

4.02

5.18

0.95

1.37

1.44

2.20

2.09

2.60

3.17

4.00

Analytical Model

0.93

1.00

0.81

1-00

0.98

1.00

0.84

O -96

ELDO Simulator

0.96

1.00

0.82

1.00

1.00

1.00

0.86

1 .O0

Analytical Model

2.20

0.87

2.56

1.74

2.06

1.13

2.45

2.12

2.39

1.71

2.70

ELDO Simulator

2.35

0.86

2.58

1.72

2.09

1.12

2.53

2.19

2.42

1.66

2.70

1.72

2 .O0

1.48

1.76

1.76

1.95

1.52

1.68

1.66

2.00

1.44

1.83

1.75

2.00

1.51

1.72

2.33 1 2.48

2.32 2.40

2.07

2 -66

2.46

2.12

2 -66

2.54

Chapter 5 Resuits and Conclusion

5.1.3 Power Dissipation

Table 5.2 compares the energy dissipations per switching event computed using the

inverter model with those obtained through ELDO simulations. Both the short-circuit

energy, E,, , and the total dynamic energy, E , are given. Inverters of different sizes were

tested under diverse switching conditions of input transition time and capacitive load.

Table 5.2

Short-Circuit Energy

Esc

Clozid (Pr)

(tFi / haiyticai 1 ELDO Model Simulator

Total Dynamic Energy 1 E

($1 Es, % E m r

% - in

Andytical ELDO E E

Mode1 Simulator

Short-circuit energy dissipation and total dynamic energy dissipation per

switching event. The results computed using the proposed analytical model are compared

with ELDO simulation results for different CMOS inverters (with transistor widths W, and

Wp), under various conditions of input transition tixne, Ti, and loading capacitance, Cload.

Chapter 5 Results and Concluiion 51.4 CPU Tïm

The maximum error in E, calculated using the analytical model, is 5%, while the

corresponding ratio of E J E is 38.8%. Therefore, in addition to proving the validity of

the rnodel, this confirrns that the short-circuit power dissipation can no longer be neglected

in submicron CMOS circuits.

Note that both Es, and (E - Es,) increase with increasing channei widths, W.

Es, increases because of an increase in the drain currents with W, while (E - Es,)

increases due to an increase in the drain capacitances. However, only ( E - Es,) increases

with C,,,,. Es, actually decreases with increasing Clond because the load current.

dv, /dr , is increased. Hence, the short-circuit current (which is the difference of the

charginddischarging current and the load current) is decreased.

5.1.4 CPU Time

When analyzing a CMOS circuit, the main advantage in using the proposed model rather

than a circuit simulator, such as ELDO or HSPICE, is speed. For a given inverter

configuration and input transition tirne, the CPU time required to simulate that circuit using

ELDO or HSPICE ir primarily dependent on the time step used and the duration of the

transient analysis (or stop time). To determine a reasonable estimate of the speedup

achieved by the proposed inverter model over ELDO, these two contributing factors were

selected as follows:

1 ) the tirne step was set to the minimum step needed to capture the delay and the

time of the peak supply current to the nearest 0.01 nsec.

2 ) the stop time was defined as the time when the output voltage waveforrn is

within 0.03 VDD of its final value. This roughly corresponds to the shortest

duration of the transient analysis, which still permits the evaluation of the

supply energy dissipation to within 5%.

Several inverters of different sizings and loads were simulated using ELDO for

various input transition times. In each case, an initial simulation was carried out to

Chapter 5 Results and Conclusion 5.2 Modsl Limitation8

determine the corresponding stop time. Then, the simulator was re-run several times to find

the average CPU time required to simulate the inverter circuit. Results show that the

inverter model, run in MATL.AB, offers about two orders of magnitude improvements in

CPU time over ELDO.

5.2 Mode1 Limitations

The errors in the delay, peak supply current. and power dissipation may exceed the

expected values. This will only occur in the following cases:

1 ) vety low fanouts. In this case, the effective inverter load is dominated by the

drain parasitic capacitances of the MOSFETS in the inverter itself. Hence, the

errors in replacing these noniinear voltage-dependent capacitances by constant

ones (as described in Section 3.6) become more apparent.

2) very slow input transitions. In this case, the charging/discharging transistor

operates at low VGS values for a dominant portion of the time spent before the

output reaches its final value. In these near-threshold regions, the n-th power

law MOSFET model fails to reproduce the 1-V characteristics of the MOSFET

accurately (as described in Section 2.5), hence the errors are large.

It is very important to emphasize that the terms 'slow' input transition and 'low' fanout are

relative: a voltage transition at the input of a given inverter may no longer be considered as

'slow' if the fanout is increased, and vice-versa.

However, the results, presented above, demonstrate the accuracy of the proposed

analytical model for fanouts lower than 3 and for input transition times as large as Snsec.

At the sarne tirne, the characteristic waveformt of the technology used has a transition time

of less than O.Snsec. Hence, the validity of the model.

--

t The chancicristic waveform is defined as the dcfinite wavefonn towards which the voltage waveforrn converges

in a suies of identicaI invcncrs.

Chapter 5 Results and Conclusion 5.3 Conclusion

5.3 Conclusion

In an attempt to satisfy the growing need for efficient techniques to estimate rapidly, yet

accuntely, the delay, power, and maximum currents in digital ICs, an analytical model for

the submicron CMOS inverter was developed.

A modified version of the n-th power law MOSFET model [25] was also proposed

and used to relate the terminal voltages to the drain current in submicron transistors.

In order for the MOSFET mode1 to most accurately describe the electrical characteristics

of the transistors over the full range of device dimensions used in circuit design, the model

parameters were optimized, following an algorithm developed for that purpose.

This is a simple one-time process that allows the full characterization of a given MOS

processing technology.

The proposed inverter model, implemented in MATLAB, was tested with a wide

range of inverters under various conditions of input transition time and capacitive load.

It predicted the delay, peak supply current, and power dissipation to within a few percent

of ELDO simulation results, white offering about two orders of magnitude gains in CPU

time over ELDO simulator. Hence, its use in CAD tools supporting low power design

is justified.

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