INFN sez. di Torino

INFN sez. di Torino

CMOS process example

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Main steps

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� FEOL ( Front End Of the Line )� up to the transistor creation

� BEOL ( Back End Of the Line )� metalization

The two steps correspond to different design teams and are treated separately

Problem� Substrate is either p doped or n doped� PMOS requires n doped substrate� NMOS requires p doped substrate

� Is it possible to have both PMOS and NMOS on the same substrate ?

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Solution : well ( or tub )A n-doped ( p-doped ) region is implanted on a p-doped ( n-doped ) substrate.CMOS process : Complementary MOS process

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Considerations

� Well and substrate creates a p-n junction� Reduced mobility in the well� P-well vs. n-well� Source-bulk connection� Twin well and pseudo twin well processes� Triple well

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Well implantation - 1

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Field implant - 1

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Field implant - 2

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Field implant - 3

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LOCOS - 1

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LOCOS - 2

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LOCOS - 3

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LOCOS - 4

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LOCOS - 5

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Parasitic MOS - 1

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Parasitic MOS - 2

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Bird�s beak

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Poly Buffered LOCOS (PBL)� For tighter geometries, the pad oxide thickness is reduced by using the following stack: Polysilicon 50 nm/oxide 5-10 nm/nitride 100-240 nm. This allows the bird 's beak to be reduced to 0.2 micron. � The sequence is the same as for LOCOS except that there are added steps to remove the polysilicon layer underneath the nitride.� The nitride layer is removed using a wet bench and acid bath whereas the polysilicon is removed using dry etching in a chlorine based plasma.

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Deep trench isolation - 1

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Plasma-Enhanced TetraEthylOrthoSilicate


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Isolation Technologies

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Gate formation - 1

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Gate formation - 2

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LDD Implant - 1

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LDD Implant - 2

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LDD Implant - 3

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Spacer

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NMOS S/D implant

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PMOS S/D implant

Silicide formation

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PMD deposition - 1

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PMD deposition - 2

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PMD deposition - 3

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Contact formation - 1

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Contact formation - 2

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W fill - 1

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W fill - 2

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First metal layer - 1

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Inter-metal dielectric - 1

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Inter-metal dielectric - 2

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Via etch

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W fill - 1

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W fill - 2

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Second metal layer

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Final cross section

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Damascene process

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BiCMOS technology

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Bipolar transistors� Requires epitaxial process ( buried layer to

decrease collector resistance )� Good npn vertical transistor� Bad pnp lateral transistor� Good pnp vertical transistor with grounded

collector

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SiGe - 1

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SiGe - 2

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Latch-up - 1

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Latch-up - 4

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To prevent latch-up :

� Substrate contacts to lower RS and R

W� Increase distance between nMOS and nWell� Shallow Trench Insulation� SOI technologies

SOI process

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SOI techniques

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� Wafer bonding and etch back� Silicon on sapphire/zirconia (Zr

2O)

� Recrystallization from the melt� Selective epitaxy over holes in the oxide (ELO)� Porous silicon (FIPOX)� Oxygen implantation (SIMOX)� Silicon-On-Nothing (SON)

SOI structure

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Parasitic capacitance

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Tolerance to SEU

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3-D ICs

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µChannel cooling

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