INFN interests to RD53 IP-BLOCK

L.Demaria - INFN IP-Block for RD53 - 18-dec-2013

INFN interests to RD53 IP-BLOCKLino DemariaOn behalf of Bari, (Milano), Padova, Pavia, (Perugia), Pisa, Torino


Introduction

All the Italian groups in RD53 have their activity funded by the approved INFN project CHIPIX65. On top of RD53 we will be reviewed closely by INFN for the work we do and the results we obtain.

We decided to present to RD53 the interest of all the groups collectively. Few items find the interest of more groups, and there are area where one groups will be leading and other might help or give support. In general we will share the commitment of the work needed for all the IP-block of which INFN will take responsibility.

This will further enhance the probability of a successful result.

PS: as specified by Jorgen in his e-mail, the IP-block relative to WG-Analog are not discussed here.


Summary of main INFN interests

Main Interests of INFN groups on 15 out of 36 IP-blocks 1. Band Gap Reference (Pv)2. 8-12 bit programmable biasing DAC (Ba)3. 4-8 bit compact DAC for threshold adjust per pixel (To,Pv,Ba)*4. 10-12 bit slow ADC for monitoring (Ba)5. Low power Clock driver and clock receivers for pixel matrix (Pv)6. PLL (Pd, Pi, To)7. Voltage Control Oscillator (for time stamping) (Pd,Pi,

To)*8. Low / High speed SLVS driver (Pv,Pi, To)9. High speed serializer for readout (Pi)10.SRAM (for data storage either in pixel regions / EOC) (Mi)10.DICE storage cell (Mi)14.Standardized control and command interface (I2C, E-link) (Ba,Pi)15.Standardized readout interface (Ba,Pi)16.LDO (To,Pi)


Other potential INFN interests Potential additional interest (6 out of 36) – depending also on

how we decide to share the work in RD53:

1. Temperature / Radiation sensor (Pv, To)3. Clock recovery and jitter filtering (Pi)4. Programmable delay for sampling clock alignment (Pi)5. SLVS receiver (Pi)


Few commentsThe list of IP-block provided is a very good starting

point but it might need some clarification, some blocks are ‘bigger’ than others:

For example: VCO

needed inside the PLL – we assume is included there, right?

a VCO for fine-time stamping should be highly customized inside the Pixel

Serializer It needs a PLL (therefore also a VCO) There should be a good connection with who designs

the PLL (or there might be some double-counting)


Typical PLL Typical serializer


Slides on Single Items


Band Gap reference (Pv)State of the art at Pv:

Sub 1V operation bandgap voltage reference – 3 versions BJT version Diode version MOS WI version

Layouts ready for the submission Evaluate their performance and study their radiation hardness

MOS in WIDiodesBJT


8-12 bit programmable biasing DAC (Ba)

Previous experience of Bari: Rad-hard 8-bit DAC for the slow control of the pixel chip of ALICE (250 nm CMOS)

In progress: VFAT3, a new FE chip for GEM detectors for the upgrade of CMS muon detector (130 nm CMOS). Submission on Feb. 2014

Calibration & Bias circuitry, 8-bit thermometer coded current steering DAC, Constant Fraction Discriminator

I0 I0 I0 I0 I0

Iout

S0 S1 S2 S3 S254

Thermometer coded DAC: 255 “identical” unit current sources connected to output node through switches controlled by a binary-to-thermometer decoder• monotonicity is guaranteed• matching conditions more relaxed common centroid is not required

140 m

170

m


4-8 bit compact DAC for threshold adjust per pixel

In our opinion should be strongly integrated in the VFE and therefore the design is highly customized. It will be followed by Pv, To that are strongly involved in the VFE

Bari could help

10-12 bit slow ADC for monitoring (Ba)

Reference generator: resistor ladder (same as full flash ADC)“Coarse” (MSBs) conversion phase: the “coarse” refs Vrc are compared with Vin and the “fine” refs Vrf are selected“Fine” (LSBs) conversion phase: the selected Vrf’s are compared with Vin.

Previous experience of Bari: Two-step 8-bit ADC with max. conversion speed: 20 MS/s (0.35 m CMOS)

Correction logic for both “bubble” errors and wrong “fine” threshold selection

Boost circuits for the clock phases applied to the CMOS switches

Final ADC structure: two ADCs, operated in “interleaved” mode

Total power consumption: 22.4mW Maximum conversion speed 20MS/s

Test chip (2.18 x 1.74

mm2)



PLL and VCO design expertise (Pd, Pi, To) Padova group (University of Padova – Engineering department)

Research group expertise: RF design, Baseband design, Testing and characterization Radiation testing and qualification (Engineering department)

Design of a 6.5-18.4 GHz PLL in 65nm CMOS for the local oscillator (LO) generation in a short-range radar front-end (M. Caruso et al., proceedings of ESSCIRC 2013)

Design of a 13-15 GHz, LC tank VCO for the local oscillator (LO) signal of a GSM transceiver in 65nm CMOS (S. dal Toso et al., IEEE Journal of Solid-StateCircuits, 2010)

Design of an LC tank VCO in 90nm CMOS for a fast-hopping LO generator operating between 6 and 9 GHz based on sub-harmonic injection locking (S. dal Toso et al., IEEE Int. Solid-State Circ. Conf., 2008)

Pisa has expertise (see later) Torino interested too


VCO for fine-time stamping

In our opinion should be strongly integrated in the VFE and therefore the design is highly customized. Interest of To to find solution for fine time-stamping in the VFE (as simple VCO)

Pd, Pi could help


Low-Medium (High?) speed SLVS driver (Pv, To, Pi)

• PAVIA Design of low-voltage differential signaling driver + receiver with supply voltage of 1.2V (with only core

transistors) Present activity:

Design 1: 320MHz frequency operation with maximum power consumption=1.25 mW Design 2: 640MHz frequency operation with maximum power consumption=2.5 mW

Schematics of the TX and RX were obtained by a merging of the UniBG and CERN version (in 130nm IBM) provided by Kostas

• TorinoThere are design in 130nm for Panda that goes to 1 GHz and could be translated in 65nm

• Pisa is also interested


Serializer (Pi)Pisa

Based on experience on two ASICS designed in the IBM 130nm (2012-2013) Collaboration between INFN-PISA (Guido Magazzu) and UCSB (Physics Department and Electronic Engineering Department): Developments of radiation tolerant IP-cores for high speed serial links : UCCF1 (submitted 2012) UCCF2 (submission in early 2014)

Rescaling of the IP-cores into the TSMC 65nm technology since February 2014 (submission of the first test ASIC foreseen in fall 2014)


UCFF1 – (Pisa)

High Speed (1 GHz) Serializer (SER) and Deserializer (DES) modules Based on Standard Cells Triple Modular Redundancy (TMR) to protect against Single Event Effects (SEEs)

VCO (Center Frequency = GHz) controlled by a Radiation Tolerant Thermometric Controller (THC)


UCFF2 (1)

PLL and Clock Data Recovery (CDR) with Triple Modular Redundancy (TMR) to protect against Single Event Effects (SEEs)

Same Serializer (SER) and Deserializer (DES) modules used in UCFF1


UCFF2 (2)

Clock Data Recovery PLL with with x25 frequency multiplication (input frequency = 40MHz => output frequency = 1GHz)

Voltage Controlled Oscillator (VCO) => It generates the 1 GHz clock for the Serializer Charge Pump (CP) => It provides the control voltage to the VCO module Frequency Divider (1/25) => It generates the local reference clock Phase/Frequency Detector (PFD) => It compares the frequency and the phase of the input reference clock and of

the local reference clock and it generates the control signals for the Charge Pump VCO modules (3x) => Same power supply and control voltages used in the PLL Low Drop-Out (LDO) regulator (providing power supply voltage to all the VCO modules)


DICE RAM Cell (Mi) Interest of Milano (in CHIPIX65, applying for RD53) to develop radiation

hard SRAM array of 256x256 DICE RAM cells almost ready for integration. It

comes from a work done in AIDA. Size of about 1.8x3.3 um2

This could be used either in the PUC or in the EOC

Schematics Layout V.1


Low power Clock driver and clock receivers for pixel (Pv) Low-power architectures are required to meet the power budget

constraint foreseen for the pixel matrix We studied different techniques for distributing clock signal to the

pixels If a reduced voltage supply (lower than 1.2V) is not available, we

simulated drivers able to reduce the clock swing to a predetermined value It is desirable to reduce the swing as much as possible in order to

reduce the power consumption -> although the recovery of the signals becomes increasingly difficult as the swing is reduced

We evaluated each architecture with the following parameters: Total Power Consumption (TXs + RXs) Skew

and compared the results with the performance of a conventional full swing buffer


Standardized control and command interface (I2C, E-link) Bari, Pisa

Slow control block that will be used in the VFAT3 chip Only one E-port connection for data reading – trigger –

Slow Control Commands and responses data are multiplexed in the

main bit-stream HDLC is used as transport protocol IPBus protocol V1.4 is used for generic command encoding

E-Port

DataController

Trigger/Data

RX MEM

TX MEM

IPbustransactor

Wishbone busConfiguration registers

Calibration

GDSP status

GDSP RAM

HDLCController


Standardized readout interface (E-link)Bari , Pisa interested

INFN interests to RD53 IP-BLOCK

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