INF4420Introduction

Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no)Spring 2012

OutlinePractical information about the course. Context (placing what we will learn in a larger context) Outline of the curriculum.

Lectures Jørgen Andreas MichaelsenRoom: 5405, Phone: 22840840Email: jorgenam@ifi.uio.no Lectures on mondays in OJD 2453, Perl

Problem solving class Kin Keung Lee (Kody)Room: 5122, Phone: 22840136Email: kklee@ifi.uio.no Assignments for each week (not mandatory)Fridays in OJD 2465, Prolog

Labs Weekly labs to learn design tools Details are not yet available ...

WebpageCourse webpage:http://www.uio.no/studier/emner/matnat/ifi/INF4420/v12/

important mesages will be posted on the course webpage. Slides for the lectures and assigments for the problem solving class are posted.

Teaching and examinationLectures (2-3 hours)Problem solving class (2 hours)Lab exercises (2 hours) 4 hour written exam (60 %)Project (design, layout, 40 %)

Course contentFrom the course webpage: "The course provides the know-how and skills needed to design analogue and mixed-signal integrated circuit modules using modern program tools. The main focus of the course is complex systems such as data converters (A/D, D/A) and phase-locked loops (PLL). An introduction is given to CMOS technology and methods in order to implement passive components such as transistors, condensers and coils. In addition, matching, optimisation and noise deflection are all key aspects. The execution of project tasks will be a central part of the teaching."

Learning outcomesFrom the course webpage: "Students will have the skills needed to design an integrated mixed-signal circuit in CMOS using modern design tools."

Student reference group1 or 2 students

What is expected of you?Basic understanding of analog CMOS (INF3410). We will build on this for most of the circuits and systems we discuss. Linear circuits (transfer functions, Laplace). Important to ask questions.

Integrated circuitsIntegrated circuits are found everywhere in our daily lives. Cost is a driver. Reduced feature size, smaller dies, CPF decreases, more features on the same die (SoC). Larger wafers. Reduced feature size also helps performance. Is scaling good for analog?

Mixed-signal in DSMDigital content dominate. Process development is geared towards reducing cost-per-function (CPF). Analog and RF functions have to keep up (cost benefits of placing all functions on one die)

Mixed-signal circuits

Analog + Digital? Time/Value Discrete Continuous

Discrete Digital ?Continuous ? Analog

What are mixed-signal circuits?

Why mixed-signal circuits?Digital circuits are more robust and can be designed more systematically. Usually, most of the system and signal processing will be digital content. We need circuits for regulating supply voltage, clocking digital circuits, interfacing with the (analog) world (filtering and converting to/from digital), communication circuits.

Uses of mixed-signal Analog and mixed-signal circuits are prevalent even in "digital" systems ● clocking and timing circuits● digital i/o (high speed bus)● supply voltage regulation● wireless communication● sensor interfacing● ...

Mixed-signal in DSMNew ideas and different designs are needed to keep up with new process technology, and new trends (e.g. portable applications). Important to have a good understanding of analog and mixed-signal circuits. Know what the limitations are and what can be improved. DALLAS, Aug. 23 /PRNewswire/ -- Texas Instruments Incorporated (TI) (NYSE: TXN) today introduced a dual-channel, single-lane serial-ATA (SATA) redriver and signal conditioner, featuring the lowest active power and lowest automatic low-power (ALP) mode of any 6-Gbps redriver/equalizers available today. The SN75LVCP601 has a maximum active power consumption of 290 mW, or approximately 50 percent less than the nearest competitor, extending critical battery life in portable electronics, such as notebook PCs. ...

Design flowTop-down designSpecification + different levels of abstractionMeeting specs accross PVT with min powerUsually, big savings are in the architecture

Levels of abstractionSystem level (block diagrams, MATLAB)Schematics (SPICE)Layout (CAD, DRC, ERC, LVS)

Curriculum

http://www.springerlink.com/content/l30184/#section=342950&page=1

Reference circuitsEvery analog and mixed signal circuit needs biasing and/or a reference independent of PVT.

Layout and mismatchDrawing layout needs careful attention in order to get predictable results.Ensuring drawn layout is manufactureable (DRC).Ensuring drawn layout is coherent with schematics (LVS, post layout simulation, but this does not reveal every problem, assumptions made by schematics)Ensuring drawn layout is robust against manufacturing imperfections.

Switched capacitorVery important technique for analog signal processing. Discrete time, continuous value.

Data convertersConverting between analog and digital representations of the signal. General data converter considerationsDifferent architectures suited to different specifications (speed, resolution).Oversampling and noise shaping

Oscillators and PLLsClock and data recovery (from serial data)Clock generation (from external crystal reference)Demodulation (e.g. frequency modulated signals)

ProjectCounts 40 % towards the final gradeFinal report is very important Last year: SAR ADCThis year: Bandgap + Current steering DAC Work in groups of twoKody will follow up on the projectMore details to follow

Design toolsHands on with high quality IC design tools in the labs and for completing the project. Virtuoso IC6.1.4 (Cadence)Virtuoso Spectre 7.2.0 (Cadence)Calibre 2010.3 (Mentor Graphics)

Process design kit (PDK)TSMC 90 nm MS/RF LP 1.2 V with 2.5 V I/Ohttp://www.europractice-ic.com/technologies_TSMC.php?tech_id=90nm

Provides simulation modelsPCells for generating component layoutRule decks for DRC, ERC, and LVS

Final exam7. June, 14:30, 4 hours written examCounts 60 % towards the final grade.

Schedule

ReferencesIn addition to the curriculum, these references have been consulted when preparing the lectures.CMOS: Circuit design, Layout, and Simulation (Baker, IEEE Press).Analog Design Essentials (Willy Sansen, Springer).IDESA (www.idesa-training.org/About.html)Analog Integrated Circuit Design (Johns and Martin, Wiley).

Next lecture 23. January Reference circuits ("Bandgaps")

INF4420Reference circuits

Spring 2012 Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no)

OutlineReference circuits and bias circuits Uses of reference circuits and bias cicuits MOSFET based references Parasitic diode based references (bandgaps)

Reference circuits"Bandgaps". Why? Every analog and mixed-signal system needs a stable reference. The reference circuit presents some physical quantity (voltage, current, frequency, other?) Image courtesy of

Texas Instruments

Biasing an analog circuitAnalog circuits need a current source to set the operating point. Circuit performance very dependent on the biasing.

Data convertersBinary word input is dimensionless.Need to multiply the dimensionless input with a dimensioned (physical) reference.

Voltage supply regulation

Temperature behaviourPredictable behaviour across temperature● Constant● Proportional (PTAT) Additionally, insensitive to supply voltage and process variations (PVT).

A very simple referenceCareful layout gives good matchingbetween resistors● Temperature affects resistors

equally, good TC● Precisely defined Vref as ratio of

Vdd● Precise value of Vdd is not

known (bad)● Poor PSRR! (bad)

MOSFET-R referenceCan be used to generate a bias voltage or reference voltage. Better PSRR than the voltage divider.

MOSFET-R reference

MOSFET-R reference

Beta multiplier referenceDeriving Iref from IoutLess dependence on Vdd Can be used for biasing and reference

Beta multiplier reference

Beta multiplier reference

Beta multiplier referenceAs a voltage reference, take Vgs1 to be the reference voltage, Vref. We know the current, Iref. Use this to find Vgs1=Vref We must find the sensitivity of Vref to Vdd and T

Beta multiplier reference

BandgapsIt turns out, we can make references with less temperature dependence using bipolar transistors.

Temperature independence

Parasitic diode CTAT and PTATNeed elements with well defined temperature behaviour. We will use diode connected BJTs. CTAT from Vbe (biased with constant current) PTAT from "delta Vbe" (biased with ratioed current or emitter area), result is the thermal voltage, Vt

Bipolar transistor diodesCurrent sinked by the device is affected by temperature● Vt is the thermal

voltage (proportional to T), 26 mV @ RT

● Is is also a function of termperature

PTAT voltage

PTAT voltageTo find temperature behaviour, we take the derivative wrt. temperature (assume the first derivative is constant)

Delta Vbe is proportional to absolute temperature. Defined by two physical constants and emitter ratio, n.

PTAT voltage

CTAT voltageFor the full bandgap circuit, we need both PTAT and CTAT. Is exhibits temperature dependence. In the delta Vbe, Is is canceled. By looking at a single junction Vbe, we get a contribution from Is.dVbe/dT assuming constant current Ic. In this case, the overall TC is CTAT.

CTAT voltage

CTAT voltageSilicon bandgap energy as a function of temperature

CTAT voltage

Bandgap circuitsWe know how to generate PTAT and CTAT, and how we should combine these contributions for temperature independence (I.e. scale and add to acheive temperature independence). How do we make a circuit that realizes this system?

Bandgap circuits

Bandgap circuitsNeed a circuit that can sense V1 and V2 and adjust the current sources so that V1=V2 V2 = Vbe2 + Vt ln n ln n must be 17.2 for V2 to be independent of T

Bandgap circuits

Bandgap circuits

Bandgap circuitsThis circuit is used for illustration purposes. Working with CMOS, there are a number of issues with this circuit which we will discuss in the following slides. We will try to find circuits which are more practical and CMOS compatible.

A more CMOS friendly BJTInstead of the diode connected npn that we have used so far, we will use a pnp. This is so that we can implement the device in a CMOS process without any special processing.

BJT in a CMOS process

CMOS bandgap

CMOS bandgap

Low-voltage bandgap

Low-voltage bandgapThe core circuit is (again) the PTAT current generator. Although the delta Vbe gives rise to a PTAT voltage (dropped accross R1), the absolute Vbe of Q1 and Q2 is CTAT. Vbe1 controls the current through R2 and R3. The result is a temperature independent current if the currents are scaled correctly.

Low-voltage bandgap

StabilityStability is a concern for any system with feedback. Must make sure that we have more negative feedback than positive.

Transient responseTransients may capacitively couple to circuit nodes. Faster opampDecoupling (opamp stability)

Startup circuitIn the discussion so far, we have assumed the circuits are at the desireable operating point.We must add circuitry to make sure the circuit is not stuck at a "zero" operating point. Typically a circuit to inject some current if we are at or close to the undesireable operating point. (Power on reset.) This is very important. Simulator does not neccessarily reveal this problem.

Curvature correctionIn our analysis we have asumed the PTAT and CTAT to be constant. This assumption will lead to a non-linearity of the TC (curvature), approximately parabolic shape. Possible to design some function to try to mitigate this effect.Even possible to use Vos constructively (Cabrini, ESSCIRC 2005). Not curriculum.

Bandgap circuit issues● Collector current variation● CMOS compatibility (BJTs)● Opamp offset voltage● Opamp resistive loading● Stability● Startup● Transient response● PSRR● Curvature● Limited supply voltage● Noise● Resistor TC

Online resources

A Paul Brokaw

This is not part of the curriculum

http://www.archive.org/details/APaulBro1989

INF4420Layout and CMOS processing technology

Spring 2012 Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no)

OutlineCMOS Fabrication overview Design rules Layout of passive and active componets Packaging

IntroductionAs circuit designers we must carefully consider how to draw layout for critical/sensitive parts of the circuit in order to get robust and predictable performance. To be sucessfull at this, we must have a basic understanding of how circuits are manufactured, packaged, tested, and even how the circuit eventually is used on a PCB (e.g. external parasitics that we need to drive off chip).

Physical designThe physical circuit is built on a disc of silicon (wafer) layer by layer.

Some layers are implanted in the substrate, other layers are stacked on top.

Physical designHow do we go from a layout (GDS2) to a physical circuit? For each step in the processing, we must get the relevant part of the design onto the wafer, do the processing (implant, etch, or grow), and ready the wafer for the next step.

Physical designLayout is "encoding" the physical realization of circuits.CMOS processing (manufacturing) is done in layers, so is layout.

PhotolithographyPhotolithography (litho) is used to define regions for each layer.For each processing step, we need to transfer the mask onto the wafer (selectively coat/shield part of the wafer). Light source and a mask defines patterns on photoresist. Photoresist hardens when exposed to light.

Lithography system

We create layout. The mask (or reticle) used for photolithography is derived from the layout.

Photoresist

(1) Photoresist hardens when exposed to light (negative photoresist), leaving a developed mask on the wafer. Remaining photoresist is removed. (2) Do processing. (3) After processing step, hardened resist is also removed. Repeat for all processing steps required for full circuit.

DiffractionSlits in the reticle cause diffraction (pattern spreads out). Wavelength of light is a limitation for feature size.

Images illustrating diffraction from Wikipedia.org.

ResolutionResolution is limited by the wavelength of light and numerical aperture (NA) of the lens (angle of light captured by the lens, and refractive index n).

Depth of focusAs the wafer is built layer by layer, geometry becomes uneven. Wavelength of light and NA will limit the allowed topology difference. Planarize wafer between processing steps (before imaging) with chemical mechanical polishing (CMP). Unfortunately, inherent tradeoff between DOF and resolution (better NA, finer pitch, more narrow DOF).

Reducing k1Optical proximity correction (OPC), sub resolution assist features (SRAF). Modelling the lithography as a non-linear low-pass 2D spatial filter, try to come up with an inverse.

Reducing k1Phase shifting masks (PSM)Instead of "binary" on/off masks, masks alter the phase of the light. Double patterningSplit layout accross two (or more) masks Off-axis illuminationOptimizing the shape of the light source

Reducing k1Result: k1=0.25 instead of k1=0.5 Restricting allowed pitch may be neccessary for pattern fidelity. Additionally, NA is improved through immersion lithography (water between lens and wafer, higher refractive index, n).

Extreme UV source20 nm process with 193 nm light source?It can be done without defying the laws of physics! Why not use 13.5 nm (EUV) instead?http://spectrum.ieee.org/semiconductors/devices/euv-faces-its-most-critical-testhttp://www.asml.com/asml/show.do?ctx=41905&rid=41906

Front end of line (FEOL)Process modules that form the active devices● Active area● Channel doping● Gate● Source/drain extension● Spacer● Junction● Silicide

Active area definition● Shallow trench isoloation (STI)● Insulation between active devices● Etch trenches in the substrate● Filled with SiO2

Channel dopingDefine p- and n-type regions for NMOS and PMOS

Gate electrodeGates made of polysilicon

Source/drain extensionMitigate short-channel effectssource/drain resistanceleakage current, drive current

SpacersAvoid bridging S/D and gate due to silicideOffset junctions (next step)

JunctionsSource and drain junctionsImplant arsenic/phosphore (n-type)or boron (p-type)

SilicideLower resistance, better Ion. Avoid current crowding. Self aligned silicide = salicide

Back end of line (BEOL)Back end of line adds connection between devices, contacts and metal layers with vias between layers Parasitic resistance and capacitance is challenging for scaled technology. In modern CMOS, copper (Cu) metallization and low k dielectric is used.

BEOL modulesPre Metal Dielectric (PMD) Contacts to source, drain, and gate (tungsten) Inter Level Dielectric (ILD) Vias and metal lines (copper)

Dual DamasceneMetallization used to be etching away aluminum. Impossible with copper. Instead: Damascene. Used throughout the BEOL. (1) Etch trenches in oxide, (2) deposit copper, (3) polish away the overfill (CMP)

Image: wikipedia.org

Dual Damascene1. Trenches are etched

in the oxide (to the barrier)

2. Metal (Cu) is deposited through electroplating (leaving excess Cu)

3. CMP to remove excess metal.

Dual = via and metal formed simultaneously

Dual DamasceneWhy should we as designers care? CMP polish rate is pattern dependent, i.e width and spacing of metal lines matter. Poor layout results in metal lines that are too thin and/or less dielectric separation of metal layers. Layout dependent delay. Post-layout simulation does not neccessarily reveal these problems.

Dishing and erosion

Dishing affecting wide metal lines (Cu polishes faster than dielectric)

Erosion affecting high density metal pattern

Drawing layoutLayout is drawing the masks used in the manufacturing process. As we have seen, the layout we draw is not perfectly reproduced on the wafer. We must comply with a set of rules to ensure that the layout we draw is manufacturable.

Design rule examples

Rule name (minimum)

P.1 Poly width

P.2 Space poly and active

P.3 Poly ext. beyond active

P.4 Enc. active around gate

P.5 Spc. field poly to active

P.6 Spc. field poly

Design rule examples

Rule name (minimum) Length

P.1 Poly width 50 nm

P.2 Space poly and active 140 nm

P.3 Poly extension beyond active 55 nm

P.4 Enclosure active around gate 70 nm

P.5 Space field poly to active 50 nm

P.6 Space field poly 75 nm

Poly rules example (FreePDK45)

Design rule examples

Rule name (minimum) Length

M1.1 Metal1 width 65 nm

M1.2 Space metal1 65 nm

M1.3 Enclosure around contact (two opposite sides) 35 nm

M1.4 Enclosure around via1 on two opposite sides 35 nm

M1.5 Space metal1 wider than 90 nm and longer than 900 nm 90 nm

M1.6 Space metal1 wider than 270 nm and longer than 300 nm 270 nm

M1.7 Space metal1 wider than 500 nm and longer than 1.8 um 500nm

... ... ...

Metal1 rules example (FreePDK45)

Density design rulesIn addition to spacing and area rules. There are density rules. Ref. dishing and erosion resulting from CMP. Typically, the layout will undergo dummy fill to comply with density rules (automatic). Neccessary for manufacturability, but increases capacitance.

Antenna design rulesLarge area metal connected to a MOSFET gate can collect ions during manufacturing and irreversibly break down gate oxide.

Design rule switchesDifferent set of rules can be invoked for different parts of the circuit. E.g. Minimum rules for high density generic digital circuitry Analog or DFM rules for sensitive circuits.

Design Rule Check, DRCDesign Rule Check (DRC) Large number of rules to comply with. Difficult to keep track of. Automated by design tools with foundry rule set. Used to be pass/fail, more recently reporting level of severity. Some rules can be waived.

Litho friendly design, LFDDesign rules does not guarantee a robust design or good yield. Possible to simulate and analyze how the layout will print on the wafer. Difficult to get access to data.Non-linear 2D spatial filter.

Lithography simulation

Litho simulation using FreePDK45 and Calibre (http://www.eda.ncsu.edu/wiki/FreePDK)

Lithography simulation

Litho simulation using FreePDK45 and Calibre (http://www.eda.ncsu.edu/wiki/FreePDK)

Layout vs. schematics, LVSRecognizing shapes in the layout (transistors and passive devices), and how they are connected. Comparing layout netlist to schematics.

Post layout simulationExtracts layout dependent parasitics (capacitance and resistance), and some layout dependent transistor parameters (e.g. LOD which we will discuss in the short-channel lecture). More accurate simulation results (but does not include all effects). Also, parasitics have fast/slow corners, temperature dependence. Results in slow simulation due to large netlists.

InterconnectDrawing metal "wires" in the layout is not like wires in the schematic. Must think about resistance, capacitance, and inductance. (E.g. 0.1 Ω/□ for metal, and 10 Ω for via) Crosstalk and ground bounce. Decoupling.

InterconnectSingle via approximately 10 Ω. Worse, single via failure. Not only resistance, but limitaions on current capability (electromigration). Process documentation should list actual values for a given process.

InterconnectOverlap capacitance low-k dielectrichelps reduceinterconnectcapacitance Additionally, fringe capacitance also important.

InterconnectSizing metal lines is a tradeoff between capcitance vs resistance (and current handling capability).Wide lines, fewer squares, less resistance,but potentially more overlap capacitance. Finally, to make it even more complicated, resistance and capacitance will vary due to dishing and erosion.

Passive componentsMixed signal and analog require passive components (resistors, capacitors). RF needs inductors. Why not use parasitic resistance and capacitance? Possible in some cases.

ResistorsSeveral possibilities. Need to consider: ● Ω/□ (area, practical limit for large R)● Temperature dependence (TC)● Voltage dependence (linearity)● Mismatch (ΔR/R, abs value +/- 20 %)● Parasitic capacitance The TC and voltage dependence is not only linear, but also quadratic in the simulator.E.g. R(T) = R(T0) [1 + TC1(T-T0) + TC2(T-T0)^2]. Similar for voltage dependency.

ResistorsRealistic alternatives for large resistors:

N-well: Large R, poor TC (> 2000 ppm/C), poor linearity (< 1 %), low mismatch, parasitic capacitance from pn-depletion. Always available.

Poly with silicide block: Large R, good TC (~ 100 ppm/C), reasonable linearity (< 0.1 %), low mismatch. Extra layer needed.

CapacitorsNeed to consider: ● F/m^2● Temperature dependence (TC)● Voltage dependence (linearity)● Mismatch (ΔR/R)● Cost

CapacitorsMOSCAP, using a mosfet as a capacitor (Cox). High capacitance per area, very non-linear, good e.g. for decoupling, but gate leakage current is problematic. PiP, using two poly layers. Usually not available in modern CMOS processes.

CapacitorsMiM (Metal-insulator-Metal). Requires extra mask. ~ 1 or few fF/um^2. Good option if available. Thin separation of metal layers and special dielectric. Usually available in RF process flavours. Cost issue. MoM (Metal-oxide-Metal). Exploit fine pitch in CMOS. No extra processing required.

MoM Capactiors

Matching passivesSystematic vs. random● Different absolute values between runs● Layout dependent problems● Stress, thermal, or doping gradients

Good layout practice helps● Unit elements● Dummies (each unit element should see the

exact same surroundings)● Interdigitation or common centroid

Unit elements

Instead, make identical unit elements. Less systematic mismatch.

Dummy elements

Dummies to make sure matching elements see the same surroundings

Interdigitated layout

Process gradient are spread more evenly between the two elements. Proximity helps with matching!

Common centroid

Better process gradient cancelation than interdigitated layout. Perfect cancelation of linear gradients.

Drawing transistorsUnit elements, dummy, and common centroid also applies to layout of transistors. However, there are additional issues that need attention when laying out transistors. ● Multi-finger devices● S/D symmetry● WPE and LOD● Latch-up

Multi-finger devices

Device orientationDevices with different orientation do not match!

Source/drain asymmetrySource and drain may not be symmetric due to ion implantation angle, neccessary to avoid implant depth issues (channeling).

Well proximity effect

High energy ion implants to form the well. Scattering from the edge of the photoresist mask, and embedding in the silicon surface (near well edge). Transistors close to the well edge will therefore have different properties. This is known as the well proximity effect (WPE). Important for matching.

Well proximity effect

As with S/D, implantation angle may render the scattering and doping asymmetric

STI stress (LOD)

Shallow trench isolation strains the active area of the transistor. Influcences mobility and threshold voltage (stress induced enhancement or suppression of dopant diffusion). Distance between gate and STI impacts perfomance. Important for matching. (Parameters SA and SB in BSIM). Also known as LOD (length of diffusion), LOD = SA + SB + L

STI stress (LOD)

Transistor interconnectUnbalanced metal routing will cause the transistors to see different source voltage. Also, distribute reference as current, not bias voltage.

Matching

This discussion about matching was about minimizing systematic mismatch. We will discuss random mismatch later.

ShieldingSubstrate ties circuits together. Digital switching couples to the substrate. ● Guard rings around the circuit: Substrate ties

and n-well (preferably deep n-well)● Separate Vdd for digital and analog● Fully differential signals See sect. 18.3 in Razavi's book.

Latch-upAs we saw with bandgap references. Parasitic BJTs are readily available in CMOS. Parasitic BJTs may inadvertently turn on due to a large injection of current into the substrate. Typical design rules make sure that substrate and n-well contacts have sufficiently small spacing. However, latchup is an important problem, and requires careful consideration.

Bond padsUsed for connecting bond wires between die and package. ● Mechanical stability● ESD protection (very important, and adds C)● Aluminum (while other metal is Cu) Pad frame usually contains supply nets (also used by ESD circuitry)

Bond pads

Bonding gone wrong ...

Seal ring

A seal ring is a structure to enclose the die (outside the pad frame). Protects the die from moisture and sawing. Also contains scribe (where to saw the die).

PackagingPackaging adds very significant parasitics.

Bond wires introduce inductance. Rule of thumb is 1 nH/mm.

Inductors like to keep current constant. Voltage will change to make this happen. Important to balance with decoupling capacitors. However, transients will remain.

References

Hastings, The Art of Analog Layout, Prentice Hall, 2001 Orshansky, et al., Design for Manufacturability and Statistical Design, Springer, 2008 Wong, et al., Nano-CMOS Circuit and Physical Design, Wiley, 2005

INF4420Short-channel effects and models

Spring 2012 Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no)

Outline

MOSFET scaling Short-channel effects MOSFET models

IntroductionScaling continues for the benefit of digital. For analog this is not neccessarily beneficial, but desirable to have everything on one die (SoC). Designing ananlog and mixed-signal circuits, we need to be aware of the implications so that we can design circuits that perform well despite short-channel effects.

Why CMOS scaling?Reducing feature size is very attractive for digital circuits ● Higher density (lower cost)● Reduced power consumption● Faster (less capacitance)

Why CMOS scaling?Can be beneficial for analog, depending on the application ● Reduced Vdd, increased current● Gain is low because because output

resistance is decreased● Higher speed (ft) opens up for new

applications in CMOS (e.g. mm-wave)

Short- vs long-channelA loose definition: Typically, a long-channel device will behave according to the square-law model

The behaviour of a short-channel device will not be accurately predicted by the square-law model

Long-channel transistor

Gate has good control over channel Square-law equations are sufficiently accurate for predicting drain current.

Short-channel transistor

Drain region has more influence on channel behaviour Short-channel effects become significant.

Constant field scaling

Constant field

Constant field scalingP=F*C*Vdd^2 Similar for SD depletion capacitance

Constant field scalingImplications for analog. gm and ro does not change.

However, kT/C is the noise floor. Lower Vdd requires larger C to maintain SNR. Larger current needed to drive C.

Constant voltage scaling

Practical scalingPractical issues makes scaling less than ideal tox scaling leads to reliability concerns and gate current tunneling. Practical limit to reducing Vdd and Vth, and Vdd/Vth-ratio decreases Devices must handle higher fields

Charge sharing

HALO implantsUsed to make threshold voltage more constant vs. gate length. Non-uniform channel doping. Reverse short channel effect (RSCE). Overcompensating droop in threshold voltage results in increasing threshold voltage with shorter gate lengths.

Trade-off Ion/Ioff (digital) vs. gain (analog). Halo reduces Ro. DITS (Drain-Induced Threshold Shift)

Vertical field

Higher gate channel field pulls carriers closer to the oxide interface. Degrades effective mobility. Effective mobility becomes a function of Vgs (mobility reduces with increasing Vgs)

Velocity saturationIncreasing Vds will increase the electric field in the channel. If field is too large, velocity will saturate (vsat = 10^7 cm/s).

Channel length modulationChannel length modulation (CLM) is present even in long-channel transistors, but less prominent. Pinch-off changes with Vds.

DIBL

Drain induced barrier lowering Drain voltage (Vd) contributes to inverting the channel, effecively reducing Vth. Increasing current with increasing Vd

Hot carriers

Velocity overshoot due to high electric field from source to drain. Impact ionization near drain, electron hole pair. Carriers may get trapped in the gate oxide.

SCBE

Substrate current induced body effect Electron hole pair from impact ionization generates a drain substrate current. Current will increase exponentially with drain voltage Substrate resistance IR drop.

Short channel Ro

CHMDIBL SCBE

Gate tunneling currentThinner gate oxide increases probability of carriers tunneling through the oxide. Also GIDL (Gate induced drain leakage) ...

MOSFET device modelsAs circuit designers we need to accurately predict circuit performance. Circuit simulators can use much more sophisticated device models than we use for hand calculation and analysis. As technology scale, models evolve to take new effects into account in order to predict device behaviour with sufficient accuracy.

Shichman Hodges Model

Also known as a "level 1 model" because of SPICE.

Approximately the simple equations we use for hand analysis of circuits. (Id and capacitance).

Usually not sufficiently accurate, except for several um gate length techology.

BSIM

Berkeley Short-Channel IGFET Model BSIM3v3 1995BSIM4 2000 (currently BSIM4.7.0, 2011) BSIM4 includes all short channel effects we have discussed. Significantly better Ro prediction (which has been a problem).

BSIM

Increasing number of non-physical parameters to fit measured device characteristics. Finding parameters to accurately model devices is challenging. Currently more than 200 parameters (binning, and several transistor flavours in one process).

Binning and corners

Different sets of parameters for different device sizes (binning). Simulator selects parameter set automatically. Different sets of parameters for process corners (FF, SS, FS, SF). Statistical parameters for monte-carlo analysis.

EKV model

Charge-based compact model. Not widespread adoption for simulation, but can be useful for hand analysis. Possible to extract parameter set e.g. from BSIM parameters supplied by the foundry.

PSP MOSFET modelFrom http://pspmodel.asu.edu/downloads/psp103p1_summary.pdf

"PSP is a surface-potential based MOS Model, containing all relevant physical effects (mobility reduction, velocity saturation, DIBL, gate current, lateral doping gradient effects, STI stress, etc.) to model present-day and upcoming deep-submicron bulk CMOS technologies."

● accurate higher order derivatives● more physics based modelling rather than

threshold voltage

ModelsDevice modeling is difficult. Parameter extraction is difficult. Do not blindly trust models.

Sophisticated device models offer little intuition for design. Square law equations can not be used for design. Instead, chart based design (gm/Id).

Corner simulation also helps robustness against model parameters.

Online resourcesAs usual, not curriculum:

● BSIM manual: http://www-device.eecs.berkeley.edu/~bsim3/BSIM4/BSIM470/BSIM470_Manual.pdf

● BSIM parameter fitting: http://ewh.ieee.org/r5/denver/sscs/References/2003_03_Assenmacher.pdf

● Check list for device models: http://effectiveelectrons.com/whitepapers/Determine%20Foundry-Model%20Problems%20Without%20Touching%20A%20Wafer.pdf

● Chart based design: http://www.ewh.ieee.org/r6/scv/ssc/May1905.pdf

INF4420Random mismatch

Spring 2012 Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no)

Outline

Systematic vs. random mismatch Hand calculation of random mismatch Sources of random mismatch Offset and calibration

MatchingPreviously we have discussed systematic mismatch. Systematic mismatch can be minimized by careful layout or trimming. Binning is also used. When "identical" devices are manufactured, random fluctuations cause electrical parameters of devices on the same die to have a statistical distribution. (Random mismatch)

MatchingNeed good matching between devices in input pair. And devices in current mirror.

Both systematic and random. Trimming can help both. Typically want to minimize inherent effect of both.

Systematic mismatchDesired mean value Systematic mismatch

Random mismatchBetter = more devices will be closer

to the desired (mean) value

Better

Worse

Worst-case analysisAssuming a normal distribution (reasonable assumption from central limit theorem). Worst case minimum value: μ - 3σWorst case maximum value: μ + 3σ 3σ would capture 99.73 %6σ would capture 99.9999998 %

Monte-carlo simulationFab provides statistical parameters for device models.

Run a large number of simulations with different permutations of parameters. Does not neccessarily give insight into which devices are causing problems, or how to improve yield.

Hand calculation

A systematic study of mismatch

between parameters of two identical

MOSFETs.

Manufacturing devices with different W/L, distance, orientation to see how this affects matching.

Hand calculation

Area proportionality constant

Size

Matching of parameter, P, between two identically drawn devices

Distance

Variation with spacing

SpDx can be made small with good layout

Hand calculationMismatch between two identically drawn transistors. Will do hand calculation to find ΔVth and Δß/ß. Use this to find ΔId/Id, Vos, etc.

Sources of randomness● Line edge roughness (LER)● Random dopand fluctuation (RDF)● Gate oxide thickness● ... Some effects due to the manufacturing process may not be truly random, but will appear random to us as designers, because it's outside our control. We will count this as "random".

Line edge roughness"LER is caused by a number of statistically fluctuating effects at these small dimensions such as shot noise (photon flux variations), statistical distributions of chemical species in the resist such as photoacid generators, the random walk nature of acid diffusion during chemical amplification, and the nonzero size of resist polymers being dissolved during development. It is unclear which process or processes dominate in their contribution to LER." [http://spie.org/x32401.xml]

Random dopant fluctuationAs features scale, fewer dopant atoms in the channel. The relative contribution of one atom increases. Single atom affects electrical parameters.

Basic rule of matching

Big devices match better. Randomness averages out more over a larger area. Big devices, more capacitance, more area. Reducing random mismatch comes at a cost. Important to know how much mismatch we can live with to avoid costly overdesign.

Threshold voltageImportant contributions are tox and dopant concentration in channel region

Improves with scaling in tox

Best guess

Technology parameter

Beta variabilityRelative current factor mismatch, Δß/ß [%]

Best guess for Aß is 2 % µm

Drain current mismatch

ΔId/Id vs Vgs

Current mirror example

One standard deviation!

Input referred offset

Digital offset calibration

ReferencesOrshansky, et al., Design for Manufacturability and Statistical Design, Springer, 2008 Pelgrom, Component matching: best practices and fundamental limits, IDESA. Pastre and Kayal, Methodology for the Digital Calibration of Analog Circuits and Systems, Springer, 2006

INF4420Non-linearity

Spring 2012 Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no)

Outline

Non-linearity and harmonic distortion Differential circuits Feedback Improving linearity

Introduction

Linear distortion from filtering (not considered) Soft non-linearity (expanding, compression) Hard non-linearity (clipping)

Introduction

Amplification and non-linearity depends on the biasing point. Soft non-linearityHard non-linearity (clipping)

Amplifier DC transfer function

Biasing point

Introduction

Measure deviation from ideal straight line approximation

Common source amp

Taylor series

Using Taylor series allows studying distortion independent of the specific shape of the non-linearity. Generic expression for total harmonic distortion (THD).

Taylor series

Harmonic distortion

Harmonic distortion

Harmonic distortion

Common source linearityLarge signal current:

Harmonic distortion:

Input signal

Differential pair

Harmonic distortion:

Differential pair

Differential circuits exhibit much less distortion (5 % vs 0.125 % for Vm = 0.2(VGS - VTH) Linearity is also better when accounting for 2x current.

Feedback

Resistive degeneration

Resistive degeneration

Resistive degeneration also works for diff pairs

Post correction

Cascade non-linear stage with inverse non-linearity. Ideally gives overall linear transfer funciton

INF4420Switched capacitor circuits

Spring 2012 Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no)

Outline

Switched capacitor introduction MOSFET as an analog switch z-transform Switched capacitor integrators

Introduction

Discrete time analog signal processing

Why?

Introduction

The arrangement of switches and the capacitor approximates a resistor. Analyze each clock phase separately

IntroductionAssuming steady-state, and arbitrarily assume VA > VB. T is one clock cycle.1. At the beginning of ϕ1, node VC is at VB Volt2. During ϕ1, VC is charged to VA. Charge

transfer from VA to C: ΔQ = C(VA - VB)

3. During ϕ2: ΔQ transfered from C to VB Net charge transfer, ΔQ, from VA to VB in T sec. IAVG = C(VA - VB)/T, RAVG = T/C

Introduction

RC accuracy (matching). Large time constants .

Introduction

Resistive loading is not ideal for CMOS

Introduction

Capacitive feedback. DC issues.

Switch-cap amplifier

Analyze ϕ1 and ϕ2 separately!

Switch-cap amplifierPhase ϕ1: C1 tracks Vin, Q = C1 Vin

Phase ϕ2: Charge transfer from C1 to C2

Switch-cap amplifier

1. During ϕ1, C1 is charged to Q = C1 Vin2. During ϕ2, the charge, Q, is transferred to C2. If C1 and C2 are of different value, the same charge will give a different voltage drop

Sampling

Discrete time, continuous amplitude

Signal, x(t), sampled at discrete time points, nT

MOSFET analog switch

During ϕ1, Vout tracks Vin After ϕ1 the switch is closed and Vin (from the end of ϕ1) is held on CH. However, the MOSFET "switch" is not perfect ...

MOSFET analog switch

● Finite resistance (settling)

● Charge injection

● Clock feed-through

Large signal behaviour

NMOS can discharge effectively from Vdd to 0 (compare to a digital inverter). Saturation, then triode.

However, the NMOS can not charge from 0 to Vdd. The MOSFET will enter subthreshold and current through the switch will be low. Output will settle to Vdd - Vth. If we wait for a long time, output will slowly approach Vdd.

Finite switch resistanceComplimentary switch resistance, still problems

for low Vdd NMOSPMOS

Finite switch resistanceThe RC time constant will define the sampling time, therefore the maximum frequency of operation.

Finite switch resistanceEven if we restrict the input voltage range so that we avoid subthreshold. The settling speed will still be limited by the finite switch resistance.

Signal dependent

Finite switch resistanceSettling behaviour introduces an error in the

final value. Need to wait several time constants for accurate settling.

Finite switch resistancets ε

3RC 5 %7RC 0.1 %9RC 0.01 %

Faster settling: Smaller C (more noise and parasitics more prominent) or smaller R (wider transistor, more channel charge)

Clock feed-throughCapacitive voltage divider (hold capacitor and

parasitic overlap capacitor)

Increasing CH helps but degrades settling speed

Signal independent!

Charge injectionChannel charge, Qch, when switch is "on". Released when switch turns off. Common assumption: Half the channel charge goes to source and other half to drain.

Charge injectionQch is a function of Vin and (worse) VTH is a function of Vin through body effect (non-linear).

Signal dependence

Charge distribution is complex and poorly modelled

Charge injectionFigure of merit (FoM) to study speed vs. precision trade-off. Larger CH makes charge injection less prominent but also increases the time constant and therefore ΔV from settling error.

Charge injectionDummy switch will ideally cancel the injected channel charge. Because the charge distribution is complex, finding the optimal size of the dummy switch is difficult.

DummyThe purpose of the dummy switch is to soak up channel charge from the main switch.

Best guess size

Charge injection

Bottom plate sampling: ϕ1a turns off slightly before ϕ1, injecting a constant channel charge. Signal dependent charge from ϕ1 will ideally not enter CH (no path to ground).

Bootstrapped switchInclude extra circuitry to generate a clock voltage that takes Vin into account to generate a constant VGS. Reliability concerns. Complexity.

Better RON independent of Vin. High clock Vin + Vdd

Amplifier specification ● Cin (contributes to gain error)● Slew rate● DC gain (loop gain, determines static error)● GBW (determines dynamic error)● Phase margin (stability)● Offset (can be compensated, CDS)● Noise (offset compensation helps 1/f noise)

Sampling and z-transformFor continuous time circuits the Laplace transform is very convenient as it allows us to solve differential equations using algebraic manipulation. Analyzing SC circuits in terms of charge transfer, and charge conservation, results in difference equations. Need a similar tool for this case.

Sampling and z-transformLaplace transform: Fourier transform:

Input signal

Sampling and z-transform

Circuit and waveforms for illustrating sampling theory

Sampling and z-transformModelling the sampled output, f*(t) Step function: Laplace transforms:

Sampling and z-transform

assuming f(t) = 0 for t < 0

Sampling and z-transformImpulse sampling: Choose τ "infinitely narrow" and the gain, k = 1/τ (area of the pulse equal to the instantaneous value of the input, f(nT)). In this case, we find:

A very convenient notation:

Sampling and z-transform

The z-transform is very convenient for sampled data systems: Delay by k samples (k periods):

Important!

Sampling and z-transformWe have assumed infinitely narrow pulses. Most switched capacitor systems will have sample and hold (S&H) behaviour.

Sampling and z-transformUse the same equation as before, but instead of letting τ be infinitely narrow, we let τ = T.

Sample & hold:

≈ 1 for impulse sampling

Sampling and z-transform Comparing F*(s) and FSH(s), we define the transfer function of the sample and hold as:

Frequency responseComparing the z-transform to the Fourier transform, we can find the frequency response from the z-domain expression, s = jω gives z = ejωT.

Frequency responsez-transform: z → esT. Mapping between s-plane and z-plane.

Points on the imaginary axis of the s-plane map to the unit circle in the z-plane, periodic with 2π

For a sampled data system, frequency response is z-domain expression evaluated on the unit circle in the z-plane. Poles must be inside unit circle for stability.

Frequency response

Sampling introduces images

Spectrum of an input signal

Frequency responseMultiplying by the transfer function of the

sample and hold, we find the frequency spectrum of FSH(jω) (sin(x)/x, sinc-response).

Linear distortion from droop.

Frequency aliasingIf the signal contains frequencies beyond fs/2 when sampled, aliasing will occur (non-linear distortion). Images of the original signal interfere.

Frequency aliasing

A continuous time low-pass filter (anti-aliasing filter) on the input to the sampled data system will ensure that the input signal is band limited to a frequency below the Nyquist frequency. Need to take some margin to account for the transition band of the filter (usually first or second order).

Switch-cap integrator

Cj parasitic capacitance

Switch-cap integratorCharge on C1 is proportional to Vin, Q1 = C1 Vin.Each clock cycle, Q1, is transferred from C1 to C2. C2 is never reset, so charge accumulates on C2 (indefinitely). We are adding up a quantity proportional to the input signal, Vin. This is a discrete time integrator. In the following, we assume the output is read during ϕ1.

Switch-cap integratorOutput at ϕ1

Delaying

Switch-cap integratorApprox frequency response: z = ejωT ≈ 1 + jωTValid when ωT is close to zero. I.e. when signal frequency is low compared to sampling freq.

Compare to continuous time

Switch-cap integratorInsensitive to non-linear parasitic cap, Cj

Critical wrt. performance

Turn off first (bottom plate sampling)

Switch-cap integrator

During ϕ1 C1 tracks Vin and Vout is constant.

Switch-cap integrator

During ϕ2 charge is transferred from C1 to C2. Vout settles to the new value.

Switch-cap integratorAnalysis similar to the parasitic sensitive integrator, however, polarity of the capacitor changes because of the switching. So gain is not inverting.

Looking at the output during ϕ1 we have a delaying non-inverting integrator.

Switch-cap integratorBy changing the switching we get a non-delaying inverting int.

ReferencesGregorian and Temes, Analog MOS Integrated Circuits for Signal Processing, Wiley, 1986

Baker, Mixed Signal Circuit Design, IEEE Wiley, 2009

Sansen, Analog Design Essentials, Springer, 2006, Ch. 17

Johns and Martin, Analog Integrated Circuit Design, Wiley, 1997

INF4420Data Converters

Spring 2012 Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no)

Outline

Quantization

Sampling jitter

DFT and windowing

Data encoding

Introduction

Digital signal processor (DSP)

Signal processing can be more efficient, robust, and convenient in the digital domain (algorithms in digital circuits and software). Need to convert to and from analog to interface with the world.

Introduction Continuous time input and output, but with digital processing.

Anti-alias filter Reconstruction filter

Digital processing

Introduction

Data conversion accuracy limits system performance.

In-depth understanding of data converter performance is important for the design of mixed-signal systems.

How do we quantify data converter performance?

IntroductionImportant to pay attention to mixed signal layout issues.

Data converters combine sensitive high accuracy circuits for generating reference levels (bandgaps) with digital switching (current spikes).

For high resolution converters, the external environment (e.g. PCB) is very important.

QuantizationData converters must represent continuous values in a range using a set of discrete values. A binary code is used to represent the value.

Hot or cold

Freezing, cold, warm, or hot.

-20 °C, -19.5 °C, ..., 20 °C.

Information is lost!

Open Clipart Library (openclipart.org)

Quantization

Number of bits, N

Quantization

The quantization error is restricted to the range -Δ/2 to Δ/2.

The quantization process is non-linear!

Quantization noiseModel the quantization error as noise added to the original signal. Enables linear analysis.

Quantization noiseQuantization noise assumptions: ● All quantization levels have equal probability● Large number of quantization levels, M● Uniform quantization steps, constant Δ● Quantization error uncorrelated with input

Quantization noise is white!

Quantization noise

Time average power (variance):

Quantization noiseAssuming sine wave input SNR due to quantization noise

Sampling jitter

Uncertainty in the timing of the sampling clock due to circuit electrical noise (white noise + 1/f).

Reference sampling edge

Sampling jitterSampling

clock timing jitter

translates to an error in

the sampled value.

Impacts SNR.

Sampling jitter

Worst-case full scale sine wave at the Nyquist frequency. Error due to jitter should be less than half the quantization step.

Discrete Fourier TransformMany data converter performance metrics are carried out more straightforward in the frequency domain.

The Discrete Fourier Transform (DFT) is used to analyze a set of N samples. Assumes the N samples are one period of an infinitely repeating signal. Result is a set of N complex numbers, the frequency domain representation of the signal.

Discrete Fourier Transform The DFT can be efficiently computed using the Fast Fourier Transform (FFT).

WindowingThe DFT assumes periodic input. Window functions are used to introduce artificial periodicity.

Time domain Freq. domain Trade-offs

● Amplitude accuracy

● Sidelobes● Width of

signal peak

Binary data coding

Alternatives for representing the quantized value in binary ● Unipolar● Bipolar● Two's complement● ...

Static specifications

Static specifications

● Gain● Offset● INL● DNL● Missing codes (output code which can not

be reached by any input value)● Monotonicity (increasing input value will

always produce equal or higher output code)● ...

Dynamic specificationsObtained from the DFT (FFT) ● SNR● SINAD● SFDR● THD● DR

SFDRSpurious free dynamic range. Relative to highest spur (not only harmonics)

SNRSignal to noise ratio. Signal power, divided by noise power (exclude harmonics)

THDTotal harmonic distortion A measure of the distortion excluding noise.

SINAD

Signal to noise and distortion ratio.

Dynamic specifications

Other dynamic specifications: ● Intermodulation distortion (IMD)● Settling time● Glitching

Figure of merit (FoM)Equivalent number of bits: Figure of merit (FoM):

ResourcesNot part of the curriculum

Converter Passion (blog covering many aspects of data converters)

Kester, The Data Conversion Handbook, Analog Devices, 2004

Heinzel et al., Spectrum and spectral density estimation ..., Max-Planck-Institut für Gravitationsphysik, 2002

INF4420Digital to analog converters

Spring 2012 Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no)

Outline

Resistive DACs Capacitive DACs Current steering

IntroductionDigital to analog converters (DACs), takes a digital input word, and converts it to a voltage or current proportional to the input value. Usually the DAC will use an arrangement of switches and resistors, capacitors, or current sources, to generate an output that is a fraction of or proportional to some reference current or voltage (bandgap).

IntroductionProper layout (to reduce mismatch) is critical for performance. Switches are also critical (signal dependent Ron, clock feed-through, and charge injection). DACs find numerous applications, from trimming and adjustment circuits to high-end video DACs (12 bit, 150 MSPS), and communication circuits.

Introduction

Outline of the full digital to analog converter.

Resistive divider (Kelvin divider) DAC

Kelvin divider

Different switching schemes are possible.

● Tree● X-Y

Output settling

There is inherent resistance in the resistive divider. Switches have both Ron and parasitic capacitance (also for switches turned off). Resistance is code dependent. Capacitance is approximately constant. Gives rise to exponential settling.

Output settlingOutput buffer will have finite slew rate (large signal) and gain bandwidth (small signal).

Slewing

Exponential settling from finite gain bandwidth

Mismatch

Resistors are affected by systematic and random mismatch, causing a deviation from their ideal value.

Linear gradient in resistor values gives rise to a parabolic INL. Harmonic distortion!

Good layout is important. Trimming or calibration may be necessary.

R-2R resistor ladder DAC

DeglitchGlitches are likely to occur when the DAC is switching (overshoot resulting in more settling and slewing). A track and hold (T&H) amplifier can be used to avoid glitches on the output of the DAC.

Timing of the T&H relative to the DAC input is critical (track while the output is constant, and hold when the output is transitioning). Noise and linearity of the T&H must be sufficient.

Capacitive divider DACArray of binary weighted capacitors. We program which capacitors are connected between out and gnd, or between out and ref.

Capacitive divider DAC

Capacitive divider where we program which capacitors belong to C1 or C2.

Digitally programming the fraction of Vref.

Capacitive divider DACSamples amplifier offset(and 1/f noise) duringreset. Avoids rail-to-railbuffer input.

Current source DAC

Current source DACCurrent

source with finite outputresistance,

switch resistance,

and resistive loading. Norton

equivalent.

Current source DAC α must be small for acceptable INL and distortion.

● Current sources with large output impedance● Differential output (cancels even harmonics)● Amplifier virtual ground (speed issues)

Current source DACUsing cascode (M1), the output resistance is approximately gmro

2.

Depending on biasing of the cascode, Vcp, we need ≥ 2VDS,sat + VTH or ≥ 2VDS,sat. Active cascode also possible.

Current source DAC

Random variation of drain current is an important limitation. Need to design current sources with sufficient area and overdrive. Gate current can be problematic.

Current source DAC

Addressing unity current sources in a 2D array.

● Sequential selection● Common centroid● Random (several possibilities) Segmenting the array with a local current replica is also useful.

Current source DAC

Switch driver must ensure switches are not off at the same time to avoid triodeing the current source (recovery time).

Ideal reconstruction filter

The DAC output has a S&H response. Need an output filter to further attenuate frequency images and smooth out the time domain waveform.

Ideal reconstruction filter

The ideal reconstruction filter is not realizable (infinite impulse response without recursion), we must use an approximation of the ideal brick wall filter instead.

ResourcesNot part of the curriculum Mercer, Digital to Analog Converter Design Baker, CMOS: Circuit Design, Layout, and Simulation, IEEE Wiley, 2010 Sansen, Analog Design Essentials, Springer, 2006, Ch. 20

INF4420Analog to digital converters

Spring 2012 Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no)

Outline

Comparators Circuit topologies for analog to digital

FlashInterleavedFoldingInterpolationTwo-stepPipelinedAlgorithmicSARIntegrating

IntroductionADCs are used in numerous applications with differing requirements on speed, accuracy, and energy efficiency. ADC architectures have different strengths and weaknesses with respect to these trade offs. It is therefore important to understand not only how each converter works, but also its limitations and key aspects for performance.

ComparatorsBasic quantization element. Propagation delayMetastabilityResolution limited by offset and noiseKickback noiseMemory, hysteresis

Comparators

Improve resolution/ sensitivity of the comparator

Amplify the decision of the comparator

Buffer result to digital levels

ComparatorsComparator

example

Decision circuit

Pre-amplifier

Buffer not shown

ComparatorsClocked (latched) comparator

example

Van Elzakker, ISSCC, 2008

Pos. output

Flash ADC The Kelvin divider is used to generate 2N reference voltages, and comparators are used for quantizationVsh is Vin sampled and held

Flash ADCResistive divider string imposes the same limitations as for the DAC case. Linear gradient results in a parabolic shape of the INL curve.

Additionally, the comparators (preamplifiers) have offset, which must be less than ½ LSB. Auto-zero and fully differential (also 1/f-noise).

Flash ADC

● Bandgap stability and loading● Dynamic gain (not full settling in the

comparator preamplifier)● Sample and hold loading from an

exponential number of comparators

Time interleaved ADCRun N ADCs in parallel to increase conversion rate. Offset and gain mismatch between channels. Clock misalignment (fixed).

Time interleaved ADCExample: Monolithic 40 Gs/s ADC in anSiGeprocess

http://www.lecroy.com/tm/Library/WhitePapers/PDF/DBI_Explained.pdf

FoldingFold the input signalinto regions. Folderdetermines MSBs. Need fewer comparators.

Interpolation

Reducing number of comparator preamplifiers.

Reduced loading of the sample and hold.

Two-step ADC

Combine output from the MSB ADC (M bits) and the LSB ADC (N bits) for the full output.The MSB ADC must be linear to M + N bits (< ½ LSB for INL and DNL)

Two-step ADCPerformance constraints for the opamp used for gain and summing:

● Open loop gain, AOL, to achieve the desired closed loop gain, ACL.

● GBW to settle fast enough to the desired accuracy.

● Amplifier linearity

Again, errors must be less than ½ LSB.

Pipelined ADC

More than 1 bit per stage is possible.

Error correction

Algorithmic ADC

A variation of the pipeline ADC is the algorithmic ADC, which reuses a single stage for all bits. Each conversion now takes N (number of bits) clock cycles.

SAR ADCThe successive approximation register (SAR) tests each bit sequentially (MSB first, one clock period per bit), and decides whether too keep the bit or not based on the comparator's output.

Charge redistribution SARhttp://dx.doi.org/10.1109/JSSC.2010.2075310

http://dx.doi.org/10.1109/JSSC.2010.2043893

Examples of energy efficient (FoM) ADCs

http://converterpassion.wordpress.com/2011/05/05/adc-survey-spring-2011-update-on-fom-state-of-the-art/

Charge redistribution SARRef. capacitive divider DAC

Inherent sample and hold function

SAR not shown

Charge redistribution SARReset and sampling: In the first clock phase, Vin and Vos are sampled.

Next, the bottom plates are switched to ground, and Vx = -Vin. Then, each bit is tested (MSB first) by switching each capacitor between ground and Vref. Vx is compared for each bit (SAR).

Charge redistribution SARSuitable for low-power. No amplifiers needed (except for the comparator).

Comparator and charging of the capacitive array decides power consumption.

Capacitor mismatch limits resolution.

Speed limited by τ = Rtotal 2N C,

e-t/τ < 1 / 2N+1 (½ LSB), t > τ (N+1) ln 2

Integrating ADCDual slope integrating ADC. c0 and c1 are control signals

Vx

Counter and control logic not shown.

Integrating ADCIn phase 1, -Vin is integrated duringa fixed interval (T1). In phase 2, Vx isintegrated (discharged) by Vref. A digital counter is running from the start of phase 2 while Vx > 0. The counter value is the digital output.

Integrating ADC

Need many clock cycles to complete the conversion (slow), but can achieve high accuracy. A simpler alternative is the single slope ADC, which counts how long it takes to integrate Vref to Vin. (Less accurate).

Resources

B. Murmann, “ADC performance survey 1997–2012,” [Online]. Available: http://www.stanford.edu/~murmann/adcsurvey.html

“IEEE Standard for Terminology and Test Methods for Analog-to-Digital Converters,” IEEE Std 1241-2010 (Revision of IEEE Std 1241-2000). http://dx.doi.org/10.1109/IEEESTD.2011.5692956

References

Baker, CMOS: Circuit Design, Layout, and Simulation, IEEE Wiley, 2010 Johns and Martin, Analog Integrated Circuit Design, Wiley, 1997 Sansen, Analog Design Essentials, Springer, 2006, Ch. 20

INF4420ΔΣ data converters

Spring 2012 Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no)

Outline Oversampling Noise shaping Circuit design issues Higher order noise shaping

IntroductionSo far we have considered so called Nyquist data converters.

Quantization noise is a fundamental limit.

Improving the resolution of the converter, translates to increasing the number of quantization steps (bits). Requires better component matching, AOL > β-1 2N+1, and

GBW > fs ln 2N+1 π-1 β-1.

IntroductionΔΣ modulator based data converters relies on oversampling and noise shaping to improve the resolution.

Oversampling means that the data rate is increased to several times what is required by the Nyquist sampling theorem.

Noise shaping means that the quantization noise is moved away from the signal band that we are interested in.

Introduction

We can make a high resolution data converter with few quantization steps! The most obvious trade-off is the increase in speed and more complex digital processing. However, this is a good fit for CMOS. We can apply this to both DACs and ADCs.

OversamplingThe total quantization noise depends only on the number of steps. Not the bandwidth. If we increase the sampling rate, the quantization noise will not increase and it will spread over a larger area. The power spectral density will decrease.

OversamplingTake a regular ADC and run it at a much higher speed than twice the Nyquist frequency.

Quantization noise is reduced

because only a fraction remains

in the signal bandwidth, fb.

Oversampling Doubling the OSR improves SNR by 0.5 bit

Increasing the resolution by oversampling is not practical. We can do better! Oversampling is almost always used with noise shaping.

Noise shaping

The idea behind noise shaping is to suppress the noise in the signal band, at the expense of increasing noise at higher frequencies. The ΔΣ modulator does noise shaping.

Noise shapingLinear discrete time model Two independent inputs, u and e. We derive a transfer function for the signal and quantization noise separately.

Noise shaping

Signal transfer function

(STF), Hs

Noise shaping

Noise transfer function

(NTF), Hn

Noise shaping

Noise shaping

NTF frequency response

Noise shapingFirst order ΔΣ modulator based data converter Assuming full-scale sine wave input (as before) Doubling OSR improves SNR by 1.5 bits

NTF OSR

Circuit exampleFirst order ΔΣ ADC (sampled data single bit quantizer) implementation.

Single-bit quantizationQuantizer nonlinearity is shaped by the NTF, but still needs to be less than the inherent quantization noise.

Feedback signal does not undergo shaping and adds directly to the input. Needs linearity better than the equivalent resolution of the ADC.

Single bit quantizer: Only two levels, inherent linearity. (Second order effects: switching, etc.)

Single-bit quantizationLinear analysis assumed quantization noise is white, however input signal may give rise to patterns in the quantization noise. Quantization noise energy will be clustered at some frequencies. Tones in the output signal.

Idle tones or pattern noise for DC input.

Intentionally add noise to decorrelate the quantization noise pattern, dithering.

Multi-bit quantizationSingle bit quantization will introduce significant (out of band) quantization noise which must be attenuated by a filter. We have assumed a brick-wall filter in our analysis.

Multi-bit quantization will reduce the inherent quantization noise, and performance is better predicted by the linear analysis.

Linearity is challenging (no shaping).

Multi-bit quantization

Several techniques for linearizing the DAC (not discussed further, see Schreier, 2005):● Dual quantization● Mismatch shaping● Digital correction

IntegratorIn the analysis so far, we have assumed an ideal integrator. Real integrators can only approximate the ideal integrator, because the amplifier has finite gain,bandwidth, offset, etc.

Finite gain

Finite gain will shift the pole of

the integrator from DC (z = 1), to inside

the unit circle (approximately z = 1 - 1 / A0).

NTF affected by finite gain

Finite bandwidthAssuming the amplifier has one dominant pole and negligible non-dominant poles.

Must allow sufficient time for settling, the settling error is proportional to

Gain error due to bandwidth and passives introduce poles in both STF and NTF

2. order noise shaping

Introduce one more integrator to achieve better noise suppression (at low frequencies).

NTF is now a second order differentiator.

2. order noise shapingDoubling the OSR improves the SNR by 2.5 bits. Compared to 1.5 bits for 1. order.

Higher order noise shapingNoise shaping can be improved even further by using a 3. order (or higher) modulator.

Possible to design the gain of each integrator to shape the NTF.

Difficult to guarantee stability. Instead we can build a higher order modulator from a cascade of lower order modulators: Multi-stage noise shaping (MASH).

Multi-stage noise shaping

Y1(z)

Y2(z)

Multi-stage noise shaping Choose H1(z) and H2(z) such that E1(z) is canceled.

E.g. H1(z) = k Hs2(z) and H2(z) = k Hn1(z).

Multi-stage noise shapingCascading an L-th order and an M-th order modulator results in an overall L + M order modulator, but prone to instability.

Non-ideal effects because Hs2(z) and Hn1(z) are in analog, while H1(z) and H2(z) are in digital. Imperfections in the analog circuitry (offset, gain, etc.) will deteriorate the noise suppression.

Oversampling DAC

● Interpolation increases the sampling rate● ΔΣ modulator quantizes and shapes noise

(digital integrator)

Interpolation

Resources Schreier and Temes, Understanding Delta-Sigma Data Converters, IEEE Wiley, 2005 Johns and Martin, Analog Integrated Circuit Design, Wiley, 1997

INF4420Ring oscillators

Spring 2012 Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no)

Outline

Barkhausen criterion Ring oscillators Voltage controlled oscillators Oscillator phase model

IntroductionOscillators are used for synchronizing computation in a digital system, timing the sampling in a data converter, carrier synthesis and LO in RF systems, etc ...

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IntroductionDifferent applications have very different requirements on accuracy and stability (e.g. jitter in data converters, timing violations, BER, etc.)Crystal oscillators are used for demanding applications. Excellent stability and frequency accuracy. Speed limitation and cost issues.

Feedback system Usually, we want the feedback system (amplifier) to be stable (difficult to guarantee stability). Now we want to ensure sustained oscillation at a fixed frequency (also difficult).

Feedback system Phase shift of 180 degrees at some frequency, ω0, gives positive feedback. Each time the signal "goes around the loop". Amplifier input, Vx, grows indefinitely if |H(jω0)| > 1

Barkhausen criterion

The criteria for oscillation is not well understood, there is no known sufficient criteria for oscillation.

The Barkhausen stability criterion is necessary but not sufficient for oscillation.

OscillatorsLC oscillator, inductor, L, and capacitor, C, to generate resonance Used mostly for RF (inductors are expensive and impractical).

Relaxation oscillators typically relies on charging and discharging a capacitor. Some active circuit will monitor and switch charging at a threshold.

Ring oscillatorRing oscillators are made from gain stages, or delay stages, in feedback.

We will first do a linear analysis of these oscillators with common source (CS) elements.

Ring oscillatorA single CS stage in feedback will not oscillate, because it does not fulfill the Barkhausen criteria.

The CS stage is inverting (180°) and has one pole (90°), 270° phase shift in total.

Ring oscillatorUsing two CS stages gives the required phase shift, but it is stable at either rail.

Ring oscillatorStill no sustained oscillation because the gain is much less than one when phase is inverted.

Ideal

Ring oscillatorThree CS stages are enough for sustained oscillation provided the gain of each stage is sufficient (in this case, A0 ≥ 2).

Ring oscillatorIf the gain of each stage is larger than necessary, A0 > 2, the output will saturate and linear analysis becomes difficult.

Ring oscillator

The frequency of oscillation becomes 1 / (2n τ), where n is the number of elements, and τ is the delay due to each element (inverter in this case).

Fully differential oscillatorSingle ended oscillators are power efficient and capable of rail-to-rail output. However, as we now know, in mixed signal circuits there is supply and substrate noise which couples directly into the oscillator, or modulates its supply voltage. Causing undesirable fluctuations in the period time of the output signal.

Fully differential circuits have CMRR and PSRR to combat this!

Fully differential oscillatorThe trip point for each stage is now the crossing of the inputs rather than a fraction of Vdd. Ideally, coupled noise will only affect the common mode. However, swing is not rail-to-rail.

In addition to rejecting coupling noise, the fully differential oscillator allows the number of stages to be even, which is a significant advantage if we need to generate a number of output phases.

Fully differential oscillator

Constant bias current.

In most cases, the resistors will be implemented by MOS transistors, requiring a bias circuit.

Symmetric load delay cellPopular choice for implementing the fully differential delay cell.

The symmetric load approximates a voltage controlled resistor Maneatis, JSSC, 1996

Symmetric load delay cell

Pseudo differential

Pseudo differential elements are common in many applications. Rail-to-rail swing. Trip point defined by Vdd (worse CMRR).

Tuning output frequencySo far, the oscillators have a "fixed" output frequency. Deviation from the ideal output frequency is undesirable (modulated by the PVT condition, and perturbed by external and internal noise sources). VCOs have an input terminal that allows external control of the frequency.

Voltage controlled osc.

Voltage controlled osc.

Different schemes for controlling the output frequency.

● Modulating the driving strength● Modulating the load

Control signal is usually a voltage (VCO) or a current (CCO). Sometimes a V/I converter is used to interface a CCO with a voltage signal.

Ring oscillator VCO

Several possibilities for implementing the delay stages and tuning circuit.

Ring oscillator VCOStarved inverter delay element

Starved inverter bias circuit

Ring oscillator VCO

Several specifications to consider

● Tuning range● Linearity (ωout vs. Vctl)● Amplitude● Power● CMRR, PSRR● Jitter (phase noise)● ...

Mathematical model

Mathematical modelPhase is not directly observable in a real oscillator. However, from observing the zero crossings of the output, we see when the phase has increased by π.

The rate of change of the phase, ϕ, is the frequency, ω.

Phase is the integral of frequency. Conversely, frequency is the derivative of the phase.

Mathematical model

Resources McNeill and Ricketts, The Designer’s Guide to Jitter in Ring Oscillators, Springer, 2009.

INF4420Phase locked loops

Spring 2012 Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no)

Outline

"Linear" PLLs

Linear analysis (phase domain)

Charge pump PLLs

Delay locked loops (DLLs)

Applications

Introduction

Phase locked loops (PLLs) are versatile building blocks found in a variety of applications

● Frequency multiplication● Frequency synthesis● Clock deskew (PLL or DLL)● Clock recovery (from serial data)● Demodulation● ...

IntroductionFeedback system for aligning (a fraction of) the phase of the VCO clock with an (external) reference clock. The VCO control voltage is adjusted to achieve this.

IntroductionWe will analyze the PLL in terms of phase. The objective of the feedback loop, the PLL, is to keep ϕref - ϕout small and constant. In this state, the PLL is said to be in lock.

This implies ωref = ωout which is what we care about in many applications.

"Linear" PLL

We will first analyze a PLL with a simple phase detector (PD) first.

Phase detector

Loop filter

Phase detectorPhase is not directly observable. We have to infer the phase difference from the output of the oscillators.

An XOR gate can be used as a phase detector.

Phase detector When ϕref and ϕout is 90° out of phase, the XOR output will have 50/50 duty cycle, and the average output will therefore be Vdd / 2. If ϕref and ϕout is at 0° or 180° phase difference, the average output will be 0 or Vdd respectively.

Phase detector

PLL with XOR PD

With the XOR PD, to generate the required Vctl, ϕref and ϕout must be out of phase.

Loop dynamicsLinear analysis of the PLL in terms of phase, H(s) = ϕout(s) / ϕin(s).

Second order TF

Natural frequency

Damping ratio

Generic second order transfer function applied to the PLL:

Loop dynamicsBy choosing PLL parameters, KVCO, KPD, and

τLF, we can design ωn and ζ, to obtain the desired loop dynamics.

Magnitude response Step response

Large signal behaviourAn important point for PLLs is the large signal behaviour when the system is not in lock. When the PLL starts up, ϕref and ϕout may be very different. We must make sure that the system is able to achieve lock. Another concern is whether the PLL will lock to a harmonic instead.

The PLL with XOR based PD is not robust in this case. In most applications, a so called charge pump (CP) PLL is preferred.

Charge pump PLLTracks whether the reference edge or the VCO clock edge comes first (for every period), and adjusts the VCO control voltage accordingly to keep the PLL in lock. When the PLL is in lock, out and ref will be in phase.

Phase frequency detector Loop filter

Charge pump

Phase Frequency DetectorIn the Charge Pump (CP) PLL, a more elaborate PD with state is used, a Phase Frequency Detector (PFD).

PDF/CP and loop filterThe PFD generates control signals for the CP to ramp up or down the VCO control voltage.

PFD/CP gainWhen the PLL is in lock, a small phase difference between the VCO clock (out) and the reference clock (ref) turns on the CP for a fraction of the clock period injecting a charge proportional to the phase error to the loop filter every period. Looking at several periods, an average current flows. KPFD is the combined gain of the PFD and the CP:

CP loop filterThe loop filter is driven by Iavg from the PFD/CP

In many cases, a second capacitor, C2, is added in parallel to reduce glitches. C2 is usually chosen to be approximately 10 % of C1 or less.

Transfer functionThe open loop transfer function from ϕref to ϕout

The closed loop CP PLL transfer function

Transfer function

R gives rise to a zero at -1/(RC). It is required as system would be unstable with R = 0.

Non-ideal effects in PLLs

● PFD/CP will exhibit zero gain when the phase difference is small because of finite rise and fall times

● Up/down current mismatch due to timing or current source impedance

● Jitter from power supply, coupling, electronic noise, reference phase noise

● ...

Delay locked loop (DLL)A DLL is similar to a PLL, but instead the delay through a voltage controlled delay line (VCDL) is locked.

Delay locked loop (DLL)Noise (jitter) does not accumulate in the delay line like it would in a VCO.

As there is no VCO, the order of the loop is one less than the PLL. Stability and settling issues are less prominent.

The DLL is not the same as a PLL and only relevant for some PLL applications. DLLs are usually preferred where applicable.

Frequency multiplicationFrequency multiplication is a common application for PLLs. High speed clocks can be generated from a stable and precise (but slow) reference clock. N can be programmable.

Frequency demodulationThe VCO performs frequency modulation (FM). The PLL can be used to find the inverse. The VCO control voltage becomes the output.

Other PLL issues

We have used a continuous time analysis for the PLL. However, the PFD samples the phase. We approximated the PFD/CP output as an average current.

When the deglitching capacitor, C2, is used, the transfer function becomes third order. Using the second order transfer function may not be appropriate.

Resources

Gardner, Phaselock Techniques, Wiley, 2005

Fischette, Dennis Fischette's 1-Stop PLL Center

Johns and Martin, Analog Integrated Circuit Design, Wiley, 1997