Proceedings of IETE 37th MTS:ICTIRD-2006, Kolkata, India P31-1

Abstract--Design of incremental encoder interface involves designing a circuit to decode the positional and directional data embedded in the output signals of the encoder , as well as designing a counter circuit to count the number of pulses. This can be done either by using a custom IC or 5-10 discrete ICs. Four monostable circuits would be needed to implement the direction sensing unit. However, with the increase in number of components, system reliability is reduced. Also, systems are easily susceptible for interference by noise. This paper presents a way of implementing the above functions using software only. In addition, the paper provides a mechanism for efficient error correction, thus making it suitable for servomotor control designs, even under noisy conditions. Index Terms--biphase , control system , encoder reader circuit , error correction , forward pulse train , microcontroller .

I. INTRODUCTION

Whenever mechanical rotary motions have to be monitored, an encoder is the most important interface between the mechanics and the control unit. Encoders transform rotary movement into a sequence of electrical pulses. As a single channel can detect only incremental rotation, a second signal, phase shifted by 90 degrees is also generated. This second signal, along with the first signal, enables the direction of rotation to be determined. The two signals from channel A and B are shown in Fig. 1 ___________________________ 1Arindam Sanyal is a B. E. Tel. E student of the Department of Electronics & Tele-Communication , Jadavpur University , Kol-32. ( email : arindam_3110@yahoo.co.in ) (Corressponding author). 2Snehasish Das is a B. E. Tel. E student of the Department of Electronics & Tele-Communication , Jadavpur University, Kol-32. ( email : snehasishetce@yahoo.co.in ). 3Sonai Ray is a M. S student of Computer Science and Engineering in IIT Kharagpur ( email : sonai@cse.iitkgp.ernet.in). 4P.Venkateswaran is with the the Department of Electronics & Tele-Communication , Jadavpur University , Kol-32 ( email : pvwn@ieee.org). 5S.K.Sanyal is with the Department of Electronics & Tele-Communication , Jadavpur University, Kol-32. ( email : s_sanyal@ieee.org) ER.Nandi is with the Department of Electronics & Tele-Communication , Jadavpur University , Kol-32. ( email : robnon@ieee.org).

Fig. 1. Typical encoder waveform showing channel B being 900 offset from channel A An incremental biphase encoder is the most commonly used device in computer-controlled feedback system. The microcomputer actuates several final control elements based on the information obtained from the encoder. In addition to providing positional and directional information[1], the encoder interface circuit must also perform some special functions to maintain proper operations, such as missing pulse correction, error correction, resetting the position counter based on control signal from the microcomputer, etc. It requires 5-10 discrete ICs to implement all the above functions. Also, certain types of combinational logic are error prone due to gate delays or threshold offsets and multivibrator imprecisions. This paper tries to do away with these errors as well as reducing drastically the amount of hardware needed. The scheme is explained in section II and the implementation details are given in section III.

II. PROPOSED SCHEME

A. Edge Detection algorithm The change of states of signals A and B (Fig. 1) can be represented in the form of the following state diagram (Fig. 2).

channel A

channel B

Incremental Encoder Reader Circuit with Error Detection and Correction using Microcontroller

1Arindam Sanyal, 2Snehasish Das, 3Sonai Ray, 4P.Venkateswaran, 5S.K.Sanyal and 6R.Nandi

Proceedings of IETE 37th MTS:ICTIRD-2006, Kolkata, India P31-2

Fig. 2 State transition diagram of a biphase incremental encoder. Dashed lines indicate erroneous transition. The above state diagram has been formed taking the value of channel A as the msb ( most significant bit ) and the value of channel B as the lsb ( least significant bit ). The state transition from 00→01→11 →10 is denoted by FPT( forward pulse train )[2] and the state transition from 00→10→11→01 is denoted by RPT ( reverse pulse train ). The erroneous state transitions are shown by dotted lines. From the state diagram it can be seen that for no state change, 01 =−⊕ nAnA and 01 =−⊕ nBnB where nA

and nB denote the nth states of A and B. For an FPT, 01 =−⊕ nBnA and, 11 =−⊕ nAnB and , for an RPT ,

11 =−⊕ nBnA and 01 =−⊕ nAnB , provided a valid transition has occurred. The program detects all the four edges (Fig. 1) in a single cycle. So any missing edge must be due to an erroneous transition. From the state diagram(Fig. 2), it is seen that if any erroneous transition occurs, then 11 =−⊕ nAnA and 11 =−⊕ nBnB . This algorithm forms the basis of decoding the positional and directional information from the output signals of the biphase encoder. However, there may be errors due to excessive noise. There are two ways to handle this error: (i) the program increments an error counter at every instance of an error and if the error counter exceeds a given limit, it sends a proper signal to the main system , (ii) otherwise, the program automatically corrects the error. The error handling mechanism is explained in the next section. B. Error Handling algorithm

The error handling algorithm follows readily from the previous algorithm. The error correction is done by first

determining whether the state transition is in the forward or reverse direction, and then generating the proper signal. The direction of the current state transition is determined on the basis of two previous transitions. If the transition is an FPT and an error has occurred, then the present state is given by 1−= nBnA and 111 ⊕−=− nAnB and , if the transition is an RPT, then the present state is given by

11 ⊕−= nBnA and 1−= nAnB . Thus, any error in the signals A and B can be readily corrected. However, the noise interference may be such that it gives rise to a valid transition. The algorithm can be used to give the correct number of transitions even in such a case. An error will occur if due to the noise, a ‘1’ appears as a ‘0’ and vice versa. If a spike occurs in any channel, it can be considered as an FPT and an RPT in succession. The program uses a counter to store the number of transitions. The counter is incremented by 1 for every forward transition and decremented by 1 for every reverse transition. Thus, there will be no change in the value of the counter due to the spike. If the spike triggers an erroneous transition, then the program will automatically correct the error and generate the correct state. This has been explained with simulation diagrams in the next section.

III. IMPLEMENTATION We have used Intel 8031 Microcontroller[3,4] to implement the reader circuit. We have also used UMPS demo version 1.75C to simulate the encoder reader circuit. We have used DS80C320 microcontroller to simulate the reader circuit. In both the hardware implementation as well as the simulator implementation, channel A was connected to port pin P1.1 and channel B was connected to port pin P1.0. The interface output was seen at port pin P1.2. The output shows a transition for every edge detected. The number of valid transitions are stored in the register R0. Its value is shown in the snapshots of the two simulation diagrams(Fig. 3 and Fig. 4) given below. In Fig. 3 below, we had taken two error free inputs as signals A and B. We had simulated 8 cycles of signals A and B and the value of position counter stored in register R0 correctly gives the number of transitions as 32. In Fig. 4 , we had

00

11

10 01

Proceedings of IETE 37th MTS:ICTIRD-2006, Kolkata, India P31-3

simulated in the presence of noise, thus leading to distorted signals A and B. In this case also, the value of program counter is 32 as it should have been if the signals were error free.

Fig. 3 Snapshot of the simulated waveform in the absence of noise

Fig. 4 Snapshot of the simulated waveform in the presence of noise

Proceedings of IETE 37th MTS:ICTIRD-2006, Kolkata, India P31-4

IV. CONCLUSION

An efficient error correction mechanism for biphase encoder interface circuit has been described. The implementation details and the simulation results have also been given. Using this implementation, the system reliability can be increased thus making it a favourable tool for automatic control system.

V. REFERENCES

[1] E. S. Tez, “Interfacing bi-phase incremental encoders”, IEEE Trans. Ind. Electron, Vol. IE – 33, No. 3, Aug. 1986, pp. 337-339 [2] Bernard Hebert, Michel Brule and Louis- A. Dessaint , “A high efficiency interface for a biphase incremental encoder with error detection” , IEEE Trans. Ind. Electron, Vol. 40, No. 1, Feb. 1998, pp. 155. [3] Myke Predko Programming and Customizing the 8051 Microcontroller, Tata McGrawHill Edition, New Delhi, 1999. [4] Advanced Electronic Systems “ALS SDA – 8031 Microcontroller Kit User’s Manual”, , Bangalore, India. .