(INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks...
Transcript of (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks...
![Page 1: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/1.jpg)
Computer Organization and Networks(INB.06000UF, INB.07001UF)
Winter 2020/2021
Stefan Mangard, www.iaik.tugraz.at
Chapter 3 – State Machines
![Page 2: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/2.jpg)
What About Storage?
• We have so far only considered functions
• We also want to store data and define sequences of computation
• So far, we have not talked about storage or about time
www.iaik.tugraz.at
2
![Page 3: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/3.jpg)
Storage
www.iaik.tugraz.at
3
![Page 4: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/4.jpg)
Storage
(“Vdd”, “high”, “1”)
(“GND”, “low”, “0”)
Register
Clock
N bitoutput
N bit data input
4
![Page 5: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/5.jpg)
Storage
(“Vdd”, “high”, “1”)
(“GND”, “low”, “0”)
Register
Clock
N bitoutput
N bit data input
• The registers sets output = input when the clock switches from low to high;
• In all other cases, the input is ignored; the last “sampled” value is kept at the output
Clock
5
![Page 6: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/6.jpg)
Naming Conventions
• Register: An n-bit storage sampling data on the rising clock edge
• Flip Flop: A 1-bit storage sampling data on the rising clock edge
6
![Page 7: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/7.jpg)
A Master-Slave Flip-Flop based on CMOS Gates
7
![Page 8: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/8.jpg)
Combining
(“Vdd”, “high”, “1”)
(“GND”, “low”, “0”)
RegistersCombinational
Circuit
Data Input Data Output
8
![Page 9: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/9.jpg)
Example Counter
(“Vdd”, “high”, “1”)
(“GND”, “low”, “0”)
Registers +1
Data Input Data Output
9
![Page 10: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/10.jpg)
Example Counter
Registers +1
Data Input Data Output
Register 0 1 2 3 4 5 6 7 …..
Clock
10
![Page 11: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/11.jpg)
Let’s Build This in Logisim
• See examples con03 available at
https://extgit.iaik.tugraz.at/con/examples-2020.git
11
![Page 12: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/12.jpg)
The Clock Frequency
• Can we increase the clock frequency arbitrarily?
• The clock frequency is limited by the time the combinational circuit needs to compute its outputs.
• The critical path is the path with the longest propagation delay in the combinational circuit. It defines the maximum clock rate
12
RegistersCombinational
Circuit
Data Input Data Output
![Page 13: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/13.jpg)
Temperature, Power Consumption
• The higher the temperature, the slower the transistors become and the lower becomes the maximum clock rate
→ The lower the temperature, the higher clock rates are possible
• Why does a CPU produce heat?
• Every time a logic gate switches, NMOS and PMOS transistors are open at the same time → there is a short current.
• Upon a switch, there is also current flowing to charge and discharge parasitics
→ The more transistors are switching, the more heat is produced
13
![Page 14: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/14.jpg)
Clock Frequency Too High
What happens, if the clock frequency is too high?
• The circuit stores an intermediate state of the combinational circuit in the registers.
• The intermediate state depends on the physical layout, the temperature, fabrication details, … → hard to predict; overclocking a processor too much typically leads to a crash
14
![Page 15: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/15.jpg)
SystemVerilog
www.iaik.tugraz.at
15
![Page 17: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/17.jpg)
SystemVerilog coding style
• Suffix _o for module outputs, _i for module inputs
• Register variables with suffix _p for previous and _n for next value
• Clocked processes only update registers,everything else has to be done in combinational blocks
• Clocked processes use non-blocking (<=) others use blocking assignments (=)
• Filename corresponds to module name: module MyDesign in file mydesign.sv
• Module instantiation always with named assignments (.A(C))
• Always use default assignments (state_n = state_p)
• Array range with [MSB:LSB], like e.g. [31:0]
• Toolchain issue: Always use default branches (default:) in case statements
• Toolchain issue: Use always @(*), not always_comb
![Page 18: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/18.jpg)
Overview of Coding Guidelines
www.iaik.tugraz.at
18
RegistersCombinational
Circuit
Data Input Data Output
always @*
Use Blocking Assignmentsa = b;
always_ff @(posedge clk_i or posedge reset_i)
Use Non-Blocking Assignmentsa_p <= a_n;
_o_i
_n _p
![Page 19: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/19.jpg)
State Machines
www.iaik.tugraz.at
19
![Page 20: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/20.jpg)
Finite State Machines (FSMs)
• FSMs are the “work horse” in digital systems.
• FSMs can be implemented with hardware.
• We look at “synchronous” FSMs only:• The “clock signal” controls the action over time
• FSMs can be described with three main “views”:• The functional view with the “state diagram”
• The timing view with the “timing diagram”
• The structural view with the “logic circuit diagram”
20
www.iaik.tugraz.at
![Page 21: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/21.jpg)
Time flows continuously
time
21
www.iaik.tugraz.at
![Page 22: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/22.jpg)
We cut time into slices
time
22
www.iaik.tugraz.at
![Page 23: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/23.jpg)
Time slices are strictly ordered
i i+1 i+2i—1 i—2
time
23
www.iaik.tugraz.at
![Page 24: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/24.jpg)
Clock signal
i i+1 i+2i—1 i—2
0
1
time
We use the clock signal (“clk”) in order to advancetime from slice to slice.
24
www.iaik.tugraz.at
![Page 25: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/25.jpg)
Rising clock edge
i i+1 i+2i—1 i—2
0
1
time
With rising clock edges we define the transition between neighboring time slices.The negative clock edges have no importance.
25
www.iaik.tugraz.at
![Page 26: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/26.jpg)
Clock period
i i+1 i+2i—1 i—2
0
1
clockperiod
time
We call the time between two rising clock edges also “clock period”.Most often, clock periods have the same length. But this is not necessarily the case. 26
www.iaik.tugraz.at
![Page 27: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/27.jpg)
Synchronous finite state machine (= automaton)
FSM
clk
A synchronous FSM is clocked by a clock signal (“clk”). In each clock period, the machine is in a defined (current) state.With each rising edge of the clock signal, the machine advances to a defined next state.
We are interested in “finite state machines” (FSMs). FSMs have only a finite number of states.
27
www.iaik.tugraz.at
![Page 28: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/28.jpg)
The sequence ofstates can bedefined in a state diagram.
28
www.iaik.tugraz.at
![Page 29: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/29.jpg)
State diagram:
We denote thestates with circlesand give them symbolic names,e.g. A, B, and C.
A
B
C
29
www.iaik.tugraz.at
![Page 30: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/30.jpg)
State diagram:
We define one of the states as theinitial state.
A
B
C
30
www.iaik.tugraz.at
![Page 31: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/31.jpg)
In the beginning…
0
1
time
Initially, i.e. shortly after switching on the FSM and before the first rising edge of clock, there is the initial period. In this period,the FSM is in the “initial state”.
initial period
A
31
www.iaik.tugraz.at
![Page 32: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/32.jpg)
State diagram:
With arrows wedefine the sequenceof states.
A
B
C
32
www.iaik.tugraz.at
![Page 33: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/33.jpg)
The sequence ofstates can also be defined in a state transitiontable.
A
B
C
presentstate
ABC
next state
BCA
33
www.iaik.tugraz.at
![Page 34: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/34.jpg)
Timing diagram
0
1
B
clk
A CC BAstate
time
Initially, the FSM is in the initial state A.
With every positive clock edge, the next statebecomes the current state.
An FSM has always a next state.34
www.iaik.tugraz.at
![Page 35: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/35.jpg)
In order to technically realize (“implement”) a state diagram,
we start by giving each state a unique number.
A
B
C
www.iaik.tugraz.at
35
![Page 36: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/36.jpg)
Popular state-encoding schemes
• Binary encoding• needs minimum amount of flip-flops.
• One-hot encoding• Tends to have a simpler next-state logic.
36
A
B
C
www.iaik.tugraz.at
![Page 37: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/37.jpg)
Binary encoding
00
01
10
state
ABC
number
000110
37
www.iaik.tugraz.at
![Page 38: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/38.jpg)
Binary encoding:The state transition tablehas also only binary numbers.
00
01
10
presentstate
000110
next state
011000
www.iaik.tugraz.at
38
![Page 39: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/39.jpg)
We also enter the unused combination “11”. This state does not exist. “x” stands for “Don’t care”.
00
01
10
presentstate
00011011
next state
011000xx
www.iaik.tugraz.at
39
![Page 40: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/40.jpg)
We define names forthe two state bits, e.g. s1, s0.
00
01
10
presents1 s0
0 00 1 1 01 1
next s1 s0
0 11 00 0x x
www.iaik.tugraz.at
40
![Page 41: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/41.jpg)
Each state bit is stored in a flipflop
flipflop stored value
41
www.iaik.tugraz.at
![Page 42: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/42.jpg)
A flipflop stores a new value, when a rising edge occurs on the clock input
flipflop stored value
clock
42
www.iaik.tugraz.at
![Page 43: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/43.jpg)
The flipflop stores the value, which it sees on its input.
flipflop stored value
clock
input
43
www.iaik.tugraz.at
![Page 44: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/44.jpg)
Summary: A D-flip-flop samples its input value D and stores this value when a rising edge of clk occurs
stored value
clk
input D Q
Thus, a D-type flipflop can be seen as a 1-bit photo camera.44
www.iaik.tugraz.at
![Page 45: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/45.jpg)
In our example, we need 2 flip-flops for storing the state bits.
s1
clk
next s1 D1 Q1
Flipflops which can store several bits are also called “registers”.
s0next s0 Q0D0
45
www.iaik.tugraz.at
![Page 46: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/46.jpg)
We use the state transition table as a “lookup table”…
s1
clk
D1 Q1
s0Q0D0
present s1 s0
0 00 1 1 01 1
next s1 s0
0 11 00 0x x
next s1
next s0
46
www.iaik.tugraz.at
![Page 47: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/47.jpg)
…and thus find out the next state
s1
clk
D1 Q1
s0Q0D0
present s1 s0
0 00 1 1 01 1
next s1 s0
0 11 00 0x x
47
www.iaik.tugraz.at
![Page 48: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/48.jpg)
At each positive edge of clk, the next state gets stored as the current state.
s1
clk
D1 Q1
s0Q0D0
presents1 s0
0 00 1 1 01 1
next s1 s0
0 11 00 0x x
48
www.iaik.tugraz.at
![Page 49: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/49.jpg)
In order to get the initial state “00”, we use flipflopswith an “asynchronous reset input”. Shortly after switching on the circuit, we apply “areset”.
s1
clk
D1 Q1
s0Q0D0
presents1 s0
0 00 1 1 01 1
next s1 s0
0 11 00 0x x
areset49
www.iaik.tugraz.at
![Page 50: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/50.jpg)
The state transition function in this example can be derived from the truth table:next s0 = (~s1) & (~s0)
s1
clk
D1 Q1
s0Q0D0
presents1 s0
0 00 1 1 01 1
next s1 s0
0 11 00 0x 0
aresetWe set the don’t care to 0.
50
www.iaik.tugraz.at
![Page 51: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/51.jpg)
The state transition function:next s0 = (~s1) & (~s0)next s1 = (~s1) & s0
s1
clk
D1 Q1
s0Q0D0
presents1 s0
0 00 11 01 1
next s1 s0
0 11 00 00 0
aresetWe set this don’t care value also to 0.
51
www.iaik.tugraz.at
![Page 52: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/52.jpg)
Structural diagram of the FSM:State-transition function, storage elements, and feedback of state.
next s0 = (~s1) & (~s0)
next s1 = (~s1) & s0
clk
D1 Q1
Q0D0
areset
next s0
next s1
s0
s1
52
www.iaik.tugraz.at
![Page 53: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/53.jpg)
Essence so far
State diagram:
“next state” is a function of (present) “state”
State transitions:
the “next state” becomes (the present) “state” on the rising edge of the clock
53
www.iaik.tugraz.at
![Page 54: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/54.jpg)
The FSM modeled and simulated with Logisim
54
www.iaik.tugraz.at
![Page 55: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/55.jpg)
For a SystemVerilog example of this FSM see
con03_fsm_moore_no_input
and
con03_fsm_moore_no_input_named_states
55
www.iaik.tugraz.at
![Page 56: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/56.jpg)
Inputs
56
www.iaik.tugraz.at
![Page 57: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/57.jpg)
FSMs can also have inputs influencing the transition to the next state
A
B
Cin == 0
in == 1
next state = f(state, input)
In this example we seethat the one-bit input “in” influences the choice ofthe state after B.
57
www.iaik.tugraz.at
![Page 58: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/58.jpg)
FSMs can also have inputs influencing the transition to the next state
A
BC
in == 0
in == 1
next state = f(state, input)
In this example we seethat the one-bit input “in” influences the choice ofthe state after B.
The following state can alsobe the same as the current state.
in == 0
in == 1
58
www.iaik.tugraz.at
![Page 59: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/59.jpg)
The state transition table
A
BC
in == 0
in == 1
in == 0
in == 1
present in nextstate state
A 0 BA 1 BB 0 AB 1 CC 0 AC 1 C
59
www.iaik.tugraz.at
![Page 60: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/60.jpg)
Timing diagram. Example 1
0
1
B
clk
B CA CAstate
time
in
For a timing diagram, we need to choose values for the inputsignal “in”. Only after some choice for “in” we can derive thesequence of states from the state diagram.
0
1
60
www.iaik.tugraz.at
![Page 61: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/61.jpg)
Timing diagram. Example 2
0
1
B
clk
C BC AAstate
time
in
For a timing diagram, we need to choose values for the inputsignal “in”. Only after some choice for “in” we can derive thesequence of states from the state diagram.
0
1
61
www.iaik.tugraz.at
![Page 62: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/62.jpg)
Timing diagram. Example 3
0
1
B
clk
A BC BAstate
time
in
For a timing diagram, we need to choose values for the inputsignal “in”. Only after some choice for “in” we can derive thesequence of states from the state diagram.
0
1
62
www.iaik.tugraz.at
![Page 63: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/63.jpg)
Binary state encoding: Instead of symbolic state names we use numbers
00
0110
in == 0
in == 1
in == 0
in == 1
63
present in nextstate state
0 0 0 0 10 0 1 0 10 1 0 0 00 1 1 1 01 0 0 0 01 0 1 1 0
www.iaik.tugraz.at
![Page 64: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/64.jpg)
“11” does not exist: We use “Don’t Care” as the following state
00
in == 0
in == 1
in == 0
in == 1
0110
64
present in nextstate state
0 0 0 0 10 0 1 0 10 1 0 0 00 1 1 1 01 0 0 0 01 0 1 1 01 1 0 x x1 1 1 x x
www.iaik.tugraz.at
![Page 65: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/65.jpg)
I have ordered the lines in the state transition table from 0 to 7. This makes it easier to “read” the table.
00
in == 0
in == 1
in == 0
in == 1
0110
65
present in nextstate state
0 0 0 0 10 0 1 0 10 1 0 0 00 1 1 1 01 0 0 0 01 0 1 1 01 1 0 x x1 1 1 x x
01234567
www.iaik.tugraz.at
![Page 66: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/66.jpg)
We call the state bits “s1” and “s0”
00
in == 0
in == 1
in == 0
in == 1
0110
66
present in nexts1 s0 s1 s0
0 0 0 0 10 0 1 0 10 1 0 0 00 1 1 1 01 0 0 0 01 0 1 1 01 1 0 x x1 1 1 x x
01234567
www.iaik.tugraz.at
![Page 67: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/67.jpg)
next s0 = ( (~s1) & (~s0) & (~in))| ( (~s1) & (~s0) & in )
00
in == 0
in == 1
in == 0
in == 1
0110
67
present in nexts1 s0 s1 s0
0 0 0 0 10 0 1 0 10 1 0 0 00 1 1 1 01 0 0 0 01 0 1 1 01 1 0 x 01 1 1 x 0
01234567
www.iaik.tugraz.at
![Page 68: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/68.jpg)
next s1 = ((~s1) & s0 & in)| ( s1 & (~s0) & in)
00
in == 0
in == 1
in == 0
in == 1
0110
68
present in nexts1 s0 s1 s0
0 0 0 0 10 0 1 0 10 1 0 0 00 1 1 1 01 0 0 0 01 0 1 1 01 1 0 0 01 1 1 0 0
01234567
www.iaik.tugraz.at
![Page 69: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/69.jpg)
Structural diagram of the FSM
next s0 = ( (~s1) & (~s0) & (~in))
| ( (~s1) & (~s0) & in )
next s1 = ((~s1) & s0 & in) | ( s1 & (~s0) & in)
clk
D1 Q1
Q0D0
areset
next s0
next s1
s0
s1
in
69
www.iaik.tugraz.at
![Page 70: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/70.jpg)
Implementation with Logisim
70
www.iaik.tugraz.at
![Page 71: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/71.jpg)
For a SystemVerilog example of this FSM see
con03_fsm_moore_no_output_function
71
www.iaik.tugraz.at
![Page 72: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/72.jpg)
Outputs
72
www.iaik.tugraz.at
![Page 73: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/73.jpg)
FSMs typically also have outputs
4
32
A
B C
in == 0
in == 1
output = f(state)
In this example we seethat the outputs are a functionof the state. We write the outputvalues into the circles.
We call such machines also“Moore machines”:
in == 0
in == 1
73
www.iaik.tugraz.at
![Page 74: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/74.jpg)
We define the outputs with the “output function”
4
32
A
B
in == 0
in == 1
Moore machines:
output = f(state)
state outputA 4B 3C 2
C
in == 0
in == 1
74
www.iaik.tugraz.at
![Page 75: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/75.jpg)
Timing diagram. Example 3
0
1
B
clk
A AC BAstate
time
in
For a timing diagram, we need to choose values for the inputsignal “in”. Only after some choice for “in” we can derive thesequence of states from the state diagram.
0
1
out 4 3 2 4 3 4
75
www.iaik.tugraz.at
![Page 76: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/76.jpg)
We define the outputs with binary values
100
011010
A
B
in == 0
in == 1
Moore machines:
output = f(state)
state outputA 100 (=4)B 011 (=3)C 010 (=2)
C
in == 0
in == 1
76
www.iaik.tugraz.at
![Page 77: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/77.jpg)
We define the outputs with binary values
100
011010
A
B
in == 0
in == 1
Moore machines:
output = f(state)
state o2 o1 o0 A 1 0 0 B 0 1 1 C 0 1 0
C
in == 0
in == 1
77
www.iaik.tugraz.at
![Page 78: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/78.jpg)
For a SystemVerilog example of this FSM see
con03_fsm_moore_with_output_function
78
www.iaik.tugraz.at
![Page 79: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/79.jpg)
Binary state encoding: We define the outputs with binary values
100
011010
A
B
in == 0
in == 1
state o2 o1 o0 0 0 1 0 0 0 1 0 1 1 1 0 0 1 0
C
in == 0
in == 1
79
www.iaik.tugraz.at
![Page 80: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/80.jpg)
We define the outputs with binary values
100
011010
A
B
in == 0
in == 1
s1 s0 o2 o1 o0 0 0 1 0 0 0 1 0 1 1 1 0 0 1 0
o2 = ~s1 & ~s0
C
in == 0
in == 1
80
www.iaik.tugraz.at
![Page 81: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/81.jpg)
We define the outputs with binary values
100
011010
A
B
in == 0
in == 1
s1 s0 o2 o1 o0 0 0 1 0 0 0 1 0 1 1 1 0 0 1 0
o2 = ~s1 & ~s0
o1 = (~s1 & s0) | (s1 & ~s0)
C
in == 0
in == 1
81
www.iaik.tugraz.at
![Page 82: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/82.jpg)
We define the outputs with binary values
100
011010
A
B
in == 0
in == 1
s1 s0 o2 o1 o00 0 1 0 0 0 1 0 1 11 0 0 1 0
o2 = ~s1 & ~s0
o1 = (~s1 & s0) | (s1 & ~s0)
o0 = ~s1 & s0
C
in == 0
in == 1
82
www.iaik.tugraz.at
![Page 83: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/83.jpg)
Structural diagram of the FSM
next s0 = (~s1 & ~s0 & ~in) | (~s1
& ~s0 & in)
next s1 = (~s1 & s0 & in) | (s1 & ~s0 & in)
clk
D1 Q1
Q0D0
areset
s0
s1
in
o2 = ~s1 & ~s0
o1 = (~s1 & s0)|( s1 & ~s0)
o0 = ~s1 & s0
o2
o1
o0
83
www.iaik.tugraz.at
![Page 84: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/84.jpg)
Implementation with Logisim
84
www.iaik.tugraz.at
![Page 85: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/85.jpg)
Essence of Moore Machines
next s0 = (~s1 & ~s0 & ~in) | (~s1
& ~s0 & in)
next s1 = (~s1 & s0 & in) | (s1 & ~s0 & in)
clk
D1 Q1
Q0D0
areset
s0
s1
in
o2 = ~s1 & ~s0
o1 = (~s1 & s0)| (s1 & ~s0)
o0 = ~s1 & s0
o2
o1
o0
the state is stored in a register
85
www.iaik.tugraz.at
![Page 86: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/86.jpg)
Essence of Moore Machines
next s0 = (~s1 & ~s0 & ~in) | (~s1
& ~s0 & in )
next s1 = (~s1 & s0 & in) | (s1 & ~s0 & in)
clk
D1 Q1
Q0D0
areset
s0
s1
in
o2 = ~s1 & ~s0
o1 = (~s1 & s0)| (s1 & ~s0)
o0 = ~s1 & s0
o2
o1
o0
the state is stored in a register
a state transition is caused by the clock signal.
86
www.iaik.tugraz.at
![Page 87: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/87.jpg)
Essence of Moore Machines
clk
D1 Q1
Q0D0
areset
s0
s1
in
o2 = ~s1 & ~s0
o1 = (~s1 & s0)| (s1 & ~s0)
o0 = ~s1 & s0
o2
o1
o0
the state is stored in a register
a state transition is caused by the clock signal.
With “areset” we can initialize the ASM(“initial state”).
next s0 = (~s1 & ~s0 & ~in) | (~s1
& ~s0 & in )
next s1 = (~s1 & s0 & in) | (s1 & ~s0 & in)
87
www.iaik.tugraz.at
![Page 88: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/88.jpg)
Essence of Moore Machines
next s0 = (~s1 & ~s0 & ~in) | (~s1
& ~s0 & in )
next s1 = (~s1 & s0 & in) | (s1 & ~s0 & in)
clk
D1 Q1
Q0D0
areset
s0
s1
in
o2 = ~s1 & ~s0
o1 = (~s1 & s0)| (s1 & ~s0)
o0 = ~s1 & s0
o2
o1
o0
With the next-state function f we compute the next state:next state = f(state, input)
88
www.iaik.tugraz.at
![Page 89: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/89.jpg)
Essence of Moore Machines
next s0 = (~s1 & ~s0 & ~in) | (~s1
& ~s0 & in )
next s1 = (~s1 & s0 & in) | (s1 & ~s0 & in)
clk
D1 Q1
Q0D0
areset
s0
s1
in
o2 = ~s1 & ~s0
o1 = (~s1 & s0)| (s1 & ~s0)
o0 = ~s1 & s0
o2
o1
o0
With the output function we compute theoutput values:
output = g(state)
89
www.iaik.tugraz.at
![Page 90: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/90.jpg)
Essence of Moore Machines
next-statelogic
state
clk
QD
areset
state
input
out-put
logic
outputnextstate
90
www.iaik.tugraz.at
![Page 91: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/91.jpg)
Essence of Moore Machines (Verilog)
next-statelogic
state
clk
QD
areset
state_p
input
out-put
logic
outputstate_n
91
www.iaik.tugraz.at
always @*
Use Blocking Assignmentsa = b;
always_ff @(posedge clk_i or posedge reset_i)
Use Non-Blocking Assignmentsstate_p <= state_n;
_o
_i
always @*
Use Blocking Assignmentsa = b;
![Page 92: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/92.jpg)
There exist 2 types of machines: check out the LITTLE but IMPORTANT difference
• Moore Machines• next state = function of present state and input
• output = function of present state
• Mealy Machines• next state = function of present state and input
• output = function of spresent tate and input
92
www.iaik.tugraz.at
![Page 93: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/93.jpg)
Essence of Moore Machines
next-statelogic
state
clk
QD
areset
state
input
out-put
logic
outputnextstate
93
www.iaik.tugraz.at
![Page 94: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/94.jpg)
Essence of Mealy Machines
next-statelogic
state
clk
QD
areset
state
input
out-put
logic
outputnextstate
output = g(state, input)
94
www.iaik.tugraz.at
![Page 95: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/95.jpg)
An example for a Mealy Machine
A
B
in == 0out = 3
in == 1out = 1
out = 4 out = 2
We write the output valuesnext to the transition arrows,since the output depends notonly on the state, but can also depend on the input.
C
in == 0
in == 1out = 0
95
www.iaik.tugraz.at
![Page 96: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/96.jpg)
The state transitions are the same as in the previous example with the Moore Machine
A
B
in == 0out = 3
in == 1out = 1
out = 4
present in nextstate state
A 0 BA 1 BB 0 AB 1 CC 0 AC 1 C
C
in == 1out = 0
out = 2in == 0
96
www.iaik.tugraz.at
![Page 97: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/97.jpg)
The output function
A
B
in == 0out = 3
in == 1out = 1
out = 4
The output function can be derived from the state diagram.output = g(state, input)
state in outputA 0 4A 1 4B 0 3B 1 1C 0 2C 1 0
out = 2in == 0
in == 1
out = 0C
97
www.iaik.tugraz.at
![Page 98: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/98.jpg)
Timing diagram
0
1
B
clk
A AC BAstate
time
in
For a timing diagram, we need to choose values for the inputsignal “in”. Only after some choice for “in” we can derive thesequence of states from the state diagram. We see here also, howthe value of “in” immediately influences the value of “out”.
0
1
out 4 3 2 4 3 41 3 1 0
98
www.iaik.tugraz.at
![Page 99: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/99.jpg)
Binary encoding: Re-writing the output table with binary values.
A
B
in == 0out = 3
in == 1out = 1
out = 4
And completing the table with the unused bit combinations.
s1 s0 in o2 o1 o00 0 0 1 0 00 0 1 1 0 00 1 0 0 1 10 1 1 0 0 11 0 0 0 1 01 0 1 0 0 01 1 0 x x x1 1 1 x x x
out = 2in == 0
in == 1out = 0
C
99
www.iaik.tugraz.at
![Page 100: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/100.jpg)
We can derive the logic functions for o2, o1, and o0
s1 s0 in o2 o1 o00 0 0 1 0 00 0 1 1 0 00 1 0 0 1 10 1 1 0 0 11 0 0 0 1 01 0 1 0 0 01 1 0 x x x1 1 1 x x x
o2 = ~s1 & ~s0
100
www.iaik.tugraz.at
![Page 101: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/101.jpg)
We can derive the logic functions for o2, o1, and o0
s1 s0 in o2 o1 o00 0 0 1 0 00 0 1 1 0 00 1 0 0 1 10 1 1 0 0 11 0 0 0 1 01 0 1 0 0 01 1 0 x x x1 1 1 x x x
o2 = ~s1 & ~s0
o1 = (~s1 & s0 & ~in) | (s1 & ~s0 & ~in)
101
www.iaik.tugraz.at
![Page 102: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/102.jpg)
We can derive the logic functions for o2, o1, and o0
s1 s0 in o2 o1 o00 0 0 1 0 00 0 1 1 0 00 1 0 0 1 10 1 1 0 0 11 0 0 0 1 01 0 1 0 0 01 1 0 x x x1 1 1 x x x
o2 = ~s1 & ~s0
o1 = (~s1 & s0 & ~in) | (s1 & ~s0 & ~in)
o0 = ~s1 & s0
102
www.iaik.tugraz.at
![Page 103: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/103.jpg)
The result
next s0 = (~s1 & ~s0 & ~in) | (~s1
& ~s0 & in )
next s1 = (~s1 & s0 & in) | (s1 & ~s0 & in)
clk
D1 Q1
Q0D0
areset
s0
s1
in
o2 = ~s1 & ~s0
o1 = (~s1 & s0 & ~in) | (s1 & ~s0 &
~in)
o0 = ~s1 & s0
o2
o1
o0
103
www.iaik.tugraz.at
![Page 104: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/104.jpg)
Modeling with Logisim
104
www.iaik.tugraz.at
![Page 105: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/105.jpg)
For a SystemVerilog example of this FSM see
con03_mealy
105
www.iaik.tugraz.at
![Page 106: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/106.jpg)
We can combine machines
• Combining Moore Machines causes no problem. We get another Moore Machine.
• Combining a Moore Machine with a Mealy Machine causes also no problem. We get a Moore Machine or a Mealy Machine.
• Combining two Mealy Machines can cause troubles: One needs to avoid combinational loops!
106
www.iaik.tugraz.at
![Page 107: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/107.jpg)
The combination of two Moore Machines creates again a (more complex) Moore Machine
next-statelogic
state
clk
QD
areset
state
input
out-put
logic
outputnextstate
next-statelogic
state
clk
QD
areset
state
input
out-put
logic
outputnextstate
107
www.iaik.tugraz.at
![Page 108: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/108.jpg)
We can even connect More Machines ina loop-like fashion
next-statelogic
state
clk
QD
areset
state
input
out-put
logic
outputnextstate
next-statelogic
state
clk
QD
areset
state
input
out-put
logic
outputnextstate
108
www.iaik.tugraz.at
![Page 109: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/109.jpg)
The combination of a Moore Machine with a Mealy Machine creates a Moore Machine or a Mealy Machine
next-statelogic
state
clk
QD
areset
state
input
out-put
logic
outputnextstate
next-statelogic
state
clk
QD
areset
state
input
out-put
logic
outputnextstate
109
www.iaik.tugraz.at
![Page 110: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/110.jpg)
The combination of a Moore Machine with a Mealy Machine creates a Moore Machine or a Mealy Machine
next-statelogic
state
clk
QD
areset
state
input
out-put
logic
outputnextstate
next-statelogic
state
clk
QD
areset
state
input
out-put
logic
outputnextstate
110
www.iaik.tugraz.at
![Page 111: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/111.jpg)
The combination of two Mealy Machines is “dangerous”: You need to avoid “combinational loops”
next-statelogic
state
clk
QD
areset
state
input
out-put
logic
outputnextstate
next-statelogic
state
clk
QD
areset
state
input
out-put
logic
outputnextstate
111
www.iaik.tugraz.at
![Page 112: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/112.jpg)
The combination of two Mealy Machines is “dangerous”: You need to avoid “combinational loops”
next-statelogic
state
clk
QD
areset
state
input
out-put
logic
outputnextstate
next-statelogic
state
clk
QD
areset
state
input
out-put
logic
outputnextstate
112
www.iaik.tugraz.at
![Page 113: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/113.jpg)
Summary
• All digital logic can in principle be built with Moore Machines and Mealy Machines.
• You always start by defining the function with a state diagram.
• If you choose values for the input signal(s), then you can derive the timing diagram by using the state diagram.
• From a state diagram, you can always derive a circuit diagram.
113
www.iaik.tugraz.at
![Page 114: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/114.jpg)
Algorithmic State Machines
114
www.iaik.tugraz.at
![Page 115: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/115.jpg)
Algorithmic State Machines (ASMs)
• ASMs are a useful extension to finite state machines
• ASMs allow to specify a system consisting of a data path together with its control logic
• All FSM state diagrams have an equivalent ASM diagram
115
www.iaik.tugraz.at
![Page 116: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/116.jpg)
FSM state diagram → ASM diagrams
4
32
B
Cin == 0
in == 1
out = 4A
out = 3
out = 2
in
1
A
B
C
0
116
www.iaik.tugraz.at
![Page 117: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/117.jpg)
Mealy Machines
A
B
Cin == 0out = 3
in == 1out = 1
out = 4out = 2
out = 4
out = 2
in1
A
B
C
0
out = 1 out = 3
117
www.iaik.tugraz.at
![Page 118: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/118.jpg)
Mealy Machines
A
B
Cin == 0out = 3
in == 1out = 1
out = 4out = 2
out = 4
out = 2
in1
A
B
C
0
out = 1 out = 3
118
www.iaik.tugraz.at
![Page 119: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/119.jpg)
Register-Transfer Statements
• Register-transfer statements define the change of a value stored in a register.
• Values in registers can only change at the active (= rising) edge of clock.
• We denote “register-transfer statements” with a “left arrow” (“”)
• Example: “a x” means that the value in the register “a” gets the value of “x” at the “next” active (= rising) edge of clock.
• We can specify register-transfer statement in an ASM diagram.
119
www.iaik.tugraz.at
![Page 120: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/120.jpg)
ASM diagram with two register-transfer statements
out = 4X 0
out = 3
out = 2X X + 1
in
1
A
B
C
0
The value stored in register X gets 0 at the state transition from state A to state B.
The value in register X gets incremented at the state transition following state C.
The value in register X does not changeupon leaving state B.
120
www.iaik.tugraz.at
![Page 121: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/121.jpg)
Timing diagram
0
1
B
clk
A BC BAstate
in0
1
out 4 3 2 4 3 3
X ? 0 0 1 0 0
121
www.iaik.tugraz.at
![Page 122: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/122.jpg)
“=“ versus “”
• With the equal sign (“=“) we denote that the output of the FSM has a certain value during a particular state.
• With the left-arrow (“”) we denote a register-transfer statement: The register value left of the arrow changes to whatever is defined right of the arrow upon the next active (= rising) edge of clock.
122
www.iaik.tugraz.at
![Page 123: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/123.jpg)
Several register-transfer statements can be specified within one state
out = 4X 0Y 0
out = 3Y X
out = 2X X + 1
in
1
A
B
C
0
The values stored in register X and register Y become 0 at the state transition from state A to state B.
The value in register X gets incremented at the state transition following state C.
The value in register X does not changeupon leaving state B. The value stored inregister Y gets the value of register X uponleaving state B.
123
www.iaik.tugraz.at
![Page 124: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/124.jpg)
Several register-transfer statements can be specified within one state
out = 4X 0Y 0
out = 3Y X
out = 2X X + 1
Y X
in
1
A
B
C
0
The values stored in register X and register Y become 0 at the state transition from state A to state B.
The value in register X gets incremented at the state transition following state C.Register Y gets the “old” value from X; i.ethe value before X gets incremented.
The value in register X does not changeupon leaving state B. The value stored inregister Y gets the value of register X uponleaving state B.
124
www.iaik.tugraz.at
![Page 125: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/125.jpg)
For a SystemVerilog example of this ASM see
con03_asm
125
www.iaik.tugraz.at
![Page 126: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/126.jpg)
Separating Control and Data Path
126
www.iaik.tugraz.at
![Page 127: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/127.jpg)
Register-Transfer Statements Define the Data Path
out = 4X 0Y 0
out = 3Y X
out = 2X X + 1
Y X
in
1
A
B
C
0
X 0X XX X+ 1
Y 0Y X
Operations for register X:
Operations for register Y:
127
www.iaik.tugraz.at
These are the actions that our system is able to perform onThe data registers X and Y
![Page 128: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/128.jpg)
Control Unit
• State machine generating control signals for the data path
www.iaik.tugraz.at
128
Data Path• Contains all functional units and
registers related to data processing
• Receives control signals to perform operations on the data.
• Provides status signals to the control-related data to the control unit
“Piano Player” “Piano”
![Page 129: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/129.jpg)
www.iaik.tugraz.at
129
Music
Data Path
implementing the actions on
X, Y
Control
defines when what action should be performed
Control Signals
provided by data path to
perform actions on X and Y
![Page 130: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/130.jpg)
Register-Transfer Statements Define the Data Path
out = 4X 0Y 0
out = 3Y X
out = 2X X + 1
Y X
in
1
A
B
C
0
X 0X XX X+ 1
Y 0Y X
Operations for register X:
Operations for register Y:
130
www.iaik.tugraz.at
These are the operations that our data path implements
![Page 131: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/131.jpg)
Operations for register X
Case 0: X XCase 1: X X+ 1Case 2: X 0
We need to distinguishbetween 3 cases.
131
www.iaik.tugraz.at
→ A one bit control signal is not enough. We need two control signals.
![Page 132: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/132.jpg)
The neighborhood of register X
clrx incx action0 0 X X0 1 X X+ 11 0 X 0
We use binary notationand name the two binaryselect variables.
132
www.iaik.tugraz.at
![Page 133: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/133.jpg)
The neighborhood of register X
clrx incx action0 0 X X0 1 X X+ 11 0 X 0
With Logisim we canmodel the neighborhood of Register and also simulate.
133
www.iaik.tugraz.at
Implementation in SystemVerilog
![Page 134: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/134.jpg)
The neighborhood of register Y
clry ldy action0 0 Y Y0 1 Y X1 0 Y 0
In a similar way, we canmodel the neighborhoodof Y.
134
www.iaik.tugraz.at
![Page 135: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/135.jpg)
The datapath
We combine the twoneighborhoods.
Note that both neighborhoodsare Moore machines.
The Moore machine for X has 2inputs: clrx and incx. Since we havechosen an 8-bit register for X,we have 256 possible states.The output function is the identityfunction.
The connection of the two isagain a Moore machine. Thus,The datapath is a Moore machine.
135
www.iaik.tugraz.at
![Page 136: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/136.jpg)
Register-transfer statements define the data path
out = 4X 0Y 0
out = 3Y X
out = 2X X + 1
Y X
in
1
A
B
C
0
Datapath:
136
www.iaik.tugraz.at
![Page 137: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/137.jpg)
The control logic needs to provide the control signals
out = 4clrx = 1clry = 1
out = 3ldy = 1
out = 2incx = 1ldy = 1
in
1
A
B
C
0
137
www.iaik.tugraz.at
![Page 138: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/138.jpg)
Truth table of output logic of controller
out = 4clrx = 1clry = 1
out = 3ldy = 1
out = 2incx = 1ldy = 1
in
1
A
B
C
0
state clrx incx clry ldy out
0 0 1 0 1 0 1000 1 0 0 0 1 0111 0 0 1 0 1 010
A 00B 01C 10
138
www.iaik.tugraz.at
![Page 139: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/139.jpg)
Truth table of next-state logic of controller
out = 4clrx = 1clry = 1
out = 3ldy = 1
out = 2incx = 1ldy = 1
in
1
A
B
C
0
state clrx incx clry ldy out
0 0 1 0 1 0 1000 1 0 0 0 1 0111 0 0 1 0 1 010
state in next_stateA 0 BA 1 BB 0 AB 1 CC 0 AC 1 A
139
www.iaik.tugraz.at
![Page 140: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/140.jpg)
Truth table of next-state logic of controller
out = 4clrx = 1clry = 1
out = 3ldy = 1
out = 2incx = 1ldy = 1
in
1
A
B
C
0
A 00B 01C 10
140
www.iaik.tugraz.at
s1 s0 clrx incx clry ldy out
0 0 1 0 1 0 1000 1 0 0 0 1 0111 0 0 1 0 1 0101 1 x x x x xxx
s1 s0 in ns1 ns00 0 0 0 10 0 1 0 10 1 0 0 00 1 1 1 01 0 0 0 01 0 1 0 01 1 0 x x1 1 1 x x
![Page 141: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/141.jpg)
From truth table to implementation
s1 s0 clrx incx clry ldy out
0 0 1 0 1 0 1000 1 0 0 0 1 0111 0 0 1 0 1 0101 1 x x x x xxx
s1 s0 in ns1 ns00 0 0 0 10 0 1 0 10 1 0 0 00 1 1 1 01 0 0 0 01 0 1 0 01 1 0 x x1 1 1 x x
outl:
nsl:
141
www.iaik.tugraz.at
![Page 142: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/142.jpg)
The controller and the data path
142
www.iaik.tugraz.at
![Page 143: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/143.jpg)
For a SystemVerilog example of this ASM with separated control and datapath see
con03_asm_separate_datapath
143
www.iaik.tugraz.at
![Page 144: (INB.06000UF, INB.07001UF) Chapter 3 State Machines · Computer Organization and Networks (INB.06000UF, INB.07001UF) Winter 2020/2021 Stefan Mangard, Chapter 3 –State Machines](https://reader033.fdocuments.us/reader033/viewer/2022052500/6054c7c30607f54ea82e456a/html5/thumbnails/144.jpg)
That’s it.
• In principle, we can describe any synchronous automaton with an ASM diagram.
• In principle, every synchronous digital system can be described by a collection of ASM diagrams.
144
www.iaik.tugraz.at