1

2

Inthislecture,wewillconsiderthevarioustypeofstorage(memory)thatFPGAsallowustoimplement.ThemajoradvantageofFPGAsisthatitcontainslotsofsmallblocksofmemorymodules,whichcaneitherbeusedindependently,orcombinedtoformlargermemoryblocks.Theyalsoprovidevariousconfigurationssuchasmulti-portorregisteredinput/outputfordataandaddress.

Therearevarioususefulreferencesyoucanlookupifyouareinterestedtolearnmoreaboutthis.Forthepurposeofexamination,thecontentsinthislectureandintheVERIexperimentaresufficient.

3

Thesimplestformofstorageisaregisterfile.Allmicroprocessorshaveregisterfiles,whichareknownas“registers” inthearchitecturalcontext.

Registerfilesarefast,largeandflexible.TheyaregenerallyusedtostoretemporarydataforeasyaccessbytheALUorfloatingpointunitofamicroprocessor,orforcomputationalengineofaapplicationspecifydigitalsystem.

OntheFPGA,registerfilesareoftenimplementedwiththeD-FF’sintheAdaptiveLogicModules(ALMs).EachALMhastwoD-FFs.Thereforea32-bitregisterwilltakeup16ALMs.Alternativelyonecouldalsousethestaticmemoryblocksforthispurpose.

4

Thecircuitofaregisterfileissimple– itconsistsofarraysofD-FFs,whichcanbedisable(andoutputbecomeshighimpedance).Theregisterselectsignalssel_reg0,sel_reg1etc.enablethecorrectregistertoputthedataonthedataline(calledbitlinehere).Theread/writecontrolsignalWEisusedtodetermineifyouarereadingorwritingtotheregister.

5

Theregisteridentification(regid)determineswhichregisteryouaretryingtoaccess.Thisisachievedthroughastandarddecoder,whichgenerateaone-hotcodewordtoselecttheappropriateregistertoaccess.

6

NowletusturntotheCycloneVFPGA.TheFPGAhasmanydifferenttypeofresourcesinadditionaltoAdaptiveLogicModules(ALMs).Theseare:memoryblocks,DigitalSignalProcessing(DSP)units,phase-lockedloopsandinput/outputpads.Inaddition,thereisadual-coreARMprocessoranditsassociatedbusinterfacecircuit(showninlightgreen).

Herewefocusonmemory.IntheC5-SE-A5series,whichistheoneweuseintheDE1board,therearenear400separatememoryblocks,eachwith10kbitsofstorage.TogetherwiththeALMs,thereis4.45Mbitsofflexiblememorystorageavailabletothedesigner.

7

Eachoftheseblocks(knownasM10K)canbeconfiguredwithdifferentdepthanddatawidthasshownintheableabove.

Evenmoreimportantly,thecanalsobeconfiguredtoactasconventionalsingle-portmemory,orsimpledual-portwithoneportforreadandoneportforwrite.

Further,theycanbemadetobetruedual-port,bothportsbeingread/writeports,orasashiftregister,aROMorafirst-in-first-outbuffer(FIFO).

8

AsyouhaveseenintheVERIexperiment,ifthememoryblockisaROM(orevenasaRAM),itscontentcanbeconfiguredviaamemoryinitializationfile.mif.Theformatofthefileisshownhere.Typingthecontentsofa1024ROMmodulebyhandissillyandimpractical.Iwrotetwoversionsofasimpleprogrammetogeneratethis.miffile,oneinMatlabandoneinPython.BelowisthecodefortheMatlabversion.TheROMisproducedusingtheIPCatalogtool.Hereisa1024x10bitROMgeneratedwithallinputandoutputregisteredandsynchronisedwiththeclocksignal.

9

Intheexperiment,youhavealreadyimplementedasinewavegeneratorusingtheROMtostoreonecycleofasinewave.Thecounterisusedtoadvancethephaseofthesinewave,whichisspecifiedastheaddressXoftheROM.ThecontentoftheROM,y=F(x)isthecontentoftheROMandisthegeneratedwaveform.Insteadofstoringasinewave,youcaneasilystoreanyothersignal(suchasavoiceormusicsegment).Inorderimplementavariablefrequencysinewave,youcouldmodifytheaddresscountersothatitisgoesupnotonlyby1countforeachclockcycle,butbyN.ForexampleifNis2,thentheaddresscounterwillskipeveryothersampleintheROMandthereforethegeneratedsinewavewillbeattwicethesignalfrequency.

10

Hereisageneratedsingle-portmemorywithALLpossiblesignalsincluded.Themeaningofallthesignalsareselfexplanatory.

11

HereisthetimingoftheRAMconfiguredasasingleport.Sincewehaveseparatedatainputport(data_a)anddataoutputport(q_a),itisimportanttounderstandwhatdatayoureadback(oldornew)fromagivenaddressduringawritecycle.

12

HereisanexampleofusingtheMegaWizardmanagertoolinQuartus.Weareproducinga1-portRAMwith1024x8,allsignalsareclocked.Thegeneratorproducesasampleheaderfile(atemplate)whichdefinestheinterfacesignaltothegeneratedblock.RememberyoumustticktheVerilogHDLradiobutton.

13

YoucanalsoconfiguretheM9Kmemoryblockasashiftregister.Hereisan8-bit16stageSR.Inaddition,itprovides“tap” outputsforeverystage,i.e.16x8=128outputsignals.ThisisveryusefultoimplementFIRfilterorperformtimedomainconvolution.

InthePartIVoftheVERIexperiment,youwillbeusingaFIFOtoimplementanechosynthesizer.TheactionofaFIFOisshowninthediagramabove.

14

HereisagenericblockdiagramofaFIFOwithitstypicalinterfacesignals.FIFOisaformofqueue.Internallytheretypicallytwocounters,onekeepingtrackofthereadaddress(orreadpointer)andanothercounterkeepingtrackofthewriteaddress(writepointer).ThereneedstobestatussignalssuchasFULL,whichisassertediftheFIFOiscompletelyfilledandwritinganymorewordstoitwilldestroystoreddata,orEMPTY,whichsignifiesthattherearenodatalefttoread.

15

16

FIFOcanbegeneratedusingtheIPCatalogmanagertool.Hereisanexampleofa32wordx8bitFIFO.