Slide 1

Importance of Interface on device characterization/operation Quantitative Discussion on Gate Current H. Watanabe, ECE, NCTU, Taiwan June 26/2013H. Watanabe, ECE, NCTU1 [1] H. Watanabe, et.al, IEEE TED 53, 1323-01330, 2006. [2] H. Watanabe, et.al, IEEE TED 57, 1129-1136, 2010. [3] H. Watanabe, IEEE TED 57, 1873-1882, 2010. Source of this talk: Slide 2 Studied Dielectrics (tunnel oxide, IPD and so on) What is Current? Material for CG (Poly, Silicide, Metal?) Electrode for TEST SUB, or Poly SUB Electrode Wide enough to measure the current June 26/20132H. Watanabe, ECE, NCTU Tunneling is integrated in space to become a tunnel current. In actual devices, the spatial integration is invalid. Slide 3 What is Current? June 26/20133H. Watanabe, ECE, NCTU Even though area is large, trap-assisted leakage is a local issue. Slide 4 D Gate In Labo S June 26/2013H. Watanabe, ECE, NCTU4 S D G Gate current itself is an issue, but too small to be usually measurable. G 20 nm On Chip Greater Gate Current to be measurable. 100 um x 100um 100nm x 100nm Limit of equipment Too small Slide 5 D Gate In Labo S June 26/2013H. Watanabe, ECE, NCTU5 Greater Gate Current to be measurable. 100 um x 100um 100nm x 100nm Stress-Induced Leakage Current (SILC) 10nm Limit of equipment Too small Slide 6 D Gate In Labo S June 26/2013H. Watanabe, ECE, NCTU6 Greater Gate Current to be measurable. Local Trap Stress-Induced Leakage Current (SILC) 100 um x 100um 100nm x 100nm 1-order 10nm Limit of equipment Too small Slide 7 D Gate In Labo S June 26/2013H. Watanabe, ECE, NCTU7 Greater Gate Current to be measurable. S D G G >10 nm On Chip Trap-enhanced Tunneling: measurable 100 um x 100um 100nm x 100nm 10nm Limit of equipment Too small Slide 8 June 26/2013H. Watanabe, ECE, NCTU8 S D G G >10 nm On Chip S D G Local Trap Slide 9 Motivation of this talk June 26/2013H. Watanabe, ECE, NCTU9 Trap-related Gate Leak should be focused for this aim. Overview of analytical method for this aim. Slide 10 Dielectric Scaling in Electron Devices June 26/2013H. Watanabe, ECE, NCTU10 Is 0.5nm a limit? Slide 11 Dielectric Scaling in Electron Devices June 26/2013H. Watanabe, ECE, NCTU11 Interface is becoming dominate dielectric. InterFace Transition Layer Slide 12 June 26/2013H. Watanabe, ECE, NCTU12 Si O O O O O O O O O Neaton, PRL 00 IFT layer = atomistic interface Muller, Nature 99 EELS Electron-energy loss spectroscopy ~4 + penetration Slide 13 Literature of IFT layers June 26/2013H. Watanabe, ECE, NCTU13 IFT widthApproachNOTE Muller et.al. Nature 99 4 EELS: O K edge count Regarding evanescent wave as origin of interfacial states Demkov et. al. PRL 99 44 Quantum Molecular Dynamics Valence band offset near interface is smaller than in bulk. Kaneta et. al. Micro. Eng. 99 1-4 First Principle Molecular Dynamics Moderate change within 1 Pantelides et. al. T. Nuc. Sci 00 2-5 First Principles IFT width from E C offset and E V offset are 5 and 2 , respectively. Neaton et. al. PRL 00 5 First Principles E G The number of second neighbor O atoms Yamazaki et. al. PRB 01 2-5 First Principle Molecular Dynamics Estimating of EG from local DOS Takahashi et. al. JJAP 02 6.1 XPSSiO 2 /Si(111) Hattori et. al. Appl. Surf. Sci. 03 5.1 XPSSiO 2 /Si(001) Giustino, et. al. PRL 03 3-5 Density Functional Approach Dielectrics inside IFT layers is governed by chemical grading but not evanescent wave. Watari et. al. PRB 04 44 Density Functional First Principles Using superlattice Present 44 CV-JV Fitting Significance of poly-Si side IFT layer Limit(?) of EOT is 0.5nm. H. Watanabe, et.al, IEEE TED 53, 1323-01330, 2006. Slide 14 June 26/2013H. Watanabe, ECE, NCTU14 Tunnel mass vs IFT Layer Neglecting IFTIFT T ox Tunnel Current T ox = T pure Under-estimated T pure Slide 15 June 26/2013H. Watanabe, ECE, NCTU15 Tunnel mass vs IFT Layer Neglecting IFT H. Watanabe, IEEE TED53, 1323, 2006M. Stadele, J. Appl. Phys. 93, 2681, 2003 Over-estimated T pure IFT Slide 16 Literature of Tunnel Mass June 26/2013H. Watanabe, ECE, NCTU16 IFT width Tunnel Mass (m 0 ) T OX - dependence Polarity of V G in fitting ApproachNOTE CVJV Brar et. al. JAP96 0 0.30 0.02 (Para) 0.41 0.01 (NP) No ++ EXP &WKB T OX T ellipso =3 5 Khairurrijal et. al. APL 00 0 0.5-0.9 Yes Maybe, EXP & WKBNo IFT Demkov et.al. PRB, 01 44 0.87-0.95 Yes NothingEither Ballistic Transport Metal/SiO 2 /M etal Stadele et. al. JAP 03 44 0.39 ( + T OX ) Yes Nothing + Comparing WKB with TB Neglecting IFT in WKB Sacconi et. al. TED04 44 0.39 [1 (E C E)/E G ] Yes Nothing Comparing WKB with TB Neglecting IFT in WKB Watanabe TED06 44 0.85 0.05 No Both CV-JV Fitting Including IFT Slide 17 Model of IFT layer June 26/2013H. Watanabe, ECE, NCTU T pure T all 17 Gradual Energy Gap (EG) Change Gradual Dielectric Const. (K) Change H. Watanabe, IEEE TED (2006) Slide 18 Impact of IFT Layers June 26/2013H. Watanabe, ECE, NCTU18 Positive V G case Negative V G case Slide 19 June 26/2013H. Watanabe, ECE, NCTU19 T OX 1.All IFT related models are considered in calculation. Thickness 2.Entire CV & JV are fitted at the same moment. Tunnel Mass Comparison with exp. CV-fitting JV-fitting Slide 20 Expansion to Alloy model June 26/2013H. Watanabe, ECE, NCTU20 Gradual Energy Gap (EG) Change Gradual Dielectric Const. (K) Change A B C A = Si B = O C = N Ex) A = HrO 2 B = Al 2 O 3 C = Si 3 N 4 A = ZrO 2 B = Al 2 O 3 C = Si 3 N 4 Slide 21 Expansion to Alloy model June 26/2013H. Watanabe, ECE, NCTU21 Gradual Energy Gap (EG) Change Gradual Dielectric Const. (K) Change A B C A simplest case Si O N SiO 2 1 2 3 4 Si 3 N 4 x 1-x A = Si B = O C = N Ex) (SiO 2 ) 1-X (Si 3 N 4 ) X Slide 22 Stoichiometric Alloy Model 22 A B C A simplest case Si O N SiO 2 1 2 3 4 Si 3 N 4 x 1-x A = Si B = O C = N Ex) (SiO 2 ) 1-X (Si 3 N 4 ) X Check by Exp. June 26/2013H. Watanabe, ECE, NCTU (Exp. Sample) AR-XPS Slide 23 Stoichiometric Alloy Model June 26/2013H. Watanabe, ECE, NCTU23 (SiO 2 ) 1-X (Si 3 N 4 ) X Check by Exp. From [O] at and From [N] at are equivalent. AR-XPS Slide 24 Stoichiometric Alloy Model June 26/2013H. Watanabe, ECE, NCTU24 (SiO 2 ) 1-X (Si 3 N 4 ) X Bonding-Rate: Change the view point: From Atoms to Bonding. Lucovsky, SSDM96 Yasuda, SSDM01 Slide 25 Stoichiometric Alloy Model June 26/2013H. Watanabe, ECE, NCTU25 Bonding-Rate: K=K OX (1-R)+K SiN R EG=EG OX (1-R)+EG SiN R Lucovsky, SSDM96 Yasuda, SSDM01 Slide 26 Further Expansion June 26/2013H. Watanabe, ECE, NCTU26 Slide 27 Expansion to Off-Stoichiometry June 26/2013 H. Watanabe, ECE, NCTU 27 Stoichiometric SiSi ON Off-stoichiometric Slide 28 June 26/2013 H. Watanabe, ECE, NCTU 28 SiSi ON Suppose: Slide 29 DB Yield June 26/2013 H. Watanabe, ECE, NCTU 29 Slide 30 June 26/2013H. Watanabe, ECE, NCTU30 DB from Si-N Si-DB is generated where N is removed from Si-N bond. N-DB is in lower level. Si-DB N-DB Kato, ICPS-28, 2006 Si with N incorporated Slide 31 Band Structure June 26/2013H. Watanabe, ECE, NCTU31 Si (SiO 2 ) 1-X (Si 3 N 4 ) X Si 3 N 4 (x=1) SiO 2 (x=0) More N Oxide Incorporate Trap Levels (DB) More Ox EG=EG OX (1-R)+EG SiN R VBA=VBA OX (1-R)+VBA SiN R Slide 32 June 26/2013H. Watanabe, ECE, NCTU32 Barrier Modulation by trapped charge Electron tunneling Hole tunneling p-Si n + poly Barrier Lowering @Negative V G BarrierIncreasing IFT Suppose: trap (DB) level above Fermi level is charged positive. Slide 33 Extraction of Y DB June 26/2013H. Watanabe, ECE, NCTU33 CV-fitting with Y DB Smaple-1 Smaple-2 Smaple-3 Smaple-4 Only Y DB modulates CV-curve, since T phys, [N]- and [O]-profiles are obtained by AR-XPS. Slide 34 June 26/2013H. Watanabe, ECE, NCTU34 Hole Tunnel Mass Tunnel masses for electrons & holes are the same, 0.85m 0. Electron 23% 31% 40% EXP.: Muraoka, JAP94 31% Slide 35 June 26/2013H. Watanabe, ECE, NCTU35 Trap-assisted tunneling (TAT) Trap TAT DT D1D1 D2D2 Tunneling Prob.: TATDT D DT Slide 36 Trap-assisted tunneling (TAT) June 26/2013H. Watanabe, ECE, NCTU36 TAT vanishes while is less than 1E-15cm 2. Slide 37 June 26/2013H. Watanabe, ECE, NCTU37 CV-JV Fitting Result Y DB (%)T Phys (nm)N poly (cm -3 )N sub (cm -3 ) 0.191.10610 19 510 16 0.151.30410 19 710 16 0.0751.14110 20 2.610 16 0.0751.36310 20 2.610 19 Enhanced Direct Tunneling Slide 38 June 26/2013H. Watanabe, ECE, NCTU38 Single Electron Sensitive 3D device simulator Put trap in 3D device structure. H. Watanabe, Transient Device Simulation of Floating Gate Nonvolatile Memory Cell With a Local Trap, IEEE TED., vol. 57, pp. 1873-1882, 2010. Trap Positive charge Gate Area: 30nm x 30nm Slide 39 June 26/2013H. Watanabe, ECE, NCTU39 Gate Area: 30nm x 30nm Vd 0V Trap (Positive Charge) Positive Charge Slide 40 Conclusions Trap-related gate leak is smallest measurable current. To make sure tunnel mass, IFT layers is carefully considered. Dangling Bond Yield is introduced. Enhanced Direct Tunneling is discovered, which is a candidate for the smallest trap-related current. Todays device engineering already detected the foot-print. Data retention degradation from 10-years to year. June 26/2013H. Watanabe, ECE, NCTU40 Slide 41 Thanks for your attention. 1.H. Watanabe, D. Matsushita, K. Muraoka, Determination of tunnel mass and physical thickness of gate oxide including poly-Si/SiO2 and Si/SiO2 interfacial transition layers, IEEE Trans. Elec. Dev. Vol. 53, no. 6, pp. 1323-1330, 2006 2.H. Watanabe, D. Matsushita, K. Muraoka, and K. Kato, Universal tunnel mass and charge trapping in [(SiO2)1-x(Si3N4)x]1-ySiy film, IEEE Trans. Elec. Dev., vol. 57, no. 5, pp. 1129-1136, 2010. 3.H. Watanabe, Transient Device Simulation of Floating Gate Nonvolatile Memory Cell With a Local Trap, IEEE TED., vol. 57, pp. 1873-1882, 2010. June 26/2013H. Watanabe, ECE, NCTU41 Co-authors of related papers: D. Matsushita, K. Muraoka, K. Kato Author is supported as Phison Electronics Chair Professor.