Implementing and Optimizing a Direct Digital Frequency Synthesizer on FPGA Jung Seob LEE Xiangning...
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Transcript of Implementing and Optimizing a Direct Digital Frequency Synthesizer on FPGA Jung Seob LEE Xiangning...
![Page 1: Implementing and Optimizing a Direct Digital Frequency Synthesizer on FPGA Jung Seob LEE Xiangning YANG.](https://reader036.fdocuments.us/reader036/viewer/2022082816/56649f555503460f94c78e06/html5/thumbnails/1.jpg)
Implementing and Optimizing a Direct Digital Frequency
Synthesizer on FPGA
Jung Seob LEE
Xiangning YANG
![Page 2: Implementing and Optimizing a Direct Digital Frequency Synthesizer on FPGA Jung Seob LEE Xiangning YANG.](https://reader036.fdocuments.us/reader036/viewer/2022082816/56649f555503460f94c78e06/html5/thumbnails/2.jpg)
Direct Digital Frequency Synthesizer (DDFS)
Generate sinusoid and cosinusoid waveform Widely used in digital communication system
– Software radio– Spread-spectrum modulation– Phase shift-keying modulation
![Page 3: Implementing and Optimizing a Direct Digital Frequency Synthesizer on FPGA Jung Seob LEE Xiangning YANG.](https://reader036.fdocuments.us/reader036/viewer/2022082816/56649f555503460f94c78e06/html5/thumbnails/3.jpg)
DFFS Algorithm
Look-up table– Fast, less sophisticated design, high precision– Huge table == large area, inflexible
Angle rotation: CORDIC, interpolation, etc.– Compact, area efficient, flexible– Complex design, low speed, wide internal data-
path to ensure desired output precision
![Page 4: Implementing and Optimizing a Direct Digital Frequency Synthesizer on FPGA Jung Seob LEE Xiangning YANG.](https://reader036.fdocuments.us/reader036/viewer/2022082816/56649f555503460f94c78e06/html5/thumbnails/4.jpg)
DFFS Algorithm
Used in our project: hybrid method– Use LUT to gives a coarse position of the angle– Use angle rotation method to fine turn the angle
Engineering trade-off of area efficiency, design complexity, computation need, and cycle times
16-bit internal data path to give 15 bit output precision 2 128x16-bit LUTs are needed
– [Lee & Park] S. Lee and I. Park, “Quadrature direct digital synthesis using fine-grain angle rotation”, ISCAS’2004
![Page 5: Implementing and Optimizing a Direct Digital Frequency Synthesizer on FPGA Jung Seob LEE Xiangning YANG.](https://reader036.fdocuments.us/reader036/viewer/2022082816/56649f555503460f94c78e06/html5/thumbnails/5.jpg)
Implementation
Implementing the algorithm on FPGA with algorithm mapping and transforming approach– Non-pipeline
Optimizing– cut-set retiming techniques => pipeline version
![Page 6: Implementing and Optimizing a Direct Digital Frequency Synthesizer on FPGA Jung Seob LEE Xiangning YANG.](https://reader036.fdocuments.us/reader036/viewer/2022082816/56649f555503460f94c78e06/html5/thumbnails/6.jpg)
FPGA Implementation
Choose Altera Cyclone II EP2C5– Low cost FPGA, – On-line listed price: $12.8– Internal RAM for LUT
![Page 7: Implementing and Optimizing a Direct Digital Frequency Synthesizer on FPGA Jung Seob LEE Xiangning YANG.](https://reader036.fdocuments.us/reader036/viewer/2022082816/56649f555503460f94c78e06/html5/thumbnails/7.jpg)
Current Status
A software implementation of the algorithm– For studying the characteristics of the algorithm
Non-pipeline version is finished– Test bench – it works!– Synthesis: max sample output frequency (max
operating frequency) : 42.84 MHz
![Page 8: Implementing and Optimizing a Direct Digital Frequency Synthesizer on FPGA Jung Seob LEE Xiangning YANG.](https://reader036.fdocuments.us/reader036/viewer/2022082816/56649f555503460f94c78e06/html5/thumbnails/8.jpg)
Next Stage
Implementing the pipe-line version Further optimization:
– Parallel processing ?– Buffering ?
![Page 9: Implementing and Optimizing a Direct Digital Frequency Synthesizer on FPGA Jung Seob LEE Xiangning YANG.](https://reader036.fdocuments.us/reader036/viewer/2022082816/56649f555503460f94c78e06/html5/thumbnails/9.jpg)
Thank You
Question ?
![Page 10: Implementing and Optimizing a Direct Digital Frequency Synthesizer on FPGA Jung Seob LEE Xiangning YANG.](https://reader036.fdocuments.us/reader036/viewer/2022082816/56649f555503460f94c78e06/html5/thumbnails/10.jpg)
Pipelined Retiming
Add registers to 3 stages:
2 stage -> 6 stage pipelined structure
![Page 11: Implementing and Optimizing a Direct Digital Frequency Synthesizer on FPGA Jung Seob LEE Xiangning YANG.](https://reader036.fdocuments.us/reader036/viewer/2022082816/56649f555503460f94c78e06/html5/thumbnails/11.jpg)
Comparison between retiming and non-retiming version
Maximum Clock rate– Non-pipelined version: 42.84MHz– Pipelined version: 116 MHz
Critical path delay is reduced as much as 2.7 times
Total cell Area change?– Non-pipelined version:– Pipelined version: