Implementation of AMBA AXI4 Protocol

By,

Nishant Saksena

Ashok

What is AMBA AXI4 Protocol ??

Advanced Microcontroller Bus architecture (AMBA) protocol is an on-chip interconnect specification for the connection and management of functional blocks in a System-on-Chip (SoC).

About AMBA AXI4 Interface Architecture

The AXI 4 protocol is burst-based.

Every transaction has address and control information on the address channel that describes the nature of the data to be transferred on data channel.

The data is transferred between master and slave using a separate read and write address and data channels.

Advantage of AXI4 Protocol

separate address/control and data phases

burst-based transactions with only start address issued

separate read and write data channels

ability to issue multiple outstanding addresses

suitable for high-bandwidth and low-latency designs

AXI4 INTERFACE ARCHITECTURE

MASTER SLAVE

READ ADDRESS CHANNEL

READ DATA CHANNEL

WRITE ADDRESS CHANNEL

WRITE DATA CHANNEL

WRITE RESPONSE CHANNEL

Channel architecture for READ

READ Address and control bus Handshaking

MASTER SLAVE

READ ADDRESS and CONTROL CHANNEL

ARVALID

ARREADY

ADDRESS, ARID, ARLEN, ARSIZE

MASTER SLAVE

READ DATA CHANNEL

RVALID

RREADY

DATA

READ DATA bus Handshaking

RLAST

Specialty of burst based transfer

ARLEN = The burst length gives the exact number of transfers in a burst.

BURST LENGTH ENCODING

ARSIZE = Specifies the maximum number of data bytes to transfer in each beat, or data transfer, within a burst.

BURST SIZE ENCODING

How to implement burst data transfer ?

Start_Address = ADDR

Number_Bytes = 2^Burst SIZE

Burst_Length = Burst LEN + 1

Aligned_Address = (INT(Start_Address / Number_Bytes) ) x Number_Bytes.

Address_N = Aligned_Address + (N 1) x Number_Bytes.

OUR IMPLEMENTATION TILL NOW

Completed the state machine design for read address channel and data channel for both MASTER and SLAVE design.

Completed the basic testing of Read address and Data channel.

Our design can be used for Variable Burst length read and variable burst size read.

STIMULUS GENERATOR MASTER

BASIC

SLAVE

MEMORY

ONLY READ TILL NOW*

WRITE Process to be implemented

MASTER SLAVE

WRITE ADDRESS and CONTROL CHANNEL

AWVALID

AWREADY

ADDRESS, AWID, AWLEN, AWSIZE

MASTER SLAVE

WRITE DATA CHANNEL

RVALID

RREADY

DATA

MASTER SLAVE

WRITE RESPONSE CHANNEL

Write Response

IMPLEMENTATION

STIMULUS GENERATOR

MASTER SLAVE-1

MEMORY- 1

SLAVE-2 MEMORY- 2

SLAVE-3 MEMORY- 3

AXI4

AXI4

AXI4

State 0

State 1

State 2 State

4

State 3

S3_State 0

S3_State 1

S3_State 2

S3_State 4

S3_State 3

S2_State 0

S2_State 1

S2_State 2

S2_State 4

S2_State 3

ARID

MASTER FSM slave1

slave2

slave3

rrq = 1

wrq = 1

wrq = 1

wrq = 1

rrq = 1

rrq = 1

s_awready

s_awready

s_awready

S2_State 0 S2_State

1

S2_State 2 S2_State

3

s2_m_arvalid_sig

S2_State 4

s2_m_awvalid_sig Read Burst

calculation

Write Burst calculation

Slave FSM graph

State 0

State 1

State 2

State 3

m_arvalid_sig

State 4

m_awvalid_sig Read Burst calculation

Write Burst calculation

State 0

State 1

State 2

State 3

s3_m_arvalid_sig

State 4

s3_m_awvalid_sig

Read Burst calculation

Write Burst calculation

Read process waveform Randomly generated parameters

Address : 17 Burst length : 4 Burst size : 2 Id : 1 (slave 1)

Read process waveform Randomly generated parameters

Address : 10 Burst length : 3 Burst size : 1 Id : 2 (slave 2)

Read process waveform Randomly generated parameters Address : 10

Burst length : 4 Burst size : 1 Id : 3 (slave 3)

Write process waveform Randomly generated parameters Address : 43

Burst length : 4 Burst size : 2 Write data : 573701956 Id : 2 (slave 2)

RAM-2 write location

Write Process Randomly generated parameters Address : 39 Burst length : 1 Burst size : 2 Write data : 3812041926 Id : 1 (slave 1)

RAM-2

Write process (burst size check) Randomly generated parameters Address : 41 Burst length : 2 Burst size : 1 Write data : 102596364 Id : 3 (slave 3)

Our data is 102596364

In binary : 110000111010111111100001100

If burst size = 1 then,

We will write just 16 bits

So, our 16 bits = 0111111100001100

In decimal = 32524

RAM location check

Applications of AXI4 protocol

AXI4 is a solution for the blocks of an SoC to interface with each other.

USED as interconnect in connecting Memory blocks including a selection of ROM, RAM inside SOCs.

Provides interconnection for microcontroller, microprocessor or DSP core(s)

Also used in PSOC, programmable SOCs Companies using AXI4 protocol :

Intel, Texas Instruments, ARM, Xilinx, HTC etc.

AHB is in AMBA AXI family

THANK YOU !!!!