IMPLEMENTATION AND VERIFICATION OF AUDIO CODEC … · industry standard tools. The power reduction...
Transcript of IMPLEMENTATION AND VERIFICATION OF AUDIO CODEC … · industry standard tools. The power reduction...
International Journal of Advanced Electrical and Electronics Engineering, (IJAEEE)
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ISSN (Print): 2278-8948, Volume-2, Issue-5, 2013
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IMPLEMENTATION AND VERIFICATION OF AUDIO CODEC
CONTROLLER USING LOW POWER TECHNIQUES
1Shobha M R,
2Sujatha K
1MTech Student, BMSCE, 2Assistant Professor, Department of E&C, BMSCE
Email : [email protected], [email protected]
Abstract- Today the Low power or power efficiency is a
key design requirement for nanometer designs. As
technologies have shrunk, leakage power consumption
has grown exponentially, thus requiring power
reduction techniques. In this report we focus on the
implementation of micro architecture design,
verification, and place and route layout using latest
industry standard tools. The power reduction is done
through frequency scaling technique and power gating
technique. Logical design (Front end design) is done
using verilog HDL and simulated using Synopsys
Verilog Simulator (VCS), Version (VCS/E-2011.03).
Analysis of power savings and tradeoffs with die size
and performance will be presented.
Index Terms—Audio codec controller, frequency
scaling and power gating.
I. INTRODUCTION
Integrated audio solutions such as AC‟97 are cost-effective
and offer a good end-user experience in both stereo and
multichannel formats, the current audio capabilities fall
short in meeting the requirements of the next generation of
PCs designed for digital entertainment. Intel has worked
with the industry to develop a new specification for
integrated audio that is capable of delivering the features
and high-end performance of an add-in audio card. Intel
High Definition Audio (Intel HD Audio) is capable of
playing back more channels at higher quality than previous
integrated audio formats.
Audio Codec AC‟97 was developed to listen music and
movies with stereo sound. With the success of DVD movies
with DTS multichannel audio formats, users have become
comfortable to listening in full surround sound with
anywhere from six to eight speakers. While AC‟97
technology has struggled to keep rate with all these
advancements, Intel HD Audio is designed specifically for
the high-quality multichannel audio experiences of today
and tomorrow and delivers significant improvements over
previous generation integrated audio and sound cards.
The primary goals of the Low power audio codec controller
specification are to describe an infrastructure to support
high quality audio in a PC environment. The Low power
Audio Codec Controller was implemented using the
Verilog hardware description language. The Synopsys VCS
simulator tool was used for simulation and verification of
the model. The hardware model was then synthesized using
the Synopsys Design Compiler tool. Synthesis is the
conversion of RTL to gate level net list. The tool will choose
gates from the provided standard cell library based on the
RTL and timing constraints provided. In physical design we
translate the net list into an actual physical layout using
Synopsys IC Compiler that can be sent to the foundry for
manufacturing it involves Floor planning, power grid
planning, placement of various components, routing
between the cells. The layout needs to verify against the
schematic (LVS). Also we need to run DRC (design rule
checks) to ensure all design rules are met. power analysis is
done to identify static and dynamic power by frequency
scaling and power gating.
II. SCOPE OF THE PAPER
The scope of the paper includes:
Architecture of the Audio Codec Controller.
Synthesizing and generating net list
Understanding the ASIC flow.
Use of low power techniques.
Learning Verilog language and using VCS tool.
III. LITERATURE SURVEY
A. Advanced Low Power Techniques
Power consumption can be divided in to two aspects.
Dynamic power and Leakage power. Dynamic power is the
power that is consumed by a device when it is actively
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switching from one state to another. Dynamic power
consists of switching power, consumed while charging and
discharging the loads on a device, and internal power,
consumed internal to the device while it is changing state.
Leakage power is the power consumed by a device not
related to state changes Leakage power is actually
consumed when a device is both static and switching, but
generally the main concern with leakage power is when the
device is in its inactive state, as all the power consumed in
this state is considered “wasted” power. The most common
low power techniques are:
Power gating is the technology in which header switch is
placed in between a block and power to control supply
power from this block with sleep In active mode, virtual
voltage (VVDD) is acting as power supply at a potential of
approximately VDD to the block; leakage power exists both
in header and this circuit block. In standby mode, header is
switched off, meaning that virtual voltage is beginning to
drop with time. Virtual voltage is no longer at VDD, but
rather at a voltage somewhat above VSS at saturation point.
Hence, transistor gate to source voltage is reduced. As soon
as virtual voltage starts to fall, leakage power saving in this
block begins. Yet, leakage still exists in the header. This is
why sleep transistors are usually made of high threshold
voltage (Vth) devices to prevent from cell leakage while
maintaining a high potential at virtual rail.
Frequency scaling – Dynamic frequency/voltage scaling
(DFS and DVS) is a widely used technique to reduce the
overall energy consumption of a system, particularly with
workloads with high variation in processing requirements.
DFS/DVS can either be used to push the operating
frequency of a circuit beyond the nominal operating
frequency assumed during design time to achieve improved
performance or reduce voltage/frequency to reduce energy
consumption at times when the full capabilities of the
hardware are not required by the application. A critical
issue for a DFS/DVS-enabled system is determining the
safe operating voltage in which maximum execution
efficiency is achieved, while guaranteeing correct operation
of all components.
B. Asic Flow
The main steps in the ASIC physical design flow are:
Design Net list (after synthesis), Floor planning,
Partitioning Placement, Clock-tree Synthesis, Routing,
Physical Verification.
The tools used in back-end design are Synopsys (Design
Compiler, IC Compiler). Finally we need check of all
parameters (timing, constraints, power, etc.) The layout
needs to verify against the schematic (LVS). Also we need
to runDRC (design rule checks) to ensure all design rules
are met.
The database is then sent to the foundry. This is Called tape
out and marks the end of the design cycle. The following
description describes the flow from system specification of
design up to tape out. The database is then sent to the
foundry. This is Called tape out and marks the end of the
design cycle.
IV. ARCHITECTURE OF HD AUDIO CODEC
CONTROLLER
Audio codec controller
Fig1. Block diagram of HD Audio
1. Controller
The High Definition Audio controller is a bus mastering I/O
peripheral, which is attached to system memory via PCI or
other typical PC peripheral attachment host interface. It
contains one or more DMA engines, each of which can be
set up to transfer a single audio “stream” to memory from
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the codec or from memory to the codec depending on the
DMA type.
2. Link
The controller is physically connected to one or more
codecs via the High Definition Audio Link. The link
conveys serialized data between the controller and the
codecs. It is optimized in both bandwidth and protocol to
provide a highly cost effective attach point for low cost
codecs. The link also distributes the sample rate time base,
in the form of a link bit clock (BCLK), which is generated
by the controller and used by all Codecs. The link protocol
supports a variety of sample rates and sizes under a fixed
data transfer rate.
3. Codec
One or more codecs connect to the link. A codec extracts
one or more audio streams from the time multiplexed link
protocol and converts them to an output stream through one
or more converters (marked “C”). A converter typically
converts a digital stream into an analog signal (or vice
versa), but may also provide additional support functions of
a modem and attach to a phone line, or it may simply
de-multiplex a stream from the link and deliver it as a single
(un-multiplexed) digital stream, as in the case of S/PDIF.
The number and type of converters in a codec, as well as the
type of jacks or connectors it supports, depend on the
codec.s intended function. The code derives its sample rate
clock from a clock broadcast (BCLK) on the link. High
Definition Audio Codecs are operated on a standardized
command and control protocol.
4. STREAMS AND CHANNELS
The High Definition Audio architecture introduces the
notion of streams and channels for organizing data that is to
be transmitted across the High Definition Audio link. A
stream is a logical or virtual connection created between a
system memory buffer(s) and the codec(s) rendering that
data, which is driven by a single DMA channel through the
link. A stream contains one or more related components or
channels of data, each of which is dynamically bound to a
single converter in a codec for rendering.
Figure2 illustrates several important concepts. First, a
stream is either output or input. Output streams are
broadcast and may be bound to more than one codec; e.g.,
stream #3 might be a two-channel (stereo) stream rendered
by both Codec-A on a headset and by Codec-C on speakers.
Input streams may be bound to only a single codec; e.g.,
stream #2 contains the single channel – the input side of a
modem.
Each active stream must be connected through a DMA
engine in the controller. If a DMA engine is not available, a
stream must remain inactive until one becomes available;
e.g., stream #4 in this example (presumably the one bound
to the headset microphone) is not connected to a DMA
engine and is therefore inactive. As a general rule, all
channels within a stream must have the same sample rate
and same sample size.
Figure 2.Streams
Figure 3 shows how streams and channels are transferred
on the link. Each input or output signal in the link transmits
a series of packets or frames. A new frame starts exactly
every 20.83 s, corresponding to the common 48-kHz
sample rate.
Figure 3. Conceptual Frame Composition
5. LINK PROTOCOL
Link Signaling
The High Definition Audio link is the digital serial
interface that connects High Definition Audio codecs to the
High Definition Audio controller. The link protocol is
controller synchronous, based on a fixed 24.00-MHz clock
and is purely isochronous (no flow control) with a 48-kHz
framing period. Separate input and output serial digital
signals support multiple inbound and outbound streams, as
well as fixed command and response channels.
Figure 4. High Definition Audio Link Conceptual View
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6. Signal Definitions
The signals required to implement a High Definition Audio
link between a High Definition Audio controller and High
Definition Audio codec are summarized in Table and the
following definitions.
Table1. High Definition Audio Link Signal Descriptions
BCLK – Bit Clock: 24.00-MHz clock sourced from the
controller and connecting to all codecs on the Link.
SYNC – This signal marks input and output frame
boundaries (Frame Sync) as well as identifying outbound
data streams (stream tags). SYNC is always sourced from
the controller and connects to all codecs on the link.
SDO – Serial Data Out: one or more serial data output
signal(s) driven by the Controller to all codecs on the link.
Data is double pumped – i.e., the controller drives data onto
SDO, and codecs sample data present on SDO with respect
to every edge of BCLK. Controllers must support at least
one SDO and may support extra SDO lines for extended
outbound bandwidth. Multiple SDOs must be implemented
in powers of 2 (1, 2, or 4). In this chapter, SDO refers to all
SDO signals collectively; specific SDO signals will always
be referenced with a subscript.
SDI – Serial Data In: one or more point-to-point serial data
input signals, each driven by only one codec. Data is single
pumped; codecs drive SDI and the controller samples SDI
with respect to the rising edge of BCLK. Controllers are
required to support at least one SDI signal. In this chapter,
SDI refers to all SDI signals collectively; specific SDI
signals will always be referenced with a subscript.
Controllers are required to support weak pull downs on all
SDI signals. These pull downs are active whenever the
controller is powered or in a wake enabled state. SDI pull
downs are required to prevent spurious wake event in
electrically noisy environments.
RST# - Active low link reset signal. RST# is sourced from
the controller and connects to all Codecs on the link.
Assertion of RST# results in all link interface logic being
reset to default power on state.
Reset and Initialization
In order to minimize link housekeeping sequences, the
High Definition Audio Link has been designed with a single
initialization sequence that always follows a reset sequence.
This section describes all of these, beginning with the two
types of reset that occur within a High Definition Audio
system.
Link Reset – generated by assertion of the link RST# signal
affecting all Link interface logic in both codec and
controller.
Codec Function Group Reset – generated by software
directing a reset command (verb) to a specific function
group within the codec affecting only the targeted codec and
nothing else on the Link.
Link Reset
A link reset is signaled on the Link by assertion of the RST#
signal. (See Figure 28 and Figure 29 for specific RST#
timing.) Link reset results in all Link interface logic in both
codec and controller, including registers, being initialized
to their default state. Note, however, that codec functional
units may contain logic that is not reset with the RST#
signal including logic associated with power management
functions, such as power state information or Caller ID in a
modem codec. Codec functional logic in general must be
reset by a soft command or verb.
Codec Function Group Reset
A codec function group reset allows software to
initialize/reset a specific Codec function group without
affecting or interrupting the operation of the Link. A codec
function group reset is initiated via the Function RESET
command verb, and results in all logic within the targeted
function group being driven to its default or reset state.
Codec Initialization
Immediately following the completion of Link Reset
sequence or when requesting a power state change when the
link is in a low power state, all affected Codec‟s proceed
through a codec initialization sequence as described in this
section and shown in Figure 8 . The purpose of this
initialization sequence is to provide each codec with a
unique address by which it can thereafter be referenced with
Commands on the SDO (broadcast) signal. During this
sequence, the Controller provides each requesting codec
with a unique address using its attached SDI signal(s).
Controllers are required to support independent
(simultaneous) initialization on all SDI signals.
Figure 6. Codec Initialization Sequence
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V. SYNTHESIS
One of the most important steps in ASIC design is the
synthesis phase. Synthesis is a method of converting a
higher level of abstraction to a lower level of
abstraction.The inputs to the synthesis process are RTL
description, circuit constraints and attributes for the design,
and a technology library. The synthesis process produces an
optimized gate-level netlist from all these inputs. This
netlist contains information on the cells used, their
interconnections, area used, and other details. Typical
synthesis tools are:
Cadence RTL Compiler/Build Gates/Physically
Knowledgeable Synthesis (PKS)
Synopsys Design Compiler only after the netlist is
verified for functionality and timing is it sent for the
Physical Design flow.
VI. LOW POWER TECHNIQUES
In this paper we implement frequency switching and power
gating techniques and find out the power consumed and
how much of power can be saved by applying these
techniques.
Frequency scaling – Dynamic frequency/voltage scaling
(DFS and DVS) is a widely used technique to reduce the
overall energy consumption of a system, particularly with
workloads with high variation in processing requirements.
Power Gating
Power gating cuts off leakage current path between supply
(V dd core) and ground (V ss) by using switch transistors
(often, high-Vth or long-channel devices). A typical power
gating methodology with header switches is illustrated in
Figure. When the pg enable signal goes low, the header
switches turn off and leakage current is reduced. While in
the sleep (i.e., power-gated) state, all logic gates connected
to the virtual supply (V dd int) lose their logical states.
Setting the pg enable signal to high resumes circuit
operation after a delay that corresponds to charging circuit
capacitive loads, resetting memory elements, and restoring
state from retention flip-flops connected to V dd core.
Leakage power is the static power and is due to
Sub-threshold conduction, Isub, Reverse bias pn junction
conduction, ID. Gate induced drain leakage, IGIDL due to
tunneling at the gate-drain overlap.
Figure 7. Power gating
VII. EXPERIMENTAL RESULTS
Simulation Waveform of HD Audio Codec Controller
Snap shot 1. Link Reset
Snap shot 2. Link Exit
A link reset is signaled on the Link by assertion of the
RSTN# signal. A controller may only initiate the link reset
entry sequence after completing any currently pending
initialization or state change requests. The link reset and
exit as shown I the above snap shots.
Snap shot 3. Frame synchronization
The Controller generates SYNC signal by dividing BCLK
by 256.All Audio Frames, transferred over AC-link is
synchronized to the rising edge of the SYNC signal.
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Snap shot 4. Frame synchronization
AC-link input frame begins with a low to high transition of
SYNC.
Snap shot 5. Primary and Secondary Codec
When the AC-link “Codec Ready” indicator bit is a „1,‟ it
indicates that the AC-link and AC „97 Codec control and
status registers are in a fully operational state.
Snap shot 6. AC-link Input Frame (SDI)
Each AC-link input frame consists of twelve (12) 20-bit
Time slots. Slot 0 is a special reserved time slot containing
16-bits which are used for AC-link protocol infrastructure.
Snap shot 7. AC Link Frames
Snap shot 8. SDI and SDO
The Codec communicates with its companion Digital
Controller via the AC-link serial interface.AC-link has
been defined to support connections between a single
Controller and up to four Codecs. All digital audio, data
streams, as well as all control (command/status)
information are communicated over this serial
interconnect, which consists of a clock (BIT_CLK), frame
synchronization (SYNC), serial data in (SDATA_IN),
serial data out (SDATA_OUT), and a reset (RESET#).
Schematic of Audio Codec Controller
Snap shot 1.
Snap shot 2. Schematic of codec Controller
VIII. PHYSICAL DESIGN RESULTS The physical design results are obtained using the Synopsys
IC Compiler tool. The obtained results are shown in the
following section.
1. Power Planning Stage
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Snap shot 1. Shows the Insertion of power rails and power
rings.
2. Placement Stage
Snap shot 2. Shows placement of various components
3. Clock Tree Synthesis
Snap shot 3. Shows Clock tree connection
Snap shot 4. Layout after Clock Tree Synthesis
Snap shot 5. Final Layout after Routing stage
IX. LOW POWER RESULTS
Frequency Switching (24kHz):
For 24kHz frequency the power analysis carried out yields
the below output. The total power consumed for frequency
24kHz is = 61.8066 nW.
Frequency Switching (48kHz):
For 48k Hz frequency the power analysis carried out yields
the below output. The total power consumed for frequency
48 kHz is = 127.9281nW.
Frequency Switching (96kHz):
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For 96kHz frequency the power analysis carried out yields
the below output. The total power consumed for frequency
96 kHz is 248.6411 nW.
X. CONCLUSION
In this paper, High Definition Audio Codec Controller was
implemented and verified using the Verilog hardware
description language. The Synopsys VCS simulator tool
was used for simulation and verification of the model. The
hardware model was then synthesized using the Synopsys
Design Compiler tool. The design is synthesized using
Nandgate 40 nm open source technology library. Most of
the power consumed by the processor is the leakage power.
By switching off or cutting down the power
non-simultaneously, most of leakage power can be reduced.
The leakage power consumption of the HD Code Controller
is reduced from 4.616 mw to 0.2mw at 1.9v supply.
Frequency Switching is being carried out for three
different frequencies 24 kHz, 48 kHz and 96 kHz. Lowest
dynamic power consumed at 24 kHz is 61.8066 nW.
XI. REFERENCES
[1] Containing the Nanometer “Pandora-Box”:
Cross-Layer Design Techniques for Variation
Aware Low Power Systems Georgios
Karakonstantis, Member, IEEE, Abhijit Chatterjee,
Fellow, IEEE, and Kaushik Roy, Fellow, IEEE
2011
[2] Ultra Low-Power Clocking Scheme Using Energy
Recovery and Clock Gating Hamid Mahmoodi,
Member, IEEE, Vishy Tirumalashetty, Matthew
Cooke, and Kaushik Roy, Fellow, IEEE 2009
[3] Power gating for ultra-low voltage nanometer ICs:
Kyung Ki Kim; Haiqing Nan; Ken Choi; Sch. of
Electron. Eng., Daegu Univ., Daegu, South Korea.
This paper appears in: Circuits and Systems
(ISCAS), Proceedings of 2010 IEEE International
Symposium. Issue Date : May 30 2010-June 2 2010
[4] “HIGH SPEED ASIC IMPLEMENTATION OF
THE RIJNDAEL ALGORITHM”, Refik Sever, A.
Neslin Ismailog lu, Yusuf C. Tekmen, Murat Askar
IEEE 2004.
[5] “Analysis and Reduction of Ground Bounce Noise
and Leakage Current During Mode Transition of
Stacking Power Gating logic circuits” , R.
Bhanuprakash, Manisha Pattanaik, S. S. Rajput and
Kaushik Mazumdar, IEEE 2009
[6] “Benefits and costs of power-gating technique”
IEEE International Conference on VLSI in
Computers and Processors, Hailin
Jiang,Marek-Sadowska, M, Nassif, S.R. IEEE 2005
[7] “Power gating design for standard-cell-like
structured ASICs” Design, Sin-Yu Chen ,
Rung-Bin Lin ,Hui-Hsiang Tung ,Kuen-Wey Lin ,
Automation & Test in Europe Conference &
Exhibition (DATE), 2010
TEXT BOOKS:
[1] Samir Palnikar “Verilog HDL – A guide to Digital
Design”, Sunsoft Press.
[2] J Bhaskar “A Verilog HDL Primer”, 2nd Edition.
WEB REFERENCES:
[1] http://en.wikipedia.org/wiki/Intel_High_Definition_
Audio
[2] http://www.intel.com/content/dam/doc/product-
specification/high-definition-audio-specification.pdf
[3 ]http://www.simulationexams.com/tutorials/
ccna/wan/hdlc.htm
[4] http://www.frsn.utn.edu.ar/tecnicas3/manuales/
Intel%20hdaudio.pdf