© IMEC 2012 / CONFIDENTIAL


III-V high mobility semiconductors for advanced CMOS applications

Epitaxial growth and in-situ passivation

Clement MERCKLING

09/10/2012


Overview

Introduction & Motivations

Options for III-V integration on Si

Gate stack & in-situ passivation

Conclusions

3 C. Merckling - FPS/WEA/EPI


Motivations for III-V MOS transistors

Higher electron carrier

mobility (@ low-field)

▸ More efficient source injection

Smaller energy bandgap

▸ VDD scaling

Band engineering capabilities

Lower temperature

processing

▸ High- gate first process possible

▸ 3D compatible architecture

C. Merckling - FPS/WEA/EPI 4

Sze, Phys. of Semicond. Devs. 2nd Ed., p.46, 1981

Ge

Si

GaAs

© IMEC 2012 / CONFIDENTIAL © IMEC 2012 / CONFIDENTIAL

ITRS believes in Ge and III-V!

Korea Winter

Public

Conference

ORTC 2011 ITRS



IMEC epi + in-situ oxide “tool park”

MBE and MOVPE

growth techniques

III-V EPI clustered with

in-situ oxide capabilities


AIXTRON Crius 300mm

III-V Selective Epitaxial growth (III-As & III-P)

AMAT/RIBER III-V logic cluster 300mm

III-V Selective Epitaxial growth (III-As & III-P)

In-situ Surface Analysis RIBER ISA 300

Oxide (ALD & MBE) chambers in-situ

RIBER “Twin-MBE 49” cluster 200mm

III-V solid source epitaxy (III-As & III-Sb)

Oxide chamber in-situ


Main issues for III-V integration 1. III-V integration on Si platform

▸ All sorts of crystalline defects

2. Gate stack formation on MOS

▸ Much more difficult to passivate interfaces

3. Smaller bandgap

▸ Increased Ioff due to band-to-band-tunneling

n-type

halo/well

EC

EV

p-type

drain

Band-to-Band Tunneling

III-

V

Ox

ide

???


Dislocation(s)

Twins

Stacking fault

Voids

Anti-phase

boundary

Monoatomic step


III-V heteroepitaxy on Si Challenges

▸ Lattice mismatch

▸ Anti-phase boundaries (APB)

▸ Mismatch stress relaxation and related defects

- Dislocations at interface

- Extended defects (threading arms, SFs)

▸ Defects caused at isolation interfaces

- Twins, stacking faults

- Facets

▸ Interdiffusion at heterogeneous interfaces

But it is possible to achieve

high quality heteroepitaxy by ...

▸ Direct epitaxy

- Metamorphic buffer

- Defect confinement

▸ Wafers bonding


Bolkhovityanov et al., The Open Nanoscience Journal (2009)


Options for III-V materials integration @ imec

Strain relaxed buffer (SRB)

InGaAs metamorphic buffer

▸ MBE growth of low defect density

device quality III-V heterostructure

using a suitable metamorphic buffer


Si: In53%GaAs

Metamorphic

buffer

Defect free

region

III-Sb on Si by MBE

▸ Route to relax III-V since the at

the interface but still defective

(2 2 4)

Si

Ge

AlSb

GaSb

Si

Ge

GaSb/AlSb

GaAs substrate

GaAs

(1 1 5) In0.53Ga0.47As

SRB


Options for III-V materials integration @ imec

Defect confinement – “Necking effect”

▸ Dislocation trapping in narrow

STI trenches for aspect ratio > 2

- low defect density material in the

upper part of the trench.


Defect confinement – “Necking effect”

▸ Selective area growth (SAG) of III-V

compounds -> MOVPE (or CBE ?)

110 nm 150 nm 200 nm

Increasing Aspect ratio improves quality of the top InP layer

Ge seed

InP

Si(001)

STI

InP

InGaAs

S

D

Defects trapped at trench edges

~250-3

00nm

GateG

STI


in-line characterizations for fast TAT

Advanced characterizations

▸ SIMS in STI

▸ Atomprob

▸ SSRM

▸ PL / CL (collab. with Gent Univ.)

in-line metrology for III-V SEG

▸ Available in imec FAB software IIO


Microscope (Leica)

▸ Uniformity, Filling

XRD (Bede)

▸ Crystallinity, ...

CD-SEM

▸ Filling

HRP

▸ Growth rate, filling

Defect counting (KT2835)

▸ Filling, defect density, ...

1E+00

1E+01

1E+02

1E+03

1E+04

1E+05

1E+06

0 20 40 60 80 100 120

Inte

nsi

ty (

Co

un

ts/s

)

Time (min)

AL113646 D06

18O-cts

28Si-cts

30Si-cts

31P-cts

70Ge-cts

74Ge-cts

75As-cts

113In-cts

115In-cts


InxGa1-xAs (x>0.5) integration on Si

Complex epitaxial process to control defects C. Merckling - FPS/WEA/EPI 12

12% 8% 20% 4%

Dislocation(s)

Twins

Stacking fault

Anti-phase

boundary

Monoatomic step

Si

InxGa1-xAs


Challenges of the ART approach ...

High defect density in parallel view

▸ twins/Stacking Faults/APBs

APBs originate from single steps along [110]?

Efficient defect necking effect

Effective double step formation on the

“rounded-Ge” surface

▸ APB observed only with an almost flat Ge surface


ZZ

[-110]

z [110]

Z [110]

w/h=2.9

InP

Ge

APB

Almost flat

Ge surface

TEM10_211

P100334 D15

TEM10_200

P100280 F02

{110} APBs

Ge

InP

{111} SF, twins

“Perpendicular” view “Parallel” view


Elimination of APBs for on-axis Si (001)

Si recess engineering

“V-grooved” surface

▸ (111) surface obtained either by

KOH or TMAH wet etching

▸ Growth inside a pre-defined Si

{111} enclosure: promote initial

III-V nucleation uniformity

▸ APBs trapping ?

“Rounded-Ge” surface

▸ Step creation by surface

engineering of a Ge seed layer

▸ Double steps on a Ge surface more

stable and easy to form with a

lower thermal budget than on Si


STI

{111} Si

G. Wang et al., Appl. Phys.

Lett., 97, 121913 (2010)


InP SEG in “V-grooved” surface

View along STI

▸ Still high density of stacking faults

▸ APBs mainly present at the edges

InP SEG directly on Si(001)

▸ Fully relaxed lattices at the

interface


FFT


InP SEG in “Rounded-Ge” surface

▸ Low density of APBs

▸ Threading dislocations (TDs) confined at

the bottom of the trenches (necking

effect)

▸ Low density of Stacking Faults/Twins

▸ Step flow growth mode due to high step

density

▸ INP LAYER AT THE TOP OF THE

TRENCH IS HIGH QUALITY


G. Wang et al., Appl. Phys. Lett., 97, 121913 (2010)

Cross sectional TEM along the length direction of a 200mm trench

w=100nm, h=50nm w=200nm, h=100nm

w=200nm, h=100nm


InGaAs channel subsequent epitaxy

Smooth InGaAs channel

with homogeneous thickness

▸ Epitaxial quality comparable with

that grown on CMP’ed InP surface

The HCl recess step doesn’t

affect the quality of further

epi grown layers


12.2 {111} {111}

{113}

InGaAs

InP

Ge

InGaAs

InP

InGaAs


Main issues for III-V integration 1. Lattice mismatch/polar vs. non-polar

▸ All sorts of crystalline defects

2. Gate stack formation on MOS

▸ Much more difficult to passivate interfaces

3. Smaller bandgap

▸ Increased Ioff due to band-to-band-tunneling

n-type

halo/well

EC

EV

p-type

drain

Band-to-Band Tunneling

III-

V

Ox

ide

???


Dislocation(s)

Twins

Stacking fault

Voids

Anti-phase

boundary

Monoatomic step


Defect in III-V MOS stack

Theoretical modeling of

oxidation process

Stress accumulation at

GaAs/GaxAsyOz interface

▸ Stress released by formation of Ga/As

vacancies pinning the Fermi level

Model for interface states

for GaAs MOS

Unified model for III-V/insulator

interface state formation

How to control these defects to

prevent Fermi level pinning ????


W.E. Spicer et al., JVST 16(5), 1422 (1979)

GaAs

G

a

A

s

O

GaAs

DO

S

TVB BCB

f

Energy

DO

S

TVB BCB

FLP

f

Energy

G

a

A

s

O

oxidation

M. Scarrozza et al., Surface Science 603, 203 (2009)


RHEED study of surface reconstruction and gate stack formation

20

Ga-rich surface (4x6)

GaAs(001)

2x4

c(4x4)

4x6

3x6

T (ºC)

As-rich surface (2x4)

Al2O3

GaAs

Pt

As

rich

G

a ri

ch

Chang, Merckling et al., Appl. Phys. Lett. (2010)

C. Merckling - FPS/WEA/EPI


Molecular Beam Passivation of high-m channels


III-

V’s

G

e

Ge(001)/H2S

Merckling et al., Microelec. Eng. (2011)

0.6

0.5

0.4

0.3

0.2

Capacitance (

µF

/cm

2)

-2 -1 0 1 2VG (V)

100Hz

1MHz

Ge(001)/GeO2

Bellenger at al., EDL (2010)

0.6

0.4

0.2

Capacitance (

µF/c

m2)

210-1-2

Gate voltage (V)

100 Hz

1 MHz

FGA @ 400°C

0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.10.0

5.0x1012

1.0x1013

1.5x1013

Dit (

eV-1

cm-2

)E-E

V (eV)

Al2O3

GaAs

H2S

Al2O3

GaAs

0.8

0.6

0.4

0.2

0.0-2 -1 0 1 2

Gate voltage (V)

150°C

0.8

0.6

0.4

0.2

0.0-3 -2 -1 0 1 2

Gate voltage (V)

0.8

0.6

0.4

0.2

3210-1-2

Gate Voltate (V)

0.8

0.6

0.4

0.2

3210-1-2

Gate Voltage (V)

100Hz

1MHz

100Hz

1MHz

100Hz

1MHz

100Hz

1MHz

n-type p-type

Merckling et al., Surf. Science (2011)

GaAs(001) w./wo. H2S

In0.53Ga0.47As

Al2O3

HfO2

3 nm

(c)

In0.53Ga0.47As(001)

Chu et al., Appl. Phys. Lett. (2011)

[110] - 4 [110] - 2(a) (b)

2.5

2.0

1.5

1.0

0.5

Capa

citance (

µF

/cm

2)

-2 -1 0 1 2

VG (V)

GaSb(001)

Merckling et al., J. Appl. Phys. (2011)

1.0

0.8

0.6

0.4

Capacitance (

µF

/cm

2)

-2 -1 0 1 2

Gate voltage (V)

100 Hz

1 MHz


UHV in-situ analysis/surface prep?

RIBER ISA300: UHV In-situ Analysis 300mm chamber

SEMI type process module

▸ Connection flange allowing SEMI cluster connection

In-situ analysis: RHEED surface analysis

Surface preparation/molecular beam passivation

High- features

22

From this ...

... to this

RIBER 200 mm “Twin-MBE49” cluster: 2 reactors, surface prep, batch load lock

C. Merckling - FPS/WEA/EPI


First RHEED of 300mm Si surface

Clear 2x1 surface reconstruction observed after

bake + transfer in robot


[110] [100]

[110] [100]

HF dip 2% prior introduction in MBE tool

Bake @ 970C in H2 in the III-V MOVPE reactor


Conclusions

Integration of III-V high mobility material in CMOS on 300mm Si substrates requires manufacturable solutions

▸ SEG hetero-epitaxy is powerful, flexible approach

▸ However MBE approach also show high potential

Key issues

▸ Epitaxy: Defect formation - Intrinsic defects

Lattice mismatch: ART

Polar/non-polar: double atomic steps

- Extrinsic defects (interaction with side walls)

▸ Gate stack: passivation - Surface control

Surface reconstruction

UHV in-situ analysis

Important progress made, more work is needed



Thank you !!!

Questions ???

Clément MERCKLING, PhD

imec, Kapeldreef 75, B-3001 Leuven, Belgium

© IMEC 2012 / CONFIDENTIAL -...

Documents

Transcript of © IMEC 2012 / CONFIDENTIAL -...