III-V MOSFETs for Next Generation · National Chiao Tung University CSD Lab. Tokyo Institute of...
Transcript of III-V MOSFETs for Next Generation · National Chiao Tung University CSD Lab. Tokyo Institute of...
National Chiao Tung University CSD Lab. Tokyo Institute of Technology Iwai Lab. 1
III-V MOSFETs for Next Generation
- Fabrication of III-V MOS Capacitors
Edward Y. Chang, Yueh-Chin LinNational Chiao Tung University
Hiroshi Iwai, Kuniyuki KakushimaTokyo Institute of Technology
National Chiao Tung University CSD Lab. Tokyo Institute of Technology Iwai Lab. 2
Importance of CMOS devices
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La2O3
La-silicate
W
500 oC, 30 min1 nm
k=8~14
k=23
Si
HfO2SiOx layer(0.5~0.7nm)
Si
Higher-kin DirectContact
Si
SiO2(~1.2nm)
Present stage
ContinousScaling for Future Electronics
EOT:Equivalent oxide thickness
III-V sub.
Higher-kin DirectContact
EOT~1.2nm
EOT~0.9nm
EOT~0.5nm
EOT~0.5nm
GreenNanoelectronics
excess leakage current
CMOS device scaling
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Advantages of high-k/ III-V integration
Si GaAs In0.53Ga0.47As In0.7Ga0.3As InAs
Eg (eV) 1.12 1.42 0.74 0.59 0.35
Bulk e mobility cm2 /V s 1400 8500 12000 20 000 40000
Bulk hole mobility cm2 /V s 450 400 300 300~ 400 500
III-V materials have:
High electron mobility
High-low field drift velocity
Good for low power logic application
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1. Redution of interface state density・Selection of high-k material・Proper surface treatments・Optimization in the annealing process2. Reduction of parasitic resistance・Alloy process, etc..
Gate oxide
Gate electrode
III-VInterface state(surface potential control)
Parasitc resistance(power consumption)
Issues in high-k/ III-V technology
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Selection of high-k material for III-V
High interface density Dit: High Dit results in Fermi level pinning, instability, carrier scattering.Oxides with high dielectric constant and large band gap are required.
Oxide Al2O3 HfO2 La2O3 CeO2
k 8~11.5 25 30 38
Eg (eV) 6.65 5.7 4.3 3.2
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National Chiao Tung University CSD Lab.
Tokyo Institute of Technology Iwai Lab.
- Verious high-k for In0.53Ga0.47As substrates
- High-k on verious III-V substrates
- Process engineering- Interface reaction upon process- Electrical characterization
Our collaborative mission
InxGa1-xAs (x=0.53, 0.70, 1.00)
HfO2, La2O3, CeO2, Pr6O11
Establish a material selection guidline for future high-k/III-V technology
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1. ALD Al2O3 on InAs substrarte
2. ALD Al2O3 on InGaAs substrate
3. Surface treatment for La2O3/InGaAs
4. Enhanced deposition for HfO2/InGaAs
Content
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1. ALD Al2O3 on InAs substrarte
National Chiao Tung University CSD Lab. Tokyo Institute of Technology Iwai Lab. 10
Experimental procedure
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(a) Native oxide coverred InAs surface
(b) Al2O3/HCl+TMA-treated InAs
interface.
(c) Al2O3/sulfide+TMA treated
interface.
- As-related oxides are reducedto below level of XPS detection
- In-O(S) bonds are also reduceafter surface treatments,HCl+TMA treatment seemsbe more effective
Al2O3/InAs
HCl+TMA
S+TMA
control
suppressed
suppressed
X-ray photoelectron spectroscopy(XPS) analysis
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- JG < 10-9 A/cm2, with -4 V < VG < 3.5 V, ensure that it is not affect C-V measurement
Al2O3/InAsJ-V analysis
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Al2O3/InAs
- “Low frequency” C-V behavior: Short minority carrier response
- Accumulation regime: ∆C is small and does not seem to be affected significantly by the different surface treatments
- Inversion regime: ∆C (control) > ∆C (sulfide+TMA) > ∆C (HCl+TMA)
TMA only (control) HCl + TMA treatment Sulfide + TMA treatment
10 cycle TMA, 300oC HCl, 1 min10 cycle TMA, 300oC
HCl, 1 min; (NH4)2S, 20min10 cycle TMA, 300oC
Multi frequency C-V analysis
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- Depletion capacitance (Cdep): HCl + TMA → Sulfide + TMA → TMA only (control)
- C-V stretch-out: HCl + TMA → Sulfide + TMA → TMA only (control)Large
Al2O3/InAs
Quasi static C-V (QSCV) analysis
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( )s
ad xnxpNNedx
xVdε
)()()(2
2 −+−−=
• Using full numerical solution of the Poisson equation:
• Nd and Na: are the donor and acceptor
concentrations in the semiconductor
• n(x) and p(x): are the electron and hole density
• εs is the dielectric constant of the semiconductor
• The Dit at the InGaAs, InAs/high-k interface was varied, until a good fit to the
experimental data was obtained
• Charge quantization effects and non-parabolicity in the conduction band is not
included in simulation
C-V simulation with Dit profiles
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QSCV curves were well fitted by the simulations
Al2O3/InAs
C-V simulation results
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TMA only (control) HCl + TMA treatment Sulfide + TMA treatment
- U-shape profile, very similar to Al2O3/In0.53Ga0.47As case (APL 95, 202109)
- Chemical + TMA surface treatments significantly reduce the donor-like traps
- HCl + TMA treated sample shows lower donor like-traps than that of sulfide + TMA treated sample
Al2O3/InAs
Extracted Dit profiles
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2. ALD Al2O3 on InGaAs substrarte
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Al2O3/In0.53Ga0.47As
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X-ray photoelectron spectroscopy (XPS) analysis
(a) Native surface
(b) After TMA treatment
(c) Sulfide + TMA treatment
(d) TMA treatment, PDA: 500C in N2
(e) Sulfide + TMA treatment, PDA: 500C in N2
(f) Sulfide + TMA treatment, PDA: 500C in H2
Sulfide + TMA treatment, PDA: 500C in H2:
strong effect in reducing native oxides
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Al2O3/In0.53Ga0.47As
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TMA treatment only, N2 PDA Sulfide + TMA treatment N2 PDA Sulfide + TMA treatment, H2 PDA
“Bump” Inversion Strong inversion
True inversion response at high frequency of 1 MHz
Multi-frequency C-V characterization
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Al2O3/In0.53Ga0.47As
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Dit extracted by conductance method and simulationSulfide + TMA treatment, H2 PDAHCl + TMA treatment, N2 PDA
Simulation is well fitted
with experimental data
U-shape profiles
Low Dit < 2x1011 eV-1cm-2
at 0.5-0.6 eV above
valence maximum
C-V simulation results
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3. Surface treatment for La2O3/InGaAs
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Gate Voltage ( V )
Cap
acita
nce
( µF/
cm2
)
CV characteristics of La2O3/InGaAs MOS capacitor
EB deposited La2O3Sputter deposited W gate
Large frequency dispersion at accumulation
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Novel interface engineering process
The impact to the CV curves are characterized
CH3
CH3-Si-CH3
O
CH3
CH3-Si-CH3
O
CH3
CH3-Si-CH3
O
In0.53Ga0.47AsInP
HMDS coating
Surface Si passivation using a self-assembled monolayerHMDS (Hexamethyldisilazane )
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HF treatment(control)
(NH4)2S treatment HMDS vapor coating
111411151116111711181119112011141115111611171118111911201114111511161117111811191120
500oC-5min@ F.G.
500oC-5min@ F.G.
500oC-5min@ F.G.
Ga-OGa-La
HF treatment S- passivated Si- passivated
Ga-OGa-O
Gate Voltage ( V ) Gate Voltage ( V ) Gate Voltage ( V )
Cap
acita
nce
( µF/
cm2 )
Impact of Si monolayer insertion to the CV curves
Less GaOx foramtion with less frequency disperssion
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E - Ev ( eV )
Dit
( eV
-1cm
-2)
1013
1012
4HF
HF+(NH4)2S
HF+HMDS
5 min, in F.G.PMA 500 oC
Impact on the interface state density (Dit)
HMDS treatment→Lower Dit especially at Ec edge
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4. Enhanced deposition for HfO2/InGaAs
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The effect of HfO2 deposition temperature
(Preparation: HF cleaning → Vacuum anneal 450oC for 30min)
Deposition at 100 oC
Deposition at 300 oC
Frequency disspersion + Large Dit
High leakage current, (hard to measure)but seems less Dit
Combination of 100 and 300 oC deposition
1nm deposition at 300 oC and the rest at 100 oC
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F.G. anneal, 420 oC
(a)
Gate Voltage ( V )
Cap
acita
nce
( µF/
cm2 )
F.G. anneal, 420 oC
(b)
Gate Voltage ( V )
Cap
acita
nce
( µF/
cm2 )
CV curves measured at RT and 100K with enhanced HfO2 deposition
Large frequency disperssionstill observed at 100K
Almost ideal CV curve obtainedAt 100K with enhanced deposition
1nm @300oC+ 9nm @100oC10nm @100oC
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1013
1014
1012
Interface HfO2depo at 300 oC
HfO2 depoat 100 oC
HfO2: 20 nmHfO2: 10 nm
E - Ei ( eV )
Dit
( eV
-1 cm
-2 )
0.30.20.1
F.G. anneal 420 oC
Dit distribution with enhanced HfO2 deposition
Smaller Dit with interface HfO2 deposited at 300 oC
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Conclusions
Surface treatment of InAs and InGaAs substrate with TMA is effective in removing the native oxide at the interface
With H2 annealing, a Dit below 2x1011 cm-2/eV can be achieved
Si insertion at La2O3/InGaAs by self-assembled monolayer can reduce the frequency disperssion at accumulation
Controling the temperature during the deposition is effective to change the interface properties to reduce the Dit