Computer and Information Engineering Lab II ECE 3102 & ECE 4102
II Ece -Ec1256- Ec II Manual
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Transcript of II Ece -Ec1256- Ec II Manual
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EC 2257 ELECTRONICS CIRCUITS II AND SIMULATION LAB
1. CURRENT SERIES FEEDBACK AMPLIFIER
2. VOLTAGE SHUNT FEEDBACK AMPLIFIER
3. RC PHASE SHIFT OSCILLATOR
4. HARTLEY OSCILLATOR
5. COLPITTS OSCILLATOR
6. COLLECTOR COUPLED ASTABLE MULTIVIBRATOR
7. EMITTER COUPLED ASTABLE MULTIVIBRATOR
8. MONOSTABLE MULTIVIBRATOR
9. CLASS –C TUNNED AMPLIFIERS
10. INTEGRATORS, DIFFERNTIATORS, CLIPPERS AND CLAMPERS.
SIMULATION USING PSPICE
1. ACTIVE FILTER : BUTTERWORTH IInd
ORDER LPF
2. ACTIVE FILTER : BUTTERWORTH IInd
ORDER HPF
3. DIFFERNTIAL AMPLIFIER
4. ASTABLE MULTIVIBRATOR
5. CMOS INVERTER
6. CMOS NOR
7. CMOS NAND
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EX.NO: CURRENT SERIES FEEDBACK AMPLIFIER
DATE:
AIM: To study the frequency response of current series amplifier with and without
feedback
APPARATUS REQUIRED:
Sl.
No.
Apparatus Range Quantity
THEORY:
An amplifier whose fraction of output is fed back to the input is called feedback
amplifier. A feedback amplifier consists of two parts namely amplifier circuit
and feedback circuit. Depending upon whether the feedback signal increases or
decreases the input signal it is classified into two i. Positive Feedback – If the
feedback signal is in phase with the input signal .ii Negative feedback – If the
feedback signal is out of phase with the input signal. The positive feedback
increases the gain of the amplifier whereas the negative feedback decreases the
gain. In the current series feedback connection a fraction of the output current
is converted into a proportional voltage by the feedback network and then
applied in series with the input.
DESIGN:
Vcc=10V, Ic=2mA, β=200, Vce=Vcc/2=10/2=5V.
Ve=Vcc/10=10/10=1V.
Re=Ve/Ie=1/2m=500Ω≈560Ω
Vrc = Vcc-Vce-Ve = 10-5-1 = 4V.
Rc = Vrc/Ic=4/2m=2KΩ≈2.2kΩ To find R1 & R2
VB = VBE + VE
0.7 + 1
VB = 1.7V
w.k.t I1 = 10 IB
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IB = I1 / 10
IC = β IB
IC = β I1 / 10
IE = β I1 / 10 (IC = IE ) From the ckt I1 = VE / R2
IE = β VE / 10R2 R2 = β VE / 10 IE R2 = β RE / 10 R2 = 10K
VB = R2Vcc / R1 + R2
1.7 = 10 x 103 x 10 / R1 + 10 x 10
3
1.7 R1 + 17 x 103 = 100 x 10
3
R1 = 48.82K
R1 = 47K
PROCEDURE : The connections are done as shown in the diagram. The input voltage
is set to a fixed value. Vary the frequency and note down the output voltage.
Repeat the same with feedback. Calculate the gain and plot the graph.
PIN DIAGRAM:
Collector
BC107
Base
Emitter
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CIRCUIT DIAGRAM:
With Feedback:
Without Feedback:
MODEL GRAPH
Without feedback
With Feedback
Gain
(in dB)
Frequency (in Hz)
CRO
CRO Vin
0.1uF
560
+10V
2.2K
0.1uF
R1 47K
R2 10K
BC107
CRO
100uF
CRO
Vin
0.1uF
560
+10V
2.2K
0.1uF
R1 47K
R2 10K
BC107
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Tabulation: With feedback Vi =
S.No FREQUENCY in Hz OUTPUT VOLTAGE
Vo in volts
GAIN = 20 log(Vo/Vi)in db
Tabulation: Without feedback
Vi =
S.No FREQUENCY in Hz OUTPUT VOLTAGE
Vo in volts
GAIN = 20 log(Vo/Vi)in db
RESULT:
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EX.NO: VOLTAGE SHUNT FEEDBACK AMPLIFIER
DATE:
AIM: To study the frequency response of voltage shunt feedback amplifier with and
without feedback
APPARATUS REQUIRED:
Sl.
No.
Apparatus Range Quantity
THEORY:
An amplifier whose fraction of output is fed back to the input is called feedback
amplifier. A feedback amplifier consists of two parts namely amplifier circuit
and feedback circuit. Depending upon whether the feedback signal increases or
decreases the input signal it is classified into two i. Positive Feedback – If the
feedback signal is in phase with the input signal .ii Negative feedback – If the
feedback signal is out of phase with the input signal. The positive feedback
increases the gain of the amplifier whereas the negative feedback decreases the
gain. In the voltage shunt feedback connection a fraction of the output voltage
is applied in parallel with the input voltage through the feedback network The
voltage shunt feedback connection decreases both input and output resistances
of the feedback amplifier by a factor equal to (1+ βAv)
DESIGN:
RC’ = 2.5KΩ, R = 1.8KΩ, RF = 10KΩ
RC’= RC
’ RF / (RC
’ + RF) = RC
’ RF / ( RF - RC
’) = 2.5K*10K/(10K-2.5K)
RC = 3.3KΩ
R = RC RC /( RC + RC)
R RS + R RF = RS RF
RC = R RF /( RF - R ) = 1.8K*10K/(10K-1.8K)
Rs=2.2KΩ
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PIN DIAGRAM:
CIRCUIT DIAGRAM:
With Feedback
CRO
Q1
BC107
Rc 3.3K
+10V
2.2K
Rf
10K
Vin
CRO
0.01uF
0.01uF
Collector
BC107
Base
Emitter
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WithoutFeedback:
CRO
Q1
BC107
Rc 3.3K
+10V
2.2K
Vin
CRO
0.01uF
0.01uF
MODEL GRAPH
Without feedback
With Feedback
Gain
(in dB)
Frequency (in Hz)
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Tabulation:
With feedback Vi =
S.No FREQUENCY in Hz OUTPUT VOLTAGE
Vo in volts
GAIN = 20 log(Vo/Vi)in db
Tabulation:
Without feedback Vi =
S.No FREQUENCY in Hz OUTPUT VOLTAGE
Vo in volts
GAIN = 20 log(Vo/Vi)in db
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PROCEDURE : The connections are done as shown in the diagram. The input voltage
is set to a fixed value. Vary the frequency and note down the output voltage.
Repeat the same with feedback. Calculate the gain and plot the graph.
RESULT :
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Ex.No: RC PHASE SHIFT OSCILLATOR
Date:
AIM: To design and construct a RC phase shift oscillator to generate a sine wave of a
frequency f = 1.98 KHz.
APPARATUS REQUIRED:
Sl.
No.
Apparatus Range Quantity
THEORY:
Oscillator is a feed back circuit where a fraction of output voltage of an amplifier
is fed back to the input in the same phase. RC phase shift oscillators are a sine wave
oscillator which is used in the audio frequency range. It has a CE amplifier ,which
provides 180°.phase shift to the input signal and three frequency selective RC phase shift
networks provides a phase shift of 60°of each , a total of 180° for a signal with frequency
equal to specific value, which corresponds to the output of the oscillator. Thus the total
phase shift between the input and output is360°.
The frequency of oscillation is given by
f = 1/( 2 Π RC √(6+4K) )
DESIGN:
VCC = 20 V
IE = 2mA, hfe = 100
VCE = VCC /2 = 10 V
VE = VCC /10 = 2 V
RE = VE / IE = VE / IC 2/2m
RE = 1KΩ
RC = Vcc – Vce – Ve / Ic
RC = 20 – 10 – 2 / 2 x 10-3
RC = 4K
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To find R1 & R2
VB = VBE + VE
0.7 + 2
VB = 2.7V
w.k.t I1 = 10 IB
IB = I1 / 10
IC = β IB
IC = β I1 / 10
IE = β I1 / 10 (IC = IE ) From the ckt I1 = VE / R2
IE = β VE / 10R2 R2 = β VE / 10 IE R2 = β RE / 10 R2 = 10K
VB = R2Vcc / R1 + R2
2.7 = 10 x 103 x 20 / R1 + 10 x 10
3
2.7 R1 + 27 x 103 = 200 x 10
3
R1 = 64K
Frequency:
F = 1/(2πRC)*1/(√(6+4(RC +R))
From circuit, R = 2.2KΩ, C = 0.01µF
F = 1/(2π*2.2K*0.01µ*√(6+4(4K/2.2K)) = 1.98 KHz.
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PIN DIAGRAM:
CIRCUIT DIAGRAM:
0.01uF
Vo
0.01uF
2.2K
1K 0.4uF
0.01uF
0.01uF
2.2K
+20V
4K
0.01uF
2.2K
R1 69K
R2 10K
BC109
MODEL GRAPH
amplitude
in volts
t in ms
Collector
BC109
Base
Emitter
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OBSERVATION
Amplitude in volts Time period (ms) (T) Frequency in Hz ( f= 1/ T)
PROCEDURE:
1. The connection is made as per the circuit diagram.
2. Set the RPS to 20Volts.
3. Observe the output and measure the time period of the output waveform Vo ,
determine the frequency and trace it
4. Plot the output on a graph sheet.
5. Compare the experimental value with the theoretical value of output frequency.
RESULT:
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Ex.NO: HARTLEY OSCILLATOR
Date:
AIM: To design a Hartley oscillator and to generate a sine wave of a frequency of
4.59 KHz.
APPARATUS REQUIRED:
Sl.
No.
Apparatus Range Quantity
THEORY: It is a sinusoidal oscillator which uses a single tapped coil having two parts
named L1 and L2.The tank circuit also includes a capacitor. The centre point of
L1 and L2 is grounded. They are inductively coupled and form an auto
transformer or a split tank inductor. Feedback between the input and output
circuit is accomplished through the autotransformer action which gives 180ο
phase shift .The transistor introduces 180ο phase shift, therefore the total phase
shift is 360ο and hence the feedback is positive or regenerative. In The circuit
R1 and R2 form a voltage divider for providing base bias and RE is an emitter
swamping resistor to add stability to the circuit. When Vcc is applied, an initial
bias is established by R1 and R2 and oscillations are produced because of
positive feedback from the LC tank circuit.
DESIGN:
Vcc = 10 V :Ie = 1mA., hfe = 200, Vce = Vcc/2 = 5 V
Ve = Vcc/10 = 1 V :Re = Ve/Ie = 2/2m :Re = 1KΩ
Rc = Vcc – Vce – Ve / Ic
= 10 – 5 – 1 / 1 x 10-3
Rc = 4K
To find R1 & R2
VB = VBE + VE
0.7 + 2
VB = 1.7V
w.k.t I1 = 10 IB
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IB = I1 / 10
IC = β IB
IC = β I1 / 10
IE = β I1 / 10 (IC = IE ) From the ckt I1 = VE / R2
IE = β VE / 10R2 R2 = β VE / 10 IE R2 = β RE / 10 R2 = 22K
VB = R2Vcc / R1 + R2
1.7 = 20 x 103 x 10 / R1 + 20 x 10
3
1.7 R1 + 17 x 103 = 200 x 10
3
R1 = 97.6K
R1 = 100K
Frequency:
L1 = L2 = 60mH, C = 0.01µF
F = 1/(2π√(LC))
L = L1+L2 = 0.12H
F = 1/(2π√(0.12*0.01µ)) = 4.59 KHz
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PIN DIAGRAM:
CIRCUIT DIAGRAM:
22uF60mH
0.01uF
1K
60mH
0.03uFVo
+10V
10K
0.01uF
R1 83K
R2 22K
BC148
MODEL GRAPH
amplitude in
volts
BC148
C B E
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T in ms
OBSERVATION
Amplitude in volts Time period (ms) (T) Frequency in Hz ( f= 1/ T)
PROCEDURE:
1. The connection is made as per the circuit diagram.
2. Set the RPS to 10Volts.
3. Observe the output and measure the time period of the output waveform Vo ,
determine the frequency and trace it
4. Plot the output on a graph sheet.
5. Compare the experimental value with the theoretical value of output frequency.
RESULT:
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Ex.No: COLPITTS OSCILLATOR
Date:
AIM: To design an Colpitts oscillator to generate a sine wave of a frequency
9.188 KHz.
APPARATUS REQUIRED:
Amplitude in volts Time period (ms) (T) Frequency in Hz ( f= 1/ T)
THEORY: A colpitts oscillator is to generate sine wave in the frequency range 1-
500Mhz.It uses a LC tuned circuit with a CE amplifier to obtain oscillations.
The feedback consists of two capacitors C1 and C2 and an inductor L.The
Resistors R1 , R2 and RE provide dc bias to the transistor. The feedback
between the output and input circuit is accomplished by the voltage developed
across the capacitor C2 Feedback between the input and output circuit is 180ο
phase shift .The transistor introduces 180ο phase shift, therefore the total phase
shift is 360ο and hence the feedback is positive or regenerative. When Vcc is
applied, an initial bias is established by R1 and R2 , the capacitors C1 and C2
are charged . The capacitors discharge through the coil(L) which sets up the
frequency of oscillations f = 1/( 2 Π √(L Ceq))where Ceq= C1 C2 / C1+ C2.The
oscillations across the capacitor C2 is fed back to the base-emitter junction and
appear in an amplified form at the collector.
DESIGN:
Vcc = 10 V :Ie = 1mA., hfe = 200, Vce = Vcc/2 = 5 V
Ve = Vcc/10 = 1 V :Re = Ve/Ie = 2/2m :Re = 1KΩ
Rc = Vcc – Vce – Ve / Ic
= 10 – 5 – 1 / 1 x 10-3
Rc = 4K
To find R1 & R2
VB = VBE + VE
0.7 + 2
VB = 1.7V
w.k.t I1 = 10 IB
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IB = I1 / 10
IC = β IB
IC = β I1 / 10
IE = β I1 / 10 (IC = IE ) From the ckt I1 = VE / R2
IE = β VE / 10R2 R2 = β VE / 10 IE R2 = β RE / 10 R2 = 22K
VB = R2Vcc / R1 + R2
1.7 = 20 x 103 x 10 / R1 + 20 x 10
3
1.7 R1 + 17 x 103 = 200 x 10
3
R1 = 97.6K
R1 = 100K
Frequency:
L = 60mH, C1 = C2 = 0.01µF
F = 1/(2π√(LC))
C = C1C2/(C1+C2) = (0.01µ)2
/(0.01µ+0.01µ) = 5nF
F = 1/(2π√(60m*5n)) = 9.188 KHz
PIN DIAGRAM
PROCEDURE:
1. The connection is made as per the circuit diagram.
2. Set the RPS to 10Volts.
3.Observe the output and measure the time period of the output waveform Vo ,
determine the frequency and trace it
4. Plot the output on a graph sheet.
5. Compare the experimental value with the theoretical value of output frequency.
BC148
C B E
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CIRCUIT DIAGRAM:
MODEL GRAPH
amplitude in
volts
T in ms
OBSERVATION
Amplitude in volts Time period (ms) (T) Frequency in Hz ( f= 1/ T)
RESULT:
Rc4K
0.01uF
0.1uF
+10V
Re1K
C10.01uF
BC148
Vo
L
60mH
C20.01uF
R222K
Ce
22uF
R1100K
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Ex.No: COLLECTOR COUPLED ASTABLE MULTIVIBRATOR
Date:
AIM : To design an astable multivibrator and to obtain the output waveform for a
frequency of 7.24KHz.
APPARATUS REQUIRED:
Sl.
No.
Apparatus Range Quantity
THEORY:
The Astable multivibrator has 2 Quasi-states. And they’re unstable. Without any
external trigger, the multivibrator keeps on alternating in states.
The frequency of the oscillations are determined by the values of R and C used in
the circuit.Astable multivibrator is also called as free running oscillator.as soon as we
switch on the power supply any one of the transistor is turned on, since both the
transistors are not identical.there will be voltage drop on the collector of that transistor,
which is taken as an input to the second transistor.the second transistor is connected to
the collector of the first transistor .Hence the second transistor turns on now.this process
repeats, finally we get a square wave as an output.
DESIGN:
Vcc = 10 V
Ic = 12 mA
β = 20
Re = 250Ω
Ic = Ie = 12mA
Ve = IeRe = 12m * 250 = 3 V
Ib = Ic/ β = 0.6 mA
Rb = (Vcc – Vbe – Ve)/Ib = (10 - 0.7 – 3)/0.6m = 10.5 KΩ
Frequency:
F = 1/(1.38RC)
From Circuit, R = 10 KΩ
C = 0.01µF
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F = 1/(1.38*10K*0.01µ) = 7.24 KHz
MODEL GRAPH:
(in volts)
Period (in us)
Amplitude
PIN DIAGRAM:
CIRCUIT DIAGRAM:
Vo
1K
BC109BC109
0.01uF
1k
0.01uF
10K10K
+10V
BC109
Base
Emitter
Collector
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TABULATION:
Amplitude
(in volts) Time Period
(in msec)
PROCEDURE:
1. Connections are given as per the circuit diagram.
2. Supply voltage is kept at 10V.
3. CRO connected at the output is adjusted and the square wave output is
obtained.
4. The amplitude and time period (Ton and Toff) of the signal is noted.
5. The output waveform is plotted in a graph, taking Amplitude in Y-axis and
Time period in X-axis.
6. Then the practical value of the frequency is calculated.
RESULT:
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Ex. No : EMITTER COUPLED ASTABLE MULTIVIBRATOR
Date:
AIM: To design an emitter coupled astable multivibrator for a pulsewidth of 6.9µS.
APPARATUS REQUIRED:
Sl.
No.
Apparatus Range Quantity
THEORY:
Square wave outputs are generated when the OPAMP is forced to operate in the
saturated region. That is, the out put of the OPAMP is forced to swing repetitively
between positive saturation V sat and negative saturation –Vsat, resulting in the square
wave output. Astable multivibrator circuit is shown in figure. The output of the OPAMP
in this circuit will be in positive or negative saturation, depending whether the differential
voltage is positive or negative, respectively.
The time period T of the out wave form is T = 2 RC ln ( (1+β)/(1-β))
β=R2/(R1+R2)
If R1 = 1.16 R2
T = 2RC
Frequency = 1/(2RC)
DESIGN SPECIFICATION: PW = 6.9µs, , Vcc = 5 V, hfe = 50
Rc = Vcc/Ic = 2.2K Ω
Re = Vcc/2Ic = 1.2K Ω
Ib = Ic/ hfe = 40µA
Rb = (Vcc – Vbe )/Ib = 100K Ω
PW = 0.69RbC
6.21µ= 0.69*150*C
C = 6.9µ/(0.69*100K) = 100pF
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PIN DIAGRAM:
CIRCUIT DIAGRAM:
Vo
2.2K
BC107BC107
100pF
2.2K
Re1.2K
100pF
100K100K
+5V
Collector
BC107
Base
Emitter
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MODEL GRAPH
(in volts)
Period (in us)
Amplitude
TABULATION:
Amplitude (in volts) Time Period (in msec)
TON (ms) TOFF (ms)
PROCEDURE:
i. Connect the circuit shown in figure using component values as obtained in
design.
ii. Observe and sketch the capacitor voltage wave form and output wave form.
iii. Determine the frequency.
RESULT :
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Ex.No: MONOSTABLE MULTIVIBRATOR
Date:
AIM: To design, construct and test a monostable multivibrator.
APPARATUS REQUIRED:
Sl.
No.
Apparatus Range Quantity
THEORY:
Monostable Multivibrator is also called as one shot Multivibrator and can be used
to generate a gating pulse, whose width can be controlled. The Monostable Multivibrator
provides a single pulse of desired duration in response to an external trigger. The external
trigger cases the circuit to go to a Quasi-stable state. After a certain interval, the circuit
comes to stable state.
The width or duration of the pulse is obtained at the collector or ouput of either
transistor of the Monostable Multivibrator, is given by the expression,
tp = 0.69 R3 C1 seconds.
DESIGN SPECIFICATIONS :
PW = 6.21µs, R = 150Ω, Vcc = 5 V, hfe = 10
Ic = 3 mA, Vcesat = 0.2 V
PW = 0.69RC
6.21µ= 0.69*150*C
C = 0.06µF
Rc2 = (Vcc – Vd - Vcesat)/Ic = (5 – 0.7 – 0.2)/3m = 1.366K ≈ 1KΩ
Rc1 = Rc2 = 1KΩ
Ib2 = Ic/ hfe = 300µA
Rb2 = (Vcc – Vbe - Vdt)/Ib2 = 12K Ω
Frequency:
F = 1/(2*pulse width) = 1/(2*6.21µ) = 80 KHz
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CIRCUIT DIAGRAM
1N4007
150 BC107 BC10712K
1K
1K 22K
FG
0.06uF
Vo
+5V
1K
MODEL GRAPH
(in volts)
Period (in us)
Amplitude
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TABULATION
Amplitude (in volts) Pulse width (in msec)
PROCEDURE :
1. The connection is made as per the circuit diagram.
2. Apply a negative going pulse as the input signal.
3. Observe the output voltage across the capacitor Vc and the output waveform Vo
and trace it.
RESULT :
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Ex.No: CLASS C TUNED AMPLIFIER
Date:
AIM: To design construct and test a Class –C tuned amplifier for a tuning frequency of
7KHz.
APPARATUS REQUIRED
Sl.
No.
Apparatus Range Quantity
THEORY:
Tuned amplifier is used to amplify the input signal at the tuned frequency only.
The input signal other than tuning frequency are attenuated . The class –C
amplifier is developed to make the circuit operate only for portion of input signal ,
I,e less than 90 degrees. The Class –C amplifier works on the principle of tuning
the parallel RLC resonant circuit to tuning frequency. The value of Lc decide the
tuning frequency and is related as f= (1/ (2 Π √(Lc))). The values of LC are
chosen for the required tuning frequency interval. During the remaining period the
Q is in cut-off region and no current flows through its collector. The energy in the
tank circuit supplies the load current through capacitor. Once the input signal
frequency is out of the tuning frequency, the oscillation in the tank circuit cannot
be sustained. Thus the circuit attenuates input signals other than tuning frequency.
DESIGN: Fr = 1/ 2π√LC , fr = 7KHz
Let C= .001µF, then L = 1/((2 Π ftune)^2*C) ;
L = 1/((2*3.14*7*10^3)^2*0.001*10^-6) ;
L = 516mH
PROCEDURE:
1. Connections are made as shown in the circuit diagram.
2. Input signal is set at 6MHz , 1V peak is given and the corresponding output is
noted from the CRO
3. Observe the output and measure the time period and amplitude of the output
waveform Vo , determine the frequency and trace it
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4. Obtain the tuning frequency from the plot of the frequency response..
CIRCUIT DIAGRAM:
OBSERVATION: Vi =
S.No FREQUENCY in Hz OUTPUT VOLTAGE
Vo in volts
GAIN = 20 log(Vo/Vi)in db
MODEL GRAPH:
RESULT:
CRO
CRO
Vin
0.01uF
+10V
516mH
0.01uF
R2 4.7K
BC107
0.001µf
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Ex.No: INTEGRATOR ,DIFFERENTIATOR , CLIPPERS AND CLAMPERS
Date:
AIM:
To construct and test integrator ,differentiator, clippers and clampers circuit and
to obtain the output waveform.
APPARATUS REQUUIRED:
Sl.
No.
Apparatus Range Quantity
THEORY: INTEGRATOR :
The circuit performs the mathematical operation of integration, that is , the o/p waveform
is the integral of the i/p waveform. The output voltage
Vo (t) = - ( 1 / R C )∫vi(t) dt
DIFFERENTIATOR :
The circuit performs the mathematical operation of differentiation , that is , the o/p
waveform is the derivative of the i/p waveform. The output voltage
Vo(t) = - R C (dvi / dt) CLIPPERS:
Clippers have the ability to clip off a portion of the input signal without distorting the
remaining part of the alternating waveform.. The half wave recitifier is an example of the
simplest form of diode clipper – one resistor and diode. Depending upon the orientation
of the diode , the positive or negative region of the input signal is clipped off.
Clippers are of two : I . Series ii. Parallel
Series configuration is defined as one where diode is in series with the load, while the
parallel the diode is connected in parallel to the load.
CLAMPERS:
The clamping network is one that will clamp a signal to different dc level. The circuit
has a diode, resistor and a capacitive element, but it can also employ an independent dc
supply to introduce an additional shift. The magnitude of R and C must be chosen that the
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time constant τ = RC is large enough that the voltage across the capacitor does not
discharge significantly during the interval diode is nonconducting.
PROCEDURE:
(i)Connect the differentiator circuit. Adjust the signal generator to produce a 1V peak
a. sine wave at 100Hz.
b. square wave at 100 Hz
(ii) Observe i/p and o/p waveform on the oscilloscope .Measure and record the peak
value of Vo and the phase angle of Vo w.r.t Vi.
(iii) Connect the integrator circuit Adjust the signal generator to produce a 1V peak
a. sine wave at 5kHz. b. square wave at 5kHz
iv.Observe and record the input and the output waveforms.
CIRCUIT DIAGRAM
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Tabulation
Differentiator Integrator
CLIPPERS
Positive Clipper:
FG
560
Vo1N4007
Negative Clipper:
Amplitude
in V
Time period
(ms)
Input
Output
Amplitude
in V
Time period
(ms)
Input
Output
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FG
560
1N4007
Vo
Tabulation
Positive Clipper: Negative Clipper:
Amplitude
(in volts)
Time Period
(in msec)
Amplitude
(in volts)
Time Period
(in msec)
Input
Input
Output
Output
CLAMPERS
Positive Clamper:
FG1N4007
1uF
Vo
Negative Clamper:
FG Vo1N4007
1uF
Clampers: Clippers: Input Signal: Input Signal:
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Positive Clamped Output: Negative Clipped Output:
Negative Clamped Output: Positive Clipped Output:
Tabulation
Positive Clamper: Negative Clamper:
Amplitude
(in volts)
Period
(in sec)
Amplitude
(in volts)
Period
(in sec)
Input
Input
Output
Output
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RESULT:
SIMULATION USING PSPICE
Ex.No: SECOND ORDER LOW PASS FILTER
AIM: To plot the frequency response of active second order low pass filter using
OP-AMP in Pspice.
SIMULATOR:
Pspice simulator.
THEORY:
An improved filter response can be obtained by using a second order active
filter consist of two RC pairs. It has a rool-off rate of -40dB/decade. The transfer
function of a low pass filter is
H(s) = AoωωωωH2
S2 + αωαωαωαωHS + ωωωωH
2
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For n=2, the clamping factor α =1.414 α =1.414 α =1.414 α =1.414,the pass band gain ,Ao=3-αααα=1.586.
Cut-off frequency of the filter =1/2ΠΠΠΠRC.
DESIGN:
f=1KHz Assume C=0.1 µµµµF, R=1.6KΩ.Ω.Ω.Ω.
Ao=1+Rf /Ri => Rf /Ri=0.586.
Let Rf = 5.86 KΩ.,Ω.,Ω.,Ω., Ri =10 KΩ.Ω.Ω.Ω.
NETLIST:
LOW PASS FILTER
V1 1 0 AC 1V
V2 6 0 DC +15V
V3 7 0 DC -15V
Rf 2 3 5.8K
Ri 1 4 10K
R3 3 7 1.6K
R4 4 6 1.6K
X 3 4 6 7 5 UA741
LIB
AC DEC 10 100 3K
PROBE
END
CIRCUIT DIAGRAM:
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RESULT: Thus, the frequency response of active second order low pass filter was
plotted.
ACTIVE HIGH PASS FILTER.
Date:
AIM : To design and simulate a second order Low –pass filter using Op-amp and to
obtain the frequency response and roll off rate.
ALGORITHM:
1. Mark the each node with a number.
2. Enter each component between nodes.
3. Call the UA 741 Op-amp from the .NOM library.
4. Use the .AC statement to vary the frequency.
5. Observe the frequency response of the filter.
6. Calculate the Roll-off rate
DESIGN:
Gain = Af =3-2K
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K= damping factor= coefficient of s/2 = 1.414/2 = 0.707
Af = 3-2(0.707) = 1.586
Af= 1+ (Rf +R1) = 1.586
Choose Rf/R1 = 0.586, Let R1= 1K, Rf=
Fh= upper 3db frequency = 1/(2*pi*( R2 * R3 * C2*C3)^(1/2)
Let R2 = R3 = R =1K ohms, C= 0.79micro farads
CIRCUIT DIAGRAM:
PROGRAM:
Vcc 4 0 DC 12V
VEE 0 7 DC 12V
Vin 1 0 AC 1V
R1 4 0 1K
R2 1 2 1K
R3 2 3 1K
Rf 4 5 0.586K
C2 2 5 0.79uf
C3 3 0 0.79uf
X1 4 3 5 0 OPAMP
.subckt OPAMP 1 2 5 4
RI 1 2 2 MEG
Ro 3 5 7 5
EA 3 4 2 1 2E+5
.ends OPAMP
.AC DEC 10Hz 100Hz 1 MEGHz
.probe
.end
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RESULT: The program for an active low pass filter is written and executed successfully
Ex.No: ASTABLE MULTIVIBRATOR
Date :
AIM : To simulate an astable multivibrator.
ALGORITHM:
1. Mark the each node with a number.
2. Enter each component between nodes
3. Simulate the circuit using PSPICE.
4. Use the .PLOT TRAN function to obtain the graph.
5.Use the .TRAN function to obtain the transient function.
CIRCUIT DIAGRAM:
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Vo
1K
BC109BC109
0.01uF
1k
0.01uF
10K10K
+10V
PROGRAM
Vcc 6 0 DC 5V
Rc1 6 1 1K
Rc2 6 2 1K
R1 6 3 30K
R2 6 4 30K
C1 1 4 150Pf
C2 2 3 150Pf
Q1 1 3 0 QN
Q2 2 4 0 QN
.model QN NPN ( IS = 2E-16 BF = 50 BR = 1 RB = 5 RC = 1 RE = 0 TF = .2ns
TR = 5ns)
.nodeset V(1) =0 V(3) =0
.TRAN / OP 0.1us 10us
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.options ABSTOL = 1.0N REILTOL = 10M VNTOL = 1M ITL5 = 40 000
.probe
.end
RESULT: The program for an astable multivibrator is written and executed successfully
CMOS INVERTOR
AIM:
To plot the transient response of the output signal of the CMOS INVERTOR
circuit from 0ms to 50ms in steps of 1ms using Pspice.
SIMULATOR:
Pspice simulator.
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THEORY:
CMOS circuits take the advantage of the fact that both N-channel and P-
channel devices can be fabricated on the same substrate. The basic CMOS circuit is
the invertor which consist of one P-channel and one N-channel transistor. The
source terminal of the P-channel is at VDD and source terminal of N-channel device is
at ground.
When the input is low, both gates are at zero potential. The input is at VDD
relative to the source of the P-channel device and at 0V relative to the source of the
N-channel device. The result is that the P-channel device is under these conditions,
there is a low impedance path from VDD to the output and a very high impedance
from output to ground. Therefore, the output voltage goes to high level , VDD under
normal loading conditions.
When the input is high both gates are at VDD and the situation is reversed.
The P-channel device is turned OFF and N-channel is turned ON. The result is that
the output approaches low level of 0V.
NETLIST:
CMOS INVERTOR
VDD 1 0 DC 5V
VIN 1 0 PULSE ( 0 5V 0 1N 1N 5M 10M )
M1 3 2 1 1 PMOD
MODEL PMOD PMOS
M2 3 2 0 0 NMOD
MODEL NMOD NMOS
TRAN 1M 50M
PROBE
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END
CIRCUIT DIAGRAM:
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TRUTH TABLE:
INPUT OUTPUT
A Y=A’
0
1
1
0
RESULT: Thus, the transient response of the output signal for 0to 50ms in steps of 1ms
was plotted.
CMOS NAND
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AIM:
To plot the transient response of the output signal of the CMOS NAND circuit
from 0ms to 50ms in steps of 1ms using Pspice.
SIMULATOR:
Pspice simulator.
THEORY:
CMOS circuits take the advantage of the fact that both N-channel and P-
channel devices can be fabricated on the same substrate. CMOS circuits consists of
both types of MOS devices, interconnected to form logic functions.
Another CMOS basic gate is the NAND gate which consists of two P-type units
in parallel and two N-type units in series as shown in circuit. If all inputs are high,
both P-type transistors are turned OFF and both N-channel transistors are turned
ON. The output has low impedance to the ground and produces a low state. If any
input is low, the associated N-channel transistor is turned OFF and the associated P-
channel transistor is turned ON. The output is coupled to VDD and goes to high state.
If both the inputs are low, the P-type transistor are turned ON and both the N-
channel transistor are turned OFF. The output has a high impedance to the ground
and produces a high state. Multiple input NAND gates may be formed by placing
equal number of P-type and N-type transistors in parallel and series respectively.
NETLIST:
CMOS NAND
VDD 1 0 DC 5V
V1 3 0 PULSE( 0 5V 0 1N 5M 10M )
V2 2 0 PULSE( 0 5V 0 1N 5M 10M )
M1 5 2 1 1 PMOD
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M2 5 3 1 1 PMOD
MODEL PMOD PMOS
M3 5 3 4 4 NMOD
M4 4 2 0 0 NMOD
MODEL NMOD NMOS
TRAN 1M 50M
PROBE
END
CIRCUIT DIAGRAM:
TRUTH TABLE:
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RESULT: Thus, the transient response of the output signal for 0to 50ms in steps of 1ms
was plotted.
CMOS NOR
INPUT OUTPUT
A B Y=(AB)’
0
0
1
1
0
1
0
1
1
1
1
0
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AIM:
To plot the transient response of the output signal of the CMOS NOR circuit
from 0ms to 50ms in steps of 1ms using Pspice.
SIMULATOR:
Pspice simulator.
THEORY:
CMOS circuits take the advantage of the fact that both N-channel and P-
channel devices can be fabricated on the same substrate. CMOS circuits consists of
both types of MOS devices, interconnected to form logic functions.
Another CMOS basic gate is the NOR gate which consists of two N-type units
in parallel and two P-type units in series as shown in circuit. If all inputs are low,
both P-type transistors are turned ON and both N-channel transistors are turned
OFF. The output is coupled to VDD and goes to high state. If any input is high, the
associated P-channel transistor is turned OFF and the associated N-channel
transistor is turned ON, connecting the output to the ground and causing a low level
output. If both the inputs are high, the P-channel units are turned OFF and both the
N-channel units are turned ON. The output goes to low state.
NETLIST:
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CMOS NOR
VDD 3 0 DC 5V
V1 1 0 PULSE ( 0 5V 0 1N 1N 5M 10M )
V2 2 0 PULSE ( 0 5V 0 1N 1N 5M 10M )
M1 4 1 3 3 PMOD
M2 5 2 4 4 PMOD
MODEL PMOD PMOS
M3 5 1 0 0 NMOD
M4 5 2 0 0 NMOD
MODEL NMOD NMOS
TRAN 1M 50M
PROBE
END
CIRCUIT DIAGRAM:
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TRUTH TABLE:
RESULT: Thus, the transient response of the output signal for 0to 50ms in steps of 1ms
was plotted.
INPUT OUTPUT
A B Y=(AB)’
0
0
1
1
0
1
0
1
1
1
1
0
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DIFFERENTIAL AMPLIFIER USING OP-AMP
AIM:
To calculate the difference output using OP-AMP and to plot the transient
response of output using Pspice.
SIMULATOR:
Pspice simulator.
THEORY:
A circuit that amplifier the difference between two signals is called as
difference amplifier or differential amplifier. This type of amplifier is very useful in
instrumentation circuits. The output voltage of the differential amplifier is given by
Vo =R2/R 1 [V 1-V 2]
Such a circuit is very useful in detecting even very small difference in the
signals, since the gain R2/R 1 can be chosen to be very large. The main purpose of
difference amplifier is to provide high gain to the difference mode signal and to
cancel the common mode signal. The relative sensitivity of an OP-AMP to a
difference signal as compared to a common mode signal is called common mode
rejection ratio and gives the figure of merit of the differential amplifier.
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NETLIST:
DIFFERENTIAL AMPLIFIER
*V1 2 0 DC 10V
*V 2 2 0 DC 5V
V1 1 0 SIN ( 0V 10V 2K )
V2 2 0 SIN ( 0V 5V 2K )
V3 5 0 DC +15V
V4 6 0 DC -15V
R1 2 3 1K
R2 1 4 1K
R3 3 7 1K
R4 4 6 1K
X 4 3 5 6 7 UA741
LIB
TRAN 1M 50M
PROBE
END
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CIRCUIT DIAGRAM:
TRUTH TABLE:
RESULT: Thus, the transient response of the difference output of a differential
amplifier using OP-AMP was plotted.
ANALYSIS
V1 [Volts]
V2[Volts] Vo =R2/R 1 [V 1-V 2]
AC
AC
10
10
5
5
5
10