II DRR Filter Design Tutoring

8/8/2019 II DRR Filter Design Tutoring

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Digital Radio Receiver Filter Design TutoringInnovative Integration. Inc

The high performance Digital Radio Receiver (DRR) system from Innovative Integration is a powerful solution for multi-channel, software defined radio (SDR) applications that combines the full

flexibility of a programmable design with high performance signal processing hardware. A high

dynamic range front end digitizer is integrated with a Xilinx Virtex II PRO FPGA, which provides the possibility of painless system upgrading and the realization of SDR.

Figure 1. Block diagram of one channel in the II DRR system.

In the DRR system, the Digital Down Converter (DDC) consists of a Cascaded Integrator-Comb

(CIC) filter, a Compensation filter (CFIR), and a Programmable filter (PFIR), as shown in Figure 2.

CIC filter is useful to realize large sample rate changes in digital systems. CIC filters aremultiplierless structures, consisting of only adders, subtractors and registers, which is a benefit for

hardware implementation. The compensation filter is used to flatten the passband frequency response.

The low-pass programmable filter is used to lower the magnitude of the ripples of the CIC filters.

Figure 2. Block diagram of DRR using System Generator.

According to Figure 1, input sample rate is 130 MHz; CIC decimation factor is 30; CFIR input

sample rate is 4.333 MHz; CFIR decimation factor is 2; PFIR input sample rate is 2.166 MHz; PFIR decimation factor is 2; PFIR output sample rate is 1.083 MHz. Figure 3 shows desired filter

specification with Fs/2=32500 kHz , Fpass=490 kHz , Fstop1=541.666kHz , Fstop2=1350kHz .

From PFIR output sample rate, the maximum bandwidth is 541.666 kHz, and the desired filter

requires almost the full bandwidth with a sharp transition area. The goal is to remove the first and

A/D

12-bit

130/208

MSPS

ACIC

30:1

NCO

Mixer J4

Link

UWB

1 of 2

Quadia Logic

1 of 2

CFIR

2:1

J4

Link

PFIR

2:1DSP



second lobes of CIC filter by low-pass filtering, as shown in Figure 4. CFIR flattens the passband of

CIC and attenuates a part of the first lobe, as shown in Figure 6 (b). But Figure 7 shows that the

passband of CFIR still keeps parts of CIC lobes at 3 and 5 MHz. In Figure 9, PFIR is applied to make

a sharp transition area around 500 kHz and attenuate the lobes.

Figure 3. Filter with Fs/2=65000kHz , Fpass=490 kHz , Fstop1=541.666kHz , Fstop2=1350kHz

Now take a look at Figure 6 (a) and Figure 9 (a). Simply speaking, we need to create CFIR and

PFIR with stopbands well aligned to the unwanted lobes in Figure 4 and Figure 7, thus we can get rid

of the irrelevant frequency bands efficiently. Here are some tricks that helps to optimize the filter.First, increase differential delay of CIC filter to 2. The lobes of CIC will be narrower and the

stopband of CFIR can cover larger area of the first lobe. Second, increase the stage of CIC filter,

which lower the magnitude of the second lobe. The drawback is that more stages in CIC consumemore hardware resource. Third, adjust the decimation factor to obtain as larger stopband as possible.

Take PFIR for example, the input sample rate is 2.166 MHz, which means a low-pass filter with a 500

kHz stopband is created as shown in Figure 8. If the CFIR decimation factor is set as 4, input samplerate of PFIR becomes 1.083 MHz, which means the available stopband of PFIR becomes less than 40

kHz. The wide lobe in Figure 9 (b) cannot be removed by such small stopband.



Figure 4. CIC filters frequency response of N = 5, M = 1, R

= 30.

Figure 5. Compensation filter of sinc power = 5,

sinc frequency factor = 0.5, R = 2.

(a) (b)

Figure 6. Magnitude response of CIC filters and compensation filter overlayed.



Figure 7. Result of cascaded CIC and CFIR. Figure 8. Programmable filter of R = 2.

(a) (b)

Figure 9. Compensated signal and programmable filter in frequency domain.

. Figure 10 shows DDC system response using Matlab Filter Design Toolbox. In Figure 10 (d), passband frequency and stopband magnitudes fit the requirements in Figure 3 and the frequency

response of DDC is theoretically correct.



(a) (b)

(c) (d)

Figure 10. (a) Frequency response of DDC of R = 120; (b) frequency response at the corner of Fpass = 490kHz; (c) at the

corner of Fstop = 541.66kHz; (d) desired filter specification on the final frequency response.

The filter design work can be easily done in three steps using Matlab tools provides by

Innovative Integration.

Step 1. Design the required filter using “II_DDC_Filters_Design.m”.Step 2. Open “II_DRR.mdl”. Load the coefficients into Xilinx System Generator modules, and

perform software simulation.

Step 3. Open “II_DRR_Sys_FreqResponse_Tool.mdl”. Use Xilinx Co-Simulation to verifyhardware performance.

In “II_DDC_Filters_Design.m”, all variables can be modified to optimize the filter and fit into the

hardware. Filter coefficients can be obtained as variable “cfir” and “pfir” in Matlab Workspace.Change parameters in CIC and DSS blocks to match the design if necessary. Make sure the sample

time in the system is consistent with the Simulink system period in the Xilinx token. Bit true, cycle

true software simulation can be performed with the Xilinx Gateway blocks. Using board support package provided by Innovative Integration, Xilinx Co-Simulation block can be compiled and the

generated bit file will be downloaded to the target FPGA and simulated in the hardware.

In Figure 11 (a), a 100 kHz sine wave is passing through the DDC blocksets shown in Figure 2.

The peak in the frequency response points the exact location and a steep slope occurs after 490 kHz.Figure 11 (b) and (c) show the overall frequency response simulated using System Generator blockset.

The simulation results are very close to the theoretical filter design results shown in Figure 10. There



is a passband attenuation within 2.5 dB from the low-pass filtering, and the noise level is effectively

suppressed around -90 dB applying limited taps FIR filters. It is possible to increase the taps of the

filters to achieve flatter passband, sharper transition area, and higher SNR.

(a)

(b) (c)

Figure 11. (a) Frequency response of 100 kHz sine wave; (b) system frequency response within 5 MHz; (c) system

frequency response within 65 MHz simulated using System Generator.

II DRR system consists of one Quadia DSP card and two UWB PMC IO modules, which perform digital down conversion on 40 channels simultaneously. The high speed, front end signal

processing for the DRR is implemented in the Xilinx Virtex II Pro VP40 FPGAs on the Quadia and

UWB modules, as shown in Figure 12 (a) and (b). The Quadia has four Texas Instruments 1 GHzTMS320C6416 DSPs that are used for baseband processing. Besides UWB module, Innovative

Integration provides a 16 channel Digital Receiver (DR) module with four 125 MSPS A/D

converters. Input signals are down converted to IF in four Texas Instruments GC5016 chips androuted back to FPGA for further applications.

To start using the DR module, a GC5016 configuration script file is compiled to “.gc101” file

using “Cmd5016” provided by Texas Instruments. The example from II shows the configuration of

downsampling from 125 MHz to 1.041 MHz with a filter of 480 kHz bandwidth. Filter coefficientscan be designed and produced by running “II_GC5016_Filters_Design.m”, copying the variable

“programmable_filter” to the “.tap” file. Board support package for Matlab Simulink will provide

customers the flexibility of utilizing the FPGA for application development.



(a)

(b) (c)

Figure 12. (a) Quadia DSP/FPGA card; (b) UWB PMC Module: 210 MSPS A/D with FPGA; (c) DR Module: 125 MSPS

A/D with FPGA and four GC5016.

Figure 13 is the chart of the captured I/Q data from one UWB. The frequency of input sine waveis 32.5 MHz, and the tuning frequency ranges from 32.51 MHz to 32.60 MHz. The output channels

are tuned at the accurate frequency with noise level around -90 dB, verifying the frequency responsein Figure 11 (a). The DRR system is proved reliable in the complete ATP tests, and in the aspects of theoretical design and hardware implementation. All the development kits, including Matlab board

support packet, can be found in the Innovative Integration website.

Figure 13. Frequency response of the II DRR system.

II DRR Filter Design Tutoring

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