IGBTGateDriverSolutions Power Electronics Europe 6 2010
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IGBT Gate Driver Solutions for Low and Medium Power Applications 18 IGBT DRIVERS www.semikron.com Issue 6 2010 Power Electronics Europe www.power-mag.com Power electronics systems are commonly used in motor drive, power supply and power conversion applications. They cover a wide output power spectrum: from several hundred watts in small drives up to megawatts in wind power installations or large drive systems. Inside the system the gate driver circuit with its extensive control and monitoring functions forms the interface between the microcontroller and the power switches (IGBT). In this second part of the article fully integrated gate driver solutions for the low power range, their technologies, circuit aspects and specific designs are shown and discussed. R. Herzer, J. Lehmann, M. Rossberg, B. Vogler, SEMIKRON Elektronik, Nuremberg, Germany IGBT driver solutions for low and medium power applications (600V, 1200V, <50A) are aimed at high volume markets, where system costs and geometric size per function are the most relevant parameters. IC-based designs are thus replacing conventional hybrid IGBT drivers [4, 14, 15, 16]. As already discussed in the chapter ‘Gate driver topologies and insulation principles’ [30] for an asymmetric grounded DC link and low power applications, the microcontroller, the primary side, the emitter and secondary side gate driver of the low side switch (BOT) can be placed on the same ground potential. In this case a potential separation is only necessary for the secondary side of high side switch (TOP). System and high voltage IC design Figure 10 shows a typical block circuit diagram of a 3-phase power conversion system with an additional 7th channel at the low side to support power factor correction schemes or to be used as a brake chopper. The topological blocks to be integrated into a gate driver HVIC are marked (orange). Depending on the different applications only high side- [17], half-bridge [14] and six-pack driver ICs [4] are also possible, as well as the integration of additional blocks such as bootstrap- diodes or charge pumps for power supply and VCE detection diodes and circuits. The corresponding block diagram of a monolithic integrated 7-channel IGBT driver (Sevenpack) is given in Figure 11. Input interfaces (IIF) serve to process logic thresholds for direct connection to 5V or 3.3V microcontrollers. An interlock and dead time between TOP and BOT switch of a half-bridge is usually implemented in the external drive controller pattern but in many cases an additional hardware interlock and dead time is implemented in the gate driver as well as a short pulse suppression. Three 600V (or 1200V) level-shifters transfer the signals to the fully insulated high sides, where the differential transmission signals are filtered and reconstructed. The signals are driven at the chip output by a CMOS stage. The output currents (sink/source) vary from several hundred mA up to 4.5A [19]. The driver operates normally at 15V (Vop,max to 20V). The branch delay times of the six main channels TOP/BOT1-3 are delay-matched to ensure synchronized switching. Logic and error management generate the appropriate internal signals. These take into account not only under-voltage lockout (UVLO, primary and secondary side) as derived from a bandgap- stabilized reference but also external analog sensor signals such as shunt current monitoring. Complete integration of an IGBT gate driver exit demands the following technological requirements: • Insulation technology for the certain electrical separation of low- and high-side circuit blocks. Here PN-insulation [4, 14], dielectric insulation (SOI) [6] and mixed technologies of both [20] are used today. • High-voltage devices of the 600V and 1200V class respectively, which can be used as level-shifter (no galvanic insulation). The lateral DMOS-transistor Figure 10: Power conversion system showing gate driver HVIC integration area
Transcript of IGBTGateDriverSolutions Power Electronics Europe 6 2010
IGBT Gate Driver Solutions for Lowand Medium Power Applications
18 IGBT DRIVERS www.semikron.com
Issue 6 2010 Power Electronics Europe www.power-mag.com
Power electronics systems are commonly used in motor drive, power supply and power conversionapplications. They cover a wide output power spectrum: from several hundred watts in small drives up tomegawatts in wind power installations or large drive systems. Inside the system the gate driver circuit withits extensive control and monitoring functions forms the interface between the microcontroller and thepower switches (IGBT). In this second part of the article fully integrated gate driver solutions for the lowpower range, their technologies, circuit aspects and specific designs are shown and discussed. R. Herzer, J.Lehmann, M. Rossberg, B. Vogler, SEMIKRON Elektronik, Nuremberg, Germany
IGBT driver solutions for low andmedium power applications (600V,1200V, <50A) are aimed at high volumemarkets, where system costs andgeometric size per function are the mostrelevant parameters. IC-based designsare thus replacing conventional hybridIGBT drivers [4, 14, 15, 16]. As alreadydiscussed in the chapter ‘Gate drivertopologies and insulation principles’ [30]for an asymmetric grounded DC link andlow power applications, themicrocontroller, the primary side, theemitter and secondary side gate driver ofthe low side switch (BOT) can be placedon the same ground potential. In thiscase a potential separation is onlynecessary for the secondary side of highside switch (TOP).
System and high voltage IC designFigure 10 shows a typical block circuitdiagram of a 3-phase power conversionsystem with an additional 7th channel atthe low side to support power factorcorrection schemes or to be used as abrake chopper. The topological blocks tobe integrated into a gate driver HVIC aremarked (orange). Depending on thedifferent applications only high side- [17],half-bridge [14] and six-pack driver ICs [4]are also possible, as well as the integrationof additional blocks such as bootstrap-diodes or charge pumps for power supplyand VCE detection diodes and circuits.
The corresponding block diagram of amonolithic integrated 7-channel IGBTdriver (Sevenpack) is given in Figure 11.Input interfaces (IIF) serve to process logicthresholds for direct connection to 5V or3.3V microcontrollers. An interlock anddead time between TOP and BOT switchof a half-bridge is usually implemented inthe external drive controller pattern but inmany cases an additional hardwareinterlock and dead time is implemented in
the gate driver as well as a short pulsesuppression.
Three 600V (or 1200V) level-shifterstransfer the signals to the fully insulatedhigh sides, where the differentialtransmission signals are filtered andreconstructed. The signals are driven at thechip output by a CMOS stage. The outputcurrents (sink/source) vary from severalhundred mA up to 4.5A [19]. The driveroperates normally at 15V (Vop,max to 20V).
The branch delay times of the six mainchannels TOP/BOT1-3 are delay-matchedto ensure synchronized switching. Logicand error management generate theappropriate internal signals. These takeinto account not only under-voltage
lockout (UVLO, primary and secondaryside) as derived from a bandgap-stabilized reference but also externalanalog sensor signals such as shuntcurrent monitoring.
Complete integration of an IGBT gatedriver exit demands the followingtechnological requirements:• Insulation technology for the certain
electrical separation of low- and high-sidecircuit blocks. Here PN-insulation [4, 14],dielectric insulation (SOI) [6] and mixedtechnologies of both [20] are used today.
• High-voltage devices of the 600V and1200V class respectively, which can beused as level-shifter (no galvanicinsulation). The lateral DMOS-transistor
Figure 10: Powerconversion systemshowing gate driverHVIC integration area
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layer, although of course the chargesincrease with the blocking voltage. This isshown in Figure 12 where the crosssections of the fundamental devicestructures are similar for the 600V and1200V class, but the dopingconcentrations and distances arecompletely different. The full blockingvoltage between high side and low sidedrops completely at the N- epitaxy / P-substrate junction and its lateral edgetermination structure. Because of thelarge depth of N- region a parasiticcoupling of the buried PN-junction onthe active circuits on the surface can beavoided, especially at floating high side(Figure 12 middle). This makes therealization of sensitive analog circuits onthe TOP-secondary side possible.
Figure 13 shows chip photographs ofdifferent driver topologies, voltage andcurrent classes of different manufactures.The insulated TOP secondary sides andtheir PN-edge termination structure aroundare clearly identifiable, as well as the driveroutput stages of every channel. In Figure13 (left) and 13 (right) the differentiallevel-shifters are embedded inside thetermination structure while in Figure 13(middle) the level-shifters are locatedseparately.
Though the market has shownconsiderable interest in these compact andcheap high voltage driver ICs, the junctioninsulation has certain fundamentaldrawbacks. Negative transient voltages atthe driver output can trigger internalparasitic thyristor structures, leading tolatch-up. The problem can be somewhatalleviated by minority carrier suppressionstructures [22, 23] but it cannot beresolved completely. Also, PN leakagecurrents which increase with a factor of 4per 10K temperature rise increase thelosses and lead to an addition self-heatingof the device which typically limits theoperation temperature to 150°C.
Gate driver in SOI substratesAppropriate high voltage silicon oninsulator SOI-CMOS (600V) platformtechnology [24, 25] can provide completelatch-up immunity since all active devicesare dielectrically insulated (see Figure 14).The regular CMOS circuits of the low sideand the high side are based on quasi-bulktransistors in fully isolated silicon islands.This enables the operational temperaturerange to be considerably extended up to200°C [6]. The active silicon is thickenough to prevent punch-through of theback side space charge region to the topside devices. The keys to the highbreakdown voltages are the thick buriedoxide layer and the selective layer thinningin the drift region of the high voltagedevices.
Advanced level shifter conceptEven in low current applications and, yetmore, in medium and high currentapplications, where high currents or highdi/dt are switched, positive and negativevoltage peaks may occur on parasiticelements in the power plane. Thesevoltage peaks might cause a strong voltagedrop between the primary and thesecondary side of the gate driver (offsetvoltage). A negative offset voltage inparticular is critical for junction-isolated HV-ICs [18, 14], commonly allowing only afew volts (typically -5V) below groundpotential to prevent latch up [4]. Thereforethe design goal for medium powerapplications is a significant extension of the
as classic RESURF (Figure 12) or as SOI-RESURF (Figure 14) device is the mostcommon solution.
• Digital and analog circuits for operationvoltages up to 20V for signal processing,control and driver functions on the lowand particularly on the high side, wherethe ground potential is coupled on theemitter potential of the TOP switch andextreme voltage transients occur.
Gate driver in PN-insulationtechnologyThe most important advantage of PN-insulation is that the device structurescan be adjusted to the different voltageclasses (600V, 1200V) by scaling ofedge termination structure and dopingconcentration and depth of epitaxial
Figure 11: Typical block diagram of a monolithic integrated IGBT driver for seven switches (Sevenpackdriver)
Figure 12:Fundamental devicestructures of a600V/1200V PN-insulation technology[18]
Figure 13: Chip photographs of different driver ICs in PN-insulation technology; left a 600V, 650/400mA Halfbridge-driver [STM,14], in the middle a 600V, 500/250mA Sixpack-driver [IR,4,21], and right a1200V, 500/250mA Sixpack-driver [IR,4,21]
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range of the operational voltage shiftbetween the primary side (control logic)and the secondary side (drivers). Thisrequires an advanced level shifter conceptfor both the BOT and the TOP channelallowing “bipolar” operation.
The circuit principle of the BOT channellevel shifter is shown in Figure 15. Itconsists of two independent transmissionpaths, an up-level shifter and acomplementary down-level shifter. Theconfiguration is that of a conventional staticCMOS level shifter with additional diodesin each path. Both the up- and the down-level shifters use two cross coupled parallelbranches with the function of a latch.Hence there are no cross currents understatic voltage conditions. Because of thefull dielectric insulation of each device, thecircuit itself is latch-up free. For this reasonand also that of the weak back gate effect
of the SOI technology used, every circuitpart can carry any desired potential. Themaximum allowable offset voltage is onlylimited by the breakdown voltage of thelevel shifter transistors.
Depending on the polarity of the offsetvoltage between the primary side and thesecondary side (Voffset = Vvs_sek - Vs) the up-
level shifter (Voffset ≥ 0V) or the down-levelshifter (Voffset ≤ 0V) transmits the appliedinput signal from the primary to thesecondary side. The inactive path isblocked by reverse-biased diodes. Toreconstruct the signal on the secondaryside, a simple logic disjunction can beused.
The circuit principle of the TOP channellevel shifter is shown in Figure 16. As inthe case of the BOT channel, the levelshifter consists of two complementaryparts - the high voltage up-level shifterand the low voltage down-level shifter.Because there are no p-MOS devicesavailable with a breakdown voltageextending to 600V, a pulsed signaltransmission simply requiring high-voltagen-DMOS transistors and high-voltagediodes, to block the high reverse voltage inthe down-level shifter, is used. A pulsedtransmission is applied to minimize thecross current and power consumption butrequires more complex signal generationand reconstruction in comparison to theBOT channel. The differential transmissionwith two branches per level shifter, arobust signal processing and reconstructionon the secondary side provide maximumimmunity against parasitic coupling fromthe power plane.
Seven channel 600V gate driverdesign Figure 17 shows the chip photograph of a7-channel gate driver IC. It contains all the
functionality needed for a 3-phase powersystem and a fourth independent BOTchannel is implemented for PFC or brakechopper applications according to thepower conversion system of Figure 10and the block diagram of Figure 11. It isrealized in a 600V CMOS-SOI technology[24] whose cross section is shown inFigure 14.
The three insulated TOP secondarysides with their HV-DMOS-transistorsand HV-diodes of up-/down- level shiftercircuit (regarding Figure 16) are clearlyto recognisable, as are the output stagesof the 3 TOP and 4 BOT channels with1.4A/1.4A (source/sink) peak current at
Figure 14: Schematiccross section offundamental devicestructures of a 600VSOI-CMOStechnology [24, NXP][25]
Figure 15: Circuit principle with up-/down- levelshifter for the BOT channel
Figure 16: Circuit principle with up-/down- levelshifter for the TOP channel
Figure 17: Chip photograph of a 600V/1.4A 7-channel gate driver IC in SOI-CMOS technology(chip size 4.6mm x 4.1mm)
Figure 18: Block diagram of a two-chip 1200V SOI half-bridge gate driver
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15V supply voltage and roomtemperature. In comparison to the PN-insulation driver designs in Figure 13,the insulation distances between lowside and high side are very small due tothe dielectric insulation. The design isextremely compact and the fullydielectric insulation of each device leadsto low leakage currents and high latch-up ruggedness even at temperatures upto 200°C [6]. The capabilities of thelevel shifters are demonstratedexperimentally in [13, 26]. The circuitremains operational for negative
Figure 19: Assembledtwo-chip 1200V,1.4A/1.4A SOI half-bridge gate driver ina 1200V, 50A Sixpack-IPM
Figure 20: Doublepulse measurement(TOP-IGBT switchedwith load, VDC=1200V,Iload=50A)
reference voltages down to -45V(bottom channel) and -20V (topchannel) respectively. The powerfuloutput stages of every channel can drivethe gates of 600V/50A IGBTs directly inIPM configurations [13]. Each TOPchannel has a separate bandgapreference and an UVLO circuit in orderto monitor the high side operationalvoltage. This may be important if theTOP channels are powered by abootstrap circuit.
Advanced level shifter concept for1200V CMOS-SOI gate drivers600V gate drive ICs based on 600V SOI-CMOS can overcome most of thedisadvantages of gate drive ICs which relyon conventional junction isolation.Nevertheless, SOI technologies for the1200V class do not currently exist. Forthis reason a new concept for 1200Vsignal transmission and high sideinsulation has been developed and wasimplemented in the half-bridge gatedriver IC here presented. Thetransmission of the control signals to thehigh side is based on a new 1200V levelshifter topology with cascaded 600Vtransistors and without further signalprocessing on the originating intermediatepotential. A balanced voltage divisionacross the HV transistors during switchingis achieved by a balanced capacitivedivider. The implemented active clampingcircuitry prevents the exceeding of themaximum voltages. The limitedbreakdown voltage of the verticaldielectric insulation of the SOI substrate(BOX, Figure 14) requires the subdivisionof the offset voltages on two physicallyseparated dies and that, in turn, requiresthat all high side functions are integratedin a separate high-side IC.
Figure 18 shows the block circuitdiagram and Figure 19 the chipphotography of a two-chip 1200V half-bridge gate driver. Exemplarily for theperformance reached, Figure 20 shows adouble pulse measurement of a1200V/50A IGBT at 1200V DC link
Figure 22: Chipphotograph of gatedriver and 500V, 1AIGBT/FWD inverter inSOI-technology [28]
Figure 21: Schematic cross section of fundamental device structures of a 500V SOI-CMOS technology [28]
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voltage and rated current (50A) withinductive load.
Driver and inverter integration on asingle chipThe fully dielectric insulation of everydevice in SOI-substrates enables also theintegration of high-voltage bipolar deviceslike IGBTs and diodes together with driverand monitoring functions on the samechip. Figure 21 presents the cross sectionof the fundamental devices of thistechnology and Fig.22 the chip photographof a 500V/1A inverter [27, 28 Mitsubishi].For chip area and cooling reasons, suchsolutions are limited today on low powerapplications (several hundred watts).
Literature[13] B. Vogler, M. Rossberg, R. Herzer,
L. Reusser et al: 600VConverter/Inverter/Brake (CIB)-Modulewith integrated SOI Gate Driver IC forMedium Power Applications, Proc. CIPS2008, pp. 261-266
[14] Data sheet, L 6384, STMicroelectronics, 2003
[15] Data sheet, SPM(tm) DIP-SPM,Fairchild Semiconductor, 2003
[16] Sung-il Yong, Bum-Seok Suhetal.: Power Systems Design Europe,
Issue September 2004, pp. 12-17[17] Datasheet 600V,10A Super Mini
DIP-IPM, Mitsubishi, 2006[18] T. Takahashi: Power Conversion
Processor(tm) Architecture and HVICTechnology for AC Motor Drive, Proc.CIPS 2000, pp. 73-81
[19] Data sheet, Half-Bridge GateDrive IC FAN 7390M1, FairchildSemiconductor, 2008
[20] R. Rudolf et al.:New Level-Shift-Transistors in 600V-Smart-Power ICsusing Thin-Film SOI-Technology, Proc.CIPS 2002, pp. 89-94
[21] D. Tam: New 1200V IntegratedCircuit Changes The Way 3-PhaseMotor Drive Inverters Are Designed, IRTechnical Paper, July 2008
[22] S. Gupta, J.C. Beckman, S.L.Kosier: Improved Latch Up Immunity inJunction-Isolated Smart Power ICs withUnbiased Guard Ring, IEEE ElectronDevice Letters, Vol. 22, No. 12, 2001
[23] J.P. Laine, O. Gonnard, G.Chariat, L. Bertolini et al. : Active Pull-Down Protection for full substratecurrent isolation in Smart Power ICs,Proceedings ISPSD 2002, pp. 273-276
[24] T. Letavic, E. Arnold, M. Simpson,R. Aquino et al.: High Performance600V Smart Power Technology Based
on Thin Layer Silicon-on-Insulator,Proceedings ISPSD 1997, pp. 49-52
[25] T. Letavic, M. Simpson, E. Arnold,E. Peters et al.: 600V Power ConversionSystem-on-a-Chip Based on Thin LayerSilicon-on-Insulator, Proceedings ISPSD1999, pp. 325-328
[26] B. Vogler, M. Rossberg, R. Herzer:600V SOI Gate Driver IC with advancedLevel Shifter Concept for Medium andHigh Power Applications, ProceedingsEPE 2007, Aalborg, Denmark
[27] T. Yamane, S. Ikeda, A.Nakagawa: Three-Phase SinusoidalCurrent PWM Brushless Motor DriverICs, Proc. ISPSD 2004, pp.147-150
[28] E. Motto, J. Dunlon, K.Watabe,H.Kazunari, T.Araki: A monolithic 500V,1A Three Phase Motor Driver withSmall Outline Surface Mount Package,Proc. of 42. IEEE Industry Applic. Conf.2007, pp. 1047-1051
[29] M. Münzer, W. Ademmer, B.Strzalkowski: Coreless Transformer, aNew Technology for Half Bridge DriverICs, Proc. PCIM 2003
[30] R. Herzer, J. Lehmann, M.Rossberg, B. Vogler: Integrated GateDriver Circuit Solutions, PowerElectronics Europe July/August 2010,pp. 26-31
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