IFTxx Schematics Document
description
Transcript of IFTxx Schematics Document
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Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
IFTXX M/B LA-3541P Schematic 0.1Cover Page
B
1 52Wednesday, November 01, 2006
2006/08/18 2007/8/18Compal Electronics, Inc.
Intel Merom Processor with Crestline + DDRII + ICH8M
IFTxx Schematics Document
REV: 0.1
Compal Confidential
(With nVIDIA MXM/B)
2006-11-01
ZZZ1
PCB
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Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
IFTXX M/B LA-3541P Schematic 0Block Diagrams
B
2 52Wednesday, November 01, 2006
2006/08/18 2007/8/18Compal Electronics, Inc.
page 37 page 33 page 42
CHARGER
page 41
SUPER I/O
page 40SCREW
page 37
I/O Conn.FRONT LCD /B.LID SW
page 29TPM
page 26
PCMCIASocket
Fan Controlpage 4
Compal Confidential
IDE
SDVO
Model Name : IFTXX
X4 mode
page 18Video Processor
USB
S-ATA
Power On/Off CKT.
File Name : LA-3541P
Touch Pad
page 42
CRT & TV-out
LPC BUS
page 38
uFCBGA-1299
3.3V 24.576MHz/48Mhz
H_A#(3..35)
Card Reader
IDSEL:AD22(PIRQG#,PIRQH#,GNT#0, REQ#0)
H_D#(0..63)
page 31
R5C833
page 19
MDC 1.5Conn
page 39
Int.KBD
page 36
PCI-Express
BANK 0, 1, 2, 3
USB conn x2TO I/O/B
667/800MHz
ALC268
DMI
page 28
DC/DC Interface CKT.
Intel Merom Processor
page 25
3.3V 48MHz
FSB
CDROM Conn.
RJ45
Clock GeneratorICS9LPRS365
page 34
G-Sensor
Power Circuit DC/DC
PCI BUS
page 18
uPGA-478 Package
3.3V 33 MHz
page 37
200pin DDRII-SO-DIMM X2
page 43
Intel Crestline
3.3V ATA-100
Dual Channel
page 28
BIOS
page 4
1.8V DDRII 533/667
page 4,5,6
page 35
HDA Codec
page 16
Memory BUS(DDRII)
BGA-676HD Audio
page 24
page 7,8,9,10,11,12,13
Intel ICH8-M
Thermal Sensor
page 14,15
page 20,21,22,23
page 36
ENE KB925
port 0
Audio AMP1394Conn.
3 in 1socket
LAN(GbE)BCM5787M/5906
page 30
New CardSocket
MINI Card x3
CMOS Camera
WLAN,3G/TV-Tuner Robson
PCI-Express
ADM1032
RTC CKT.page 21
LCD Conn.
page 35
Switch/B Conn.
page 24
S-ATA HDDConn.
MXM II VGA/BBluetoothConnpage 17
page 33page 32
page 29
page 44,45,47,48 49,50,51
LVDSLVDS
LPC47N217
page 33
USB conn x2TO M/B
page 42
Finger PrintConn
CardBuspage 26
ENE CB1410
page 46
IDSEL:AD20(PIRQC#,PIRQD#,GNT#2, REQ#2)
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Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
IFTXX M/B LA-3541P Schematic 0Notes List
B
3 52Wednesday, November 01, 2006
2006/08/18 2007/8/18Compal Electronics, Inc.
ON
SLP_S3#SLP_S1#
S5 (Soft OFF)
S4 (Suspend to Disk)
S3 (Suspend to RAM)
LOW
ONON
ON
ON
ON
ON
ON
ON
HIGH
OFF
OFF
OFF
OFF
OFF
SLP_S4#
OFF
ON
ON
LOWLOWLOW
LOW
OFF
OFF
SLP_S5#
HIGH
HIGH HIGH HIGH
HIGHHIGHHIGHHIGH
LOW
LOW
LOW
LOW LOW LOW
+VALW
HIGH
+V +VS Clock
S1(Power On Suspend)
Full ON
STATE
OFFOFF
OFF
OFFON
ON
ON
OFF
OFF
OFFOFFON
ON*ON
ON
+CPU_CORE
1.5V switched power railOFF
OFF
ON
Voltage Rails
+5VS
+2.5VS1.8V switched power rail+1.8VS
+1.5VS
RTC power+RTCVCC
0.9V switched power rail for DDR terminator+0.9VS
OFFOFFON
3.3V switched power rail5V always on power rail
3.3V always on power rail
Adapter power supply (19V)
+1.05VS
1.8V power rail for DDR
+3VALW
B+VIN
S5
2.5V switched power rail
+1.8V
+5VALW
S3S1
+3VS
ONON*ONVSB always on power rail+VSB
5V switched power rail
1.05V switched power rail
Core voltage for CPUAC or battery power rail for power circuit.
OFFONOFFON
ONON
ON
DescriptionPower Plane
N/A N/A N/AN/AN/AN/A
ON OFF
ON1.25V switched power rail+1.25VS
ONON
ON
OFFOFF
OFFON*
OFF
BOARD ID TableID1
1(R741)
A-TESTID0
1(R742)0(R744)0(R745)
B-TESTC-TEST
TEST
PANEL ID TableRRa (R743)
Size
14WRb (R740)15W
SIGNAL
Address1001 100X b0001 011X b
EEPROM(24C16/02)
1010 010XbDDR DIMM11010 000XbDDR DIMM0
C,DCARD BUS CB1410
IDSEL #
20
1101 001Xb
ICH8M SM Bus address
AD22
DEVICE
AD20
REQ/GNT #
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Address
Address
Clock Generator(ICS9LPRS325AKLFT_MLF72)
Device
1394+Cardreader G,H
PIRQ
ADI ADM1032
1010 000X b
External PCI Devices
Device
EC SM Bus1 address
Smart Battery
Device
EC SM Bus2 address
NVIDIA NB8X
0(R745)
0(R744)
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55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H_A#[3..35]
H_REQ#[0..4]
H_RS#[0..2]H_A#4H_A#3
H_A#6H_A#5
H_A#8H_A#7
H_A#9H_A#10
H_A#12H_A#11
H_A#15H_A#14H_A#13
H_A#17
H_A#16
H_A#18H_A#19H_A#20
H_A#22H_A#21
H_A#23H_A#24
H_A#26H_A#25
H_A#27H_A#28H_A#29H_A#30H_A#31
H_REQ#0H_REQ#1H_REQ#2
H_REQ#4H_REQ#3
H_RESET#
H_IERR#
THERMDATHERMDC
H_RS#0
H_RS#2H_RS#1
H_A#32H_A#33H_A#34H_A#35
THERMDA
THERMDC
ITP_TCK
ITP_TRST#
ITP_TDI
ITP_TMS
H_IERR#
H_PROCHOT#
ITP_TRST#
ITP_TCK
ITP_DBRESET#
ITP_TMS
ITP_TDI
H_PREQ#
H_PREQ#
+VCC_FAN1EN_FAN1
+VCC_FAN1
H_PROCHOT#
H_A#[3..35]
H_REQ#[0..4]
H_RS#[0..2]
H_ADSTB#0
H_ADSTB#1
H_RESET#
H_ADS# H_BNR# H_BPRI#
H_BR0#
H_DEFER# H_DRDY#
H_HIT# H_HITM#
H_LOCK#
CLK_CPU_BCLK# CLK_CPU_BCLK
H_A20M#
H_INIT#
H_IGNNE#
H_NMIH_INTR
H_FERR#
H_STPCLK#
H_SMI#
H_DBSY#
H_THERMTRIP#
H_TRDY#
EC_SMB_CK2
EC_SMB_DA2 ITP_DBRESET#
H_PROCHOT#
FAN_SPEED1
EN_FAN1
+3VS
+1.05VS
+5VS
+3VS
+5VS
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
IFTXX M/B LA-3541P Schematic 0Merom (1/3)
B
4 52Wednesday, November 01, 2006
2006/08/18 2007/8/18Compal Electronics, Inc.
F75383M_MSOP8
Place close to CPU within 500mil
CRB pull 75 Ohm
Connect SB SYS_RESET# or just left NC
40mil
FAN1 Conn
ADM1032
H_THERMDA, H_THERMDC routing together,Trace width / Spacing = 10 / 10 mil
Checklist recommend 39 Ohm
C28 10U_1206_16V4Z
1 2
C688
2200P_0402_50V7K
1
2
R568 27.4_0402_1%
1 2
JP6
ACES_85205-03001
112233
GND4GND5
R559 56_0402_5%
1 2
ADDR GRO
UP 0ADDR G
ROUP 1
C
O
N
T
R
O
L
X
D
P
/
I
T
P
S
I
G
N
A
L
S
H CLK
THERMALR
E
S
E
R
V
E
D
ICH
JP36A
Merom Ball-out Rev 1aconn@
A[10]#N3A[11]#P5A[12]#P2A[13]#L2A[14]#P4A[15]#P1A[16]#R1
A[17]#Y2A[18]#U5A[19]#R3A[20]#W6A[21]#U4A[22]#Y5A[23]#U1A[24]#R4A[25]#T5A[26]#T3A[27]#W2A[28]#W5A[29]#Y4
A[3]#J4
A[30]#U2A[31]#V4
RSVD[01]M4RSVD[02]N5RSVD[03]T2RSVD[04]V3RSVD[05]B2RSVD[06]C3RSVD[07]D2RSVD[08]D22
A[4]#L5A[5]#L4A[6]#K5A[7]#M3A[8]#N2A[9]#J1
A20M#A6
ADS# H1
ADSTB[0]#M1
ADSTB[1]#V1
RSVD[09]D3
BCLK[0] A22BCLK[1] A21
BNR# E2
BPM[0]# AD4BPM[1]# AD3BPM[2]# AD1BPM[3]# AC4
BPRI# G5
BR0# F1
DBR# C20
DBSY# E1
DEFER# H5DRDY# F21
FERR#A5
HIT# G6HITM# E4
IERR# D20
IGNNE#C4
INIT# B3
LINT0C6LINT1B4
LOCK# H4
PRDY# AC2PREQ# AC1
PROCHOT# D21
REQ[0]#K3REQ[1]#H2REQ[2]#K2REQ[3]#J3REQ[4]#L1
RESET# C1RS[0]# F3RS[1]# F4RS[2]# G3
SMI#A3
STPCLK#D5
TCK AC5TDI AA6
TDO AB3
THERMTRIP# C7
THERMDA A24THERMDC B25
TMS AB5
TRDY# G2
TRST# AB6
A[32]#W3A[33]#AA4A[34]#AB2A[35]#AA3
RSVD[10]F6
U38
ADM1032ARMZ_MSOP8
VDD1
ALERT# 6
THERM#4 GND 5
D+2
D-3
SCLK 8
SDATA 7
R569 680_0402_5%
1 2
R4410K_0402_5%
1
2
R562 56_0402_5%
1 2
C311000P_0402_50V7K
1
2
C6870.1U_0402_16V4Z
1 2
R560 56_0402_5%
1 2
C2910U_1206_16V4Z
1 2
C301000P_0402_50V7K
1 2
R563 150_0402_1%
1 2
D51N4148_SOT23@
1 2
U5
G993P1UF_SOP8
VEN1VIN2
GND 5GND 6
GND 8
VO3VSET4
GND 7
D4
1SS355_SOD323@
1
2
R565 56_0402_5%
1 2
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H_D#[0..63]
H_PWRGOODH_CPUSLP#
H_D#56H_D#57
H_D#59H_D#58
H_D#60
H_D#62H_D#61
H_D#63
H_D#49H_D#50
H_D#48
H_D#51H_D#52H_D#53H_D#54H_D#55
H_D#40
H_D#43
H_D#41
H_D#44
H_D#42
H_D#45H_D#46H_D#47
H_D#36
H_D#33H_D#32
H_D#34H_D#35
H_D#37
H_D#39H_D#38
H_D#8
H_D#10H_D#11
H_D#9
H_D#15
H_D#12
H_D#14H_D#13
H_D#2H_D#1
H_D#3
H_D#0
H_D#4
H_D#7
H_D#5H_D#6
H_D#24H_D#25
H_D#29
H_D#26
H_D#28H_D#27
H_D#30H_D#31
H_D#16H_D#17
H_D#19H_D#18
H_D#21H_D#20
H_D#23H_D#22
COMP1COMP0
COMP3COMP2
GTL_REFTEST1TEST2
TEST4TEST3
TEST5TEST6
VSSSENSE
VCCSENSE
H_D#[0..63]
H_DINV#3
H_DSTBN#1 H_DSTBN#3 H_DSTBP#1 H_DSTBP#3
H_DINV#2 H_DSTBP#0 H_DSTBP#2 H_DSTBN#0 H_DSTBN#2
H_DINV#1
H_DINV#0
H_PSI#
CPU_BSEL0CPU_BSEL1CPU_BSEL2
H_DPRSTP# H_DPSLP# H_DPWR# H_PWRGOOD H_CPUSLP#
CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6
VCCSENSE
VSSSENSE
+1.05VS
+CPU_CORE
+1.05VS
+CPU_CORE
+1.5VS
+CPU_CORE
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
IFTXX M/B LA-3541P Schematic 0Merom (2/3)
B
5 52Wednesday, November 01, 2006
2006/08/18 2007/8/18Compal Electronics, Inc.
Width=20 mil
20mils
Place this cap more close toB26/C26 rather than 10UF
CPU_BSEL CPU_BSEL2 CPU_BSEL1
166
200
0 1
0 1
CPU_BSEL0
1
0
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs Resistor placed within0.5" of CPU pin.Traceshould be at least 25mils away from any othertoggling signal.COMP[0,2] trace width is18 mils. COMP[1,3] tracewidth is 4 mils.
Close to CPU pin AD26within 500mils.
Length match within 25 mils.The trace width/space/other is20/7/25.Close to CPU pinwithin 500mils.
C685
10U_0805_10V4Z
1
2
C684 0.1U_0402_16V4Z@1 2
JP36C
Merom Ball-out Rev 1a .conn@
VCC[001]A7VCC[002]A9VCC[003]A10VCC[004]A12VCC[005]A13VCC[006]A15VCC[007]A17VCC[008]A18VCC[009]A20VCC[010]B7VCC[011]B9VCC[012]B10VCC[013]B12VCC[014]B14VCC[015]B15VCC[016]B17VCC[017]B18VCC[018]B20VCC[019]C9VCC[020]C10VCC[021]C12VCC[022]C13VCC[023]C15VCC[024]C17VCC[025]C18VCC[026]D9VCC[027]D10VCC[028]D12VCC[029]D14VCC[030]D15VCC[031]D17VCC[032]D18VCC[033]E7VCC[034]E9VCC[035]E10VCC[036]E12VCC[037]E13VCC[038]E15VCC[039]E17VCC[040]E18VCC[041]E20VCC[042]F7VCC[043]F9VCC[044]F10VCC[045]F12VCC[046]F14VCC[047]F15VCC[048]F17VCC[049]F18VCC[050]F20VCC[051]AA7VCC[052]AA9VCC[053]AA10VCC[054]AA12VCC[055]AA13VCC[056]AA15VCC[057]AA17VCC[058]AA18VCC[059]AA20VCC[060]AB9VCC[061]AC10VCC[062]AB10VCC[063]AB12VCC[064]AB14VCC[065]AB15VCC[066]AB17VCC[067]AB18
VCC[068] AB20VCC[069] AB7VCC[070] AC7VCC[071] AC9VCC[072] AC12VCC[073] AC13VCC[074] AC15VCC[075] AC17VCC[076] AC18VCC[077] AD7VCC[078] AD9VCC[079] AD10VCC[080] AD12VCC[081] AD14VCC[082] AD15VCC[083] AD17VCC[084] AD18VCC[085] AE9VCC[086] AE10VCC[087] AE12VCC[088] AE13VCC[089] AE15VCC[090] AE17VCC[091] AE18VCC[092] AE20VCC[093] AF9VCC[094] AF10VCC[095] AF12VCC[096] AF14VCC[097] AF15VCC[098] AF17VCC[099] AF18VCC[100] AF20
VCCA[01] B26
VCCP[03] J6VCCP[04] K6VCCP[05] M6VCCP[06] J21VCCP[07] K21VCCP[08] M21VCCP[09] N21VCCP[10] N6VCCP[11] R21VCCP[12] R6VCCP[13] T21VCCP[14] T6VCCP[15] V21VCCP[16] W21
VCCSENSE AF7
VID[0] AD6VID[1] AF5VID[2] AE5VID[3] AF4VID[4] AE3VID[5] AF3VID[6] AE2
VSSSENSE AE7
VCCA[02] C26
VCCP[01] G21VCCP[02] V6
T20 PAD
R557 100_0402_1% 1 2
R554 27.4_0402_1%
1 2
DATA
GR
P 0DA
TA G
RP 1
D
A
T
A
G
R
P
2
D
A
T
A
G
R
P
3
MISC
JP36B
Merom Ball-out Rev 1aconn@
COMP[0] R26COMP[1] U26COMP[2] AA1COMP[3] Y1
D[0]#E22D[1]#F24
D[10]#J24D[11]#J23D[12]#H22D[13]#F26D[14]#K22D[15]#H23
D[16]#N22D[17]#K25D[18]#P26D[19]#R23
D[2]#E26
D[20]#L23D[21]#M24D[22]#L22D[23]#M23D[24]#P25D[25]#P23D[26]#P22D[27]#T24D[28]#R24D[29]#L25
D[3]#G22
D[30]#T25D[31]#N25
D[32]# Y22D[33]# AB24D[34]# V24D[35]# V26D[36]# V23D[37]# T22D[38]# U25D[39]# U23
D[4]#F23
D[40]# Y25D[41]# W22D[42]# Y23D[43]# W24D[44]# W25D[45]# AA23D[46]# AA24D[47]# AB25
D[48]# AE24D[49]# AD24
D[5]#G25
D[50]# AA21D[51]# AB22D[52]# AB21D[53]# AC26D[54]# AD20D[55]# AE22D[56]# AF23D[57]# AC25D[58]# AE21D[59]# AD21
D[6]#E25
D[60]# AC22D[61]# AD23D[62]# AF22D[63]# AC23
D[7]#E23D[8]#K24D[9]#G24
TEST5AF1
DINV[0]#H25
DINV[1]#N24
DINV[2]# U22
DINV[3]# AC20
DPRSTP# E5DPSLP# B5DPWR# D24
DSTBN[0]#J26
DSTBN[1]#L26
DSTBN[2]# Y26
DSTBN[3]# AE25
DSTBP[0]#H26
DSTBP[1]#M26
DSTBP[2]# AA26
DSTBP[3]# AF24
GTLREFAD26
PSI# AE6
PWRGOOD D6SLP# D7
TEST3C24
BSEL[0]B22BSEL[1]B23BSEL[2]C21
TEST2D25
TEST4AF26
TEST6A26
TEST1C23
R5491K_0402_1%
1
2
R552 54.9_0402_1%
1 2
C686
0.01U_0402_16V7K
1
2
R5562K_0402_1%
1
2
+ C677
330U_D2E_2.5VM_R9
1
2
R558 100_0402_1% 1 2
T21 PAD
R553 1K_0402_5%@12T19 PAD R555 54.9_0402_1%
1 2
R550 27.4_0402_1%
1 2R551 1K_0402_5%@12
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+1.05VS
+CPU_CORE
+CPU_CORE
+CPU_CORE
+CPU_CORE
+CPU_CORE
+CPU_CORE
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
IFTXX M/B LA-3541P Schematic 0Merom (3/3)
B
6 52Wednesday, November 01, 2006
2006/08/18 2007/8/18Compal Electronics, Inc.
6X330uF 9m ohm/6 1.8nH/6
+CPU-COREDecoupling
32X22uF 3m ohm/32 0.6nH/32
C,uF ESR, mohm ESL,nH
SPCAP,Polymer
MLCC 0805 X5R
3 x 330uF(9mOhm/3) 3 x 330uF(9mOhm/3)
South Side Secondary North Side Secondary
(Place these capacitors on South side,Secondary Layer)
(Place these capacitors on South side,Primary Layer)
(Place these capacitors on North side,Primary Layer)
(Place these capacitors on North side,Secondary Layer)
32X10uF 3m ohm/32 0.6nH/32
CRB no stuff. Reserved!
9/25 10U checked. OK for use!
C671
10U_0805_6.3V6M
1
2
JP36D
Merom Ball-out Rev 1a .conn@
VSS[082] P6
VSS[148] AE11
VSS[002]A8VSS[003]A11VSS[004]A14VSS[005]A16VSS[006]A19VSS[007]A23VSS[008]AF2VSS[009]B6VSS[010]B8VSS[011]B11VSS[012]B13VSS[013]B16VSS[014]B19VSS[015]B21VSS[016]B24VSS[017]C5VSS[018]C8VSS[019]C11VSS[020]C14VSS[021]C16VSS[022]C19VSS[023]C2VSS[024]C22VSS[025]C25VSS[026]D1VSS[027]D4VSS[028]D8VSS[029]D11VSS[030]D13VSS[031]D16VSS[032]D19VSS[033]D23VSS[034]D26VSS[035]E3VSS[036]E6VSS[037]E8VSS[038]E11VSS[039]E14VSS[040]E16VSS[041]E19VSS[042]E21VSS[043]E24VSS[044]F5VSS[045]F8VSS[046]F11VSS[047]F13VSS[048]F16VSS[049]F19VSS[050]F2VSS[051]F22VSS[052]F25VSS[053]G4VSS[054]G1VSS[055]G23VSS[056]G26VSS[057]H3VSS[058]H6VSS[059]H21VSS[060]H24VSS[061]J2VSS[062]J5VSS[063]J22VSS[064]J25VSS[065]K1VSS[066]K4VSS[067]K23VSS[068]K26VSS[069]L3VSS[070]L6VSS[071]L21VSS[072]L24VSS[073]M2VSS[074]M5VSS[075]M22VSS[076]M25VSS[077]N1VSS[078]N4VSS[079]N23VSS[080]N26VSS[081]P3 VSS[162] A25
VSS[161] AF21VSS[160] AF19VSS[159] AF16VSS[158] AF13VSS[157] AF11VSS[156] AF8VSS[155] AF6VSS[154] A2VSS[153] AE26VSS[152] AE23VSS[151] AE19
VSS[083] P21VSS[084] P24VSS[085] R2VSS[086] R5VSS[087] R22VSS[088] R25VSS[089] T1VSS[090] T4VSS[091] T23VSS[092] T26VSS[093] U3VSS[094] U6VSS[095] U21VSS[096] U24VSS[097] V2VSS[098] V5VSS[099] V22VSS[100] V25VSS[101] W1VSS[102] W4VSS[103] W23VSS[104] W26VSS[105] Y3
VSS[107] Y21VSS[108] Y24VSS[109] AA2VSS[110] AA5VSS[111] AA8VSS[112] AA11VSS[113] AA14VSS[114] AA16VSS[115] AA19VSS[116] AA22VSS[117] AA25VSS[118] AB1VSS[119] AB4VSS[120] AB8VSS[121] AB11VSS[122] AB13VSS[123] AB16VSS[124] AB19VSS[125] AB23VSS[126] AB26VSS[127] AC3VSS[128] AC6VSS[129] AC8VSS[130] AC11VSS[131] AC14VSS[132] AC16VSS[133] AC19VSS[134] AC21VSS[135] AC24VSS[136] AD2VSS[137] AD5VSS[138] AD8VSS[139] AD11VSS[140] AD13VSS[141] AD16VSS[142] AD19VSS[143] AD22VSS[144] AD25VSS[145] AE1VSS[146] AE4
VSS[106] Y6
VSS[001]A4
VSS[149] AE14VSS[150] AE16
VSS[147] AE8
VSS[163] AF25
C675
10U_0805_6.3V6M
1
2
C682
0.1U_0402_16V4Z
1
2
C703
10U_0805_6.3V6M
1
2
C664
10U_0805_6.3V6M
1
2
C678
0.1U_0402_16V4Z
1
2
C654
10U_0805_6.3V6M
1
2
C661
10U_0805_6.3V6M
1
2
C665
10U_0805_6.3V6M
1
2
C656
10U_0805_6.3V6M
1
2
C655
10U_0805_6.3V6M
1
2
C666
10U_0805_6.3V6M
1
2
+C646
330U_D2E_2.5VM_R9
1
2
C660
10U_0805_6.3V6M
1
2
+C643
330U_D2E_2.5VM_R9
1
2
C651
10U_0805_6.3V6M
1
2
C669
10U_0805_6.3V6M
1
2
C670
10U_0805_6.3V6M
1
2
C673
10U_0805_6.3V6M
1
2
C652
10U_0805_6.3V6M
1
2
C672
10U_0805_6.3V6M
1
2
C662
10U_0805_6.3V6M
1
2
C683
0.1U_0402_16V4Z
1
2
C680
0.1U_0402_16V4Z
1
2
C658
10U_0805_6.3V6M
1
2
C663
10U_0805_6.3V6M
1
2
+C648
330U_D2E_2.5VM_R9@
1
2
C676
10U_0805_6.3V6M
1
2
C679
0.1U_0402_16V4Z
1
2
C681
0.1U_0402_16V4Z
1
2
C650
10U_0805_6.3V6M
1
2
C700
10U_0805_6.3V6M
1
2
C667
10U_0805_6.3V6M
1
2
C657
10U_0805_6.3V6M
1
2
+C645
330U_D2E_2.5VM_R9@
1
2
C668
10U_0805_6.3V6M
1
2
C653
10U_0805_6.3V6M
1
2
C701
10U_0805_6.3V6M
1
2
C674
10U_0805_6.3V6M
1
2
C649
10U_0805_6.3V6M
1
2
+C647
330U_D2E_2.5VM_R9
1
2
C702
10U_0805_6.3V6M
1
2
+C644
330U_D2E_2.5VM_R9
1
2
C659
10U_0805_6.3V6M
1
2
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H_SWNG
H_D#0H_D#1H_D#2H_D#3H_D#4H_D#5H_D#6H_D#7
H_D#11
H_D#13
H_D#9
H_D#14
H_D#8
H_D#15
H_D#12
H_D#10
H_D#19
H_D#21
H_D#17
H_D#22
H_D#16
H_D#23
H_D#20
H_D#18
H_D#27
H_D#29
H_D#25
H_D#30
H_D#24
H_D#31
H_D#28
H_D#26
H_D#35
H_D#37
H_D#33
H_D#38
H_D#32
H_D#39
H_D#36
H_D#34
H_D#43
H_D#45
H_D#41
H_D#46
H_D#40
H_D#47
H_D#44
H_D#42
H_D#51
H_D#53
H_D#49
H_D#54
H_D#48
H_D#52
H_D#50
H_D#55
H_D#59
H_D#61
H_D#57
H_D#62
H_D#56
H_D#63
H_D#60
H_D#58
H_A#3H_A#4H_A#5H_A#6H_A#7
H_A#11
H_A#8
H_A#10
H_A#12
H_A#9
H_A#13
H_A#15
H_A#17
H_A#14
H_A#21
H_A#18
H_A#20
H_A#22
H_A#19
H_A#26
H_A#23
H_A#25
H_A#27
H_A#24
H_A#31
H_A#28
H_A#30H_A#29
H_ADSTB#1
H_HIT#
H_BNR#H_BPRI#
H_DPWR#
H_ADS#H_ADSTB#0
H_LOCK#
H_DBSY#
H_BR0#
H_HITM#
H_DRDY#
H_DEFER#
H_TRDY#
H_A#16
CLK_MCH_BCLK#CLK_MCH_BCLK
H_CPUSLP#H_RESET#
H_SCOMP#H_SCOMP
H_RCOMP
H_RCOMPH_SWNG
H_A#33H_A#34
H_A#32
H_A#35
H_VREF
H_RS#0
H_REQ#0
H_DSTBP#0
H_REQ#4
H_REQ#2
H_DSTBP#2
H_REQ#3
H_DINV#2
H_REQ#1
H_DINV#0
H_DSTBP#3
H_DSTBN#3
H_DSTBP#1
H_DINV#3
H_RS#2
H_DSTBN#1H_DSTBN#0
H_DSTBN#2
H_RS#1
H_DINV#1
H_D#[0..63]H_A#[3..35]
H_ADSTB#1 H_ADSTB#0
H_RESET#
H_ADS#
H_TRDY#
H_DPWR# H_DRDY#
H_DEFER# H_BR0#
H_BNR# H_BPRI#
H_DBSY#
H_CPUSLP#
H_HITM# H_HIT#
H_LOCK#
CLK_MCH_BCLK# CLK_MCH_BCLK
H_REQ#[0..4]
H_DSTBP#0
H_DSTBN#0
H_DSTBP#1
H_DSTBN#1
H_DSTBP#2
H_DSTBN#2
H_DSTBP#3
H_DSTBN#3
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
H_RS#[0..2]
+1.05VS
+1.05VS
+1.05VS
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
IFTXX M/B LA-3541P Schematic 0Crestline (1/7)-GTL
B
7 52Wednesday, November 01, 2006
2006/08/18 2007/8/18Compal Electronics, Inc.
within 100mil to Ball A9,B9
layout note: Route H_SCOMP and H_SCOMP# withtrace width, spacing andimpedance (55 ohm) same as FSBdata traces
Near B3 pin
Layout Note:H_RCOMP / H_VREF / H_SWNG
trace width and spacing is 10/20
C642
0.1U_0402_16V4Z
1
2
H
O
S
T
U37A
CRESTLINE_1p0PM@
H_A#_10 G17H_A#_11 C14H_A#_12 K16H_A#_13 B13H_A#_14 L16H_A#_15 J17H_A#_16 B14H_A#_17 K19H_A#_18 P15H_A#_19 R17H_A#_20 B16H_A#_21 H20H_A#_22 L19H_A#_23 D17H_A#_24 M17H_A#_25 N16H_A#_26 J19H_A#_27 B18H_A#_28 E19H_A#_29 B17
H_A#_3 J13
H_A#_30 B15H_A#_31 E17
H_A#_4 B11H_A#_5 C11H_A#_6 M11H_A#_7 C15H_A#_8 F16H_A#_9 L13
H_ADS# G12H_ADSTB#_0 H17H_ADSTB#_1 G20
H_BNR# C8H_BPRI# E8
H_BREQ# F12
HPLL_CLK# AM7
H_CPURST#B6
HPLL_CLK AM5
H_D#_0E2
H_REQ#_2 A11H_REQ#_3 H13
H_D#_1G2
H_D#_10M10
H_D#_20M3
H_D#_30W3
H_D#_40AB2
H_D#_50AJ14
H_D#_60AE5
H_D#_8N8H_D#_9H2
H_DBSY# C10
H_D#_11N12H_D#_12N9H_D#_13H5H_D#_14P13H_D#_15K9H_D#_16M2H_D#_17W10H_D#_18Y8H_D#_19V4
H_D#_2G7
H_D#_21J1H_D#_22N5H_D#_23N3H_D#_24W6H_D#_25W9H_D#_26N2H_D#_27Y7H_D#_28Y9H_D#_29P4
H_D#_3M6
H_D#_31N1H_D#_32AD12H_D#_33AE3H_D#_34AD9H_D#_35AC9H_D#_36AC7H_D#_37AC14H_D#_38AD11H_D#_39AC11
H_D#_4H7
H_D#_41AD7H_D#_42AB1H_D#_43Y3H_D#_44AC6H_D#_45AE2H_D#_46AC5H_D#_47AG3H_D#_48AJ9H_D#_49AH8
H_D#_5H3
H_D#_51AE9H_D#_52AE11H_D#_53AH12H_D#_54AJ5H_D#_55AH5H_D#_56AJ6H_D#_57AE7H_D#_58AJ7H_D#_59AJ2
H_D#_6G4
H_D#_61AJ3H_D#_62AH2H_D#_63AH13
H_D#_7F3
H_DEFER# D6
H_DINV#_0 K5H_DINV#_1 L2H_DINV#_2 AD13H_DINV#_3 AE13
H_DPWR# H8H_DRDY# K7
H_DSTBN#_0 M7H_DSTBN#_1 K3H_DSTBN#_2 AD2H_DSTBN#_3 AH11
H_DSTBP#_0 L7H_DSTBP#_1 K2H_DSTBP#_2 AC2H_DSTBP#_3 AJ10
H_SCOMPW1
H_AVREFB9H_DVREFA9
H_TRDY# B7
H_HIT# E4H_HITM# C6H_LOCK# G10
H_REQ#_0 M14H_REQ#_1 E13
H_REQ#_4 B12
H_A#_32 C18H_A#_33 A19H_A#_34 B19H_A#_35 N19
H_SWINGB3
H_CPUSLP#E5
H_RCOMPC2
H_RS#_0 E12H_RS#_1 D7H_RS#_2 D8
H_SCOMP#W2
R543
54.9_0402_1%
1
2
R540
100_0402_1%
1
2
U37
965GMGM@
R546
2K_0402_1%
1
2
C641
0.1U_0402_16V4Z
1
2
R542
54.9_0402_1%
1
2
R539
221_0402_1%
1
2
R544
1K_0402_1%
1
2
R541
24.9_0402_1%
1
2
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DMI_ITX_MRX_N0
DMI_ITX_MRX_P1DMI_ITX_MRX_P0
DMI_ITX_MRX_P3DMI_ITX_MRX_P2
DMI_MTX_IRX_P1DMI_MTX_IRX_P0
DMI_MTX_IRX_P3DMI_MTX_IRX_P2
DMI_ITX_MRX_N3DMI_ITX_MRX_N2
DMI_MTX_IRX_N3
DMI_MTX_IRX_N1DMI_MTX_IRX_N0
DMI_MTX_IRX_N2
DMI_ITX_MRX_N1
CLK_MCH_3GPLL
SMRCOMPSMRCOMP#
MCH_CLKSEL1MCH_CLKSEL2
MCH_CLKSEL0
PM_EXTTS#0
GMCH_PWROK
MCH_CLKREQ#
CLK_MCH_3GPLL#
GMCH_PWROK
ICH_POK
VGATE
SM_RCOMP_VOL
SM_RCOMP_VOH
SM_RCOMP_VOHSM_RCOMP_VOL
MCH_CFG_5
MCH_CFG_9
MCH_CFG_12MCH_CFG_13
MCH_CFG_16
MCH_CFG_19MCH_CFG_20
MCH_CFG_13
MCH_CFG_20
MCH_CFG_9
MCH_CFG_16
MCH_CFG_12
MCH_CFG_19
MCH_CFG_5
MCH_TEST_1MCH_TEST_2
CL_VREF
PM_EXTTS#1
MCH_RSTIN#
PM_EXTTS#1
PM_EXTTS#0
MCH_CLKREQ#
DDRA_SMA14DDRB_SMA14
SM_RCOMP_VOH
CLK_DREF_SSCCLK_DREF_SSC#
CLK_DREF_96M#CLK_DREF_96M
SM_VREF
CLK_DREF_96M#
CLK_DREF_SSC#
CLK_DREF_96M
CLK_DREF_SSC
SDVO_CTRL_CLK
SDVO_CTRL_DATA
SDVO_CTRL_CLKSDVO_CTRL_DATA
MCH_CLKREQ#
PM_BMBUSY#
CLK_MCH_3GPLL# CLK_MCH_3GPLL
H_THERMTRIP#
MCH_ICH_SYNC#
MCH_CLKSEL2
MCH_CLKSEL0
PM_EXTTS#0
PM_DPRSLPVR
MCH_CLKSEL1
VGATE
ICH_POK
DDRA_CLK0 DDRA_CLK1 DDRB_CLK0 DDRB_CLK1
DDRA_CLK0# DDRA_CLK1# DDRB_CLK0# DDRB_CLK1#
DDRA_CKE0 DDRA_CKE1 DDRB_CKE0 DDRB_CKE1
DDRA_SCS0# DDRA_SCS1# DDRB_SCS0# DDRB_SCS1#
DDRA_ODT0 DDRA_ODT1 DDRB_ODT0 DDRB_ODT1
DMI_ITX_MRX_N0 DMI_ITX_MRX_N1 DMI_ITX_MRX_N2 DMI_ITX_MRX_N3
DMI_ITX_MRX_P0 DMI_ITX_MRX_P1 DMI_ITX_MRX_P2 DMI_ITX_MRX_P3
DMI_MTX_IRX_N0 DMI_MTX_IRX_N1 DMI_MTX_IRX_N2 DMI_MTX_IRX_N3
DMI_MTX_IRX_P0 DMI_MTX_IRX_P1 DMI_MTX_IRX_P2 DMI_MTX_IRX_P3
CL_CLK0 CL_DATA0 CL_PWROK CL_RST#
PM_EXTTS#1
H_DPRSTP#
PLT_RST#
DDRA_SMA14DDRB_SMA14
CLK_DREF_SSC CLK_DREF_SSC#
CLK_DREF_96M CLK_DREF_96M#
+1.8V+1.8V
+1.8V
+3VS
+1.25VS
+3VS
+1.05VS
Title
Size Document Number R ev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
IFTXX M/B LA-3541P Schematic 0Crestline (2/7)-DMI/DDR
Custom
8 52Wednesday, November 01, 2006
2006/08/18 2007/8/18Compal Electronics, Inc.
CFG[13:12]
1 = PCIE/SDVO are operating simu.
CFG19
(Default)
CFG20
0 = DMI x 2
*
Strap Pin Table
*10 = All Z Mode Enabled
(Default)
1 = Normal Operation
CFG5
SDVO_CTRLDATA
1 = DMI Lane Reversal Enable*
1 = Dynamic ODT Enabled (Default)
*
(Default)
00 = Reserved*
1 = DMI x 4
0 = No SDVO Device Present
(Default)
*
* (Default)
0 = Normal Operation
(Default)
0 = Only PCIE or SDVO is operational.
0 = Dynamic ODT Disabled
(PCIE/SDVO select)
01 = XOR Mode Enabled
010 = 800MT/s FSB
CFG16
011 = 667MT/s FSB
0 = Lane Reversal Enable CFG9
1 = SDVO Device Present
CFG[2:0]
11 = Normal Operation
20mil
Use VGATE for GMCH_PWROK
If THERMTRIP no used, left NC
9/20 Modify NB symbol for Pin BJ29/BE24/C48/D47
Layout Note: SM_VREF tracewidth and spacingis 20/20.
CFG[17:3] have internal pull upCFG[19:18] have internal pull down
R530 4.02K_0402_1%@
R534 10K_0402_5%
R517 20_0402_1% 1 2
R5143.01K_0402_1%
R518
1K_0402_1%
1
2
C636
0.01U_0402_16V7K
C637
2.2U_0805_10V6K
R5131K_0402_1%
R575 0_0402_5%PM@1 2
PM
M
I
S
C
NC
D
D
R
M
U
X
I
N
G
C
L
K
D
M
I
CFGRS
VD
G
R
A
P
H
I
C
S
V
I
D
M
E
U37B
CRESTLINE_1p0PM@
SM_CK_0 AV29SM_CK_1 BB23
RSVD28BF23
SM_CK_3 BA25
SM_CK#_0 AW30SM_CK#_1 BA23
RSVD29BG23
SM_CK#_3 AW25
SM_CKE_0 BE29SM_CKE_1 AY32SM_CKE_3 BD39SM_CKE_4 BG37
SM_CS#_0 BG20SM_CS#_1 BK16SM_CS#_2 BG16SM_CS#_3 BE13
RSVD34BH39
SM_ODT_0 BH18SM_ODT_1 BJ15SM_ODT_2 BJ14SM_ODT_3 BE16
SM_RCOMP BL15SM_RCOMP# BK14
SM_VREF_0 AR49SM_VREF_1 AW4
CFG_18L32CFG_19N33
CFG_2N24
CFG_0P27CFG_1N27
CFG_20L35
CFG_3C21CFG_4C23CFG_5F23CFG_6N23CFG_7G23CFG_8J20CFG_9C20CFG_10R24CFG_11L23CFG_12J23CFG_13E23CFG_14E20CFG_15K23CFG_16M20CFG_17M24
PM_BM_BUSY#G41
PM_EXT_TS#_0L36PM_EXT_TS#_1J36PWROKAW49RSTIN#AV20
DPLL_REF_CLK B42DPLL_REF_CLK# C42
DPLL_REF_SSCLK H48DPLL_REF_SSCLK# H47
DMI_RXN_0 AN47DMI_RXN_1 AJ38DMI_RXN_2 AN42DMI_RXN_3 AN46
DMI_RXP_0 AM47DMI_RXP_1 AJ39DMI_RXP_2 AN41DMI_RXP_3 AN45
DMI_TXN_0 AJ46DMI_TXN_1 AJ41DMI_TXN_2 AM40DMI_TXN_3 AM44
DMI_TXP_0 AJ47DMI_TXP_1 AJ42DMI_TXP_2 AM39DMI_TXP_3 AM43
RSVD10AR37
RSVD12AL36RSVD11AM36
RSVD13AM37
RSVD22BJ20RSVD23BK22RSVD24BF19RSVD25BH20RSVD26BK18
PM_DPRSTP#L39
SM_CK_4 AV23
SM_CK#_4 AW23
RSVD30BC23RSVD31BD24
RSVD35AW20RSVD36BK20
RSVD5AR12RSVD6AR13RSVD7AM12RSVD8AN13
RSVD1P36RSVD2P37RSVD3R35RSVD4N35
GFX_VID_0 E35GFX_VID_1 A39GFX_VID_2 C38GFX_VID_3 B39
GFX_VR_EN E36
RSVD27BJ18
SM_RCOMP_VOH BK31SM_RCOMP_VOL BL31
THERMTRIP#N20DPRSLPVRG36
RSVD9J12
CL_CLK AM49CL_DATA AK50
CL_PWROK AT43CL_RST# AN49CL_VREF AM50
LVDSA_DATA#_3C48LVDSA_DATA_3D47RSVD39B44RSVD40C44
SA_MA_14BJ29SB_MA_14BE24
RSVD21B51
NC_1BJ51NC_2BK51NC_3BK50NC_4BL50NC_5BL49NC_6BL3NC_7BL2NC_8BK1NC_9BJ1NC_10E1NC_11A5NC_12C51NC_13B50NC_14A50NC_15A49
SDVO_CTRL_CLK H35SDVO_CTRL_DATA K36
CLK_REQ# G39
RSVD14D20
ICH_SYNC# G40
RSVD20H10
RSVD41A35RSVD42B37RSVD43B36RSVD44B34RSVD45C34
PEG_CLK# K45PEG_CLK K44
TEST_1 A37NC_16BK2 TEST_2 R32
R525 100_0402_5%
R536 10K_0402_5%
R523 4.02K_0402_1%@
R516 20_0402_1% 1 2
R524 4.02K_0402_1%@
R5281K_0402_1%
1
2
R576 0_0402_5%PM@1 2
R532 10K_0402_5%
R535 0_0402_5% 1 2
R537 0_0402_5%
R521 4.02K_0402_1%@
R578 0_0402_5%@1 2
C639
0.1U_0402_16V4Z
1
2
R538 20K_0402_5%
R5151K_0402_1%
C640
0.1U_0402_16V4Z
1
2
R577 0_0402_5%PM@1 2
R522 4.02K_0402_1%@
R527 0_0402_5%
1 2
R579 0_0402_5%@1 2
R526 4.02K_0402_1%@
R533 0_0402_5%@1 2
R531392_0402_1%
1
2
R520
1K_0402_1%
1
2
C635
2.2U_0805_10V6K
R529 4.02K_0402_1%@
C638
0.01U_0402_16V7K
R574 0_0402_5%PM@1 2
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDRB_SMA3
DDRB_SMA7
DDRB_SMA0
DDRB_SMA2
DDRB_SMA10
DDRB_SMA1
DDRB_SMA6DDRB_SMA5
DDRB_SMA12DDRB_SMA11
DDRB_SMA4
DDRB_SMA8DDRB_SMA9
DDRB_SMA13
DDRB_SDQ2DDRB_SDQ3
DDRB_SDQ0DDRB_SDQ1
DDRB_SDQ7DDRB_SDQ6DDRB_SDQ5DDRB_SDQ4
DDRB_SDQ40DDRB_SDQ41DDRB_SDQ42DDRB_SDQ43DDRB_SDQ44DDRB_SDQ45DDRB_SDQ46DDRB_SDQ47
DDRB_SDQ12
DDRB_SDQ14DDRB_SDQ15
DDRB_SDQ13
DDRB_SDQ8DDRB_SDQ9DDRB_SDQ10DDRB_SDQ11
DDRB_SDQ48DDRB_SDQ49DDRB_SDQ50DDRB_SDQ51DDRB_SDQ52DDRB_SDQ53DDRB_SDQ54DDRB_SDQ55
DDRB_SDQ22DDRB_SDQ21
DDRB_SDQ17DDRB_SDQ18
DDRB_SDQ23
DDRB_SDQ16
DDRB_SDQ19DDRB_SDQ20
DDRB_SDQ56DDRB_SDQ57DDRB_SDQ58DDRB_SDQ59DDRB_SDQ60DDRB_SDQ61DDRB_SDQ62DDRB_SDQ63
DDRB_SDQ27DDRB_SDQ26
DDRB_SDQ29
DDRB_SDQ31DDRB_SDQ30
DDRA_SDQ2DDRA_SDQ3
DDRA_SDQ0
DDRB_SDQ24DDRB_SDQ25
DDRB_SDQ28
DDRB_SDQ32DDRB_SDQ33DDRB_SDQ34
DDRA_SDQ1
DDRA_SDQ7DDRA_SDQ6DDRA_SDQ5DDRA_SDQ4
DDRB_SDQ35DDRB_SDQ36DDRB_SDQ37DDRB_SDQ38DDRB_SDQ39
DDRA_SDQ40DDRA_SDQ41DDRA_SDQ42DDRA_SDQ43DDRA_SDQ44DDRA_SDQ45DDRA_SDQ46DDRA_SDQ47
DDRA_SDQ12
DDRA_SDQ14DDRA_SDQ15
DDRA_SDQ13
DDRA_SDQ8DDRA_SDQ9DDRA_SDQ10DDRA_SDQ11
DDRA_SDQ48DDRA_SDQ49DDRA_SDQ50DDRA_SDQ51DDRA_SDQ52DDRA_SDQ53DDRA_SDQ54DDRA_SDQ55
DDRA_SDQ22DDRA_SDQ21
DDRA_SDQ17DDRA_SDQ18
DDRA_SDQ23
DDRA_SDQ16
DDRA_SDQ19DDRA_SDQ20
DDRA_SDQ56DDRA_SDQ57DDRA_SDQ58DDRA_SDQ59DDRA_SDQ60DDRA_SDQ61DDRA_SDQ62DDRA_SDQ63
DDRA_SDQ27DDRA_SDQ26
DDRA_SDQ29
DDRA_SDQ31DDRA_SDQ30
DDRA_SDQ24DDRA_SDQ25
DDRA_SDQ28
DDRA_SDQ32DDRA_SDQ33DDRA_SDQ34DDRA_SDQ35DDRA_SDQ36DDRA_SDQ37DDRA_SDQ38DDRA_SDQ39
DDRA_SMA3
DDRA_SMA7
DDRA_SMA0
DDRA_SMA2
DDRA_SMA10
DDRA_SMA1
DDRA_SMA6DDRA_SMA5
DDRA_SMA12DDRA_SMA11
DDRA_SMA4
DDRA_SMA8DDRA_SMA9
DDRA_SMA13
DDRB_SDQ[0..63]
DDRB_SMA[0..13]
DDRB_SDM[0..7]
DDRB_SDQS0
DDRB_SDQS5DDRB_SDQS4
DDRB_SDM6
DDRB_SDM1
DDRB_SDM5
DDRB_SDM0
DDRB_SDM4DDRB_SDM3
DDRB_SDM7
DDRB_SDM2
DDRB_SDQS3
DDRB_SDQS7
DDRB_SDQS2
DDRB_SDQS6
DDRB_SDQS1
DDRB_SDQS5#
DDRB_SDQS0#
DDRB_SDQS4#DDRB_SDQS3#
DDRB_SDQS7#
DDRB_SDQS2#
DDRB_SDQS6#
DDRB_SDQS1#
DDRA_SDQS5
DDRA_SDQS0
DDRA_SDQS4DDRA_SDQS3
DDRA_SDQS7
DDRA_SDQS2
DDRA_SDQS6
DDRA_SDQS1
DDRA_SDQS5#
DDRA_SDQS0#
DDRA_SDQS4#DDRA_SDQS3#
DDRA_SDQS7#
DDRA_SDQS2#
DDRA_SDQS6#
DDRA_SDQS1#
DDRA_SDQ[0..63]
DDRA_SMA[0..13]
DDRA_SDM[0..7]
DDRA_SDM6DDRA_SDM5
DDRA_SDM0
DDRA_SDM4
DDRA_SDM1
DDRA_SDM7
DDRA_SDM2DDRA_SDM3
SA_RCVEN#SB_RCVEN#
DDRA_SBS2
DDRA_SBS0 DDRA_SBS1
DDRA_SDQS6
DDRA_SDQS3
DDRA_SDQS6#
DDRA_SDQS3#
DDRA_SDQS7#
DDRA_SDQS5#
DDRA_SDQS0#
DDRA_SDQS4#
DDRA_SDQS1# DDRA_SDQS2#
DDRA_SDQ[0..63]
DDRA_SMA[0..13]
DDRA_SDM[0..7]
DDRA_SDQS7
DDRA_SDQS5
DDRB_SDQ[0..63]
DDRB_SMA[0..13]
DDRB_SDM[0..7]
DDRA_SDQS0
DDRA_SWE#
DDRA_SDQS4
DDRB_SWE#
DDRA_SDQS1
DDRB_SBS2
DDRB_SBS0 DDRB_SBS1
DDRA_SDQS2
DDRB_SDQS6
DDRB_SDQS3
DDRB_SDQS6#
DDRB_SDQS3#
DDRB_SDQS7#
DDRB_SDQS5#
DDRB_SDQS0#
DDRB_SDQS4#
DDRB_SDQS1# DDRB_SDQS2#
DDRB_SDQS7
DDRB_SDQS5
DDRB_SDQS0
DDRB_SDQS4
DDRB_SDQS1 DDRB_SDQS2
DDRA_SCAS#
DDRA_SRAS#
DDRB_SCAS#
DDRB_SRAS#
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
IFTXX M/B LA-3541P Schematic 0Crestline (3/7)-DDRII
B
9 52Wednesday, November 01, 2006
2006/08/18 2007/8/18Compal Electronics, Inc.
T18PAD
D
D
R
S
Y
S
T
E
M
M
E
M
O
R
Y
B
U37E
CRESTLINE_1p0PM@
SB_DQ_0AP49SB_DQ_1AR51
SB_DQ_10BA49SB_DQ_11BE50SB_DQ_12BA51SB_DQ_13AY49SB_DQ_14BF50SB_DQ_15BF49SB_DQ_16BJ50SB_DQ_17BJ44SB_DQ_18BJ43SB_DQ_19BL43
SB_DQ_2AW50
SB_DQ_20BK47SB_DQ_21BK49SB_DQ_22BK43SB_DQ_23BK42SB_DQ_24BJ41SB_DQ_25BL41SB_DQ_26BJ37SB_DQ_27BJ36SB_DQ_28BK41SB_DQ_29BJ40
SB_DQ_3AW51
SB_DQ_30BL35SB_DQ_31BK37SB_DQ_32BK13SB_DQ_33BE11SB_DQ_34BK11SB_DQ_35BC11SB_DQ_36BC13SB_DQ_37BE12SB_DQ_38BC12SB_DQ_39BG12
SB_DQ_4AN51
SB_DQ_40BJ10SB_DQ_41BL9SB_DQ_42BK5SB_DQ_43BL5SB_DQ_44BK9SB_DQ_45BK10SB_DQ_46BJ8SB_DQ_47BJ6SB_DQ_48BF4SB_DQ_49BH5
SB_DQ_5AN50
SB_DQ_50BG1SB_DQ_51BC2SB_DQ_52BK3SB_DQ_53BE4SB_DQ_54BD3SB_DQ_55BJ2SB_DQ_56BA3SB_DQ_57BB3SB_DQ_58AR1SB_DQ_59AT3
SB_DQ_6AV50
SB_DQ_60AY2SB_DQ_61AY3SB_DQ_62AU2SB_DQ_63AT2
SB_DQ_7AV49SB_DQ_8BA50SB_DQ_9BB50
SB_BS_0 AY17SB_BS_1 BG18SB_BS_2 BG36
SB_CAS# BE17
SB_DM_0 AR50SB_DM_1 BD49SB_DM_2 BK45SB_DM_3 BL39SB_DM_4 BH12SB_DM_5 BJ7SB_DM_6 BF3SB_DM_7 AW2
SB_DQS_0 AT50SB_DQS_1 BD50SB_DQS_2 BK46SB_DQS_3 BK39SB_DQS_4 BJ12SB_DQS_5 BL7SB_DQS_6 BE2SB_DQS_7 AV2
SB_DQS#_0 AU50SB_DQS#_1 BC50SB_DQS#_2 BL45SB_DQS#_3 BK38SB_DQS#_4 BK12SB_DQS#_5 BK7SB_DQS#_6 BF2SB_DQS#_7 AV3
SB_MA_0 BC18SB_MA_1 BG28
SB_MA_10 BG17SB_MA_11 BE37SB_MA_12 BA39SB_MA_13 BG13
SB_MA_2 BG25SB_MA_3 AW17SB_MA_4 BF25SB_MA_5 BE25SB_MA_6 BA29SB_MA_7 BC28SB_MA_8 AY28SB_MA_9 BD37
SB_RAS# AV16SB_RCVEN# AY18
SB_WE# BC17
T17PAD
D
D
R
S
Y
S
T
E
M
M
E
M
O
R
Y
A
U37D
CRESTLINE_1p0PM@
SA_DQ_0AR43SA_DQ_1AW44
SA_DQ_10BG47SA_DQ_11BJ45SA_DQ_12BB47SA_DQ_13BG50SA_DQ_14BH49SA_DQ_15BE45SA_DQ_16AW43SA_DQ_17BE44SA_DQ_18BG42SA_DQ_19BE40
SA_DQ_2BA45
SA_DQ_20BF44SA_DQ_21BH45SA_DQ_22BG40SA_DQ_23BF40SA_DQ_24AR40SA_DQ_25AW40SA_DQ_26AT39SA_DQ_27AW36SA_DQ_28AW41SA_DQ_29AY41
SA_DQ_3AY46
SA_DQ_30AV38SA_DQ_31AT38SA_DQ_32AV13SA_DQ_33AT13SA_DQ_34AW11SA_DQ_35AV11SA_DQ_36AU15SA_DQ_37AT11SA_DQ_38BA13SA_DQ_39BA11
SA_DQ_4AR41
SA_DQ_40BE10SA_DQ_41BD10SA_DQ_42BD8SA_DQ_43AY9SA_DQ_44BG10SA_DQ_45AW9SA_DQ_46BD7SA_DQ_47BB9SA_DQ_48BB5SA_DQ_49AY7
SA_DQ_5AR45
SA_DQ_50AT5SA_DQ_51AT7SA_DQ_52AY6SA_DQ_53BB7SA_DQ_54AR5SA_DQ_55AR8SA_DQ_56AR9SA_DQ_57AN3SA_DQ_58AM8SA_DQ_59AN10
SA_DQ_6AT42
SA_DQ_60AT9SA_DQ_61AN9SA_DQ_62AM9SA_DQ_63AN11
SA_DQ_7AW47SA_DQ_8BB45SA_DQ_9BF48
SA_BS_0 BB19SA_BS_1 BK19SA_BS_2 BF29
SA_CAS# BL17
SA_DM_0 AT45SA_DM_1 BD44SA_DM_2 BD42SA_DM_3 AW38SA_DM_4 AW13SA_DM_5 BG8SA_DM_6 AY5
SA_DQS_0 AT46SA_DQS_1 BE48SA_DQS_2 BB43SA_DQS_3 BC37SA_DQS_4 BB16SA_DQS_5 BH6SA_DQS_6 BB2SA_DQS_7 AP3
SA_DM_7 AN6
SA_DQS#_0 AT47SA_DQS#_1 BD47SA_DQS#_2 BC41SA_DQS#_3 BA37SA_DQS#_4 BA16SA_DQS#_5 BH7SA_DQS#_6 BC1SA_DQS#_7 AP2
SA_MA_0 BJ19SA_MA_1 BD20
SA_MA_10 BC19SA_MA_11 BE28SA_MA_12 BG30SA_MA_13 BJ16
SA_MA_2 BK27SA_MA_3 BH28SA_MA_4 BL24SA_MA_5 BK28SA_MA_6 BJ27SA_MA_7 BJ25SA_MA_8 BL28SA_MA_9 BA28
SA_RAS# BE18SA_RCVEN# AY20
SA_WE# BA19
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
GMCH_TZOUT0+
GMCH_TZOUT1-
GMCH_TXOUT1-
GMCH_TZOUT2-
GMCH_TXOUT2-
GMCH_TZOUT1+
GMCH_TXOUT0+
GMCH_TZOUT2+
GMCH_TXOUT2+
GMCH_TXOUT0-
GMCH_TXOUT1+
GMCH_TZOUT0-
GMCH_TV_LUMAGMCH_TV_CRMA
GMCH_TV_COMPS
LVDS_IBG
GMCH_LCD_CLKGMCH_LCD_DATA
LCTLB_DATALCTLA_CLK
PCIE_MTX_GRX_N2PCIE_MTX_GRX_N1PCIE_MTX_GRX_N0
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_N8PCIE_MTX_GRX_N9PCIE_MTX_GRX_N10
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_N11PCIE_MTX_GRX_N12
PCIE_MTX_GRX_N15PCIE_MTX_GRX_N14PCIE_MTX_GRX_N13
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_N1PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_N15
PCIE_MTX_C_GRX_N13
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_P2PCIE_MTX_GRX_P3
PCIE_MTX_GRX_P0
PCIE_MTX_GRX_P4PCIE_MTX_GRX_P5
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_P11PCIE_MTX_GRX_P10PCIE_MTX_GRX_P9
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_P15PCIE_MTX_GRX_P14PCIE_MTX_GRX_P13PCIE_MTX_GRX_P12
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_P1PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_P5PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_P10PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_P12PCIE_MTX_C_GRX_P13PCIE_MTX_C_GRX_P14
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_P9PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_N10PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_N12PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_N15
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_N0
PCIE_MTX_C_GRX_P[0..15]
PCIE_MTX_C_GRX_N[0..15]
PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]
GMCH_LCD_CLK
GMCH_LCD_DATA
LCTLB_DATA
LCTLA_CLK
LBKLT_EN
GMCH_CRT_DATAGMCH_CRT_CLK
PEG_COMP
GMCH_TXCLK-GMCH_TXCLK+
GMCH_TZCLK-GMCH_TZCLK+
TV_DCONSEL_0
TV_DCONSEL_1
TV_DCONSEL_0TV_DCONSEL_1
CRT_IREF
GMCH_CRT_CLK
GMCH_CRT_DATA
GMCH_LCD_CLK
GMCH_LCD_DATA
TV_DCONSEL_0
TV_DCONSEL_1
LCTLB_DATA
LCTLA_CLK
GMCH_TV_LUMA
GMCH_TV_CRMA
GMCH_CRT_B
GMCH_CRT_G
GMCH_CRT_R
GMCH_TV_COMPS
PCIE_MTX_GRX_N4 PCIE_MTX_C_GRX_N4
GMCH_ENVDD PCIE_MTX_C_GRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
GMCH_LCD_DATAGMCH_LCD_CLK
GMCH_ENBKL
GMCH_TXOUT0-GMCH_TXOUT1-GMCH_TXOUT2-
GMCH_TXOUT0+GMCH_TXOUT1+GMCH_TXOUT2+
GMCH_TZOUT0-GMCH_TZOUT1-GMCH_TZOUT2-
GMCH_TZOUT0+GMCH_TZOUT1+GMCH_TZOUT2+
GMCH_TXCLK-GMCH_TXCLK+
GMCH_TZCLK-GMCH_TZCLK+
GMCH_TV_COMPSGMCH_TV_LUMAGMCH_TV_CRMA
GMCH_CRT_B
GMCH_CRT_G
GMCH_CRT_R
GMCH_CRT_VSYNC
GMCH_CRT_HSYNC
GMCH_CRT_CLKGMCH_CRT_DATA
+3VS
+1.05VS
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
IFTXX M/B LA-3541P Schematic 0Crestline (4/7)-VGA/LVDS/TV
B
10 52Wednesday, November 01, 2006
2006/08/18 2007/8/18Compal Electronics, Inc.
20/25mils
Change to 0Ohm when use PM chip
CRB 2.37K_1% to GND
CRB 2.2K , Follow!
R493 2.4K_0402_1%GM@1 2
C632 0.1U_0402_10V7KPM@1 2
C609 0.1U_0402_10V7KPM@1 2
R498 150_0402_1%GM@12
C629 0.1U_0402_10V7KPM@1 2
C618 0.1U_0402_10V7KPM@1 2
R494
150_0402_1%GM@
1
2
R503 2.2K_0402_5%GM@ 1 2
R499 150_0402_1%GM@12
C615 0.1U_0402_10V7KPM@1 2
R495
150_0402_1%GM@ 1
2
C604 0.1U_0402_10V7KPM@1 2
R5021.3K_0402_1%
1
2
C624 0.1U_0402_10V7KPM@1 2
R5000_0402_5%PM@
R585 0_0402_5%PM@1 2R504 2.2K_0402_5%GM@1 2
R505 10K_0402_5%GM@ 1 2
C621 0.1U_0402_10V7KPM@1 2
R492 24.9_0402_1%
1 2
R594 0_0402_5%PM@1 2
C610 0.1U_0402_10V7KPM@1 2
C630 0.1U_0402_10V7KPM@1 2
C607 0.1U_0402_10V7KPM@1 2
R580 0_0402_5%PM@1 2
C627 0.1U_0402_10V7KPM@1 2
R592 0_0402_5%PM@1 2
R593 0_0402_5%PM@1 2
C616 0.1U_0402_10V7KPM@1 2
R510 2.2K_0402_5%GM@
R719 39_0402_1%GM@1 2
C613 0.1U_0402_10V7KPM@1 2
LVDS
P
C
I
-
E
X
P
R
E
S
S
G
R
A
P
H
I
C
S
TVVGA
U37C
CRESTLINE_1p0
PM@
PEG_COMPI N43PEG_COMPO M43
PEG_RX#_0 J51PEG_RX#_1 L51PEG_RX#_2 N47PEG_RX#_3 T45PEG_RX#_4 T50PEG_RX#_5 U40PEG_RX#_6 Y44PEG_RX#_7 Y40PEG_RX#_8 AB51PEG_RX#_9 W49
PEG_RX#_10 AD44PEG_RX#_11 AD40PEG_RX#_12 AG46PEG_RX#_13 AH49PEG_RX#_14 AG45PEG_RX#_15 AG41
PEG_RX_0 J50PEG_RX_1 L50PEG_RX_2 M47PEG_RX_3 U44PEG_RX_4 T49PEG_RX_5 T41PEG_RX_6 W45PEG_RX_7 W41PEG_RX_8 AB50PEG_RX_9 Y48
PEG_RX_10 AC45PEG_RX_11 AC41PEG_RX_12 AH47PEG_RX_13 AG49PEG_RX_14 AH45PEG_RX_15 AG42
PEG_TX#_0 N45
PEG_TX#_10 AC46
PEG_TX#_3 N51PEG_TX#_4 R50PEG_TX#_5 T42PEG_TX#_6 Y43PEG_TX#_7 W46PEG_TX#_8 W38PEG_TX#_9 AD39
PEG_TX#_1 U39
PEG_TX#_11 AC49PEG_TX#_12 AC42PEG_TX#_13 AH39PEG_TX#_14 AE49PEG_TX#_15 AH44
PEG_TX#_2 U47
PEG_TX_0 M45PEG_TX_1 T38PEG_TX_2 T46PEG_TX_3 N50PEG_TX_4 R51PEG_TX_5 U43PEG_TX_6 W42PEG_TX_7 Y47PEG_TX_8 Y39PEG_TX_9 AC38
PEG_TX_10 AD47PEG_TX_11 AC50PEG_TX_12 AD43PEG_TX_13 AG39PEG_TX_14 AE50PEG_TX_15 AH43
L_CTRL_CLKE39L_CTRL_DATAE40L_DDC_CLKC37L_DDC_DATAD35L_VDD_ENK40
LVDS_IBGL41LVDS_VBGL43LVDS_VREFHN41LVDS_VREFLN40LVDSA_CLK#D46LVDSA_CLKC45
LVDSA_DATA#_0G51LVDSA_DATA#_1E51LVDSA_DATA#_2F49
LVDSA_DATA_1E50LVDSA_DATA_2F48
LVDSB_CLK#D44LVDSB_CLKE42
LVDSB_DATA#_0G44LVDSB_DATA#_1B47LVDSB_DATA#_2B45
LVDSB_DATA_1A47LVDSB_DATA_2A45
L_BKLT_ENH39
TVA_DACE27TVB_DACG27TVC_DACK27
TVA_RTNF27TVB_RTNJ27TVC_RTNL27
CRT_BLUEH32CRT_BLUE#G32
CRT_DDC_CLKK33CRT_DDC_DATAG35
CRT_GREENK29CRT_GREEN#J29
CRT_HSYNCF33CRT_TVO_IREFC32
CRT_REDF29CRT_RED#E29
CRT_VSYNCE33
LVDSA_DATA_0G50
LVDSB_DATA_0E44
L_BKLT_CTRLJ40
TV_DCONSEL_0M35TV_DCONSEL_1P33
C633 0.1U_0402_10V7KPM@1 2
R588 0_0402_5%GM@1 2
C622 0.1U_0402_10V7KPM@1 2
R589 0_0402_5%PM@1 2
C619 0.1U_0402_10V7KPM@1 2
R718 39_0402_1%GM@1 2
C608 0.1U_0402_10V7KPM@1 2
R590 0_0402_5%PM@1 2
C628 0.1U_0402_10V7KPM@1 2
C605 0.1U_0402_10V7KPM@1 2
R509 2.2K_0402_5%GM@
C625 0.1U_0402_10V7KPM@1 2
C614 0.1U_0402_10V7KPM@1 2
R582 0_0402_5%PM@1 2
C634 0.1U_0402_10V7KPM@1 2
C611 0.1U_0402_10V7KPM@1 2
C631 0.1U_0402_10V7KPM@1 2
C620 0.1U_0402_10V7KPM@1 2
R584 0_0402_5%PM@1 2
R506 10K_0402_5%GM@1 2
C603 0.1U_0402_10V7KPM@1 2
R497 150_0402_1%GM@12
C617 0.1U_0402_10V7KPM@1 2
R583 0_0402_5%PM@1 2
C606 0.1U_0402_10V7KPM@1 2
R586 0_0402_5%PM@1 2
C626 0.1U_0402_10V7KPM@1 2
R591 0_0402_5%PM@1 2
C623 0.1U_0402_10V7KPM@1 2
R587 0_0402_5%PM@1 2
R581 0_0402_5%PM@1 2
R5010_0402_5%PM@
C612 0.1U_0402_10V7KPM@1 2
R496
150_0402_1%GM@
1
2
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCCSM_LF4
VCCSM_LF7
VCCSM_LF2
VCCSM_LF5
VCCSM_LF3
VCCSM_LF6
VCCSM_LF1
+1.05VS
+1.8V
+VCC_AXG
+VCC_AXG+1.05VS
+1.05VS
+1.05VS
+1.05VS
+1.8V
+VCC_AXG
+1.05VS
+1.05VS +VCC_AXG
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
IFTXX M/B LA-3541P Schematic 0Crestline (5/7)-VCC
B
11 52Wednesday, November 01, 2006
2006/08/18 2007/8/18Compal Electronics, Inc.
VCC: 1573mA(220UF*1, 22UF*1, 0.22UF*2, 0.1UF*1)
VCC_SM: 3300mA(330UF*1, 22UF*2, 0.1UF*1)
VCC_AXG: 7700mA(330UF*2, 22UF*1, 10UF*1, 1U*1, 0.47U*1, 0.1UF*2)
VCC_AXM: 540mA (22UF*2, 0.22UF*2, 0.1UF*2)
CRB 270uF , there is no 270u part.
Replace 0 Ohmby directlyconnection
9/19 change to 330u, 9/29 change to 220u
9/14 add for reservation
Follow DG 1.1
9/18 modify from +1.05VS to +VCC_AXG
9/18 modify from +1.05VS to +VCC_AXG
9/18 modify from +1.05VS to +VCC_AXG 9/18 Add for 965PM use
1005 This is for GM@
9/29 +1.05VS_AXM change to +1.05VS
9/29+1.05VS_AXMchange to+1.05VS
Remember open stencil at GM@
+C583
330U_D2E_2.5VMGM@
1
2
+C582
330U_D2E_2.5VMGM@
1
2
C580
22U_0805_6.3V6M
1
2
C589
0.1U_0402_16V4ZGM@
1
2
C601
1U_0603_10V4Z
C575
0.22U_0603_16V7K
C579
22U_0805_6.3V6M@
1
2
C600
0.47U_0603_16V4Z
C602
1U_0603_10V4Z
C599
0.22U_0603_16V7K
C593
0.1U_0402_16V4Z
1
2
C691
1U_0603_10V4Z@
+C578
330U_D2E_2.5VM
1
2
C585
10U_0805_10V4ZGM@
1
2
POWER
V
C
C
C
O
R
E
V
C
C
S
M
V
C
C
G
F
X
V
C
C
G
F
X
N
C
T
F
V
C
C
S
M
L
F
U37G
CRESTLINE_1p0PM@
VCC_5AC32
VCC_6AK32VCC_7AJ31VCC_8AJ28VCC_9AH32VCC_10AH31VCC_11AH29VCC_12AF32
VCC_2AT34
VCC_4AC31
VCC_SM_10BA35
VCC_SM_20BF33
VCC_SM_30BJ34
VCC_SM_6AW35VCC_SM_7AY35VCC_SM_8BA32VCC_SM_9BA33
VCC_SM_11BB33VCC_SM_12BC32VCC_SM_13BC33VCC_SM_14BC35VCC_SM_15BD32VCC_SM_16BD35VCC_SM_17BE32VCC_SM_18BE33VCC_SM_19BE35
VCC_SM_2AU33
VCC_SM_21BF34VCC_SM_22BG32VCC_SM_23BG33VCC_SM_24BG35VCC_SM_25BH32VCC_SM_26BH34VCC_SM_27BH35VCC_SM_28BJ32VCC_SM_29BJ33
VCC_SM_3AU35
VCC_SM_31BK32VCC_SM_32BK33VCC_SM_33BK34VCC_SM_34BK35
VCC_AXG_NCTF_10 U17VCC_AXG_NCTF_11 U19VCC_AXG_NCTF_12 U20VCC_AXG_NCTF_13 U21VCC_AXG_NCTF_14 U23VCC_AXG_NCTF_15 U26VCC_AXG_NCTF_16 V16VCC_AXG_NCTF_17 V17VCC_AXG_NCTF_18 V19VCC_AXG_NCTF_19 V20
VCC_AXG_NCTF_2 T18
VCC_AXG_NCTF_20 V21VCC_AXG_NCTF_21 V23VCC_AXG_NCTF_22 V24VCC_AXG_NCTF_23 Y15VCC_AXG_NCTF_24 Y16VCC_AXG_NCTF_25 Y17VCC_AXG_NCTF_26 Y19VCC_AXG_NCTF_27 Y20VCC_AXG_NCTF_28 Y21VCC_AXG_NCTF_29 Y23
VCC_AXG_NCTF_3 T19
VCC_AXG_NCTF_30 Y24VCC_AXG_NCTF_31 Y26VCC_AXG_NCTF_32 Y28VCC_AXG_NCTF_33 Y29VCC_AXG_NCTF_34 AA16VCC_AXG_NCTF_35 AA17VCC_AXG_NCTF_36 AB16VCC_AXG_NCTF_37 AB19VCC_AXG_NCTF_38 AC16VCC_AXG_NCTF_39 AC17
VCC_AXG_NCTF_4 T21
VCC_AXG_NCTF_40 AC19VCC_AXG_NCTF_41 AD15VCC_AXG_NCTF_42 AD16VCC_AXG_NCTF_43 AD17VCC_AXG_NCTF_44 AF16VCC_AXG_NCTF_45 AF19VCC_AXG_NCTF_46 AH15VCC_AXG_NCTF_47 AH16VCC_AXG_NCTF_48 AH17VCC_AXG_NCTF_49 AH19
VCC_AXG_NCTF_5 T22
VCC_AXG_NCTF_50 AJ16VCC_AXG_NCTF_51 AJ17VCC_AXG_NCTF_52 AJ19VCC_AXG_NCTF_53 AK16VCC_AXG_NCTF_54 AK19VCC_AXG_NCTF_55 AL16VCC_AXG_NCTF_56 AL17VCC_AXG_NCTF_57 AL19VCC_AXG_NCTF_58 AL20VCC_AXG_NCTF_59 AL21
VCC_AXG_NCTF_6 T23
VCC_AXG_NCTF_60 AL23VCC_AXG_NCTF_61 AM15VCC_AXG_NCTF_62 AM16VCC_AXG_NCTF_63 AM19
VCC_AXG_NCTF_65 AM21VCC_AXG_NCTF_66 AM23VCC_AXG_NCTF_67 AP15VCC_AXG_NCTF_68 AP16VCC_AXG_NCTF_69 AP17
VCC_AXG_NCTF_7 T25
VCC_AXG_NCTF_70 AP19VCC_AXG_NCTF_71 AP20VCC_AXG_NCTF_72 AP21
VCC_AXG_NCTF_8 U15VCC_AXG_NCTF_9 U16
VCC_SM_35BL33
VCC_SM_4AV33VCC_SM_5AW33
VCC_AXG_NCTF_1 T17VCC_1AT35
VCC_SM_1AU32
VCC_AXG_1R20VCC_AXG_2T14VCC_AXG_3W13VCC_AXG_4W14VCC_AXG_5Y12VCC_AXG_6AA20VCC_AXG_7AA23VCC_AXG_8AA26VCC_AXG_9AA28VCC_AXG_10AB21VCC_AXG_11AB24VCC_AXG_12AB29VCC_AXG_13AC20VCC_AXG_14AC21VCC_AXG_15AC23VCC_AXG_16AC24VCC_AXG_17AC26VCC_AXG_18AC28VCC_AXG_19AC29VCC_AXG_20AD20VCC_AXG_21AD23VCC_AXG_22AD24VCC_AXG_23AD28VCC_AXG_24AF21VCC_AXG_25AF26
VCC_AXG_27AH20VCC_AXG_28AH21VCC_AXG_29AH23VCC_AXG_30AH24
VCC_AXG_NCTF_73 AP23VCC_AXG_NCTF_74 AP24VCC_AXG_NCTF_75 AR20VCC_AXG_NCTF_76 AR21VCC_AXG_NCTF_77 AR23VCC_AXG_NCTF_78 AR24VCC_AXG_NCTF_79 AR26
VCC_13R30
VCC_AXG_31AH26
VCC_AXG_33AJ20VCC_AXG_34AN14
VCC_SM_LF1 AW45VCC_SM_LF2 BC39VCC_SM_LF3 BE39VCC_SM_LF4 BD17VCC_SM_LF5 BD4VCC_SM_LF6 AW8VCC_SM_LF7 AT6
VCC_AXG_26AA31
VCC_AXG_32AD31
VCC_3AH28
VCC_AXG_NCTF_64 AM20
VCC_SM_36AU30
VCC_AXG_NCTF_80 V26VCC_AXG_NCTF_81 V28VCC_AXG_NCTF_82 V29VCC_AXG_NCTF_83 Y31
C592
0.22U_0603_16V7K
POWER
V
C
C
N
C
T
F
V
S
S
N
C
T
F
V
S
S
S
C
B
V
C
C
A
X
M
V
C
C
A
X
M
N
C
T
F
U37F
CRESTLINE_1p0PM@
VCC_NCTF_1AB33
VCC_NCTF_20AK37
VCC_NCTF_29AP35
VCC_NCTF_42U31
VCC_NCTF_9AF33VCC_NCTF_10AF36VCC_NCTF_11AH33VCC_NCTF_12AH35VCC_NCTF_13AH36VCC_NCTF_14AH37VCC_NCTF_15AJ33
VCC_NCTF_17AK33VCC_NCTF_18AK35VCC_NCTF_19AK36
VCC_NCTF_2AB36
VCC_NCTF_24AL33VCC_NCTF_25AL35
VCC_NCTF_3AB37
VCC_NCTF_30AP36VCC_NCTF_31AR35VCC_NCTF_32AR36
VCC_NCTF_38T30VCC_NCTF_39T34VCC_NCTF_40T35VCC_NCTF_41U29
VCC_NCTF_4AC33
VCC_NCTF_43U32VCC_NCTF_44U33VCC_NCTF_45U35VCC_NCTF_46U36
VCC_NCTF_48V33VCC_NCTF_49V36VCC_NCTF_50V37
VCC_NCTF_5AC35VCC_NCTF_6AC36VCC_NCTF_7AD35
VSS_NCTF_1 T27VSS_NCTF_2 T37VSS_NCTF_3 U24VSS_NCTF_4 U28VSS_NCTF_5 V31VSS_NCTF_6 V35
VSS_NCTF_8 AB17VSS_NCTF_9 AB35
VSS_NCTF_10 AD19
VCC_NCTF_8AD36
VSS_NCTF_7 AA19
VSS_NCTF_11 AD37VSS_NCTF_12 AF17
VSS_NCTF_14 AK17
VSS_NCTF_16 AM24VSS_NCTF_17 AP26
VSS_NCTF_19 AR15VSS_NCTF_20 AR19VSS_NCTF_21 AR28
VCC_NCTF_33Y32
VCC_AXM_4 AK24VCC_AXM_5 AK23VCC_AXM_6 AJ26VCC_AXM_7 AJ23
VCC_AXM_NCTF_1AL24VCC_AXM_NCTF_2AL26VCC_AXM_NCTF_3AL28VCC_AXM_NCTF_4AM26VCC_AXM_NCTF_5AM28VCC_AXM_NCTF_6AM29VCC_AXM_NCTF_7AM31
VCC_AXM_NCTF_10AP29VCC_AXM_NCTF_11AP31
VCC_AXM_NCTF_17AR31
VCC_NCTF_34Y33VCC_NCTF_35Y35VCC_NCTF_36Y36VCC_NCTF_37Y37 VSS_SCB1 A3
VSS_SCB2 B2VSS_SCB3 C1VSS_SCB4 BL1VSS_SCB5 BL51VSS_SCB6 A51
VCC_NCTF_26AA33VCC_NCTF_27AA35VCC_NCTF_28AA36
VCC_NCTF_16AJ35
VCC_NCTF_21AD33
VSS_NCTF_13 AF35
VCC_NCTF_22AJ36
VCC_AXM_3 AK29
VCC_AXM_NCTF_14AL29VCC_AXM_NCTF_15AL31VCC_AXM_NCTF_16AL32
VSS_NCTF_15 AM17
VCC_AXM_NCTF_8AM32VCC_AXM_NCTF_9AM33
VCC_NCTF_23AM35
VSS_NCTF_18 AP28
VCC_AXM_NCTF_12AP32VCC_AXM_NCTF_13AP33
VCC_AXM_NCTF_18AR32VCC_AXM_NCTF_19AR33
VCC_AXM_2 AT31VCC_AXM_1 AT33
VCC_NCTF_47V32
C594
0.1U_0402_16V4Z
1
2
R609
0_0805_5%PM@
C584
22U_0805_6.3V6MGM@
1
2
C574
22U_0805_6.3V6M
1
2
C598
0.22U_0603_16V7K
C590
22U_0805_6.3V6M
1
2
C692
4.7U_0805_10V4Z
C576
0.22U_0603_16V7K
C591
0.22U_0603_16V7K
+C573
220U_D2_2VMR15
1
2
J6
PAD-OPEN 3x3m@
1 2
C577
0.1U_0402_16V4Z
1
2
C597
0.1U_0402_16V4Z
1
2
C586
1U_0603_10V4ZGM@
C690
0.1U_0402_16V4Z@
1
2
C587
0.47U_0603_16V4ZGM@
C595
0.1U_0402_16V4Z
1
2
C596
0.1U_0402_16V4Z
1
2
C581
1U_0603_10V4Z
C588
0.1U_0402_16V4ZGM@
1
2
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VTTLF_CAP3VTTLF_CAP2VTTLF_CAP1
+1.25VS_A_PEGPLL
+1.25VS_A_PEGPLL
VCCD_CRT
+1.8V_LVDS
+1.05VS
+1.25VS_AXD
+1.25VS
+1.25VS_AXF
+1.25VS
+1.25VS
+1.8V_SM_CK
+1.8V
+1.8V_TX_LVDS
+1.8V
+3VS
+3VS
+1.05VS_PEG
+1.05VS_PEG
+3VS_CRTDAC
+3VS_DACBG
+1.25VS_A_SM
+1.25VS
+1.25VS_A_SM_CK
+1.25VS
+1.25VS
+1.8V_TX_LVDS
+3VS
+1.25VS_DPLLA
+1.25VS_DPLLB
+1.25VS_HPLL
+1.25VS_MPLL
+1.25VS
+1.25VS_DPLLA
+1.25VS_DPLLB
+1.25VS_HPLL
+1.25VS_MPLL
+1.25VS
+1.5VS_QDAC
+1.5VS
+1.25VS
+1.8V
+1.05VS +3VS
+3VS_SYNC
+1.5VS_QDAC
+3VS
+3VS_A_TVDAC
+1.5VS
+1.5VS_TVDAC
+3VS
+3VS_SYNC
+3VS
+3VS_CRTDAC
+3VS
+3VS_DACBG
+3VS_A_TVDAC
+1.5VS_TVDAC
+1.5VS_TVDAC
+1.05VS
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
IFTXX M/B LA-3541P Schematic 0Crestline (6/7)-VCC
B
12 52Wednesday, November 01, 2006
2006/08/18 2007/8/18Compal Electronics, Inc.
VTT: 850mA(220UF*1, 4.7UF*21, 2.2UF*1, 0.47UF*1)
VCC_AXD: 515mA(22UF*1, 1UF*1)
VCC_AXF: 495mA(10UF*1, 1UF*1)
VCC_DMI: 100mA (0.1UF*1)
VCC_SM_CK: 200mA (22UF*1, 0.1UF*1)
+1.8V_TX_LVDS: 100mA(220UF*1, 1000PF*1)
+1.05VS_PEG: 1260mA (220UF*1, 10UF*1)
+1.05VS_DMI: 100mA (220UF*1, 10UF*1)
VCC_HV: 100mA
VCC_SYNC: 10mA (0.1UF*1)
VCCA_CRT_DAC: 80mA (0.1UF*1, 0.022UF*1)
VCCA_DAC_BG: 5mA (0.1UF*1, 0.022UF*1)
VCCA_SM: 640mA(22UF*21, 4.7UF*1, 1UF*1)
VCCA_SM_CK: 35mA(22UF*1, 1UF*2, 0.1UF*1)
VCCA_DPLLA/B: 100mA(470UF*1, 0.1UF*1)
VCCA_DPLLA/B: 100mA(470UF*1, 0.1UF*1)
VCCA_HPLL: 50mA(22UF*1, 0.1UF*1)
VCCD_HPLL: 250mA (0.1UF*1)
VCCA_MPLL:150mA(10UF*1, 0.1UF*1)
VCCA_PEG_PLL: 100mA (0.1UF*1)
VCCA_PEG_PLL: 100mA (0.1UF*1)
VCCA_PEG_BG: 5mA (0.1UF*1)
VCCA_LVDS: 10mA (0.1UF*1)
VCCD_LVDS: 150mA (10UF*1, 0.1UF*1)
VCCD_TVDAC / CRT: each 60mA (0.1UF*1, 0.022UF*1)
VCCD_QDAC: 5mA (0.1UF*1, 0.022UF*1)
VCCA_TV_DAC: 40mA each DAC (0.1UF*1, 0.022UF*1 for each DAC)
Close to VCC_HV (pin C40/B40)L53MBK1608121YZF_0603
1 2
C552
0.1U_0402_16V4ZGM@
1
2
C568
0.1U_0402_16V4ZGM@
1
2
C571
0.1U_0402_16V4ZGM@
1
2
C567
0.022U_0402_16V7KGM@
L45MBK1608121YZF_0603GM@
1 2
C555
0.1U_0402_16V4Z
1
2
C523
22U_0805_6.3V6M
1
2C525
1000P_0402_50V7KGM@
1
2
C517
2.2U_0805_10V6K
POWER
C
R
T
P
L
L
A
P
E
G
A
S
M
T
V
D
T
V
/
C
R
T
L
V
D
S
V
T
T
L
F
P
E
G
S
M
C
K
A
X
D
A
X
F
V
T
T
D
M
I
H
V
A
C
K
A
L
V
D
S
U37H
CRESTLINE_1p0PM@
VTT_19 T2VTT_20 R3VTT_21 R2VTT_22 R1
VCCD_CRTM32
VCCA_PEG_BGK50
VCCA_PEG_PLLU51
VCCA_CRT_DAC_1A33VCCA_CRT_DAC_2B33
VCCA_DPLLAB49
VCCA_DPLLBH49
VCCA_HPLLAL2
VCCA_LVDSA41
VCCA_MPLLAM2
VCCA_TVA_DAC_1C25VCCA_TVA_DAC_2B25VCCA_TVB_DAC_1C27VCCA_TVB_DAC_2B27VCCA_TVC_DAC_1B28VCCA_TVC_DAC_2A28
VCCD_PEG_PLLU48
VTT_15 T7VTT_16 T6VTT_17 T5VTT_18 T3
VTT_12 T11VTT_13 T10VTT_14 T9
VCCSYNCJ32
VCCD_HPLLAN2
VTT_1 U13VTT_2 U12
VTT_4 U9VTT_5 U8VTT_6 U7VTT_7 U5VTT_8 U3VTT_9 U2
VTT_10 U1VTT_11 T13
VTT_3 U11
VCCA_SM_CK_1BC29VCCA_SM_CK_2BB29
VCCA_DAC_BGA30
VCCD_TVDACL29
VTTLF1 A7VTTLF2 F2VTTLF3 AH1
VCC_RXR_DMI_1 AH50VCC_RXR_DMI_2 AH51
VCC_SM_CK_1 BK24VCC_SM_CK_2 BK23VCC_SM_CK_3 BJ24VCC_SM_CK_4 BJ23
VCCD_LVDS_1J41
VCCD_QDACN28
VCC_AXD_2 AU28VCC_AXD_3 AU24
VCC_AXD_5 AT25
VCC_AXF_1 B23VCC_AXF_2 B21VCC_AXF_3 A21
VCCA_SM_1AW18VCCA_SM_2AV19VCCA_SM_3AU19VCCA_SM_4AU18VCCA_SM_5AU17
VCCA_SM_7AT22VCCA_SM_8AT21VCCA_SM_9AT19
VCC_DMI AJ50
VCC_TX_LVDS A43
VSSA_DAC_BGB32
VSSA_LVDSB41
VSSA_PEG_BGK49
VCC_HV_1 C40VCC_HV_2 B40
VCC_PEG_1 AD51
VCCA_SM_10AT18VCCA_SM_11AT17VCCA_SM_NCTF_1AR17VCCA_SM_NCTF_2AR16
VCCD_LVDS_2H42
VCC_PEG_2 W50VCC_PEG_3 W51VCC_PEG_4 V49VCC_PEG_5 V50
VCC_AXD_NCTF AR29
VCC_AXD_4 AT29
VCC_AXD_6 AT30
VCC_AXD_1 AT23
L49MBK1608121YZF_0603GM@
1 2
C530
0.1U_0402_16V4Z
1
2
L41MBK1608121YZF_0603
1 2
C512
0.1U_0402_16V4Z
1
2
C547
0
.
0
2
2
U
_
0
4
0
2
_
1
6
V
7
K
GM@
C556
0.47U_0603_16V4Z
C543
0.1U_0402_16V4Z
1
2
C532
22U_0805_6.3V6M@
1
2
C560
10U_0805_10V4Z
1
2
C572
0.022U_0402_16V7K
GM@
C563
10U_0805_10V4ZGM@
1
2
C540
22U_0805_6.3V6M
1
2
R4781_0603_5%
C531
0.1U_0402_16V4Z
1
2
C526
0.1U_0402_16V4Z
1
2C527
10U_0805_10V4Z
1
2
C537
22U_0805_6.3V6M
1
2
L4010U_FLC-453232-100K_0.25A_10%
1 2
C533
22U_0805_6.3V6M
1
2
C562
1U_0603_10V4ZGM@
R479 0_0603_5%
R488
0_0402_5%PM@
R482
0_0402_5%PM@
C541
1U_0603_10V4Z@
R475 0_0805_5%1 2
L46MBK1608121YZF_0603GM@
1 2
C522
22U_0805_6.3V6M
1
2
R572 0_0402_5%GM@
C546
0.1U_0402_16V4ZGM@
1
2
C528
1U_0603_10V4Z
R485
0_0402_5%PM@
C561
10U_0805_10V4Z@
1
2
C689
10U_0805_10V4ZPM@
1
2
C570
0.1U_0402_16V4Z
1
2
C518
0.47U_0603_16V4Z
R481
0_0402_5%PM@
C534
4.7U_0805_10V4Z
+C519
470U_D2_2.5VMR12
1
2
C524
1U_0603_10V4Z
R476 0_0402_5%GM@
L54MBK1608121YZF_0603GM@
1 2
C564
0.1U_0402_16V4ZGM@
1
2
C542
1U_0603_10V4Z@
R473 0_0603_5%
L39MBK1608121YZF_0603
1 2
C553
0
.
0
2
2
U
_
0
4
0
2
_
1
6
V
7
K
GM@
C565
0.022U_0402_16V7KGM@
R477
0_0402_5%PM@
C511
22U_0805_6.3V6M
1
2
R472 0_0603_5%
C535
1U_0603_10V4Z
C569
0.022U_0402_16V7KGM@
C53910U_0805_10V4Z
1 2
C548
0.1U_0402_16V4Z
1
2
C513
0.1U_0402_16V4Z
1
2
L4210U_FLC-453232-100K_0.25A_10%
1 2
C538
0.1U_0402_16V4Z
1
2
R720 0_0805_5%1 2
C52910U_0805_10V4Z
12
C521
0.1U_0402_16V4Z
1
2
C557
0.47U_0603_16V4Z
+C544
220U_D2_2VMR15GM@
1
2
R486
10_0603_5%
1 2
+C550
220U_D2_2VMR15
1
2
R484
0_0402_5%PM@
R474 1_0603_5%
C551
10U_0805_10V4Z
1
2
D41
RB751V_SOD323
2 1
R483 0_0402_5%GM@
C549
0.022U_0402_16V7K
C515
4.7U_0805_10V4Z
C566
0.1U_0402_16V4ZGM@
1
2
C558
0.47U_0603_16V4Z
C516
4.7U_0805_10V4Z
R4800_0402_5%PM@
+C510
470U_D2_2.5VMR12
1
2
C536
0.1U_0402_16V4ZGM@
1
2
L52MBK1608121YZF_0603GM@
1 2
C545
1000P_0402_50V7KGM@
1
2
C554
0.1U_0402_16V4Z
1
2
+C514
330U_D2E_2.5VM
1
2
R5730_0402_5%PM@
C520
0.1U_0402_16V4Z
1
2
R471
0.5_0603_1%
L44MBK1608121YZF_0603
1 2
L43MBK1608121YZF_0603
1 2
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
IFTXX M/B LA-3541P Schematic 0Crestline (7/7)-GND
B
13 52Wednesday, November 01, 2006
2006/08/18 2007/8/18Compal Electronics, Inc.
VSS
U37J
CRESTLINE_1p0PM@
VSS_199C46VSS_200C50VSS_201C7VSS_202D13VSS_203D24VSS_204D3VSS_205D32VSS_206D39VSS_207D45VSS_208D49VSS_209E10VSS_210E16VSS_211E24VSS_212E28VSS_213E32VSS_214E47VSS_215F19VSS_216F36VSS_217F4VSS_218F40VSS_219F50VSS_220G1VSS_221G13VSS_222G16VSS_223G19VSS_224G24VSS_225G28VSS_226G29VSS_227G33VSS_228G42VSS_229G45VSS_230G48VSS_231G8VSS_232H24VSS_233H28VSS_234H4VSS_235H45VSS_236J11VSS_237J16VSS_238J2VSS_239J24VSS_240J28VSS_241J33VSS_242J35VSS_243J39
VSS_245K12VSS_246K47VSS_247K8VSS_248L1VSS_249L17VSS_250L20VSS_251L24VSS_252L28VSS_253L3VSS_254L33VSS_255L49VSS_256M28VSS_257M42VSS_258M46VSS_259M49VSS_260M5VSS_261M50VSS_262M9VSS_263N11VSS_264N14VSS_265N17VSS_266N29VSS_267N32VSS_268N36VSS_269N39VSS_270N44VSS_271N49VSS_272N7VSS_273P19VSS_274P2VSS_275P23VSS_276P3VSS_277P50VSS_278R49VSS_279T39VSS_280T43VSS_281T47VSS_282U41VSS_283U45VSS_284U50
VSS_287 W11VSS_288 W39VSS_289 W43VSS_290 W47VSS_291 W5VSS_292 W7VSS_293 Y13VSS_294 Y2VSS_295 Y41
VSS_285V2VSS_286V3
VSS_296 Y45VSS_297 Y49VSS_298 Y5VSS_299 Y50VSS_300 Y11VSS_301 P29VSS_302 T29VSS_303 T31VSS_304 T33VSS_305 R28
VSS_306 AA32VSS_307 AB32VSS_308 AD32VSS_309 AF28VSS_310 AF29VSS_311 AT27VSS_312 AV25VSS_313 H50
VSS
U37I
CRESTLINE_1p0PM@
VSS_1A13
VSS_198 C41
VSS_2A15VSS_3A17VSS_4A24VSS_5AA21VSS_6AA24VSS_7AA29VSS_8AB20VSS_9AB23VSS_10AB26VSS_11AB28VSS_12AB31VSS_13AC10VSS_14AC13VSS_15AC3VSS_16AC39VSS_17AC43
VSS_19AD1VSS_20AD21VSS_21AD26VSS_22AD29VSS_23AD3VSS_24AD41VSS_25AD45VSS_26AD49VSS_27AD5VSS_28AD50VSS_29AD8VSS_30AE10VSS_31AE14VSS_32AE6VSS_33AF20VSS_34AF23VSS_35AF24VSS_36AF31VSS_37AG2VSS_38AG38VSS_39AG43VSS_40AG47VSS_41AG50VSS_42AH3VSS_43AH40VSS_44AH41VSS_45AH7VSS_46AH9VSS_47AJ11VSS_48AJ13VSS_49AJ21VSS_50AJ24VSS_51AJ29VSS_52AJ32VSS_53AJ43VSS_54AJ45VSS_55AJ49VSS_56AK20VSS_57AK21VSS_58AK26VSS_59AK28VSS_60AK31VSS_61AK51VSS_62AL1VSS_63AM11VSS_64AM13VSS_65AM3VSS_66AM4VSS_67AM41VSS_68AM45VSS_69AN1VSS_70AN38VSS_71AN39VSS_72AN43VSS_73AN5VSS_74AN7VSS_75AP4VSS_76AP48VSS_77AP50VSS_78AR11VSS_79AR2VSS_80AR39VSS_81AR44VSS_82AR47VSS_83AR7VSS_84AT10VSS_85AT14VSS_86AT41VSS_87AT49
VSS_97AW1
VSS_100 AW24VSS_101 AW29VSS_102 AW32VSS_103 AW5VSS_104 AW7VSS_105 AY10VSS_106 AY24VSS_107 AY37VSS_108 AY42VSS_109 AY43VSS_110 AY45VSS_111 AY47VSS_112 AY50VSS_113 B10VSS_114 B20VSS_115 B24VSS_116 B29VSS_117 B30VSS_118 B35VSS_119 B38VSS_120 B43VSS_121 B46VSS_122 B5VSS_123 B8VSS_124 BA1VSS_125 BA17VSS_126 BA18VSS_127 BA2VSS_128 BA24VSS_129 BB12VSS_130 BB25VSS_131 BB40VSS_132 BB44VSS_133 BB49VSS_134 BB8VSS_135 BC16VSS_136 BC24VSS_137 BC25VSS_138 BC36VSS_139 BC40VSS_140 BC51VSS_141 BD13VSS_142 BD2VSS_143 BD28VSS_144 BD45VSS_145 BD48VSS_146 BD5VSS_147 BE1VSS_148 BE19VSS_149 BE23VSS_150 BE30VSS_151 BE42VSS_152 BE51VSS_153 BE8VSS_154 BF12VSS_155 BF16VSS_156 BF36VSS_157 BG19VSS_158 BG2VSS_159 BG24VSS_160 BG29VSS_161 BG39VSS_162 BG48VSS_163 BG5VSS_164 BG51VSS_165 BH17VSS_166 BH30VSS_167 BH44VSS_168 BH46VSS_169 BH8VSS_170 BJ11VSS_171 BJ13VSS_172 BJ38VSS_173 BJ4VSS_174 BJ42VSS_175 BJ46VSS_176 BK15VSS_177 BK17VSS_178 BK25VSS_179 BK29
VSS_88AU1VSS_89AU23VSS_90AU29VSS_91AU3VSS_92AU36VSS_93AU49VSS_94AU51VSS_95AV39VSS_96AV48
VSS_99AW16VSS_98AW12
VSS_180 BK36
VSS_182 BK44
VSS_184 BK8
VSS_186 BL13
VSS_188 BL22
VSS_18AC47
VSS_191 C12
VSS_193 C19
VSS_195 C29
VSS_197 C36
VSS_181 BK40
VSS_183 BK6
VSS_185 BL11
VSS_187 BL19
VSS_189 BL37VSS_190 BL47
VSS_192 C16
VSS_194 C28
VSS_196 C33
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDRA_SMA[0..13]
DDRA_SDM[0..7]
DDRA_SDQ[0..63]
DDRA_SMA3
DDRA_SMA2
DDRA_SMA6
DDRA_SMA10
DDRA_SMA12
DDRA_SMA8
DDRA_SMA11
DDRA_SBS1
DDRA_SWE#
DDRA_SMA13DDRA_ODT0
DDRA_CKE0
DDRA_SCS1#
DDRA_SCS0#
EC_RX_P80_CLK
DDRA_SDM5
DDRA_SMA10
DDRA_SDQ8
DDRA_SDQ55
DDRA_SDM6
DDRA_SDQ29
DDRA_SDQ12
DDRA_SDQ4
DDRA_SDM7
DDRA_SDQ48
DDRA_SDQS4
DDRA_SBS0
DDRA_SMA3
DDRA_SDQ0
DDRA_SDQ39
DDRA_SDQ32
DDRA_SMA12
DDRA_SDQS2#
DDRA_SDQS0#
DDRA_SDQ58
DDRA_SDQ56
DDRA_SDQ33
DDRA_SCS1#
DDRA_SMA5
DDRA_SDQ19
DDRA_SDQ62
DDRA_SDQ54
DDRA_SDM4
DDRA_SDQ21
DDRA_SDQ15
DDRA_SDQ57
EC_RX_P80_CLK_R
DDRA_SMA1
DDRA_SDQ53
DDRA_SDQ14
DDRA_SDM0
DDRA_SDQ5
DDRA_SDQ59
DDRA_SDQS4#
DDRA_SMA8
DDRA_SDQ25
DDRA_SDQ38
DDRA_SDQ31
DDRA_SDQ28
DDRA_SDM2
DDRA_SDQ7
DDRA_SDQ49
DDRA_SDQS0
DDRA_SDQ1
DDRA_SDQS7
DDRA_SCS0#
D_CK_SDATADDRA_SDQ63
DDRA_SDQ61
DDRA_SMA6
DDRA_SDQ6
D_CK_SCLK
DDRA_SDQS6#
DDRA_SDQ43
EC_RX_P80_CLK
DDRA_SDQ27
DDRA_SDQS1
DDRA_SDQ9
DDRA_SDQ60
DDRA_SDQ52
DDRA_ODT0
DDRA_SDQ23
DDRA_SDQ3
DDRA_SDQ37
DDRA_SMA13
DDRA_SMA14
DDRA_SDQ30
DDRA_SDQS3#
DDRA_SDQ40
DDRA_SDQ16
DDRA_SDQ2
DDRA_SDQS5
DDRA_SMA11
DDRA_SWE#
DDRA_SMA9
DDRA_SDQ17
DDRA_SDQ10
DDRA_SDQ46
DDRA_SDQ45
DDRA_SRAS#
DDRA_SMA0
DDRA_SDQS3
DDRA_SDQ20
DDRA_SDQ13
DDRA_SDQ42
DDRA_SDQ35
DDRA_SBS2
DDRA_SDQS1#
DDRA_SDQ22
DDRA_ODT1
DDRA_SDQS5#
DDRA_SDQ36
DDRA_SBS1
DDRA_SMA7
DDRA_SDQ24
DDRA_SDQ18
DDRA_SDQS7#
DDRA_SMA4
DDRA_SDM1
DDRA_SDQS6
DDRA_SDQ41
DDRA_CKE0
DDRA_SDQ26
EC_TX_P80_DATADDRA_SDM3
DDRA_SDQS2
DDRA_SDQ47
DDRA_SDQ44
DDRA_SMA2
DDRA_CKE1
DDRA_SDQ51DDRA_SDQ50
DDRA_SDQ34
DDRA_SCAS#
DDRA_SDQ11
DDRA_SBS2
DDRA_SMA9
DDRA_SMA5
DDRA_SMA1
DDRA_SBS0
DDRA_SCAS#
DDRA_ODT1
DDRA_SMA14
DDRA_SMA7
DDRA_SMA4
DDRA_SMA0
DDRA_SRAS#
DDRB_SMA14
DDRA_CKE1
DDRA_SCAS#
DDRA_SWE#
DDRA_SCS1#
DDRA_CKE0
DDRA_SBS0
DDRA_CLK0# DDRA_CLK0
DDRA_CLK1# DDRA_CLK1
DDRA_SCS0# DDRA_SRAS# DDRA_SBS1
DDRA_SDQS1
DDRA_SDQS2
DDRA_SDQS3
DDRA_SDQS4
DDRA_SDQS5#
DDRA_SDQS6
DDRA_SDQS0
DDRA_SDQS1#
DDRA_SDQS2#
DDRA_SDQS4#
DDRA_SDQS6#
DDRA_SDQS0#
DDRA_SDQS3#
DDRA_SDQS5
DDRA_SDQS7# DDRA_SDQS7
DDRA_ODT1
DDRA_ODT0
DDRA_CKE1
DDRA_SDQ[0..63]
DDRA_SDM[0..7]
DDRA_SMA[0..13]
D_CK_SDATAD_CK_SCLK
DDRA_SBS2
PM_EXTTS#0
EC_RX_P80_CLK
EC_TX_P80_DATA
EC_RX_P80_CLK_R
DDRA_SMA14
DDRB_SMA14
+1.8V +1.8V
+3VS
+DIMM_VREF
+0.9VS
+1.8V
+1.8V
+1.8V
+0.9VS
+0.9VS
+0.9VS
+3VS
+DIMM_VREF
+DIMM_VREF
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
IFTXX M/B LA-3541P Schematic 0DDRII-SODIMM0
B
14 52Wednesday, November 01, 2006
2006/08/18 2007/8/18Compal Electronics, Inc.
DIMM0 STD H:5.2mm (BOT)Change PCB Footprint
20mils
9/25 Change DIMM0 to SP070004Z00 (HBL50)
95.10.5 modify
Layout Note:Place one cap close to every 2 pullup resistors terminated to +0.9VS
Layout Note:Place near JP35
Layout Note:Place these resistorclosely JP35,alltrace length Max=1.5"
JP35
P-TWO_A5652C-A0G16
VREF1VSS3DQ05DQ17VSS9DQS0#11DQS013VSS15DQ217DQ319VSS21DQ823DQ925VSS27DQS1#29DQS131VSS33DQ1035DQ1137VSS39
VSS 2DQ4 4DQ5 6VSS 8DM0 10VSS 12DQ6 14DQ7 16VSS 18
DQ12 20DQ13 22
VSS 24DM1 26VSS 28CK0 30
CK0# 32VSS 34
DQ14 36DQ15 38
VSS 40
VSS41DQ1643DQ1745VSS47DQS2#49DQS251VSS53DQ1855DQ1957VSS59DQ2461DQ2563VSS65DM367NC69VSS71DQ2673DQ2775VSS77CKE079VDD81NC83BA285VDD87A1289A991A893VDD95A597A399A1101VDD103A10/AP105BA0107WE#109VDD111CAS#113NC/S1#115VDD117NC/ODT1119VSS121DQ32123DQ33125VSS127DQS4#129DQS4131VSS133DQ34135DQ35137VSS139DQ40141DQ41143VSS145DM5147VSS149DQ42151DQ43153VSS155DQ48157DQ49159VSS161NC,TEST163VSS165DQS6#167DQS6169VSS171DQ50173DQ51175VSS177DQ56179DQ57181VSS183DM7185VSS187DQ58189DQ59191VSS193SDA195SCL197VDDSPD199
VSS 42DQ20 44DQ21 46
VSS 48NC 50
DM2 52VSS 54
DQ22 56DQ23 58
VSS 60DQ28 62DQ29 64
VSS 66DQS3# 68
DQS3 70VSS 72
DQ30 74DQ31 76
VSS 78NC/CKE1 80
VDD 82NC/A15 84NC/A14 86
VDD 88A11 90
A7 92A6 94
VDD 96A4 98A2 100A0 102
VDD 104BA1 106
RAS# 108S0# 110
VDD 112ODT0 114
NC/A13 116VDD 118
NC 120VSS 122
DQ36 124DQ37 126
VSS 128DM4 130VSS 132
DQ38 134DQ39 136
VSS 138DQ44 140DQ45 142
VSS 144DQS5# 146
DQS5 148VSS 150
DQ46 152DQ47 154
VSS 156DQ52 158DQ53 160
VSS 162CK1 164
CK1# 166VSS 168DM6 170VSS 172
DQ54 174DQ55 176
VSS 178DQ60 180DQ61 182
VSS 184DQS7# 186
DQS7 188VSS 190
DQ62 192DQ63 194
VSS 196SAO 198SA1 200
C484
2.2U_0805_10V6K
1
2
C487
2.2U_0805_10V6K
1
2
C488
2.2U_0805_10V6K
1
2
C507
0.1U_0402_16V4Z
1
2
C497
0.1U_0402_16V4Z
1
2
C502
0.1U_0402_16V4Z
1
2
C485
220P_0402_50V7K@
1
2
C491
0.1U_0402_16V4Z
1
2
C500
0.1U_0402_16V4Z
1
2
C495
0.1U_0402_16V4Z
1
2
R469 10K_0402_5% 1 2R470 10K_0402_5% 1 2
C483
0.1U_0402_16V4Z
1
2
C505
0.1U_0402_16V4Z
1
2
C508
2.2U_0805_10V6K
1
2
RP40 56_0404_4P2R_5%
1 42 3
C503
0.1U_0402_16V4Z
1
2
RP44 56_0404_4P2R_5%
1 42 3
C499
0.1U_0402_16V4Z
1
2
C506
0.1U_0402_16V4Z
1
2
R466
1K_0402_1%
1
2
C490
2.2U_0805_10V6K
1
2
R749 56_0402_5%
1 2
R465
1K_0402_1%
1
2
R748 56_0402_5%
1 2
C509
0.1U_0402_16V4Z
1
2
RP48 56_0404_4P2R_5%
1 42 3
RP42 56_0404_4P2R_5%
1 42 3
C498
0.1U_0402_16V4Z
1
2
RP39 56_0404_4P2R_5%
1 42 3
C501
0.1U_0402_16V4Z
1
2
C504
0.1U_0402_16V4Z
1
2
C486
2.2U_0805_10V6K
1
2
RP51 56_0404_4P2R_5%
1 42 3
RP45 56_0404_4P2R_5%
1 42 3
RP47 56_0404_4P2R_5%
1 42 3
RP50 56_0404_4P2R_5%
1 42 3
C494
0.1U_0402_16V4Z
1
2
RP49 56_0404_4P2R_5%
1 42 3
C489
2.2U_0805_10V6K
1
2
R622 0_0402_5%
1 2
C496
0.1U_0402_16V4Z
1
2
RP46 56_0404_4P2R_5%
1 42 3
R468 0_0402_5%
1 2
C492
0.1U_0402_16V4Z
1
2
C493
0.1U_0402_16V4Z
1
2
RP43 56_0404_4P2R_5%
1 42 3
RP41 56_0404_4P2R_5%
1 42 3
-
AA
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
DDRB_SDQS1
DDRB_SDQS2
DDRB_SDQ40
DDRB_SDQS4
DDRB_SDQS6
DDRB_SDQS4#
DDRB_SDQS1#
DDRB_SDQS2#
DDRB_SDQ41
DDRB_SDQS6#
DDRB_SDQ11DDRB_SDQ10
DDRB_SDQ1DDRB_SDQ0
DDRB_SMA3
DDRB_SWE#
DDRB_SCAS#
DDRB_SMA9
DDRB_SMA5
DDRB_SMA12
DDRB_SMA10
DDRB_SMA1
DDRB_CKE0
DDRB_SCS1#
DDRB_SMA8
DDRB_SDM3
DDRB_SBS0
DDRB_SDQ25
DDRB_SDQ35DDRB_SDQ34
DDRB_SDM5
DDRB_SDQ18
DDRB_SDQ49DDRB_SDQ48
DDRB_SDQ9DDRB_SDQ8
DDRB_SDQ19
DDRB_SDM7
DDRB_SDQ43
DDRB_ODT1
DDRB_SDQ42
DDRB_SDQS0#DDRB_SDQS0
DDRB_SDQ2
DDRB_SDQ33DDRB_SDQ32
DDRB_SDQ56
DDRB_SDQ3
DDRB_SDQ37
DDRB_SDQ7DDRB_SDQ6
DDRB_SDM6
DDRB_SDM1
DDRB_SRAS#
DDRB_SMA7
DDRB_SMA2DDRB_SMA0
DDRB_SMA6
DDRB_SMA4
DDRB_SMA11
DDRB_SCS0#
DDRB_CKE1
DDRB_SBS1
DDRB_SMA13
DDRB_SDQ54
DDRB_SDQS5
DDRB_SDQ55
DDRB_SDQ44
DDRB_SDQS5#
DDRB_SDQ45
DDRB_SDQ14DDRB_SDQ15
DDRB_SDQS7
DDRB_SDM0
DDRB_SDQS7#
DDRB_SDQ62DDRB_SDQ63
DDRB_ODT0
DDRB_SDM2
DDRB_SDQ60
DDRB_SDQ52DDRB_SDQ53
DDRB_SDQ22DDRB_SDQ23
DDRB_SDQ12DDRB_SDQ13
DDRB_SDQS3DDRB_SDQS3#
DDRB_SDM4
DDRB_SDQ46DDRB_SDQ47
DDRB_SDQ36
DDRB_SDQ[0..63]
DDRB_SMA[0..13]
DDRB_SDM[0..7]
D_CK_SCLKD_CK_SDATA
DDRB_SCS0#
DDRB_SBS1
DDRB_SMA2
DDRB_SMA6
DDRB_SMA11
DDRB_SMA13
DDRB_SBS2
DDRB_CKE0
DDRB_SWE#
DDRB_SCS1#
DDRB_SMA3
DDRB_SMA10
DDRB_SMA12
DDRB_SMA8DDRB_SMA5
DDRB_SDQ5DDRB_SDQ4
DDRB_SDQ16DDRB_SDQ21DDRB_SDQ17DDRB_SDQ20
DDRB_SDQ29DDRB_SDQ24
DDRB_SDQ31
DDRB_SDQ28
DDRB_SDQ27DDRB_SDQ26 DDRB_SDQ30
DDRB_SDQ39DDRB_SDQ38
DDRB_SDQ51DDRB_SDQ50
DDRB_SDQ61DDRB_SDQ57
DDRB_SDQ58DDRB_SDQ59
DDRB_SMA14
EC_TX_P80_DATA
EC_RX_P80_CLK
EC_RX_P80_CLK_R
DDRB_SBS2
DDRB_SMA9
DDRB_SMA1
DDRB_SBS0
DDRB_SCAS#
DDRB_ODT1
DDRB_CKE1
DDRB_SMA7
DDRB_SMA4
DDRB_SMA0
DDRB_SRAS#
DDRB_ODT0
DDRB_SCS0#
DDRB_SCS1#DDRB_SCAS#
DDRB_SWE#
DDRB_CKE0
DDRB_SBS0
DDRB_SDQS1
DDRB_SDQS2
DDRB_SDQS0
DDRB_SDQS1#
DDRB_SDQS2#
DDRB_SDQS0#
DDRB_SDQS4
DDRB_SDQS6
DDRB_SDQS4#
DDRB_ODT1
DDRB_SDQS6#
DDRB_SDQS5# DDRB_SDQS5
DDRB_ODT0
DDRB_SDQS7# DDRB_SDQS7
DDRB_SRAS# DDRB_SBS1
DDRB_SDQS3 DDRB_SDQS3#
DDRB_CKE1
DDRB_SMA[0..13]
DDRB_SDM[0..7]
DDRB_SDQ[0..63]
D_CK_SDATAD_CK_SCLK
DDRB_SBS2
PM_EXTTS#1
EC_TX_P80_DATA
EC_RX_P80_CLK
EC_RX_P80_CLK_R
DDRB_SMA14
DDRB_CLK1# DDRB_CLK1
DDRB_CLK0# DDRB_CLK0
+1.8V+1.8V
+3VS
+DIMM_VREF
+0.9VS
+DIMM_VREF
+1.8V
+1.8V
+0.9VS
+0.9VS
+0.9VS
+3VS
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
IFTXX M/B LA-3541P Schematic 0DDRII-SODIMM1
B
15 52Wednesday, November 01, 2006
2006/08/18 2007/8/18Compal Electronics, Inc.
DIMM1 STD H:9.2mm (BOT)
DDRB_CLK0?
DDRB_CLK1?
9/25 Change DIMM1 to SP070006F00
Layout Note:Place one cap close to every 2 pullup resistors terminated to +0.9VS
Layout Note:Place near JP34
Layout Note:Place these resistorclosely JP35,alltrace length Max=1.5"
RP32 56_0404_4P2R_5%
1 42 3
C481
0.1U_0402_16V4Z
1
2
C480
0.1U_0402_16V4Z
1
2
RP28 56_0404_4P2R_5%
1 42 3
C469
0.1U_0402_16V4Z
1
2
C461
2.2U_0805_10V6K
1
2
RP31 56_0404_4P2R_5%
1 42 3
C471
0.1U_0402_16V4Z
1
2
C478
0.1U_0402_16V4Z
1
2
JP34