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Informatique Industrielle
Insa-GE, DUT+3
Thomas Grenier,
Dominique Tournier.
Microcontrleurs
Famille PIC 16
Objectifs de ce cours
1 Prsenter la structure gnrale desordinateurs et les concepts associs
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Organisation de la formation
En DUT+3 : 15h Cours (7h) TD (8h) Examen (devoir de 2h)
Thme: matriel et/ou logiciel Documents autoriss
En 4GE (2ime semestre)
Un TP sur les interruptions (4h) Question TP (dans lexamen du module IF3) Projets
Plan du cours
I. Gnralits Structure lmentaire dun calculateur
L i t l PIC16
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I Description globale
Schma fonctionnel dun systmeinformatique
Ordinateur
Programme
Donnesen entre
Donnesen sortie
Actions
I Description globale
Definition : Un systme informatique est unsystme que fait interagir du logiciel ,(Software) sur du matriel (Hardware),en vue d'une finalit code dans le logiciel
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I Description globale
a) L'ordinateur : lment matriel central, il comporteessentiellement- un calculateur et sa mmoire, un ensemble clavier, cran, despriphriques informatiques conventionnels tels que : units desauvegarde, units d'dition, units de communication,- des priphriques spcialiss : carte d'acquisition de son,
d'images, des dispositifs de contrle de processus industriels ...b) Le programme : lment logiciel central, il indique l'ordinateur- le type de traitement effectuer sur les donnes d'entre,- les donnes fournir et les actions entreprendre en sortie.c) Les donnes en entre : Elles peuvent tre d'origines
diverses- ensemble de nombres traiter issus de la gestion bancaire, dutraitement des signaux d'images, des bases de donnes ....- informations en provenance de capteurs (temprature,hygromtrie...)- donnes issues du clavier, (dialogue homme machine)
I Description globale
d) Les donnes en sortie :
Elles reprsentent le rsultat attendu du traitementspcifi par le programme des donnes en entre.e) Actions :
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I Description globale
Exemple: systme microcontrleur
I Description globale
II Architecture Description de Von Neumann
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II Architecture de Von Neumann
Historique : Cette architecture a t introduite dans les annes 50
l'Institute for Advanced Study (IAS) de Princeton.
Von Neumann a donn son nom l'architecture de VonNeumann utilise dans la quasi totalit des ordinateurs
modernes, l'apport d'autres collaborateurs de l'EDVAC enest par consquent grandement minimis (on citera J.Presper Eckert et John William Mauchly parmi d'autres).Cela est d au fait qu'il est, en 1944, le rapporteur destravaux pionniers en la matire (First Draft of a Report onthe EDVAC).
Le modle de calculateur programme auquel son nomreste attach et qu'il attribuait lui-mme Turing, possdeune unique mmoire qui sert conserver les logicielset les donnes. Ce modle, extrmement innovant pourl'poque, est la base de la conception de nombred'ordinateurs mais a fortement volu depuis.
II Architecture de Von Neumann
Larchitecture de von Neumann dcompose lordinateur en 4 units distinctes 3 bus (outre les liaisons externes)
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II Architecture de Von Neumann
Unit Arithmtique et Logique (UAL)o effectue les oprations arithmtiques ou logiques lmentaires(+, -, *, /, ; ET, OU, complmentation)o une batterie de registres gnraux permet de stoker temporairementles oprandes et rsultats en cours. Laccumulateurdsigne le registre
stockant lune des deux oprandes et le rsultat (A, AC, ACC, W).
Reprsentation
standard
II Architecture de Von Neumann
Unit Mmoire2 types de mmoires fonctionnellement et
technologiquement diffrents:
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II Architecture de Von Neumann
Unit de contrle (UC)o chef d'orchestre de l'ensemble des units
o ralise 3 taches:
lire une instruction du programme en cours,
la dcoder et pointer vers la suivante*,
faire excuter linstruction par lesdiffrentes units
grer les vnement exceptionnels
susceptible d'intervenir de manireimpromptus
*LUC contient souvent un dispositif d'incrmentation du PC, vitant ainside surcharger et de ralentir lUAL
II Architecture de Von Neumann
Unit de contrle (UC)o comporte 2 registres principaux :
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II Architecture de Von Neumann
Bus dAdresses (Address Bus)o voie de communication unidirectionnelle
seuls l'UCou l'UAL peuvent ecrire seuls les units mmoires ou dE/S peuvent lire
Remarques: L'UCpositionne l'adresse de l'instruction traiter, et gnralement l'UAL qui contient(soit directement soit l'issu d'un calcul)l'adresse d'un oprande en mmoire ou enE/S.
La taille de ce bus TAB en bit (nombre de filsdeAB) reprsente la capacit maximale Cmd'adressage du calculateur, suivant la relation
ABT
mC 2Bus dadresses
Qq ex.
II Architecture de Von Neumann
Bus de Contrle (Control Bus) Permet lUC de synchroniser et de commander lesautres units (slection dadresse (Mem), selectiondune opration (UAL) activation/dsactivation des
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II Architecture de Von Neumann
Evolution de larchitecture :sparation des espaces mmoiresprogramme et donnes
architecture Harvard
Architecture Harvard :- mmoires programme et donnes distinctes,- bus programme et donnes distincts,
- transfre simultan des instructions excuter et des donnes.- modle plus rapide que Von Neumann,- structure interne plus complexe complexitinterne de la structure.
II Architecture de Von Neumann
III Communication par bus
grer les accs aux bus bidirectionnels
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III Communication par bus
1- Reprsentationplan mmoire
Exemple:bus dadresse 16 bits, bus de donnes 8 bits
adresses donnes units
0x0000
0x0002
0x0001
...
...
0xABCD
0xABCE
0xFFFF
ROM
RAM
E/Sdonnes 8 bits
adresses 16 bits
0xA2
CB: active et dsactive les units,slectionne lecture ou criture
III Communication par bus
2- Logique 3 tats
Communication bidirectionnelle :Comment dsactiver des units ?
Logique 3 tatsO d 3
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III Communication par bus
2- Logique 3 tats
A chaque instant, au plus une unit doit tre active en criture sur un busbidirectionnel, sinon: risque de court circuit!
gnralement, en plus de lUC: une seule unit active
Unit A
Unit B
Un bit du busde donnesUnit C
III Communication par bus
2- Logique 3 tats
Le bus de contrle gre lactivation des units (ou circuits)
Bus de contrle
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III Communication par bus
3- Exemple
Bus de donnes : 8 bitsBus dadresses : 12 bitsRAM : 1 koROM : 1 koE/S : 1 ko
Activation/dsactivation
Bus dadresses (12bits)
1
IV Diversit et applications
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IV Diversit et applications
Caractristiques dun microcontrleur Priphriques: CAN/CNA(PWM), ports dentre/sortie, ports sries
(protocole I2C, usb), compteur, IRQ, Mmoires
programme ROM (qq ko qq 100ko) donnes RAM (qq ko qq 100ko) donnes non volatile (qq ko qq Mo)
Registres largeurs: 8, 16, 32 bits type (oprande): entiers, virgule fixe/flottantes
Fonctionnalit internes instructions: frq. excution, nombres et types (maths,
spcialises) compteurs/timers, Watch Dog, dbogage
Alimentation plage de tension de fonctionnement consommation lectrique
IV Diversit et applications
Fabricants et familles Intel (80C51) Motorola (Srie 68HC11)
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IV Diversit et applications
interfaage ? microcontrleur !!
Utilisation en augmentation miniaturisation des cartes systme autonome: alimentation (faible consommation),
communication, puissances de calcul diverses: mise en forme de signal,
pilotage dautomate applications complexes aveccalcul
Programme
Structuration en couches logiciellesNiveau du langage
L5: Lang. C
Langages volus
et applications
Compilateur C
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Plan
I. GnralitsII. Les microcontrleurs PIC
I. Familles PICsII. Caractristiques des PICs
Mmoire, E/S standards et fonctionnalits intgresIII. Architecture PIC16
Structure, Registres, Mmoires RAM / ROM
III. Jeu dinstructions des PIC16IV. Ports dentres/sorties des PIC16V. Fonctionnalits standards des PIC16VI. Considrations techniques
I PICs
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I Famille PICs: intgration
PIC 16F87x
I Familles PICS
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I Familles PICs: identification
II Caractristiques
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II Caractristiques
II Caractristiques
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II Caractristiques, rsum
Reduce Instruction Set Computer (RISC): PIC16 35 instructions Temps constant dexcution des instructions (1 ou 2 cycles instruction) 1 type de mmoire programme / PIC : ROM, EEPROM, FLASH 1 type de mmoire donnes / PIC : RAM
et 1 type de mmoire donnes optionnel: EEPROM
III Architecture PIC16
Famille choisie : PIC16 Microcontrleurs utiliss
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III Architecture:
Boitier PIC 16F877
III Architecture:
Caractristiques PIC 16F87x
III
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Architecture
PIC16
Pic 16 F 877
III Architecture (Harvard) des PIC16
Tailles des bus
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III Architecture des PIC16
Registres Accumulateur: W (8 bits) Pointeur programme: PC (13 bits) Registre dinstruction: Instruction Reg (14 bits)
Drapeaux dtat UAL : 3 (Z, DC, C) Adressage indirect :
adresse: FSR(8bits), valeur: INDF (8bits) Zone SFR: Special Function Registers
Paramtrer et accder aux priphriques et
fonctionnalits intgrs du PIC En RAM !
III Architecture Mmoire
Memoire programme ROM (PIC 16F877) Flash 8k mots (1 mot = 14bits)
III A hit t
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III Architecture
Mmoire ROM
4 pages de programme Aprs un Reset
Reset PC = 0000h Interruption
IRQ PC = 0004h 1 seul vecteur Gestion de la source dIRQ
par programme! (TP 4GE) Pile: 8 niveaux
Rserve PC Empilage/dpilage de PC
auto. par le microcontrleur Empilage/dpilage des autres
registres par programme !!!(TP 4GE)
III Architecture Mmoire ROM
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III Architecture Mmoire RAM
SFR: SpecialFunctionRegisters
Accs fonctionnalitsdu microcontrleur
GPR: GeneralPurpose
RegistersVariables utilisateur
III Architecture
Mmoire RAM
Problme Bus adresse donnes : 9 bits Nb bits adressage / instruction : 7 bits
III Architecture
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SFR
Dtails: cf. doc technique
III Architecture SFR : bank
Exemple daccs aux Bank
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III Architecture: qq registres SFR
Plan
II. Les microcontrleurs PIC16III. Jeu dinstructions des PIC16
I Les types dinstruction
I Instructions des PIC16
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I Instructions des PIC16
PIC16: 35 instructions 3 catgories dinstructions
Manipulation de valeurs littrales(constantes)
Manipulation de variables en RAM(SFR ou GPR)
Manipulation de bit(mise 1 ou 0 dun bit)
Support : Listes des instructions et dtails de fonctionnement(issu du document constructeur PIC16 User Guide)
I - Format
des instructions
f : adresse en mmoire donnes
I Instructions des PIC16
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I Instructions des PIC16
manipulation de constante
k: valeur constante ou littrale de 8 ou 11 bits
Ex: addlw2 ; W + 2 W
I Instructions des PIC16
manipulation de bit
I Instructions des PIC16
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I Instructions des PIC16
manipulation de variables RAM
f: adresse 7 bits dune donnes en RAM (SFR ou GPR)d: destination du rsultat 0 ou W W
1 ou f f (mme adresse en RAM)
I Instructions des PIC16
manipulation de variables RAM
I Instructions des PIC16
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I Instructions des PIC16,
exemples simples
1- Mettre 0 dans W
2- Charger la valeur 20h dans W
3- Charger la valeur de W ladresse 020h
4- Charger la valeur ladresse 020h dans W
5- Mettre 1 le bit 5 de la valeur ladresse 003h
6- dcrmenter la valeur ladresse 020h,et stoker le rsultat la mme adresse
7- dcrmenter la valeur ladresse 020h,et stoker le rsultat dans W
8- dcrmenter la valeur ladresse 020h,et stoker le rsultat ladresse 021h
II Adressage
PIC16: 3 types adressages des valeurs Immdiat (literal)
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II Adressage immdiat
Valeur (littrale) passe linstruction Bases des valeurs (reconnues par mpasm)
.100 d100
h9f
2b- Charger la valeur 20 dans W ?
II Adressage direct
Adresse contenant une valeur Utilisation dquivalences
adresse nom du registre
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II Adressage indirect
Adresse dune adresse contenant une valeur Utiliser pour les tableaux Pointeur Accs rapide une autre banque
PIC16 utilisation de 2 registresFSR : adresse de la donne
File Select Register
INDF : valeur stocke ladresse contenudans FSRINDirect File
char a = 5;
char *FSR =&a;
*FSR = 6;
INDF
II Adressage indirect, exemple
020h FSRINDF = ??
Exo: Dterminer INDF si
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II Adressage indirect, et les bank?
FSR : 8 bits, bus dadresse RAM : 9 bits
IRP : bit 7 de STATUSRP0, RP1 : bit 5 et 6de STATUS
III - Cycle instruction
1 cycle instruction (Tcy) est dcomposen 4 tapes Q1 Q4
Q1: Dcodage dinstruction (ou nop)
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III - Cycle instruction
Une instruction sexcute entirementen 2 cycles instructions 1ier Tcy : fetch (gestion de PC, chargement
instruction dans Instruction Reg)
2ime Tcy : dcodage et excution
Pipelining : traitement en parallledu fetch et du dcodage-excution !
III - Cycle instruction
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IV Les Instructions en dtails
Cf. document annexe
V Accs aux mmoires
RAM en lecture / criture Pas de problmes
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V Accs lEEPROM et la ROM
Accs via des SFR EEPROM et ROM : mme mthode 6 registres utiliss
EEDATAH:EEDATA donne EEADRH:EEADR adresse lire/crire EECON1 registre de contrle et de
paramtrage des accs EECON2 registre de contrle en criture
(squences de valeur pour lcriture)
V EECON1(adr : 18Ch)
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V Lire en EEPROM
1. Ecrire dans EEADR ladresse lire2. Choisir un accs lEEPROM
0 EECON1
3. Dmarrer la lecture1 EECON1
4. Lire la valeur EEDATA
Code associ :
V Ecrire en EEPROM (sans IRQ)
1. Vrifier quune criture ne soit pas en cours2. Choisir ladresse EEPROM et la valeur crire
Ch i i lEEPROM
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V Ecrire en EEPROM, code
V Lire et Ecrire en mmoire
programme
Possibilit de lire en ROM, 2 mthodes
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Plan
I. GnralitsII. Les microcontrleurs PIC16III. Jeu dinstructions des PIC16
IV. Ports dentres/sorties des PIC16I. Port dE/S standardsII. Port srieIII. Autres entres/sorties
V. Fonctionnalits standards des PIC16VI. Considrations techniques
Introduction
Plusieurs types d E/S Port E/S standards
Lire / crire un tat logique sur une broche Port parallle
Introduction
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Remarque:Grande diversit des fonctions dE/S
+ Beaucoup de possibilits dinterfacemais Nombre de broches limit
Multiplexage des broches: Chaque broche peut raliser plusieurs fonctions Jamais simultanment !!! Besoin de configurer les interfaces et donc
lutilisation des broches Attention aux compatibilits lectriques
(viter double utilisation dune mme broche)
I Port E/S standards (I/O Ports)
Configuration par dfaut du PIC Lire ou crire un tat logique sur une
broche
I Port E/S standards (I/O Ports)
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Bit de chaque port en lecture ou criture 3 tats lectriques possibles de la broche
0L (0V) ou 1L (Vcc) critureHaute Impdance lecture
Choix de la direction de communication !! Rle des registres SFR: TRISA, TRISB, Ltat du bit i de TRISx ( TRISx )
contrle la direction du bit i de PORTx (PORTx ):
TRISx = 0 PORTx en sortie (criture)TRISx = 1 PORTx en entre (lecture)
Exemple : TRISB = 0xFF les 8 bits du PORTB en entresTRISC = 0x0F RC7 RC4 en sorties, RC3 RC0 en entres
I Port E/S standards (I/O Ports)
SchmaValeur crire ou lire
I Port E/S standards (I/O Ports)
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Les broches des ports dE/S sontmultiplexes afinde raliser plusieursfonction
PORTC3 fonctions
I Port E/S standards
Parallel Slave Port
Port parallle esclave Port (communication) pilot par un autre
composant
II Port srie
SS
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SSP
SSP: Synchronous Serial Port SSP = BSSP (B pour Basic) ~ MSSP, M pour Master
Communication avec priphriques srieEEPROM, registres dcalage, convertisseur A/D, afficheur,
SSP opre dans les modes Serial Peripheral Interface (SPITM) Inter-Integrated Circuit (I2CTM)
Mode esclave Mode maitre ou multi maitre
Registres de paramtrages principaux SSPSTAT : status SSP SSPCON : contrle SSP
II Port srie
USART
USART: Universal Synchronous Asynchronous ReceiverTransmitter Autre nom: Serial Communication Interface (SCI)
communication avec priphriques
II Port srie, USART
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TransmissionAsyn
chrone
(Master)
Transmission
Synchrone
(Mas
ter)
III Autres ports
Entre pour dtection dvnements Interruptions Compteurs
III Autres ports:
t di t ti ?
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entres dinterruption ?
INT : mme broche que RB0 entre dinterruption externe
RB7:RB4
interruption si changement dtat dun des4 bits
Comparator Change IRQ IRQ si une tension dpasse un seuil
CCP, SSP, USART
III Autres ports:
compteur
Permet de compter des impulsions arrivant surdes broches
2 compteurs dimpulsion
III Autres ports: compteur
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TIMER0 :
OPTION_REG
0
choisir
1
choisir
III Autres ports:
capture/compare/PWM
Deux modules CCP CCP1 et CCP2
III Autres ports:
capture/compare/PWM
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capture/compare/PWM
Capture (16 bits) mmorisation de la valeur du TIMER1 (cf. prochain
cours) lapparition dun front sur une entre CCPx
Compare (16 bits) une valeur constante est compare avec celle de
TIMER1 (qui volue) quand une galit apparat une sortie CCPx peut
passer 0L ou 1L, ou rester inchange
PWM (max. 10 bits) cration dune impulsion de rapport cyclique variable
(frquence constante) il sagit dune sortie PWM La PWM est lie au TIMER2
III Autres ports:
convertisseur A/N
CAN: charge dune capacit + conversion A/N Temps dacquisition (TACQ) + temps conversion !!
~12.10-6.s + 9,5*TAD
III Autres ports:
convertisseur A/N
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convertisseur A/N
8 Entres analogiques, 1 module de conversion: Choisir lentre convertir !!!
Conversion par rapport unetension de rfrence!
III Autres ports:
convertisseur A/N
Registres ADRES : rsultat de la conversion A/N (8bits) ADCON0, ADCON1 : registres de configuration de la
III Autres ports:
comparateur de tension
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comparateur de tension
2 comparateurs analogiques disponibles 2*2 entres analogiques
Les 2 comparateurs sont indpendants Possibilit de gnrer une tension de rfrence
par le pic 8 possibilits dutilisation des 2 comparateurs
Dsactiv, indpendants, rfrence commune,multiplexage des entres
Registre CMCON : configuration et tats des comparateurs
III Autres ports: comparateur de tension
CMCON
III Autres ports:
gnrateur de tension
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gnrateur de tension
quivalent un convertisseur N/A 4 bits
Plan
I. GnralitsII. Les microcontrleurs PIC16
I Compteur / Timer
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Rle dun timer : compter !Compter un nombre dimpulsions
externes
internes (bases sur fosc) Intrt principal
lincrmentation est automatique
Utilit Comptage automatique Temporisation (trs prcise)
I Compteur / Timer
3 TIMERs disponibles sur PIC16F877 TIMER0 : 8 bits TIMER1 : 16 bits
I Compteur / Timer
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Fonctionnement dun TIMERexemple du TIMER1TM
R1H:TMR1L
Les impulsions sont comptes siT1CON = 1
0xFFFF
Le TIMER1 est bloqu siT1CON = 0
Au retour 0x0000mise 1 du bit PIR1
0x0002La valeur du comptage est stockedans TMR1H:TMR1L
(accessible en lecture et criture)
0x00010x0000
impulsion
I Compteur / Timer
Paramtrage, ex TIMER1
I Compteur / Timer, reg T1CON
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I Compteur / Timer
exemple de paramtrage
Raliser une temporisation dunemilliseconde avec le TIMER1
I Compteur / Timer
exemple temporisation 1ms
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exemple temporisation 1ms
; INIT compteurbsf STATUS, RP0 ; Bank1
clrf PIE1 ; Disable peripheral interrupts
bcf STATUS, RP0 ; Bank0
clrf PIR1 ; Clear peripheral interrupts Flags
movlw 0x10 ; Internal Clock source with 1:2 prescaler,
movwf T1CON ; Timer1 is stopped and T1 osc is disabled
movlw 0xF6movwf TMR1H ;
movlw 0x3C
movwf TMR1L ;
bsf T1CON, TMR1ON ; Timer1 starts to increment
Tempo_Wms_OVFL_WAIT:
btfss PIR1, TMR1IFgoto Tempo_Wms_OVFL_WAIT
; Timer has overflowed
bcf PIR1, TMR1IF
bcf T1CON, TMR1ON ; Timer1 stops to increment
II Interruption (IRQ),
dfinitionrap
ide
Interruption vnement produisant linterruption du programme
en cours dexcution pour excuter une routinedinterruption
II Interruption (IRQ),
PIC?
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PIC?
PIC16 : 1 vecteur reset 0x0000 lancement programme 1 seul vecteur dinterruption 0x0004
une seule routine dinterruption
PIC 16 : ~15 sources dinterruption
LA routine dinterruption doit trouver quelle est lasources (tester les registres et trouver la source)
Registres INTCON: registre principal PIR1, PIR2 : registres des IRQ des sources(1bit ou flag par source) PIE1, PIE2 : registres dactivation des IRQ pour
les sources
II Interruption (IRQ)
INTCON
II Interruption (IRQ)
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Dtails des registres associs:
II Interruption (IRQ)
INTCON
II Interruption (IRQ)
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Sauvegarde et restauration du contexte dans lISR:
II Interruption (IRQ)
temps de latence
Plan
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I. GnralitsII. Les microcontrleurs PIC16III. Jeu dinstructions des PIC16IV. Ports dentres/sorties des PIC16V. Fonctionnalits standards des PIC16VI. Considrations techniques
I. Alimentation et protection lectrique
II. OscillateurIII. Cycle instruction et pipelineIV. Solutions de dveloppement
I Alimentation et
protection lectrique
I Alimentation et
protection lectrique
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p q
Circuit RESET recommand
Temps ncessaire au PICpour dmarrer aprs un reset:
moins de 132msTemps minimal dun reset:2ms
II Oscillateur
4 modes doscillateurs disponibles: RC : Resistance/capacit
LP : Low Power Crystal
II Oscillateur
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Il est ncessaire de configurer le PIC enfonction du mode doscillateur utilis! Adresse 0x2007 en mmoire programme(zone bits de configuration )
III - Cycle instruction et pipeline
1 cycle instruction (Tcy) est dcomposen 4 tapes Q1 Q4
Q1: Dcodage dinstruction (ou nop)
III - Cycle instruction et pipeline
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Une instruction sexcute entirementen 2 cycles instructions 1ier Tcy : fetch (gestion de PC, chargement
instruction dans Instruction Reg)
2ime Tcy : dcodage et excution
Pipelining : traitement en parallledu fetch et du dcodage-excution !
III - Cycle instruction et pipeline
III - Cycle instruction supplmentaire
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Annulation du cycle fetch GOTO, CALL, RET, RETLW et RETFIE Excution dIRQ
Ajout de cycles internes Modification des valeurs TIMER (TMR0,
TMR1H:TMR1L,) 2 cycles non compts par le TIMER
IV Solutions de dveloppement
Compilateurs Assembleur: MPASM Langage C :MPLAB-C
Sommaire :
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MMIICCRROOCCOONNTTRROOLLEEUURR,, FFAAMMIILLLLEE PPIICC1166
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Section 29. Instruction Set
29.4 Q Cycle Activity
Each instruction cycle (Tcy) is comprised of four Q cycles (Q1-Q4). The Q cycle is the same asthe device oscillator cycle (TOSC). The Q cycles provide the timing/designation for the Decode,Read, Process Data, Write etc., of each instruction cycle. The following diagram shows the rela-tionship of the Q cycles to the instruction cycle.
Th f Q l th t k i t ti l (T ) b li d
PICmicro MID-RANGE MCU FAMILY
29.5 Instruction Descriptions
ADDLW Add Literal and WSyntax: [label] ADDLW k
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1997 Microchip Technology Inc. DS31029A-page 29-7
Instruction
Set
29
The four Q cycles that make up an instruction cycle (Tcy) can be generalized as:
Q1: Instruction Decode Cycle or forced No OperationQ2: Instruction Read Cycle or No OperationQ3: Process the DataQ4: Instruction Write Cycle or No Operation
Each instruction will show the detailed Q cycle operation for the instruction.
Figure 29-2: Q Cycle Activity
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Tcy1 Tcy2 Tcy3
Tosc
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DS31029A-page 29-8 1997 Microchip Technology Inc.
y [ ]
Operands: 0 k 255Operation: (W) + k W
Status Affected: C, DC, Z
Encoding: 11 111x kkkk kkkk
Description: The contents of the W register are added to the eight bit literal 'k' and the result isplaced in the W register.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal 'k'
Process
data
Write to W
register
Example1 ADDLW 0x15
Before InstructionW = 0x10
After InstructionW = 0x25
Example 2 ADDLW MYREG
Before InstructionW = 0x10
Address of MYREG = 0x37
MYREGis a symbol for a data memory locationAfter Instruction
W = 0x47
Example 3 ADDLW HIGH (LU_TABLE)
Before InstructionW = 0x10
Address of LU_TABLE = 0x9375
LU_TABLEis a label for an address in program memory
After InstructionW = 0xA3
Example 4 ADDLW MYREGBefore Instruction
W = 0x10
Address of PCL = 0x02
PCLis the symbol for the Program Counter low byte location
After InstructionW = 0x12
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Section 29. Instruction Set
ADDWF Add W and fSyntax: [ label] ADDWF f,d
Operands: 0 f 127d [0 1]
PICmicro MID-RANGE MCU FAMILY
ANDLW And Literal with WSyntax: [ label] ANDLW k
Operands: 0 k 255
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1997 Microchip Technology Inc. DS31029A-page 29-9
Instruction
Set
29
d [0,1]
Operation: (W) + (f) destination
Status Affected: C, DC, Z
Encoding: 00 0111 dfff ffff
Description: Add the contents of the W register with register 'f'. If 'd' is 0 the result is stored in theW register. If 'd' is 1 the result is stored back in register 'f'.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f'
Process
data
Write to
destination
Example 1 ADDWF FSR, 0
Before InstructionW = 0x17
FSR = 0xC2
After InstructionW = 0xD9
FSR = 0xC2
Example 2 ADDWF INDF, 1
Before InstructionW = 0x17
FSR = 0xC2Contents of Address (FSR) = 0x20
After InstructionW = 0x17
FSR = 0xC2
Contents of Address (FSR) = 0x37
Example 3 ADDWF PCL
Case 1: Before InstructionW = 0x10
PCL = 0x37
C = x
After InstructionPCL = 0x47
C = 0
Case 2: Before InstructionW = 0x10
PCL = 0xF7
PCH = 0x08
C = x
After InstructionPCL = 0x07
PCH = 0x08
C = 1
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DS31029A-page 29-10 1997 Microchip Technology Inc.
Operation: (W).AND. (k) WStatus Affected: Z
Encoding: 11 1001 kkkk kkkk
Description: The contents of W register are ANDed with the eight bit literal 'k'. The result isplaced in the W register.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read l iteral
'k'
Process
data
Write to W
register
Example 1 ANDLW 0x5F
Before InstructionW = 0xA3
After InstructionW = 0x03
; 0101 1111 (0x5F)
; 1010 0011 (0xA3)
;---------- ------
; 0000 0011 (0x03)
Example 2 ANDLW MYREG
Before InstructionW = 0xA3
Address of MYREG = 0x37
MYREGis a symbol for a data memory location
After InstructionW = 0x23
Example 3 ANDLW HIGH (LU_TABLE)
Before InstructionW = 0xA3
Address of LU_TABLE = 0x9375
LU_TABLEis a label for an address in program memory
After InstructionW = 0x83
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Section 29. Instruction Set
ANDWF AND W with fSyntax: [ label] ANDWF f,d
Operands: 0 f 127d [0 1]
PICmicro MID-RANGE MCU FAMILY
BCF Bit Clear fSyntax: [ label] BCF f,b
Operands: 0 f 1270 b 7
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1997 Microchip Technology Inc. DS31029A-page 29-11
Instruction
Set
29
d [0,1]
Operation: (W).AND. (f) destination
Status Affected: Z
Encoding: 00 0101 dfff ffff
Description: AND the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If'd' is 1 the result is stored back in register 'f'.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f'
Process
data
Write to
destination
Example 1 ANDWF FSR, 1
Before InstructionW = 0x17
FSR = 0xC2
After InstructionW = 0x17
FSR = 0x02
; 0001 0111 (0x17)
; 1100 0010 (0xC2)
;---------- ------
; 0000 0010 (0x02)
Example 2 ANDWF FSR, 0
Before InstructionW = 0x17
FSR = 0xC2After Instruction
W = 0x02
FSR = 0xC2
; 0001 0111 (0x17)
; 1100 0010 (0xC2)
;---------- ------; 0000 0010 (0x02)
Example 3 ANDWF INDF, 1
Before InstructionW = 0x17
FSR = 0xC2
Contents of Address (FSR) = 0x5A
After InstructionW = 0x17
FSR = 0xC2
Contents of Address (FSR) = 0x15
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DS31029A-page 29-12 1997 Microchip Technology Inc.
0 b 7
Operation: 0 f
Status Affected: None
Encoding: 01 00bb bfff ffff
Description: Bit 'b' in register 'f' is cleared.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f'
Process
data
Write
register 'f'
Example 1 BCF FLAG_REG, 7
Before InstructionFLAG_REG = 0xC7
After Instruction
FLAG_REG = 0x47
; 1100 0111
; 0100 0111
Example 2 BCF INDF, 3
Before InstructionW = 0x17
FSR = 0xC2
Contents of Address (FSR) = 0x2F
After InstructionW = 0x17
FSR = 0xC2
Contents of Address (FSR) = 0x27
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Section 29. Instruction Set
BSF Bit Set fSyntax: [ label] BSF f,b
Operands: 0 f 1270 b 7
PICmicro MID-RANGE MCU FAMILY
BTFSC Bit Test, Skip if ClearSyntax: [ label] BTFSC f,b
Operands: 0 f 1270 b 7
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1997 Microchip Technology Inc. DS31029A-page 29-13
Instruction
Set
29
0 b 7
Operation: 1 f
Status Affected: None
Encoding: 01 01bb bfff ffff
Description: Bit 'b' in register ' f' is set.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f'
Process
data
Write
register 'f'
Example 1 BSF FLAG_REG, 7
Before InstructionFLAG_REG =0x0A
After Instruction
FLAG_REG =0x8A
; 0000 1010
; 1000 1010
Example 2 BSF INDF, 3
Before InstructionW = 0x17
FSR = 0xC2
Contents of Address (FSR) = 0x20
After InstructionW = 0x17FSR = 0xC2
Contents of Address (FSR) = 0x28
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DS31029A-page 29-14 1997 Microchip Technology Inc.
0 b 7
Operation: skip if (f) = 0
Status Affected: None
Encoding: 01 10bb bfff ffff
Description: If bit 'b' in register 'f' is '0' then the next instruction is skipped.If bit 'b' is '0' then the next instruction (fetched during the current instruction execu-
tion) is discarded, and a NOP is executed instead, making this a 2 cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f'
Process
data
No
operationIf skip (2nd cycle):
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
Example 1 HEREFALSE
TRUE
BTFSC
GOTO
FLAG, 4
PROCESS_CODE
Case 1: Before InstructionPC = addressHERE
FLAG= xxx0 xxxxAfter InstructionSince FLAG= 0,
PC = addressTRUE
Case 2: Before InstructionPC = addressHERE
FLAG= xxx1 xxxx
After InstructionSince FLAG=1,
PC = addressFALSE
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Section 29. Instruction Set
BTFSS Bit Test f, Skip if SetSyntax: [ label] BTFSS f,b
Operands: 0 f 1270 b < 7
PICmicro MID-RANGE MCU FAMILY
CALL Call SubroutineSyntax: [ label] CALL k
Operands: 0 k 2047
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1997 Microchip Technology Inc. DS31029A-page 29-15
Instruction
Set
29
Operation: skip if (f) = 1
Status Affected: None
Encoding: 01 11bb bfff ffff
Description: If bit 'b' in register 'f' is '1' then the next instruction is skipped.If bit 'b' is '1', then the next instruction (fetched during the current instruc-tion execution) is discarded and a NOP is executed instead, making this a2 cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Readregister 'f'
Processdata
Nooperation
If skip (2nd cycle):
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
Example 1 HEREFALSE
TRUE
BTFSS
GOTO
FLAG, 4
PROCESS_CODE
Case 1: Before Instruction
PC = addressHEREFLAG= xxx0 xxxx
After InstructionSince FLAG= 0,
PC = addressFALSE
Case 2: Before InstructionPC = addressHERE
FLAG= xxx1 xxxx
After InstructionSince FLAG=1,
PC = addressTRUE
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DS31029A-page 29-16 1997 Microchip Technology Inc.
Operation: (PC)+ 1TOS,k PC,(PCLATH) PC
Status Affected: None
Encoding: 10 0kkk kkkk kkkk
Description: Call Subroutine. First, the 13-bit return address (PC+1) is pushed onto thestack. The eleven bit immediate address is loaded into PC bits . Theupper bits of the PC are loaded from PCLATH. CALLis a two cycleinstruction.
Words: 1
Cycles: 2
Q Cycle Activity:
1st cycle:Q1 Q2 Q3 Q4
Decode Read l iteral
'k'
Process
data
No
operation
2nd cycle:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
Example 1 HERE CALL THERE
Before InstructionPC = AddressHERE
After InstructionTOS = AddressHERE+1
PC = AddressTHERE
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Section 29. Instruction Set
CLRF Clear fSyntax: [ label] CLRF f
Operands: 0 f 127
PICmicro MID-RANGE MCU FAMILY
CLRW Clear WSyntax: [ label] CLRW
Operands: None
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1997 Microchip Technology Inc. DS31029A-page 29-17
Instruction
Set
29
Operation: 00h f1 Z
Status Affected: Z
Encoding: 00 0001 1fff ffff
Description: The contents of register 'f' are cleared and the Z bit is set.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f'
Process
data
Write
register 'f'
Example 1 CLRF FLAG_REG
Before InstructionFLAG_REG=0x5A
After InstructionFLAG_REG=0x00
Z = 1
Example 2 CLRF INDF
Before InstructionFSR = 0xC2
Contents of Address (FSR)=0xAA
After Instruction
FSR = 0xC2Contents of Address (FSR)=0x00
Z = 1
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DS31029A-page 29-18 1997 Microchip Technology Inc.
Operation: 00h W1 Z
Status Affected: Z
Encoding: 00 0001 0xxx xxxx
Description: W register is cleared. Zero bit (Z) is set.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f'
Process
data
Write
register 'W'
Example 1 CLRW
Before InstructionW = 0x5A
After InstructionW = 0x00
Z = 1
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Section 29. Instruction Set
CLRWDT Clear Watchdog TimerSyntax: [ label] CLRWDT
Operands: None
PICmicro MID-RANGE MCU FAMILY
COMF Complement fSyntax: [ label] COMF f,d
Operands: 0 f 127d [0,1]
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1997 Microchip Technology Inc. DS31029A-page 29-19
Instruction
Set
29
Operation: 00h WDT0 WDT prescaler count,1 TO1 PD
Status Affected: TO, PD
Encoding: 00 0000 0110 0100
Description: CLRWDTinstruction clears the Watchdog Timer. It also clears the pres-caler count of the WDT. Status bits TO and PD are set.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Nooperation
Processdata
ClearWDT
Counter
Example 1 CLRWDT
Before InstructionWDT counter= x
WDT prescaler =1:128
After InstructionWDT counter=0x00
WDT prescaler count=0
TO = 1PD = 1WDT prescaler =1:128
Note: The CLRWDTinstruction does not affect the assignment of the WDT prescaler.
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DS31029A-page 29-20 1997 Microchip Technology Inc.
Operation: (f) destination
Status Affected: Z
Encoding: 00 1001 dfff ffff
Description: The contents of register 'f' are 1s complemented. If 'd' is 0 the result isstored in W. If 'd' is 1 the result is stored back in register 'f'.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f'
Process
data
Write to
destination
Example 1 COMF REG1, 0
Before InstructionREG1= 0x13
After InstructionREG1= 0x13
W = 0xEC
Example 2 COMF INDF, 1
Before InstructionFSR = 0xC2
Contents of Address (FSR)=0xAA
After InstructionFSR = 0xC2
Contents of Address (FSR)=0x55
Example 3 COMF REG1, 1
Before InstructionREG1= 0xFF
After InstructionREG1= 0x00
Z = 1
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Section 29. Instruction Set
DECF Decrement fSyntax: [ label] DECF f,d
Operands: 0 f 127d [0,1]
PICmicro MID-RANGE MCU FAMILY
DECFSZ Decrement f, Skip if 0Syntax: [ label] DECFSZ f,d
Operands: 0 f 127d [0,1]
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1997 Microchip Technology Inc. DS31029A-page 29-21
Instruction
Set
29
Operation: (f) - 1 destination
Status Affected: Z
Encoding: 00 0011 dfff ffff
Description: Decrement register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 theresult is stored back in register 'f'.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f'
Process
data
Write to
destination
Example 1 DECF CNT, 1
Before InstructionCNT= 0x01
Z = 0
After InstructionCNT= 0x00
Z = 1
Example 2 DECF INDF, 1
Before InstructionFSR = 0xC2
Contents of Address (FSR) = 0x01Z = 0
After InstructionFSR = 0xC2
Contents of Address (FSR) = 0x00
Z = 1
Example 3 DECF CNT, 0
Before InstructionCNT= 0x10
W = x
Z = 0
After InstructionCNT= 0x10
W = 0x0FZ = 0
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DS31029A-page 29-22 1997 Microchip Technology Inc.
Operation: (f) - 1 destination; skip if result = 0
Status Affected: None
Encoding: 00 1011 dfff ffff
Description: The contents of register 'f' are decremented. If 'd' is 0 the result is placedin the W register. If 'd' is 1 the result is placed back in register 'f'.If the result is 0, then the next instruction (fetched during the currentinstruction execution) is discarded and a NOP is executed instead, mak-ing this a 2 cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
Q1 Q2 Q3 Q4Decode Read
register 'f'
Process
data
Write to
destination
If skip (2nd cycle):
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
Example HERE DECFSZ CNT, 1 GOTO LOOP
CONTINUE
Case 1: Before InstructionPC = address HERECNT = 0x01
After InstructionCNT = 0x00
PC = address CONTINUE
Case 2: Before InstructionPC = address HERECNT = 0x02
After InstructionCNT = 0x01
PC = address HERE+ 1
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Section 29. Instruction Set
GOTO Unconditional BranchSyntax: [ label] GOTO k
Operands: 0 k 2047
Operation: k PCPCLATH 4 3 PC 12 11
PICmicro MID-RANGE MCU FAMILY
INCF Increment fSyntax: [ label] INCF f,d
Operands: 0 f 127d [0,1]
O ti (f) 1 d ti ti
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1997 Microchip Technology Inc. DS31029A-page 29-23
Instruction
Set
29
PCLATH PC
Status Affected: None
Encoding: 10 1kkk kkkk kkkk
Description: GOTOis an unconditional branch. The eleven bit immediate value is loadedinto PC bits . The upper bits of PC are loaded from PCLATH.GOTOis a two cycle instruction.
Words: 1
Cycles: 2
Q Cycle Activity:
1st cycle:
Q1 Q2 Q3 Q4
Decode Read l iteral'k'
Processdata
Nooperation
2nd cycle:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
Example GOTO THERE
After InstructionPC =AddressTHERE
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DS31029A-page 29-24 1997 Microchip Technology Inc.
Operation: (f) + 1 destination
Status Affected: Z
Encoding: 00 1010 dfff ffff
Description: The contents of register 'f' are incremented. If 'd' is 0 the result is placed inthe W register. If 'd' is 1 the result is placed back in register 'f'.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f'
Process
data
Write to
destination
Example 1 INCF CNT, 1
Before InstructionCNT = 0xFF
Z = 0
After InstructionCNT = 0x00
Z = 1
Example 2 INCF INDF, 1
Before InstructionFSR = 0xC2
Contents of Address (FSR) = 0xFFZ = 0
After InstructionFSR = 0xC2
Contents of Address (FSR) = 0x00
Z = 1
Example 3 INCF CNT, 0
Before InstructionCNT= 0x10
W = x
Z = 0
After InstructionCNT= 0x10
W = 0x11
Z = 0
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Section 29. Instruction Set
INCFSZ Increment f, Skip if 0Syntax: [ label] INCFSZ f,d
Operands: 0 f 127d [0,1]
Operation: (f) + 1 destination skip if result = 0
PICmicro MID-RANGE MCU FAMILY
IORLW Inclusive OR Literal with WSyntax: [ label] IORLW k
Operands: 0 k 255
Operation: (W).OR. k W
S
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1997 Microchip Technology Inc. DS31029A-page 29-25
Instruction
Set
29
Operation: (f) + 1 destination, skip if result = 0
Status Affected: None
Encoding: 00 1111 dfff ffff
Description: The contents of register 'f' are incremented. If 'd' is 0 the result is placed inthe W register. If 'd' is 1 the result is placed back in register 'f'.If the result is 0, then the next instruction (fetched during the currentinstruction execution) is discarded and a NOP is executed instead, makingthis a 2 cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
Q1 Q2 Q3 Q4Decode Read
register 'f'
Process
data
Write to
destination
If skip (2nd cycle):
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
Example HERE INCFSZ CNT, 1 GOTO LOOP
CONTINUE
Case 1: Before InstructionPC = address HERECNT = 0xFF
After InstructionCNT = 0x00
PC = address CONTINUE
Case 2: Before InstructionPC = address HERECNT = 0x00
After InstructionCNT = 0x01
PC = address HERE+ 1
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DS31029A-page 29-26 1997 Microchip Technology Inc.
Status Affected: Z
Encoding: 11 1000 kkkk kkkk
Description: The contents of the W register is ORed with the eight bit literal 'k'. The result isplaced in the W register.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal 'k'
Process
data
Write to W
register
Example 1 IORLW 0x35
Before InstructionW = 0x9A
After InstructionW = 0xBF
Z = 0
Example 2 IORLW MYREG
Before InstructionW = 0x9A
Address of MYREG = 0x37
MYREGis a symbol for a data memory location
After InstructionW = 0x9F
Z = 0
Example 3 IORLW HIGH (LU_TABLE)
Before InstructionW = 0x9A
Address of LU_TABLE = 0x9375
LU_TABLEis a label for an address in program memory
After InstructionW = 0x9B
Z = 0
Example 4 IORLW 0x00
Before InstructionW = 0x00
After InstructionW = 0x00
Z = 1
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Section 29. Instruction Set
IORWF Inclusive OR W with fSyntax: [ label] IORWF f,d
Operands: 0 f 127d [0,1]
Operation: (W).OR. (f) destination
PICmicro MID-RANGE MCU FAMILY
MOVLW Move Literal to WSyntax: [ label] MOVLW k
Operands: 0 k 255
Operation: k W
Status Affected: None
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Instruction
Set
29
Operation: (W).OR. (f) destination
Status Affected: Z
Encoding: 00 0100 dfff ffff
Description: Inclusive OR the W register with register 'f'. If 'd' is 0 the result is placed inthe W register. If 'd' is 1 the result is placed back in register 'f'.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f'
Process
data
Write to
destination
Example 1 IORWF RESULT, 0
Before InstructionRESULT=0x13
W = 0x91
After InstructionRESULT=0x13
W = 0x93
Z = 0
Example 2 IORWF INDF, 1
Before Instruction
W = 0x17FSR = 0xC2
Contents of Address (FSR) = 0x30
After InstructionW = 0x17
FSR = 0xC2
Contents of Address (FSR) = 0x37
Z = 0
Example 3 IORWF RESULT, 1
Case 1: Before InstructionRESULT=0x13
W = 0x91
After Instruction
RESULT=0x93W = 0x91
Z = 0
Case 2: Before InstructionRESULT=0x00
W = 0x00
After InstructionRESULT=0x00
W = 0x00
Z = 1
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DS31029A-page 29-28 1997 Microchip Technology Inc.
Status Affected: None
Encoding: 11 00xx kkkk kkkk
Description: The eight bit literal 'k' is loaded into W register. The dont cares will assemble as 0s.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal 'k'
Process
data
Write to W
register
Example 1MOVLW 0x5A
After InstructionW = 0x5A
Example 2 MOVLW MYREG
Before InstructionW = 0x10
Address of MYREG = 0x37
MYREGis a symbol for a data memory location
After InstructionW = 0x37
Example 3 MOVLW HIGH (LU_TABLE)
Before InstructionW = 0x10
Address of LU_TABLE = 0x9375
LU_TABLEis a label for an address in program memory
After InstructionW = 0x93
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Section 29. Instruction Set
MOVF Move fSyntax: [ label] MOVF f,d
Operands: 0 f 127d [0,1]
Operation: (f) destination
PICmicro MID-RANGE MCU FAMILY
MOVWF Move W to fSyntax: [ label] MOVWF f
Operands: 0 f 127
Operation: (W) f
Status Affected: None
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Instruction
Set
29
p ( )
Status Affected: Z
Encoding: 00 1000 dfff ffff
Description: The contents of register f is moved to a destination dependent upon thestatus of d. If d = 0, destination is W register. If d = 1, the destination isfile register f itself. d = 1 is useful to test a file register since status flag Zis affected.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Readregister 'f'
Processdata
Write todestination
Example 1 MOVF FSR, 0
Before InstructionW = 0x00
FSR = 0xC2
After InstructionW = 0xC2
Z = 0
Example 2 MOVF INDF, 0
Before InstructionW = 0x17
FSR = 0xC2
Contents of Address (FSR) = 0x00
After InstructionW = 0x17
FSR = 0xC2
Contents of Address (FSR) = 0x00
Z = 1
Example 3 MOVF FSR, 1
Case 1: Before InstructionFSR = 0x43
After InstructionFSR = 0x43
Z = 0
Case 2: Before InstructionFSR = 0x00
After InstructionFSR = 0x00
Z = 1
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DS31029A-page 29-30 1997 Microchip Technology Inc.
Status Affected: None
Encoding: 00 0000 1fff ffff
Description: Move data from W register to register 'f' .
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f'
Process
data
Write
register 'f'
Example 1 MOVWF OPTION_REG
Before InstructionOPTION_REG=0xFF
W = 0x4F
After InstructionOPTION_REG=0x4F
W = 0x4F
Example 2 MOVWF INDF
Before InstructionW = 0x17
FSR = 0xC2
Contents of Address (FSR) = 0x00
After InstructionW = 0x17
FSR = 0xC2
Contents of Address (FSR) = 0x17
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Section 29. Instruction Set
NOP No OperationSyntax: [ label] NOP
Operands: None
Operation: No operation
Status Affected: None
PICmicro MID-RANGE MCU FAMILY
OPTION Load Option RegisterSyntax: [label] OPTION
Operands: None
Operation: (W) OPTION
Status Affected: None
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Instruction
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29
Status Affected: None
Encoding: 00 0000 0xx0 0000
Description: No operation.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation
No
operation
No
operation
Example HERE NOP
: Before InstructionPC = address HERE
After InstructionPC = address HERE+ 1
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DS31029A-page 29-32 1997 Microchip Technology Inc.
Encoding: 00 0000 0110 0010
Description: The contents of the W register are loaded in the OPTION register. Thisinstruction is supported for code compatibility with PIC16C5X products.Since OPTION is a readable/writable register, the user can directlyaddress it.
Words: 1
Cycles: 1
To maintain upward compatibility with future PIC16CXX products, do
not use this instruction.
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Section 29. Instruction Set
RETFIE Return from InterruptSyntax: [ label] RETFIE
Operands: None
Operation: TOS PC,
1 GIE
PICmicro MID-RANGE MCU FAMILY
RETLW Return with Literal in WSyntax: [ label] RETLW k
Operands: 0 k 255
Operation: k W;
TOS PC
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Instruction
Set
29
Status Affected: None
Encoding: 00 0000 0000 1001
Description: Return from Interrupt. The 13-bit address at the Top of Stack (TOS) isloaded in the PC. The Global Interrupt Enable bit, GIE (INTCON), isautomatically set, enabling Interrupts. This is a two cycle instruction.
Words: 1
Cycles: 2
Q Cycle Activity:
1st cycle:
Q1 Q2 Q3 Q4
Decode Nooperation
Processdata
Nooperation
2nd cycle:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
Example RETFIE
After InstructionPC = TOS
GIE = 1
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DS31029A-page 29-34 1997 Microchip Technology Inc.
Status Affected: None
Encoding: 11 01xx kkkk kkkk
Description: The W register is loaded with the eight bit literal 'k'. The program counter isloaded 13-bit address at the Top of Stack (the return address). This is atwo cycle instruction.
Words: 1
Cycles: 2
Q Cycle Activity:
1st cycle:
Q1 Q2 Q3 Q4
Decode Readliteral 'k'
Processdata
Write to Wregister
2nd cycle:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
Example HERE
TABLE
CALL TABLE ; W contains table
; offset value
; W now has table value
ADDWF PC ;W = offset
RETLW k1 ;Begin table
RETLW k2 ;
RETLW kn ; End of table
Before InstructionW = 0x07
After InstructionW = value of k8
PC = TOS = Address Here + 1
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Section 29. Instruction Set
RETURN Return from SubroutineSyntax: [ label] RETURN
Operands: None
Operation: TOS PC
Status Affected: None
PICmicro MID-RANGE MCU FAMILY
RLF Rotate Left f through CarrySyntax: [ label] RLF f,d
Operands: 0 f 127d [0,1]
Operation: See description below
S Aff d C
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Instruction
Set
29
Encoding: 00 0000 0000 1000
Description: Return from subroutine. The stack is POPed and the top of the stack(TOS) is loaded into the program counter. This is a two cycle instruc-tion.
Words: 1
Cycles: 2
Q Cycle Activity:
1st cycle:
Q1 Q2 Q3 Q4
Decode No
operation
Process
data
No
operation2nd cycle:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
Example HERE RETURN
After InstructionPC = TOS
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DS31029A-page 29-36 1997 Microchip Technology Inc.
Status Affected: C
Encoding: 00 1101 dfff ffff
Description: The contents of register 'f' are rotated one bit to the left through the CarryFlag. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result isstored back in register 'f'.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4Decode Read
register 'f'
Process
data
Write to
destination
Example 1 RLF REG1,0
Before InstructionREG1= 1110 0110
C = 0
After InstructionREG1=1110 0110
W =1100 1100
C =1
Example 2 RLF INDF, 1
Case 1: Before InstructionW = xxxx xxxx
FSR = 0xC2
Contents of Address (FSR) = 0011 1010
C = 1
After InstructionW = 0x17
FSR = 0xC2
Contents of Address (FSR) = 0111 0101
C = 0
Case 2: Before InstructionW = xxxx xxxx
FSR = 0xC2
Contents of Address (FSR) = 1011 1001C = 0
After InstructionW = 0x17
FSR = 0xC2
Contents of Address (FSR) = 0111 0010
C = 1
Register fC
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Section 29. Instruction Set
RRF Rotate Right f through CarrySyntax: [ label] RRF f,d
Operands: 0 f 127d [0,1]
Operation: See description below
Status Affected: C
PICmicro MID-RANGE MCU FAMILY
SLEEPSyntax: [ label] SLEEP
Operands: None
Operation: 00h WDT,0 WDT prescaler count,1 TO
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1997 Microchip Technology Inc. DS31029A-page 29-37
Instruction
Set
29
Status Affected: C
Encoding: 00 1100 dfff ffff
Description: The contents of register 'f' are rotated one bit to the right through the CarryFlag. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result isplaced back in register 'f'.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4Decode Read
register 'f'
Process
data
Write to
destination
Example 1 RRF REG1,0
Before InstructionREG1= 1110 0110
W = xxxx xxxx
C = 0
After InstructionREG1= 1110 0110
W = 0111 0011
C = 0
Example 2 RRF INDF, 1
Case 1: Before InstructionW = xxxx xxxx
FSR = 0xC2
Contents of Address (FSR) = 0011 1010
C = 1
After InstructionW = 0x17
FSR = 0xC2
Contents of Address (FSR) = 1001 1101
C = 0
Case 2: Before InstructionW = xxxx xxxx
FSR = 0xC2Contents of Address (FSR) = 0011 1001
C = 0
After InstructionW = 0x17
FSR = 0xC2
Contents of Address (FSR) = 0001 1100
C = 1
Register fC
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DS31029A-page 29-38 1997 Microchip Technology Inc.
1 TO,0 PD
Status Affected: TO, PD
Encoding: 00 0000 0110 0011
Description: The power-down status bit, PD is cleared. Time-out status bit, TO is set.Watchdog Timer and its prescaler count are cleared.The processor is put into SLEEP mode with the oscillator stopped.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4Decode No
operation
No
operation
Go to sleep
Example: SLEEP
Note: The SLEEPinstruction does not affect the assignment of the WDT prescaler
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Section 29. Instruction Set
SWAPF Swap Nibbles in fSyntax: [ label] SWAPF f,d
Operands: 0 f 127d [0,1]
Operation: (f) destination,(f) destination
PICmicro MID-RANGE MCU FAMILY
TRIS Load TRIS RegisterSyntax: [label] TRIS f
Operands: 5 f 7
Operation: (W) TRIS register f;
Status Affected: None
Encoding: 00 0000 0110 0fff
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1997 Microchip Technology Inc. DS31029A-page 29-41
Instruction
Set
29
Status Affected: None
Encoding: 00 1110 dfff ffff
Description: The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0 theresult is placed in W register. If 'd' is 1 the result is placed in register 'f'.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f'
Process
data
Write to
destination
Example 1 SWAPF REG, 0
Before Instruction
REG1= 0xA5
After Instruction
REG1= 0xA5
W = 0x5A
Example 2 SWAPF INDF, 1
Before Instruction
W = 0x17FSR = 0xC2
Contents of Address (FSR) = 0x20
After InstructionW = 0x17
FSR = 0xC2
Contents of Address (FSR) = 0x02
Example 3 SWAPF REG, 1
Before Instruction
REG1= 0xA5
After Instruction
REG1= 0x5A
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DS31029A-page 29-42 1997 Microchip Technology Inc.
g
Description: The instruction is supported for code compatibility with the PIC16C5X prod-ucts. Since TRIS registers are readable and writable, the user can directlyaddress them.
Words: 1
Cycles: 1
Example
To maintain upward compatibility with future PIC16CXX products, donot use this instruction.
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Section 29. Instruction Set
XORLW Exclusive OR Literal with WSyntax: [ label] XORLW k
Operands: 0 k 255
Operation: (W).XOR. k W
Status Affected: Z
Encoding: 11 1010 kkkk kkkk
PICmicro MID-RANGE MCU FAMILY
XORWF Exclusive OR W with fSyntax: [ label] XORWF f,d
Operands: 0 f 127d [0,1]
Operation: (W).XOR. (f) destination
Status Affected: Z
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Instruction
Set
29
Encoding: 11 1010 kkkk kkkk
Description: The contents of the W register are XORed with the eight bit literal 'k'. Theresult is placed in the W register.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal 'k'
Process
data
Write to W
register
Example 1 XORLW 0xAF ; 1010 1111 (0xAF)
Before Instruction ; 1011 0101 (0xB5)
W = 0xB5 ; --------- ------
After Instruction ; 0001 1010 (0x1A)
W = 0x1A
Z = 0
Example 2 XORLW MYREG
Before InstructionW = 0xAF
Address of MYREG = 0x37
MYREGis a symbol for a data memory locationAfter Instruction
W = 0x18
Z = 0
Example 3 XORLW HIGH (LU_TABLE)
Before InstructionW = 0xAF
Address of LU_TABLE = 0x9375
LU_TABLEis a label for an address in program memory
After InstructionW = 0x3C
Z = 0
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DS31029A-page 29-44 1997 Microchip Technology Inc.
Encoding: 00 0110 dfff ffff
Description: Exclusive OR the contents of the W register with register 'f'. If 'd' is 0 theresult is stored in the W register. If 'd' is 1 the result is stored back in regis-ter 'f'.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f'
Process
data
Write to
destination
Example 1 XORWF REG, 1 ; 1010 1111 (0xAF)
Before Instruction ; 1011 0101 (0xB5)
REG= 0xAF
W = 0xB5; --------- ------
; 0001 1010 (0x1A)
After Instruction
REG= 0x1A
W = 0xB5
Example 2 XORWF REG, 0 ; 1010 1111 (0xAF)
Before Instruction ; 1011 0101 (0xB5)REG= 0xAF
W = 0xB5; --------- ------
; 0001 1010 (0x1A)
After Instruction
REG= 0xAF
W = 0x1A
Example 3 XORWF INDF, 1
Before InstructionW = 0xB5
FSR = 0xC2
Contents of Address (FSR) = 0xAF
After InstructionW = 0xB5
FSR = 0xC2
Contents of Address (FSR) = 0x1A
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Section 29. Instruction Set
29.7 Related Application Notes
This section lists application notes that are related to this section of the manual. These applica-tion notes may not be written specifically for the Mid-Range MCU family (that is they may be writ-ten for the Base-Line, or High-End families), but the concepts are pertinent, and could be used(with modification and possible limitations). The current application notes related to the instruc-tion set are:
Currently No related Application Notes
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1997 Microchip Technology Inc. DS31029A-page 29-47
Instruction
Set
29
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