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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1

Test Escapes of Stuck-Open Faults Caused byParasitic Capacitances and Leakage Currents

Daniel Arumí, Rosa Rodríguez-Montañés, and Joan Figueras, Member, IEEE

Abstract— Intragate open defects are responsible for a signifi-cant percentage of defects in present technologies. A majorityof these defects causes the logic gate to become stuck open,and this is why they are traditionally modeled as stuck-openfaults (SOFs). The classical approach to detect the SOFs is basedon a two-vector sequence, and has been proved effective for awide range of technologies. However, factors typically neglectedin past technologies have become a major concern in nanometertechnologies, i.e., leakage currents and downstream parasiticcapacitances. Some recent works have examined the influenceof leakage currents. However, to the best of our knowledge,no one has considered the influence of downstream parasiticcapacitances. In this paper, the influence of both factors isinvestigated and experimentally measured with a test chip builton a 65-nm technology. An analysis based on the electricalsimulations is performed to quantify the number of test escapesin the presence of SOFs. Test recommendations are derived fromthe analysis results to maximize the detectability of these faultsin present and future technologies.

Index Terms— Integrated circuit (IC) testing, leakage currents,parasitic capacitances, stuck-open faults (SOFs), test escapes.

I. INTRODUCTION

THE aggressive scaling of technology and the increasingnumber of transistor counts pose a major challenge for

keeping the integrated circuit (IC) quality under control. Thisis especially critical in automotive and medical applicationsamong others, where approximately ten defective parts permillion (DPPM) is demanded. Because of the increasingnumber of contacts and vias [1], the open defects are cur-rently one of the most common yield killer defects affectingpresent ICs. An open defect consists in undesired partial ortotal breaking of electrical connection between two points,which should be connected by design. Opens may appear bothin the interconnect structures and the logic structures, openingconnections to the source and the drain terminals of transistors.In the latter case, opens have traditionally been modeled asstuck-open faults (SOFs) [2].

Since the SOF model was first proposed in [2], intensiveresearch effort has been devoted to improving the characteri-zation [3], testing [4]–[6], and diagnosis [9]–[12] of this class

Manuscript received May 14, 2015; revised July 27, 2015; acceptedSeptember 2, 2015. This work was supported by the Spanish Ministry ofScience and Technology and Fondos Europeos de Desarrollo Regional Fundsunder Research Project TEC2013-41209-P.

The authors are with the Department of Electronics Engineering,Universitat Politècnica de Catalunya, Barcelona 08208, Spain (e-mail:[email protected]; [email protected]; [email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TVLSI.2015.2477103

of faults. These studies have demonstrated its efficiency for awide spectrum of technologies, including the deep submicrom-eter domain. Today, 30 years after its proposal, the complexityof this fault’s behavior still attracts the interest of the researchcommunity [13]–[16]. In fact, new paradigms have arisenwhich appeal for the revision of the classical model to extendthe detectability of these faults in nanometer technologies.In this direction, the works in [17] and [18] demonstrate theinfluence of leakage on the behavior of the faulty cells affectedby the SOFs. Downstream parasitic capacitances related tothe faulty node, which were considered a second-order factorin past technologies, also arise as a nonnegligible factor.These capacitances generate a pull-up/down, influencing thebehavior of the faulty nodes. If the leakage currents and thedownstream parasitic capacitances are not properly addressed,SOFs may become an important source of test escapes,causing unacceptable DPPM levels, especially in applicationswhere high test quality and low escape rates are required.

In this paper, the impact of downstream parasiticcapacitances on SOF behavior is analyzed. It is demonstratedhow these capacitances may become the major contributorto test escapes for at-speed testing, even greater than theleakage currents. A test IC was designed and built on 65-nmtechnology to experimentally demonstrate this influence. Thispaper is organized as follows. The classical SOF model isbriefly reviewed in Section II. In Section III, a simple analysisis carried out to demonstrate the influence of downstream par-asitic capacitances on nanometer technologies. In Section IV,the SOF model including leakage currents and downstreamparasitic capacitances is proposed. The experimental resultsobtained with the test IC are shown in Section V. Section VIpresents the results from electrical simulations of circuitswith SOFs for several technology nodes. Section VII providesrecommendations to improve SOF detectability. Finally, theconclusions are drawn in Section VIII.

II. CLASSICAL STUCK-OPEN FAULT MODEL

An SOF is a failure mechanism modeled as a loss of chargetransfer in one transistor of the defective gate in such a waythat the output is set to a high impedance state for at leastone logic state [2]. In this situation, the output voltage dependson the previously applied state. Throughout this paper, theSOFs are assumed to be caused by opens at the drain termi-nals of transistors. Opens at the source terminals are almostequivalent to those affecting the drain terminals in terms ofthe charge transfer path. Therefore, they are also covered bythis paper.

1063-8210 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.


2 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Fig. 1. (a) SOF at a two-input NAND gate. (b) Truth table.

Fig. 2. Inverter with an SOF at the drain terminal of the pMOS transistor.

Without loss of generality, consider the example in Fig. 1(a),which illustrates a two-input NAND gate with an SOF atthe drain terminal of the pMOS transistor driven by B. Thetruth table for this faulty gate is displayed in Fig. 1(b).Note that how the output node remains in a high impedancestate for the input combination (A B) = (1 0). Thus, if thepreviously applied vector were (A B) = (1 1), the output (Z)would be interpreted as a logic 0. For the input combinations(0 0) and (0 1), Z would be interpreted as a logic 1. Sincean SOF induces a sequential behavior, a two-vector sequenceis required. The first vector initializes the faulty node and thesecond one excites the fault.

III. DOWNSTREAM PARASITIC CAPACITANCE

CONDITIONS TO GENERATE A TEST ESCAPE

A simple analysis is presented to demonstrate that down-stream parasitic capacitances may influence the behavior of thefaulty circuits affected by SOFs. For simplicity, the impact ofleakage currents is neglected. Consider the example in Fig. 2.An SOF disconnects the pMOS transistor from the output (Z).The capacitances influencing the faulty node are the gate-to-drain [Cgd(n)] and drain-to-bulk [Cdb(n)] capacitances of thenMOS transistor and the downstream capacitances related to Z.These downstream capacitances, which summarize the para-sitic capacitances to neighboring lines and transistor capac-itances of downstream gates, are denoted by Crt , Cft , C0,and C1. In fact, Crt (Cft) represents the part of the down-stream capacitances undergoing a rising (falling) transitionand C0 (C1) the part remaining constant at a logic 0 (1) value.

During the application of the two-vector sequence, theinverter output is first discharged to GND. Subsequently, thetransition is generated at the inverter input. Z remains in a highimpedance state and cannot be charged to VDD. The parasiticcapacitances induce a pull-up/down on Z. To derive the exact

Fig. 3. Minimum faulty line length to enable a test escape for anSOF affecting the pMOS transistor of an inverter.

voltage variation, it must be considered that node A undergoesa falling transition, the substrate remains constant and theinfluence of the downstream parasitic capacitances dependson the test sequence applied. The faulty node voltage canbe obtained by applying the charge conservation law derivedin (1)

VZ = Crt − Cft − Cgd(n)

CTD + Cgd(n) + Cdb(n)VDD (1)

where CTD represents the total downstream parasiticcapacitances, as follows:

CTD = Crt + Cft + C0 + C1. (2)

A positive or a negative voltage variation is due to theinfluence of the downstream parasitic capacitances. In thisexample, a drop helps to detect the fault whereas a positivevariation may generate a test escape. Assuming the fault isnot detected as long as the faulty node voltage is equal to orhigher than VDD/2, from (1) and by rearranging the inequality,we have

Crt − Cft ≥ 1

2(CTD + 3Cgd(n) + Cdb(n)). (3)

This inequality describes the relationship betweenCrt and Cft as a function of CTD and the inverter transistorparasitic capacitances [Cgd(n) and Cdb(n)] in order to generatea test escape. For long lines, around hundred of micrometers,transistor capacitances become negligible and it is expectedthat the high number of neighbors induces similar values forCft and Crt . Hence, the probability of accomplishing (3) maybe low. On the contrary, transistor capacitances are importantfor short lines. If 1/2 [CTD + 3Cgd(n) + Cdb(n)] is higherthan CTD, (3) cannot be fulfilled and no test escape can begenerated.

A minimum faulty line length, with the correspondingCTD value, is required to enable a test escape. Lmin refersto this length and was predicted for different technologynodes, as shown in Fig. 3. A minimum distance betweenadjacent lines was assumed for coupling purposes. Observethat Lmin values are low, around a few micrometer. Whatis more, Lmin decreases for every technology node since therelative importance of the downstream parasitic capacitancesincreases with technology shrinking. The similar results wouldbe obtained if the corresponding analysis were carried out fordifferent faulty gates.


ARUMÍ et al.: TEST ESCAPES OF SOFs CAUSED BY PARASITIC CAPACITANCES AND LEAKAGE CURRENTS 3

Fig. 4. SOF model in nanometer technologies including the influence ofleakage currents and downstream parasitic capacitances.

IV. STUCK-OPEN FAULT MODEL IN

NANOMETER TECHNOLOGIES

The output voltage of a faulty gate affected by an SOF hastraditionally been considered to remain constant during thehigh impedance state. However, the transistor leakages anddownstream parasitic capacitances invalidate this assumption.The classical model must, therefore, be reviewed to compriseboth factors, which are described in Sections IV-A–IV-C.

A. Influence of Leakage Currents

The two major leakage contributors in the presence of anSOF are subthreshold leakage and gate leakage. Subthresholdleakage [19] is the current between the source and drainterminals of a transistor when it operates in the weak inversionregion. For ultrathin silicon oxide layers and low electric fields,gate leakage current [19] becomes nonnegligible and is mainlycaused by the direct tunneling mechanisms.

An example of the influence of leakage currents is shownin Fig. 4. The output of the NAND gate (Z) is disconnectedfrom the drain terminal of one of the pMOS transistors. Thefaulty cell is in turn driving an inverter and is cross-coupledwith i neighboring lines. For ease of simplicity, the dashed lineomits some of the neighbors from Fig. 4. In the highimpedance state [(A B) = (1 0)], leakage currents influencethe behavior of Z. These leakage currents are made up of thesubthreshold leakage and gate leakage components from theaffected transistors, namely, the subthreshold current [Isub(pA)]and the gate-to-drain current [Igd(pA)] from the pMOS tran-sistor driven by A, the subthreshold current [Isub(nB)] and thegate-to-drain current [Igd(nB)] from the nMOS transistor drivenby B, and the gate-to-drain [Igd(nZ) and Igd(pZ)] and gate-to-source [Igs(nZ) and Igs(pZ)] current from the nMOS and pMOStransistors of the downstream inverter.

A circuit like that in Fig. 4 was simulated to show theinfluence of leakage currents. The faulty line was cross-coupled with 20 neighbors, deriving a total downstreamparasitic capacitance equal to 6 fF. All the neighborsremained constant during the application of the vectorsequence to excite the SOF. The simulation results showingthe evolution of Z in the high impedance state using 16-nmpredictive technology model (PTM), low power (LP), andhigh performance (HP) model [20]–[21] are summarizedin Fig. 5. Note that how the leakage currents generate

Fig. 5. Transient simulation results of the faulty node (Z) considering theinfluence of leakage currents using 16-nm PTM model. (a) LP. (b) HP.

a charge flow. Its voltage increases with time until thesteady state is reached, that is, once the sum of all currentcomponents flowing into and out of Z is null. At this point,any small deviation (caused by noise, interference, andso on) may be decisive for the logic interpretation of Z.It must be pointed out that the LP technology reports a largetime constant, in the order of microsecond, a time constantseveral orders of magnitude higher than the one reported byHP technology, which is of a few tens of nanosecond. Theexact behavior depends on the technology and the faulty circuittopology, i.e., the faulty gate, the particular fault location, thedownstream parasitic capacitances, and the downstream gates.

B. Influence of Downstream Parasitic Capacitances

The faulty node is cross-coupled with the parasiticcapacitances. These capacitances are related to neighboringlines [CN1, CN2, . . . , CNi in Fig. 4], the transistor parasiticcapacitances of the faulty gate [Cgd(pA), Cgb(pA), Cgd(nB),and Cgb(nB)] and the transistor parasitic capacitances of thedownstream gate [Cgd(pZ), Cgb(pZ), Cgd(nZ), and Cgb(nZ)].When applying a test sequence, the parasitic capacitancesundergoing a rising (falling) transition may generate a pull-up(down) of the faulty node. The exact influence depends onthe relationship between the capacitances undergoing a rising(falling) transition or remaining at a constant value. Thefaulty node behaves similar to an interconnect line affectedby a full open [22]–[25]. The difference lies in that thefaulty node is in a high impedance state for some specificexcitations whereas the interconnect line affected by a fullopen always remains disconnected from the driver.

Increasing the parasitic capacitances undergoing a rising(falling) transition leads to higher positive (negative) voltage



Fig. 6. Voltage variation induced by neighboring parasitic capacitances fordifferent coupling lengths (Lc). 16-nm PTM LP model results.

variations induced in the faulty node. This is demonstrated inthe results from Fig. 6. The simulated circuit was composedof the faulty NAND gate like the one in Fig. 4, but cross-coupled with a single neighboring capacitance. It is assumedthat neighboring line is cross-coupled along all the line atthe minimum distance allowed by the technology. A fallingtransition is applied at the faulty input of the NAND gate anda rising transition (RT) at the neighboring line. A positivevoltage variation is thus generated due to the influence ofthe neighboring line. Fig. 6 shows �VZ , the induced voltagevariation, for different cross-coupling lengths between thefaulty line and the neighboring line (Lc). For lengths longerthan 5 μm, a variation higher than VDD/2 is already induced.

C. Stuck-Open Fault Behavior in Nanometer Technologies

An electrical model including the leakage currents and thedownstream parasitic capacitances is required to accuratelydescribe the SOF behavior. Simulations were carried out withthe same circuit used to obtain the results in Fig. 5, butin this case applying test vectors causing the neighboringlines to undergo transitions as these vectors were applied.The simulations results are given in Fig. 7(a) and (b), where16-nm PTM, LP, and HP models are considered, respectively.The plots report the transient evolution of the faulty nodesupon application of the same ten sets of two-vector sequenceswith a test period of 100 ns. The first vector of the sequenceinitialized the faulty node (Z) and the second one excited thefault. Every test sequence induced different excitation condi-tions on the neighboring lines. Black vertical lines and graydotted vertical lines represent the moments where the first andthe second vector of the sequence were applied, respectively.

From the plots in Fig. 7, observe how when the first vectoris applied, VZ = 0 V. Every time the second vector of thesequence is applied, a pull-up/down up to several tenths ofvolts is induced due to the downstream parasitic capacitances.This influence is clearly observable in both technologies.

Charge flow then occurs due to the leakage currents in asimilar manner as shown in Fig. 5. However, this influence islimited in time by the test period, since when the first vectorof the next sequence is applied, VZ = 0 V. The impact ofleakage currents is negligible for LP model [Fig. 7(a)]. Thisis due to the fact that the induced time constant is a feworders of magnitude higher than the test period (100 ns).

Fig. 7. Faulty node evolution based on simulations results using 16-nm PTMmodels. (a) LP. (b) HP.

By contrast, the influence of leakage currents is significantfor HP model, where VZ increases with time until the nextvector is applied [Fig. 7(b)]. These results are consistentwith those in Fig. 5. The HP model circuits are expectedto work for shorter periods than 100 ns. For higher workingfrequencies, the influence of leakage currents may be similarto the LP model case. By contrast, the parasitic capacitancesinduce voltage variations up to several tenths of volts, whichbecome of concern irrespective of test frequency.

V. EXPERIMENTAL BEHAVIOR

A design based on STMicroelectronics CMOS 65-nm tech-nology was sent to fabrication to corroborate the impact ofparasitic capacitances and leakage currents on defective circuitbehavior. The layout of the design is shown in Fig. 8 andthe picture of one of the devices is shown in Fig. 9. It is amultiproject IC where the design area and its correspondingpads occupies part of the bottom left area of the die. Apartfrom the power supply pads, the circuit comprises five digitalpads, four inputs, and one output. The rest of pads pinpointedin Fig. 9 are devoted to another circuit. The design inputs andthe output are enumerated as follows.

1) TIN: test input.2) SE: scan enable.3) CLK1: scan in/out clock.4) CLK2: launch clock.5) TO: test output.



Fig. 8. Layout of the design.

Fig. 9. Photograph of the fabricated circuit.

Fig. 10. Simplified schematic of the circuit with intentional defective gates.

A simplified schematic is shown in Fig. 10. It comprisesrandom logic with open defects intentionally injected affect-ing the pMOS and nMOS networks of inverters (IV),NAND and NOR gates. These defective topologies were gener-ated realistically according to the cell layout by including opencontacts in the affected gates. Neighboring lines were routedto derive different topologies of the parasitic capacitances.Table I summarizes the topology information. Length refersto the defective line length, CTD to the total downstreamparasitic capacitances reported by the layout extractor, andCN to the percentage of CTD corresponding to downstreamneighboring coupling capacitances. The inputs of the defectivegates and the neighboring lines are fully controllable, i.e., anypossible state can be induced in the circuit. Two registers areused for this purpose: 1) the scan register shifts in the inputvectors (TIN) and 2) the launch register maintains the state ofthe system between the application of the first vector and theload of the second one. Each register is managed by its ownclock signal. The scan and launch registers are managed byCLK1 and CLK2, respectively. Once the response is captured,

TABLE I

NEIGHBORING INFORMATION OF THE DEFECTIVE TOPOLOGIES

TABLE II

NEIGHBORING CAPACITANCES INDUCING A TEST ESCAPE

the scan register shifts out the results through TO, activat-ing the scan enable signal (SE). The power supply voltageis 1.2 V, the clock period 100 ns, and the delay between thelaunch and capture 50 ns.

An automatic test equipment (ATE) was used to perform themeasurements. A set of tests was applied to experimentallydetermine the defect detectability under different excitationsof the neighboring lines and the leakage currents. The testsinduced different proportions of the neighboring couplingcapacitances undergoing an rising transition, a falling transi-tion, and remaining at a constant value. The faulty gates werealso excited to derive the different leakage current conditions.Table II summarizes the experimental results when consideringthe influence of neighboring parasitic capacitances. Amongall range of neighboring lines excitations applied to the cir-cuit, CTD_CRIT stands for the minimum percentage of CTDundergoing the same transition as the defective node inducinga test escape. Hence, for SOFs affecting a pMOS (nMOS)network, CTD_CRIT represents the minimum percentage of CTDundergoing a rising (falling) transition which induces a testescape. Observe that CTD_CRIT ranges between 51% and 64%,depending on the topology. The percentage required by theinverters is higher since their topologies have the lower para-sitic neighboring capacitances, as reported in Table I.

Experiments were also conducted to demonstrate the influ-ence of leakage currents. Figs. 11 and 12 show these results forgates with defective nMOS and pMOS networks, respectively.The plots represent the time required by the leakage to gener-ate a change in the logic interpretation of the defective node fordifferent �VCN values, where �VCN stands for pulls up/downinduced by the neighboring lines. This voltage variation wasobtained from the electrical simulations of the same condi-tions used for the ATE. Neglecting transistor capacitances,�VCN can be approximated by

�VCN = Crt − Cft

CTDVDD. (4)

�VCN = 0 V accounts for the reference case, wherethe measured delay is maximum, in the order of hundreds/thousands of microsecond. The delay decreases for thehigher �VCN values until an excitation already inducing adifferent logic interpretation of the defective gate is applied.In this case, the delay becomes null. Observe how the



Fig. 11. Impact of leakage in gates with defective nMOS networks. Differentexcitations of neighboring lines are considered.

Fig. 12. Impact of leakage in gates with defective pMOS networks. Differentexcitations of neighboring lines are considered.

topology with the lowest delay and �VCN value is reportedfor the inverters. This is again expected because they havethe lowest node capacitances and the highest ratio betweenthe transistor and the neighboring parasitic capacitances.

The experimental results demonstrate the influence ofleakage currents and neighboring parasitic capacitances.As the former derive high time constants, the latter isexpected to become the most important contributor to testescapes for at-speed-testing.

VI. ANALYSIS OF TEST ESCAPES DUE

TO STUCK-OPEN FAULTS

This section presents the analysis of HSPICE simulationscarried out with the faulty circuits affected by SOFs. Thesource of the analysis was an industrial design in a 90-nmtechnology, although the same circuits were subsequentlyscaled-down to other technology nodes. A set of SOFs wasintentionally injected to affect the four transistor networkconfigurations, as shown in Fig. 13. These four networks sum-marize the topology of any open affecting the source or drainterminals of transistor(s), considering simple faulty paralleland serial networks for the pMOS and nMOS transistors.

The subcircuit comprising the faulty gate, the extractedneighboring parasitic capacitances, and the downstream gateswas considered during the simulations to speed up the analysis.The parasitic capacitances were extracted from the design

Fig. 13. SOFs affecting (a) pMOS transistor from a serial network, (b) nMOStransistor from a serial network, (c) nMOS transistor from a parallel network,and (d) pMOS transistor from a parallel network.

exchange format (.def) file. A recreation of a pattern file con-sisting of 250 pairs of test vectors was made. Thousand SOFswere randomly injected in every fault topology. The wholeset of 250 pairs of vectors was considered for the evaluationof faulty circuit responses. In case any of the downstreamgates propagated a faulty logic value for any two-vectorsequence, the fault was detected; otherwise, a test escape wasgenerated. The extracted circuits were scaled down to the32- and 16-nm technology [20], and also to the 16-nm FinFETtechnology (PTM-MG model) [26]. It must be pointed outthat the equivalent model, such as the one in Fig. 4, can beeasily derived for a FinFET technology. The main differencefor FinFET devices lies in that gate leakage components aresmall compared with the subthreshold ones. The LP and HPapplications are considered for every technology node. Theworking period during electrical simulation was 100 ns for theLP circuits and 1 ns for the HP counterparts. In fact, 100 nsis the test period of the 90-nm technology design in the realtest environment.

Information about test escapes obtained from postprocessingof the electrical simulation results is given in Table III. Thenumber of test escapes rises with technology shrinkingirrespective of fault topology. This increase is more abruptfor the LP technologies than for the HP technologies, exceptfor the FinFET technology. This tendency is mainly due todifferences in scalability of transistor physical dimensionsand power supply voltage. It is also worth noting that theFinFET circuits have more test escapes than the MOScounterparts. As transistor capacitances are lower in theFinFET technologies, the downstream parasitic capacitanceeffect becomes preponderant.

Leakage currents have a slight influence considering a testperiod of 1 ns. For this reason, the same simulations arerepeated for the HP circuits over a longer test period; that is,the same post-processing analysis is performed while increas-ing the test period to 10 and 100 ns. The downstream parasiticcapacitances have the same logic influence irrespective of thetest period since the applied patterns are the same. However,



TABLE III

TEST ESCAPES(%) FOR SOFs AFFECTING LP AND HP TECHNOLOGIES

TABLE IV

TEST ESCAPES(%) FOR DIFFERENT TEST PERIODS (HP TECHNOLOGIES)

the increasing test period implies increasing the time thefaulty node is in the high impedance state. Hence, the leakagecurrents have more time to generate a charge flow and modifythe voltage of the faulty node. Differences in the resultscan thus be justified only by the influence of these leakagecurrents. The results are summarized in Table IV. Note thesmall influence for the 32- and 16-nm PTM models whenthe test period is 10 ns. However, the influence becomes morenoticeable for 100 ns. The 16-nm PTM-MG model simulationsundergo leakage influence for 10 ns, mainly because of thelower transistor capacitances and dimension scalability due tothe discrete width of the transistor fins.

When an SOF affects a serial network configuration, theleakage influence is dominated by the subthreshold currentof the fault free transistor network connected to the gateoutput, which pulls the node to the faulty voltage value.For this reason, the number of test escapes decreases forlonger test periods, irrespective of the technology. In fact,the number of test escapes is almost null for the 16-nmPTM-MG model for 100 ns. By contrast, when the SOF affectsa parallel network, there is a fight between the p-network andthe n-network connected to the output. An intermediate voltagevalue which may be interpreted either as 0 or 1, dependingon the exact topology of the faulty and downstream gates, isthus induced.

A tendency to interpret these intermediate voltages as 0is reported for the technologies used in this paper. For thisreason, the leakage currents induce an increase in the num-ber of test escapes for SOFs affecting parallel n-networksand a decrease for the faulty parallel p-networks. Observethat 14.780% of test escapes are reported for SOFs affectingparallel n-networks for the 16-nm PTM HP model over atest period of 100 ns. This percentage increases dramaticallyin PTM-MG, reaching up to 95.745% of test escapes. Thisis partially justified by logic threshold variations resultingfrom downscaling of this technology and the discrete widthof transistor fins. On the contrary, the number of test escapesis extremely low for the faulty parallel p-networks.

The results show that the influence of leakage currents isnot noticeable at the working frequency whereas it is highly

Fig. 14. DPPM versus POFcontact assuming Ncontacts = 2 × 107 andPescape = 0.01.

significant at lower test frequencies. In this context, the leakagecurrents help detect the SOFs affecting serial networks. Forparallel networks, they can help detect or mask the fault,depending on the faulty circuit topology. For the configurationsin this paper, leakage currents help detect SOFs affectingparallel p-networks but increase the number of test escapeswhen SOFs affect parallel n-networks.

The results in Table III lead to the question whether theseescape rates are critical. Assuming that the most probablecause of an SOF is an open contact, it is possible to deriveDPPM according to

DPPM = Ncontacts · POFcontact · Pescape (5)

where Ncontacts is the number of contacts prone to SOFs,POFcontact the probability of failure of a single contact andPescape the escape probability of an SOF. Considering amedium-sized circuit with 2 × 107 contacts and accordingto the results in Tables III and IV, a representative escapeprobability Pescape = 0.01 is assumed. The relationshipbetween DPPM and POFcontact can be derived from (6), asshown in Fig. 14. DPPM reaches nonnegligible values whenPOFcontact ranges between 10−11 and 10−10. These DPPM val-ues due to SOFs may be unacceptable for a single fault class,even for noncritical applications. This is, however, a pes-simistic scenario since every SOF is assumed to be testedonly once.



Fig. 15. Test configuration example to improve SOF detectability.

TABLE V

BEST TEST SCENARIO TO MINIMIZE LEAKAGE

VII. TEST RECOMMENDATIONS

The results presented in this paper show that the numberof test escapes due to SOFs is of concern in nanometertechnologies. Hence, the test strategy must be refined toimprove test robustness. For this purpose and without loss ofgenerality, consider the example in Fig. 15, where an SOFis affecting an nMOS transistor of an AO gate. The faultygate is in turn driving a NAND and a NOR gate and the faultynode (D) is also cross-coupled with a neighboring line (H).In the classical two-vector sequence, an rising transition isapplied at A to excite the fault. Assuming the output of thefaulty gate is propagated through the NOR gate, then G is setto 0.

According to the work in [18], some recommendationscan be followed when configuring the faulty gate and thecorresponding downstream gates to minimize the influence ofleakage currents. In the above example, three combinationsfor inputs (B C) can be used to propagate the fault. Amongthem, (0 0), (0 1), and (1 0), the most appropriate one is(0 0) since it minimizes the leakage through the stack ofthe two serial nMOS transistors. Regarding the downstreamNAND gate, setting F = 0 provides the scenario with thelowest leakage. Table V summarizes the configuration of thesignals to derive the best test scenario in terms of leakage.

The influence of downstream parasitic capacitances issummarized by interconnect line H, which may undergofour different activation conditions during the test sequence:remaining constant at 0 or 1 and undergoing a rising(or falling) transition. The implications of these configurationsare summarized in Table VI. Remaining constant at a logicvalue is an appropriate test condition since it induces neithera pull-up nor a pull down. An rising transition is the besttest scenario because it reinforces the logic interpretation ofthe faulty node. On the contrary, a falling transition must beavoided since it induces a pull down, enabling a test escape.By applying an RT in H, together with the recommendation

TABLE VI

TEST SCENARIOS ACCORDING TO THE INFLUENCE OF

DOWNSTREAM PARASITIC CAPACITANCES

in Table V, the most robust test condition to detect this SOFis obtained.

In a general configuration with multiple neighbors, the stateof the entire neighborhood should be considered to determinefault detectability, as already considered for interconnect fullopen faults [24], [27], [28]. The problem is similar to thatabout crosstalk in [29] and [30], but with more relaxedconditions. In fact, it is not feasible to set the best test scenariofor every possible fault. Instead, a different approach shouldbe taken to minimize the risk of test escapes while avoidingincreasing test complexity. The use of N-detect appears as avalid option for this purpose [31], [32]. As this strategy excitesthe same fault multiple times by generating different neighbor-ing excitations, it should increase the probability of inducingat least one proper configuration to detect the SOF. Althoughsuccessful in some contexts, N-detect improves detectabilityat the expense of increasing the number of test vectors. If thecriterion for pattern generation is not deterministically basedon optimizing the neighboring conditions, its application maynot be feasible.

An alternative approach consists in a previous analysis offaulty topologies prone to the test escapes and the subsequentmodification or even addition of some test vectors. Thisprocess is expected to be time consuming but must be doneonce for every design, with no implications on product devel-opment time. The diagram flow in Fig. 16 shows an example ofthe process steps. The first one consists in extracting the para-sitic information between coupling lines, i.e., from a .def file.Based on this information, the subset of potential candidatesto undergo a test escape is selected. For every possible SOFaffecting the selected nodes, the two-vector sequences excitingthe fault are obtained from the pattern file. Subsequently, theneighboring state is analyzed for the vector pairs excitingthe fault. If any induces a robust test scenario, the SOF isconsidered as covered. Otherwise, these vectors should berevisited to modify the don’t care bits in order to generate arobust test scenario. If no appropriate conditions are derived,a new vector sequence must be added to cover this fault.

It must be pointed out that if multiple two-vector sequencesexcite the same fault, finding a single case with a robust testscenario is sufficient, making it unnecessary to analyze the restof vectors. The analysis to check the possible occurrence oftest escapes is based on (3), which specifies the conditions forevery fault topology. At the end of this process, the patternfile obtained is optimized to cover the maximum numberof SOFs.



Fig. 16. Diagram flow to improve SOF coverage.

VIII. CONCLUSION

The continuous demand for better products requires high-quality tests and low escape rates, especially for safety criticalapplications. In present technologies, the intragate opens are animportant source of defects, most of which can be modeled asSOFs. The classical approach to the SOF detection, based ona two-pattern sequence, has proved to be effective for a widerange of technologies. However, this paper demonstrated thatSOF detectability decreases with technology shrinking becauseof the influence of leakage currents and downstream parasiticcapacitances. This was experimentally corroborated using adesign fabricated on a 65-nm technology.

Electrical simulations were carried out to analyze the testescape ratio of SOFs for different technology nodes. Theresults demonstrated that the dominant factor for at-speedtesting is downstream parasitic capacitances. These induce anonnegligible number of test escapes, which increase with

technology shrinking. The obtained escape ratios may beunaffordable, especially for critical applications where thelow DPPM values are demanded. Although the influenceof leakage currents is demonstrated to be insignificant forat-speed testing, their impact becomes preponderant if thefrequency is reduced at least one order of magnitude. Thisfact may be of interest in those cases where an increase oftotal test time is affordable.

Test strategy of the SOFs must be reviewed to extendtheir detectability in present and future technologies. In thisdirection, a proposal for the analysis of SOFs prone to thegeneration of test escapes was proposed. In critical cases,modification of the don’t care bits or even addition of newpatterns is required to assure the detectability of these SOFs.

ACKNOWLEDGMENT

The authors would like to thank NXP Semiconductors,The Netherlands, for providing the 90-nm technology andthe industrial circuit used as a basis for its scaled downversions.

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Daniel Arumí received the M.S. degree inindustrial engineering and the Ph.D. degreein electronic engineering from the UniversitatPolitècnica de Catalunya (UPC), Barcelona, Spain,in 2003 and 2008, respectively.

He is currently an Assistant Professor withthe Department of Electronic Engineering, UPC.His current research interests include defect-basedtesting, fault modeling, defect diagnosis, andsecurity in ICs.

Rosa Rodríguez-Montañés received the M.S.degree in physics from the Universitat de Barcelona,Barcelona, Spain, in 1988, and the Ph.D. degree inphysical science from the Universitat Politècnica deCatalunya (UPC), Barcelona, in 1992.

She has been an Associate Professor withthe Department of Electronic Engineering, UPC,since 1994. She spent her sabbatical leave withthe Test Group, Philips Research, Eindhoven,The Netherlands, in 2002. She is currently involvedin fault models, defect characterization, and defect

diagnosis of digital nanometric CMOS technologies.

Joan Figueras (M’88) received the M.Sc. andPh.D. degrees from the University of Michigan,Ann Arbor, MI, USA, and the Ph.D. degree from theUniversitat Politècnica de Catalunya (UPC),Barcelona, Spain.

He is currently with the Department of ElectronicsEngineering, UPC, where he has research andteaching responsibilities in the areas of electronicsand digital- and mixed-signal design and test.He has an extensive publication record, and haspresented seminars and tutorials in professional

meetings and NATO seminars on topics related to low-power design andquality in electronics. His current research interests include emerging topicsin low-power design and advanced test of electronic circuits and systems.

Dr. Figueras was an Associate Editor of the IEEE TRANSACTIONS ON

COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, andis an Editor of the Journal of Electronic Testing: Theory and Applications,and a member of the Steering and Program Committee of several Test andLow Power Design Conferences.

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