Design of Folded Cascode Opamp UsingPotential Distribution MethodRishi TodaniECE Dept.NIT DurgapurINDIA - 713209

Email: todani.rishi@gmail.com

Ashis Kumar MalECE Dept.NIT DurgapurINDIA - 713209

Email: akmal@ece.nitdgp.ac.in

Abstract—In this work, design of CMOS opamps using Poten-tial Distribution Method (PDM) is discussed. PDM is a newlyproposed device sizing technique for analog circuits based onvoltage distribution at different nodes. This technique is free fromcomplex mathematical expressions governing the devices and thecircuit. Instead of relying on analytical design approach, PDMdirectly utilizes the simulator as a device sizing tool to meet thetarget specifications. This is achieved by first designing the circuitwith moderate performance by logically or uniformly allocatingnode voltages and then modifying these node potentials to meetthe target specifications. PDM is also technology independentand can be applied to both, long and short channel devices. Afully differential folded cascode opamp is then designed usingPDM. Dependency of response of the opamp on different nodevoltages is discussed. It is shown how PDM can be employed tofine tune the opamp’s response to meet the specifications and thesimulation results are presented.

I. INTRODUCTION

Typically, analog designers first design any analog circuitwith pen and paper using some device model whose equationscan be manipulated with hand calculations [1]–[4]. Usuallythese models are based on long channel devices (SPICE level1 or 2). Once the device dimensions are obtained mathemati-cally, the designer implements the schematic on a simulator. Iftargeting fabrication, designer often uses state-of-the-art simu-lators which use an extremely complex and accurate deep sub-micron device models like BSIM3,4 etc. When this schematicis implemented on simulators, it is seen that the simulationresults do not match with mathematical expectations. It maybe mentioned that this error is primarily due to modelingof short channel devices with long channel equations. Thedesigner now adopts an ad-hoc mechanism, adjusts the devicedimensions and attempts to bring all transistors in saturationto meet the desired response from the circuit. The differencein predicted and final design values can be reduced if complexmodels like BSIM etc. are used while carrying out the designanalytically. To handle such complex equations, the designerseeks help of another simulator, optimizer or programmingmethod [5], [6]. Whatever may be the approach, the net timeto design any analog block increases, specially for circuitswith short channel devices. Moreover, such methods increasethe design complexity and makes the task difficult for novicedesigners.

Potential Distribution Method (PDM) [7], [8] is a technol-ogy independent approach which is free from mathematicalexpressions and can be applied to all kind of devices, bothlong and short channel. Being free from analytical models,even novice designers can design any analog block includingopamps with reasonably good performance and within a shortcycle of time. For designing a block, PDM directly utilizesa simulator as a device sizing tool to find out the devicedimensions. PDM also enables us to fine tune the block’sresponse as per the desired specifications. While designinga CMOS opamp, the designer often finds it difficult to keepthe transistors in saturation. It is to be mentioned that PDMinherently eliminates this problem and provides the sizes ofthe devices based on the saturation condition.In the following sections, principles of PDM is illustrated

and application of PDM in designing and fine tuning afully differential folded cascode opamp designed using UMC180 nm CMOS technology is demonstrated.

II. PRINCIPLES OF PDM

The first task of PDM is to stabilize the DC operating pointsof a circuit. Once a circuit with appropriate DC conditionsis ready, it is fine tuned to meet the target specifications. InPDM, the simulator is used to find the device dimensions ata pre-defined bias which are based on saturation condition.Thus, all transistors are in saturation even during the first DCsimulation. The process of PDM comprises of the followingsteps.

A. Initial Bias Conditions

Deciding the initial bias conditions for individual transistorsis the first step in PDM.

1) PDM starts by first choosing a schematic. For illustra-tion, a stacked transistor chain as shown in Fig. 1 isassumed. The process technology sets the supply leveland the minimum channel length of devices. Typicallyfor CMOS analog design, the length of all transistorsare set to 2 to 3 times the minimum channel length.As per application and accuracy requirement, a suitablesimulator is chosen. State-of-the-art simulators typicallyuse highly complex and accurate device model likeBSIM3, 4 etc.

Vout

Vin

VDD

Vb1

Vb2

Vb3

Vb4

u=0

u=1

u=2

u=0

u=1

v=n

v=p

v=n

v=n

v=p

A

B

C

Fig. 1. Cadcoded structure

2) In a cascoded structure, leaving the top and bottomtransistors, all other transistors are affected by bodybias. For threshold voltage estimation of these tran-sistors, a plot of body bias versus threshold voltage(|VBS | Vs. |VTH |) for NMOS and PMOS is generatedfor the chosen technology using the simulator.

3) For ease of illustration, all transistors are assigned au and v value. Where ′u′ is the number of transistorsbetween the chosen device and the supply rail (GND forNMOS and VDD for PMOS), and ′v′ denotes whetherthe device is of type NMOS or PMOS and takes notation′n′ or ′p′ respectively.

4) The nodes along the drain-source path are labelled in theschematic shown as A, B, C, etc. in Fig 1. Nodes whichare kept at known potentials like common mode levelare identified. Typically, the input and output terminalsare kept at common mode levels (VCM ) or at VDD/2.

5) The supply voltage is distributed along the drain-sourcepath of the transistor stack. Typically, this can beachieved by simply distributing the voltages evenlyabout the known node potentials. For the resulting bodybias, the (|VBS | Vs. |VTH |) plot is referred and thethreshold voltage of all transistors are estimated.

6) As per the threshold voltage of individual transistors, thegate drives are allocated. Gate voltage is chosen suchthat the overdrive is small (at around 5% of VDD). Thisallows adequate inversion with large gm and ro. Thisalso provides large input common mode range (ICMR)and output swing.

7) From power dissipation constraint and slew rate re-quirement, the drain current of all the transistors arecalculated. A complete database of all transistors, theirterminal voltages and their drain current is created.

B. Transistor Sizing

1) Transistors with u = 0 is selected as the starting point.The predefined terminal voltages are applied, and usingthe simulator the width of the device is found which

+−

+−

VDSVGS

ID

(a)

u=0v=n

v=n

v=nu=m

u=m-1

+−

+−

+−

+− VDC

VDC

VDC

VDC

(b)

Fig. 2. Sizing transistor with (a) u = 0 (b) u = m

sets the desired drain current. A sample circuit for atransistor with u = 0 and v = n is shown in Fig. 2(a). Asimilar circuit may be considered for u = 0 and v = ptransistors. As mentioned earlier, the length of all thedevices are fixed. Next, transistors with u = 1 is targetedand transistor with u = 0 of the same type is includedin its sizing schematic.

2) Generalizing the sizing algorithm, to find the width of atransistor with u = m, we draw a schematic comprisingof transistors with u = m, m−1, ..., 0, of either v = nor v = p, and connect them as in original schematic.We now apply only the end terminal voltages manually,i.e., for transistor with u = m, we apply the topmostdrain voltage if v = n or bottommost source voltage ifv = p and all the gate potentials. The intermediate drain-source nodes need not be biased since their potentials aregenerated by transistors with u = m− 1, m− 2, ..., 0which are already sized before sizing transistor withu = m. A sample schematic to estimate the size oftransistor with u = m is shown in Fig. 2(b).

3) Once all the transistor dimensions are known and fedinto the simulator, the entire circuit is simulated for DCoperating points. It would be seen that the transistors arecarrying the desired drain current and all the nodes haveachieved the predefined voltage levels. If node potentialsare selected based on saturation condition, all transistorswould be in saturation.

The first task of stabilizing the DC operating points is nowcomplete and the circuit is checked for AC response. PDMallows us to fine tune the opamps AC response to meet thetarget specifications.

C. Performance Tuning

In any analog circuit, the DC node voltages play a signif-icant role in deciding its response. The schematic is initiallybiased with all transistors in saturation and then the nodevoltages are adjusted to set the final operating points to meetthe desired response. It is to be noted that node voltages canonly be changed within a limit which keeps the transistors insaturation.

CMFBCircuit

VDD

VCMFB

vb1

vb2

vb3

vb4

A

B

C

D

M0 M1

M2

M3

M4

M6

M5

M7

M8 M9

M10 M11vb1

ITail

ITail

ITail/2

ITail/2

ITail/2

ITail

A′

B′

Vin+ Vin-Vout-

Vout+

Fig. 3. Fully Differential Folded Cascode Opamp

III. DESIGN OF A FULLY DIFFERENTIAL FOLDEDCASCODE OPAMP

A fully differential folded cascode opamp is shown in Fig. 3with nodes labelled as A, B, C, etc. In PDM, the first version ofthe opamp is designed without caring much about its response.Once a schematic with all transistors in saturation is ready,the bias conditions are tuned by resizing the transistors tomeet the target specifications. In this example, VDD = 1.8 V,VSS = 0 V = GND and the length of all transistors is takenas 500 nm.

A. Initial Bias Conditions

The initial bias conditions of the opamp may be decided bythe below mentioned steps.1) Current Constraint: As per the power dissipation con-

straint, the total current drawn from the supply is given by:

ITotal ≤Total Power Dissipation (Pdiss)

Supply Level (VDD)(1)

Referring to Fig. 3, typically in a folded cascode opamp it isassumed that 50% of the current flowing through M4 branchesat node A and enters the differential pair [9]. Thus, the tailtransistors, M2 and M3 carry the same current as M4 and M5.If ITail flows through M2, the total current drawn from supplycan be calculated by

ITotal = (2ITail) + ICMFB (2)

where ICMFB is the current drawn by the common modefeedback (CMFB) circuit. The current necessary to meet theslew rate requirement is given by

ITail ≥ Slew Rate (SR)× Load Capacitance (Cload) (3)

Therefore, it is seen that the tail current of the differentialpair is limited by the slew rate requirement on the lower sideand power dissipation on the upper side. Mathematically, thepossible range of ITail can be found by combining (1), (2)and (3) and can be given as:

0 0.2 0.4 0.6 0.8 1 1.2

450

500

550

600

650

700

750

Body Bias (V)

Thr

esho

ld V

olta

ge (

mV

)

NMOS

PMOS

Fig. 4. Effect of body bias for UMC 180 nm technology

SR× Cload ≤ ITail ≤1

2

(Pdiss

VDD

− ICMFB

)(4)

In this work, ITail = 30 μA is assumed. Once ITail is decided,ICMFB is calculated from (2).2) Node Voltage Distribution: The nodes to be kept at fixed

DC level are identified. For instance, in a single supply circuit,the input and output nodes are typically kept at common modelevel of VDD/2 = 0.9 V.The potential at node A (VA) is taken as the arithmetic mean

of known potentials above and below it. Similarly, potentialat node B (VB) is also set. Therefore, node A is kept at1.35 V and node B at 0.45 V.

VA = mean(VDD, Vout) = mean(1.8 V, 0.9 V) = 1.35 V(5)

VB = mean(Vout, GND) = mean(0.9 V, 0 V) = 0.45 V(6)

For the folded cascode opamp shown in Fig. 3, it is seenthat if potential at node C (VC ) and D (VD) are found usingthe same principle as VA and VB , the differential pair enterssubthreshold region. Transistors M0 and M1 experience a bodybias of VC , due to which their threshold voltage increasesand can be read from Fig. 4. The gate-source voltage fordifferential pair is (Vin − VC ). Care should be taken that thisgate-source drive is greater than its effective threshold voltage.If not, then a lower value for VC is to be taken.

Vin − VC ≥ VTH01; for VSB01 = VC (7)

For achieving large gm and ro the overdrive of all transistorsare kept low at around 5% of VDD .

VGS − VTH = Vov ≈ 5% of VDD (8)

It is known that for biasing transistors in saturation region, thedrain-source drop should be larger than its overdrive. For safeoperation, drain-source drop is kept around 5% of VDD aboveoverdrive.

VDS − Vov = 5% of VDD (9)

TABLE INODE POTENTIALS AT INITIAL DESIGN

Node Potential (V) Node Potential (V)

A, A′ 1.35 B, B′ 0.45

C 0.35 D 0.175

vb1 0.55 vb2 0.775

vb3 0.55 vb4 1.00

Vin+, Vin− 0.90 VCMFB 1.2

Vout+, Vout− 0.90 - -

Thus, combining (8) and (9), we conclude that minimum drain-source drop is given by:

VDSmin ≈ 10% of VDD (10)

Since VC accounts for drain-source drop of two transistors,M2 and M3, the lower limit of VC becomes:

VCmin ≈ 20% of VDD = 0.35V (11)

For a 1.8 V technology, it is seen that If VC = 0.35 V, thethreshold voltage of M0 and M1 is approximately 0.5 V. SinceVin = 0.9 V, Vov > VTH and thus M0 and M1 are on. ForVC ≥ 0.35 V, M0 and M1 enter subthreshold region. Thus(11) gives the potential at node C subjected to the conditionthat (7) holds true. For node D, we apply the mean principleas:

VD = mean(VC , GND) = mean(0.35 V, 0 V) = 0.175V(12)

Thus, node D is biased at 0.175 V. The complete set ofnode potentials is shown in Table I.3) Threshold voltage estimation: Once the node potentials

are allocated, the threshold voltage of all transistors are readfrom Fig. 4 for their corresponding body bias.4) Gate bias: As per the threshold voltages, gate biases

are allotted. Gate voltages are set such that the overdrive isaround 5% of VDD. This small overdrive keeps gm and rolarge. A large gm is particularly of interest for the differentialpair to achieve large DC gain. For transistors M6 throughM9, large gm and ro leads to larger output resistance. It isto be mentioned that smaller overdrive also gives wider inputcommon mode range (ICMR) and output swing at the cost oflarger device.

B. Transistor Sizing

Once the initial bias conditions are finalized, the transistorsizing procedure is begun.1) Tail Transistor M2 and M3: Transistor M3 experiences

zero body bias. Referring to Fig. 4 its threshold voltageis 0.45 V. For 5% overdrive, vb1 = 0.55 V is set. WithVD = 0.175 V, the width of M3 is found which setsID = 30 μA. Threshold voltage of M2 increases due to bodybias of VD . For 5% overdrive, vb2 = 0.775 V is set and thewidth of M2 is found for ID = 30 μA.

TABLE IIINITIAL RESPONSE

Performance Response

Parameter for Cload = 100 fF

DC Gain 63.01 dB

Rout 7.07 MΩ

gm01 200 μA/V2

ωpout 1.413 MHz

2) Differential Pair M0 and M1: With a body bias ofVC = 0.35 V, referring to Fig. 4, the differential pair havea threshold voltage of around 0.5 V. Gate-source drive of0.55 V leads to large gm and hence an increased DC gainas per

Av = gm01Rout (13)

where, Av represents voltage gain, gm01 is the transconduc-tance of differential pair and Rout is the output resistanceof the opamp. With these bias conditions, the width of thedifferential pair is found which sets ID = 15 μA.3) NMOS Transistors M8 through M11: M10 and M11 do

not see any body bias and with VB = 0.45 V, their width isfound for ID = 15 μA. Output resistance due to NMOS pathis given by:

Rn = ro89 + ro1011(1 + gm89ro89) (14)

For maximizing Rn, gm89 should be maximized. To achievethis, the overdrive of M8 and M9 is kept small at around 5%of VDD . Due to increased threshold voltage of M8 and M9,vb4 = 1 V and its width is found which sets ID = 15 μA.4) PMOS Transistors M4 and M5: Experiencing a zero

body bias, threshold voltage of M4 and M5 is 0.5 V. For anoverdrive of 5% of VDD , VCMFB is taken as 1.2 V. Theirwidths are thus found which causes ID = 30 μA.5) PMOS Transistors M6 and M7: Transistors M6 and M7

experience increased threshold voltage due to body bias asVA = 1.35 V. Output resistance due to PMOS path is givenby:

Rp = ro67 + ro45(1 + gm67ro67) (15)

To maximize Rp, gate overdrive of M6 and M7 is kept low at5% of VDD . For this vb3 is set to 0.55 V. With other knownterminal potentials, their widths are found for ID = 15 μA.Once all the device dimensions are known, the complete

opamp schematic is simulated. The node potentials as desiredare checked after DC simulation. The AC response of theinitial design with Cload = 0.1 μF is given in Table II.

C. Performance Tuning

It is observed that the response of opamp is significantlyaffected by the potentials at node A and B and the currentdistribution occurring at node A. Potentials at node C and Dare fixed and should not be changed due to the reasons dis-cussed earlier. A detailed study on the effect of the potentialsat node A and B on response of the opamp is carried out by

varying one node potential while keeping the other conditionsconstant. This range is set such that all transistors operate inthe saturation region. It is shown that by setting these nodepotentials appropriately, the specifications of the opamp canbe met.The output resistance of the opamp is given by

Rout = Rn||Rp (16)

where, Rn and Rp are given by (14) and (15). Rout can bemaximized by maximizing both, (14) and (15). As per (13),for maximum DC gain, both gm01 and Rout of the opampshould be maximized.The primary pole, which directly determines the bandwidth

of the opamp is given by

ωp(out) =1

Rout × Cload

(17)

Thus, for increasing the bandwidth, Rout must be reduced.The effect of node potentials and current distribution on theresponse of the opamp are now discussed.1) Potential at node A: As the potential at node A (VA) is

varied, the threshold voltage of M6 and M7 also vary. Thusvb3 is adjusted so as to keep the overdrive constant. This giveslarge gm67 at all times. Considering Vout = 50% of VDD andfor allowing minimum 10% of VDD drop for M4 through M7at all times, the possible range of VA becomes 10% of VDD

above Vout to 10% of VDD below VDD .

60% of VDD ≤ VA ≤ 90% of VDD (18)

In this example, VA is thus varied from 1.1 V to 1.6 V.2) Potential at node B: With the change in VB , vb4 must be

changed to keep overdrive constant. Using the same principleused to decide the range of VA, the possible range for VB

becomes 10% of VDD above GND to 10% of VDD belowVout.

10% of VDD ≤ VB ≤ 40% of VDD (19)

In this example, VB is thus varied from 0.2 V to 0.7 V.The effect of VA and VB can be illustrated using Fig. 5

to Fig. 9. Using Fig. 5, 6 and 7 the output resistance can beoptimized. From Fig. 7, values of VA and VB can be readto either maximize Rout for large DC gain or minimize Rout

for large bandwidth. VA and VB can also be read to achieve agiven Rout. Thus VA and VB can be selected to meet the targetspecifications. Table III lists the potential at node A and B formeeting the desired performance or achieving a trade-off.3) Current Distribution: Keeping the total current drawn

by the opamp constant, out of the current carried by M4, thepercentage of current entering the differential pair transistorafter branching from node A is varied. This however isdone with the lower limit set by the slew rate requirementas per (3). Fig. 10 depicts this effect and shows how theDC gain and bandwidth vary with the percentage of currententering differential pair out of current through M4. Typically,

1.11.2

1.31.4

1.51.6

0.20.3

0.40.5

0.60.7

0

0.5

1

1.5

2

2.5x 10

7

Potential at node APotential at node B

Out

put

resi

stan

ce c

ompo

nent

(N

MO

S P

ath)

Rn (

Ω)

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

2.2x 10

7

Maximum Rn

Fig. 5. NMOS path component in output resistance

1.11.2

1.31.4

1.51.60.2

0.30.4

0.50.6

0.70

0.5

1

1.5

2

2.5x 10

7

Potential at node APotential at node B

Out

put

resi

stan

ce c

ompo

nent

(PM

OS

path

) R

p (Ω

)

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

2.2

x 107

Maximum Rp

Fig. 6. PMOS path component in output resistance

as a trade-off between DC gain and bandwidth, design iscarried out such that 50% current enters differential pair andremaining flows into the load. This feature can be exploitedif the desired specifications are not met by choosing suitablepotentials at nodes A and B.

Table IV lists the drain-source voltage distribution ratio fortransistors M4 through M11 of a folded cascode opamp forperformance tuning.

1.11.2

1.31.4

1.51.60.2

0.30.4

0.50.6

0.70

2

4

6

8

10

12x 10

6

Potential at node APotential at node B

Out

put

Res

ista

nce

Rou

t (Ω

)

2

3

4

5

6

7

8

9

10

11x 10

6

Maximum Rout

Fig. 7. Output Resistance

1.11.2

1.31.4

1.51.60.2

0.30.4

0.50.6

0.745

50

55

60

65

70

Potential at node APotential at node B

Vol

tage

Gai

n (d

B)

48

50

52

54

56

58

60

62

64

66Maximum voltage gain

Fig. 8. Voltage gain

1.11.2

1.31.4

1.51.6

0.20.3

0.40.5

0.60.7

0

2

4

6

8

10x 10

6

Potential at node APotential at node B

Loc

atio

n of

pri

mar

y po

le (

Hz)

1

2

3

4

5

6

7

8x 10

6

Maximum bandwidth

Fig. 9. Location of primary pole due output node ωp(out)

10 20 30 40 50 60 70 80 90200

240

280

320

Ban

dwid

th (

KH

z)

Percentage of current entering differential pair transistor10 20 30 40 50 60 70 80 90

50

60

70

DC

Gai

n (d

B)

DC Gain

Bandwidth

Fig. 10. Effect of current distribution at node A

TABLE IIIBIAS POINT SELECTION TABLE FOR 1.8V TECHNOLOGY

VA VB DC Gain Rout ωpout Maximized

(V) (V) (dB) (MΩ) (MHz) Parameters

1.1 0.7 67.12 11.35 0.88 DC Gain & Rout

1.6 0.2 47.71 1.21 8.22 ωpout

1.35 0.45 63.01 7.07 1.413 Trade-off

TABLE IVVOLTAGE DISTRIBUTION AT NODES A AND B

Drain-Source Voltage Distribution Maximized

M4:M6 ; M8:M10 Parameters

7:2 ; 2:7 DC Gain & Rout

2:7 ; 7:2 ωpout

1:1 ; 1:1 Trade-off

IV. CONCLUSION

Potential Distribution Method (PDM) is an extremely simpledesign methodology for analog circuits. Besides being tech-nology independent it is also free from complex mathematicalexpressions. Analog designers with less experience can alsodesign opamps in short time using PDM. This methodology isnot only quick in designing complex opamp structures, but alsoprovide a mechanism for performance tuning. Being directlybased on the simulator, which uses state-of-the-the-art MOS-FET models like BSIM, the results obtained from this methodare highly accurate. In this work, a fully differential foldedcascode opamp is designed using PDM. Tuning capabilitiesfor meeting target specifications, like DC gain, bandwidth,output resistance etc. is shown. The opamp is realized usingUMC 180 nm CMOS process and the simulation results arepresented.

ACKNOWLEDGMENT

The authors gracefully acknowledge Dr. Debashis Datta,Ministry of Communication and Information Technology,Govt. of India, for extending the SMDP project at NIT Dur-gapur. Prof. S. K. Datta, ex-chair of SMDP at NIT Durgapuris heartily thanked.This paper would not have been possible without the support

of our parents, who allowed us to work overnight. Dr. Mal alsoacknowledges his teachers Late Sri. Kanai Lal Samui, Prof. R.Saran (IIT Kanpur) and Prof. S. K. Lahiri (IIT Kharagpur).

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