WELL TAPPING METHODOLOGIES IN POWER-GATING DESIGN

Kaijian Shi1 and David Tester2

Cadence Design Systems, Dallas, USA1 and Structured Custom, Cambridge, UK2 kaijians@cadence.com and david.tester@structured-custom.com

ABSTRACT

65nm and beyond CMOS designs are commonly implemented with “tapless” library cells which do not provide built-in n-well or substrate taps, improving cell density. This cell efficiency results in additional layout complexity for power-gating designs. Three well tapping methods are described for production power-gating designs considering design schedule, leakage power, chip area and complexity.

I. INTRODUCTION Tapless designs have been popular in 65nm and

beyond CMOS designs to increase cell density and silicon area efficiency. In tapless designs, the logic is implemented using cells which do not have built-in tap contacts connecting n-well and p-substrate to power and ground rails in the cells. To prevent latch-up and maintain proper transistor back biasing, tap cells which have built-in contacts to n-well and p-substrate are inserted in the layout at required intervals to connect n-wells to VDD and p-substrate to VSS, based on design rules defined in the technology DRC file. The n-wells of tapless logic cells extend out of the cell boundaries to ensure n-well connections when the cells are placed next to each other. Consequently, n-well and p-substrate regions of the logic cells are properly biased by power and ground supplies. through the tap cells insertedin the design..

The tap insertion becomes complicated in power-gating designs [1-6] where logic cells can be powered-off while power management (PM) cells, such as power switch cells, isolation cells, retention registers and always-on logic cells, must remain powered to maintain controllability and state retention within the design. For power-gating designs that implement header switches to shut off power supply, the main challenge is to maintain proper n-well bias in those logic cells that are powered-off and the PM cells that remain alive.

Three well tapping methods are described in this paper, addressing challenges in power-gating designs using tapless standard cells. The methods have been applied successfully to production designs meeting different design goals and priorities.

The first method implements always-on tap cells to keep n-well biased at VDD when the design operates in the shutdown mode, i.e. power gated.

The second method requires built-in taps in the PM cells to maintain well biasing of the PM cells when the design is in the shutdown mode.

The third method partitions the design into always-on and shut-down regions. The PM cells are placed exclusively in the always-on region to sustain required n-well biasing. Each method has advantages and shortcomings. The choice of method depends on the considerations and priorities on leakage power, silicon utilization efficiency and implementation complexity.

In the following part of the paper, the methods will be described in detail. Considerations for reliable production power-gating designs will be discussed. Overheads and tradeoffs will be explained. Next, the three methods will be compared in terms of impact on leakage power, silicon utilization efficiency and implementation complexity. Finally, recommendations will be provided for selection of a method based on design goals and priorities.

II. ALWAYS-ON TAP CELL BASED METHOD The first method provides dedicated power supply

to n-wells using the tap cells to keep n-wells of the design biased to VDD in shutdown mode. This requires an always-on tap cell, since the normal tap cells are not powered in the shutdown mode. A. Always-on tap cell vs. normal tap cell

The normal tap cell is a simple design (Fig. 1a) which has two metal contacts; one connects n-well to VDD rail and the other connects p-substrate to VSS. When the tap cells are inserted into a design, their VDD and VSS rails are connected, by abutment, to the power and ground network of the design to provide n-well bias. In the power-gating design, the power supply to VDD rails is shut-off in the shutdown mode. To maintain the power supply to the n-well, the n-well contact in the tap cell must be separated from the VDD rail and directly connected to the power supply. This design change is depicted in Fig. 1b resulting in the always-on tap cell where the n-well

tap becomes a pin that can be connecpower supply. The p-substrate is still VSS rail to maintain well bias as the VSconnected in the shutdown mode.

Figure 1 a) normal tap cell, b) always-o

B. Method description

For a single domain power-gatingalways-on tap cells are inserted at defined by the technology tapping run-well pins of the tap cells are routed always-on VDD supply network in the constant power supply. Since n-wells logic cells are overlapped with adjacenrow in the layout, forming continuing n-wrows, the n-wells of the logic cells are always-on VDD through the tap cells’ n-

The main advantage of the methosimple to implement, leveraging the etap insertion flow. It also results in utilization efficiency compared with odue to no additional well spacing requplacement. Moreover, it does not impoon PM cell placement which helps physHowever, the method incurs a leakage in the shutdown mode because n-wtransistors are biased at VDD while theto the transistors is shutoff. This createbias from n-well to drain and gate of pin higher junction and gate leakagConsequently, the shutdown mode design can increase up to 10 times technology nodes, Vth cell types and sswitch and logic cells. At smaller techthis causes a higher leakage penaltthinner tox and hence larger well leaother hand, lower Vth logic cells haleakage penalty because the reductiothreshold leakage from the reversed becomes more effective and the releakage makes the n-well leakage corelatively less effective. As we look to thon the transistor size ratio of the swcells, a smaller ratio results in larger ledue to lower shutdown voltage on the hence lower cell leakage and higher n-wis worth mentioning that the shutdown

ted to the chip connected to

SS rail remains

on tap cell

g design, the the intervals

les. Then, the to connect the design to get of the tapless

nt cells in each wells in the cell biased by the

-wells. od is that it is existing normal highest silicon

other methods, uirement in cell ose constraints sical synthesis. power penalty

wells of pMOS e power supply es a significant pMOS resulting ge in pMOS. leakage of a depending on

size ratio of the hnology nodes ty due to the akage. On the ave a smaller on of the sub-

back biasing elatively large

ontributing part he dependency witch and logic eakage penalty logic cells and well leakage. It voltage on the

logic never reaches close to switch cells are far from ideal ain 40nm node and beyond. Adetermined by IR-drop constraiof the design in normal opershows the leakage penalty biasing from SPICE simulation different technology nodes and switch to logic cells is 0.096.

Table I. Ioff in gated nwell vs

Node/Vth Ioff_well_off

(nA) Ioff

28HP/LVt 16.2 28HP/SVt 15.78 28HP/HVt 12.9 40LP/LVt 0.169

40LP/SVt 0.166 40LP/HVt 0.143 65LP/LVt 0.082 65LP/SVt 0.081 65LP/HVt 0.070

In power-gating designs wit

power gated power domains, thare inserted in the power gatedon domains, normal tap cells apower routing needed for aexample of the method implemdomain design is shown in Fidomain is always-on with normaligned to the rails. Always-on tin the rest of the design wconnected to the always-on VDD

III. TAP PM CELL BASED METFor leakage critical designs,

the always-on tap cell based mthe leakage target. In that case,off the power supply to the n-wcells are active in shutdown mPM cells must remain being functional. To address this isbased method has been develo

The method implements spcells containing built-in n-well their internal always-on power sn-well biased in shutdown momixed tap and tapless design wcells and rest of the logic cells ashutdown mode, the power suinserted in the tapless design re

ground because the and considerably leaky Also, the size ratio is nts and power density ration mode. Table 1

of always-on n-well of a small test case in Vth’s. Size ratio of the

s. always-on nwell f_well_on (nA)

Ioff_ratio

77.4 4.78 153.4 9.72 57.65 4.47 1.06 6.27

1.43 8.61 1.05 7.33

0.443 5.40 0.439 5.42 0.467 6.67

h both always-on and he always-on tap cells

d domains. For always-are use to avoid VDD always-on taps. An mented in a two power ig. 2. The bottom left mal tap cells inserted aps were implemented with tap n-well pins D straps next to them.

THOD the leakage penalty in

method might not meet , it is necessary to shut

well taps. However, PM mode so n-wells in the

biased at VDD to be sue, the tap PM cell ped. pecially designed PM

taps that connect to straps (Fig. 3) keeping de, This results in a

where PM cells are tap are tapless cells. In the upply to the tap cells egions is shut off which

Figure 2. Domain-based tap insertion e

in turn shuts off power to the n-well of ln-well of the PM cells is biased througto the always-on VDD, maintaining norm

Since n-well of the PM cells is surrounding n-well in the tapless loshutoff, the n-well of PM cells can no n-well in surrounding tapless cells. between PM cells and tapless cells mhot-well spacing rule defined in the teworth noting that the n-well of a textended beyond the cell boundary sotapless cells are overlapped forming awell. This tapless cell n-well extension wthe PM cell placed next to the taptherefore must be considered in the hocheck. Consequently, PM cells needspace at cell boundaries, consuming sproduction designs, cells are commonadjacent rows and n-wells of cells in theoverlap. This is leveraged in designincells to occupy both mirrored rows to hof the PM cell from the top and bottboundaries and hence eliminate needs spacing at top and bottom to improve aFig. 3 shows an example PM cell.

Only those PM cells that require pMto be active in shutdown mode need buFor those isolation-low cells which impdown nMOS at the output, there is no nversion cells, because pMOS transistornot contribute to the isolation in the shand so isolation-low cells can be taplessThe main advantage of the method ipower in shutdown mode, since n-wecells are not biased. Impact on implementation is much smaller than the

example

logic cells. The h internal taps

mal operation. biased while

ogic cells are longer overlap Well spacing

must satisfy the echnology. It is apless cell is n-wells of the continuous n-will intrude into less cell, and ot-well spacing d considerable silicon area. In nly mirrored on e mirrored rows ng the tap PM ide the n-wells tom of its cell of the hot-well

area efficiency.

MOS transistors uilt-in well taps. plement a pull-eed for the tap s of the cell do hutdown mode s. s low leakage

ell of the logic the physical

e always-on

Figure 3. Tap PM cell (

region based method describePM cells can be freely placed ilong as their always-on VDD pinalways-on power straps. Horequires custom PM cells and aright boundaries of the PM cellsilicon utilization efficiency consgating designs often implemeswitches, always-on buffers and

IV. ALWAYS-ON REGION BASThis method has been de

leakage penalty of the first metcustom tap PM cells in the secase, PM cells are all tapless insertion to maintain n-well biasof separating n-wells of the PMof the logic cells, placement regregions, are created exclusivealways-on region has its ownVDD rails separated from rails on-well of the cells in the regioalways-on VDD through tap region. These always-on regionchip based on the predictionpositions of the PM cellimplementation. In the physiccells are only allowed to be plaregions. An illustration example

The always-on regions are sand bottom regions are for switcthe right is where the output isoThe four regions in the middle oto place always-on repeaters.

Advantages of the method ain shutdown mode and no needtap PM cells. However, theconsiderable physical implem

double row)

ed in the next section. in optimal positions as ns can be routed to the owever, the method area wasted at left and is significant lowering siderably since power-

ent tens of thousands d isolation cells.

SED METHOD veloped to avoid the thod and the design of econd method. In this cells requiring tap cell

s. To address the need M cells from the n-wells gions, called always-on ly for PM cells. Each dedicated always-on

outside the region. The on is connected to the

cells inserted in the ns are placed cross the n of the needs and ls in the physical

cal synthesis, the PM aced in the always-on is shown in Fig. 4.

shown in red. The top ch cells. The region on

olation cells are placed. of the block are created

are low leakage power d to create the custom e method introduces mentation complexity.

Moreover, the region creation and phighly design dependent and difficultcould often result in lower silicon utilizaand negative impact on design timing an

Figure 4. Always-on region based m An always-on region can be create

exclusive region or a custom placemeformer case, a special filler cell not cois needed at region boundaries to sewells from outside. VDD rails in thassigned to the always-on VDD and srails outside of the region.

In practice, always-on region plannininitial physical implementation to scope cells are needed and where they shoAssuming PM cells can be clustered inalways-on regions are created and plasize and position requirements. To ensucan hold the required PM cells, always-often created larger than actually reduces silicon utilization efficiency.

Always-on regions also add placemeand obstructions, impacting placemenThis could result in sub-optimal physica

V. COMPARISON AND RECOMMENDEach method is appropriate for volu

designs and has advantages and shoralways-on tap cell based method implement with little impact on timing, silicon utilization efficiency at the expenpower.

The tap PM cell method is easy to ilittle impact on timing and routability. Icustom design of tap PM cells, thougrelatively easy to create by adding extending cell boundaries of the taplescells that are already available. It is fea

placement are t to predict. It ation efficiency nd routability.

method

d by either an ent site. In the ntaining n-well eparate the n-he region are separated from

ng is done after how many PM uld be placed. to regions, the

aced based on ure the regions -on regions are needed. This

ent constraints nt and routing. l synthesis.

DATION ume production rtcomings. The

is simple to routability and

nse of leakage

mplement with It does require h they can be well taps and ss version PM asible to reuse

timing models of the tapless PMhas minimal impact on funoverhead of the method is usua

The always-on region based complicated to implement and effect on the design. Moreovedesign timing and routability.varies with the quality of tplanning and could be signmethod does not introduce a requires development of custom

The choice of the method dgoals and priority in terms ofleakage power, schedule, adevelopment schedule and pepriorities than leakage power inalways-on tap based method other hand, for battery opeshutdown mode leakage is criticis less important, the tap PM cgood choice. In the case wherenot available to create the tap Pregion based method is an alter

VI. SUMMARY Three well tapping methods

to address the challenges in thedesigns. The methods aimplementation details. Each mand shortcomings which compared. The proper choice oon design goals and prioritieperformance, leakage power, dand silicon area. The methodsuccessfully to production powmeet different design goals and

REFERENCES [1] Kaushik Roy, Saibal Mukhopadhy

meimand, “Leakage current mechatechniques in deep-submicromeIEEE Vol. 91, no. 2, Feb. 2003

[2] M. Anis, S. Areibi and M. Elmasry,multi-threshold CMOS (MTCMOS)ICS, 2003

[3] Benton H Calhoun, Frank A Chandrakasan, “A leakage redistributed MTCMOS”, IEEE J. Sno. 5, May, 2004, pp. 818-826

[4] Kaijian Shi and David Howard, “SImplementation – Simple ConceOptimum”, Proc.. IEEE VLSI-DAT,

[5] David Flynn, Michael Keating, Rand Kaijian Shi , “Low Power Methon-Chip Design”, Springer, 2007

[6] Kaijian Shi, Zhian Lin, Yi-min JianSleep Transistor Insertion and PoIndustrial Power Gating DesignAcademy Publisher Vol. 3 No.3 M

M cells, as modification nctional layout. Area ally less than 5%.

method is much more less predictable in its

er, it often impacts the The area overhead the always-on region ificant. However, the leakage penalty, nor

m PM cells. depends on the design f design performance, and silicon area. If erformance are higher n shutdown mode, the is the choice. On the rated designs where cal and area efficiency

cell based method is a e design resources are PM cells, the always-on rnative method.

have been developed e tapless power-gating are described with

method has advantages are discussed and

of the method depends s in terms of design

development schedule, ds have been applied wer-gating designs to priorities.

yay, and Hamid Mahmoodi-anism and leakage reduction ter CMOS circuits”, Proc.

, “Design and optimization of ) circuits”, IEEE Trans. CAD-

Honore and Anantha P eduction methodology for Solid-State Circuits, vol. 39,

Sleep Transistor Design and pts Yet Challenges To Be April, 2006

obert Aitken, Alan Gibbons hodology Manual for System-

ng, Lin Yuan “Simultaneous ower Network Synthesis for ns”, Journal of Computer, March, 2008