IEEE SF Bay Area GRID MagazineMATLAB & Simulink for Design & Digital Signal Processing 12 week...

O c t o b e r 2 00 7 V i s i t u s a t w w w . e - G R I D . n e t P a g e 1

GRID.pdf

Vis i t us at e-GRID.netOctober 2007

CHAPTER MEETINGS

SCV-LEOS - 10/2 | Photonic Crystal Slab: a Tool for Manipulating Photons and Lightwaves - nanolasers, silicon photonics ... [more]

SCV-LEOS - 10/4 | Compact High-Repetition-Rate Soft X-ray Lasers - generation of soft x-ray beams on a table-top ... [more]

SCV-PSES+VTS - 10/6 | Tour: Military Vehicle Technology Foundation Collection - tanks, armored cars, other vehicles ... [more]

SCV-SPS - 10/8 | Overview of Multimedia Signal Processing on Multi-Core Processors - impact on developments ... [more]

SCV-EMC - 10/9 | The Four Most Confusing Principles In Signal Integrity And How Not To Be Confused - impedance, loss ... [more]

SCV-ED - 10/9 | Metal Catalyzed Silicon Nanowires: Growth and Devices - supplanting conventional electronics beyond CMOS ... [more]

SCV-CPMT - 10/10 | High Complexity, Low Cost 3D Sub-Systems as a Large-Scale BGA - blind/buried vias, higher speed materials... [more]

SCV-MTT - 10/11 | Recent Advances and Trends in Microwave Synthetic Instrumentation - minimizing rack space, costs ... [more]

WRRF - 10/13 | Northern California Robot Games - high school robotics competition; excitement of a varsity sport; no cost ... [more]

SCV-CAS - 10/15 | Full-Chip Electro-Thermal Simulation using Loosely Coupled Electrical and Thermal Simulators ... [more]

SF-PES - 10/15 | Cyber Security for the Electric Utility Industry - protect from intentional or unintentional cyber incidents ... [more]

SCV-Mag - 10/16 | Imaging Magnetic Surfaces with Atomic Resolution - spin-polarized scanning tunneling microscopy ... [more]

SCV-EMB - 10/17 | Surgery with the da Vinci Surgical System (Video) - 3D view of the surgical site ... [more]

SCV-PES+IAS - 10/17 | Power and Cooling Optimization Techniques for High Density Data Centers - compressing IT loads ... [more]

SCV-SSC - 10/18 | A 2x2 MIMO Baseband for High-Throughput Wireless Local-Area Networking (802.11n) - specs, results ... [more]

SCV-PACE - 10/19 | All-Day Career Workshop 2007 - help for those in transition: career experts from throughout the IEEE ... [more]

SCV-CE - 10/23 | Human-in-the-Loop Simulation at NASA Ames Research Center - vehicle controls, pilot training ... [more]

SCV-Rel - 10/24 | Formation of a Warranty Chain Management Institute and its Applicability for Reliability Engineers ... [more]

SCV-LEOS - 11/6 | Prospects for Ultra-Short-Reach Optical Interconnects: Bringing Light to the Chip - latest results ... [more]

SCV-EMC - 11/13| Experimental and Theoretical Analysis of Electromagnetic Shielding of Cables and Connectors ... [more]

SCV-CPMT - 11/14 | An Alternative Method for Manufacturing Robust Electronic Assemblies Without Solder - its future ... [more]

SCV-ComSoc - 11/14 | Advancements in Transcoding for Optimized Unified Group Communications ... [more]

SCV-CE - 12/4 | "TV 2.0" - Digital TV in the Networked Home - commercial and behavioral challenges ... [more]

Support our advertisers

MARKETPLACE – Services page 3

Assoc. Professor position page 11

Professional Skills Courses - Management Essentials, Influential Communication,

Interviewing, Presentation Skills [more]

Technical Skills Courses - Analog CMOS Integrated Circuit Design,

MATLAB for Digital Signal Processing [more]

Materials and IC/System Packaging Courses - Oct. 3 in San Jose - 7 half-day Courses [more]

Workshops

All-Day IEEE Career Workshop 2007 - Oct. 19 - San Jose Fairmont Hotel [more]

Upcoming Conferences

Oct 3-5: Int'l Electronics Manufacturing Techno-logy Symposium with the Advanced Packaging Materials Symposium - Holiday Inn San Jose [more]

Oct 8: OFDM Workshop - Santa Clara Univ - SCV ComSoc Chapter [more]

Oct 15-17: Int'l Symposium on Semiconductor Manufacturing (ISSM) - SC Marriott Hotel [more]

Oct 16-18: AdvancedTCA Summit - Santa Clara Convention Center [more]

Oct 21-26: Int'l Test Conference & Test Week - Santa Clara Convention Center [more]

Oct 22-24: 3D Architectures for Semiconductor Integra- tion and Packaging - Hyatt Regency S.F. Airport - Early Bird rates through October 1 [more]

Oct 25-26: RoboDevelopment Conference & Expo 07 - San Jose Convention Center [more]

Nov 4-8: Int’l Symposium for Testing and Failure Analysis - San Jose Convention Center [more

Nov 12-15:Printed Electronics USA 2007 - South San Francisco Conference Center [more]

Call for Papers: SEMI-THERM and ISQED

http://www.e-grid.net/docs/0710-wrrf.pdf

http://www.cpmt.org/iemt/

http://techventure.rti.org/fall2007/

http://www.semi-therm.org/

O c t o b e r 2 0 0 7 V i s i t u s a t w w w . e - G R I D . n e t P a g e 2

Your Networking Partner ®

October 2007 • Volume 54 • Number 10

IEEE-SFBAC ©2007

IEEE GRID is the monthly newsmagazine of the San Francisco Bay Area Council of the Institute of Electrical and Electronics Engineers, Inc. As a medium for news for technologists, managers and professors, the editorial objectives of IEEE GRID are to inform readers of newsworthy IEEE activities sponsored by local IEEE units (Chapters, Affinity Groups) taking place in and around the Bay Area; to publicize locally sponsored conferences and seminars; to publish paid advertising for conferences, workshops, symposia and classes coming to the Bay Area; and advertise services provided by local firms and entrepreneurs. IEEE GRID is published as the GRID Online Edition

residing at www.e-GRID.net, in a handy printable GRID.pdf edition at the end of each month, and also as the e-GRID sent by email twice each month to more than 24,000 Bay Area members and other professionals.

Editor: Paul Wesling IEEE GRID PO Box 2110 Cupertino CA 95015-2110 Tel: 408 331-0114 / 510 500-0106 / 415 367-7323 Fax: 408 904-6997 Email: edi tor@e-gr id.net www.e-GRID.net

From the editor . . . The IEEE has several “grades” of membership,

with most of us being classified simply as a “Member of IEEE.” Some percentage, though, are classified as “Senior Members.” What’s that all about, and how would you become a Senior Member? Why should you care?

I’ll answer the second part first. Becoming a Senior Member gives you some additional certification that you are skilled in the practice of engineering. This is useful especially when you are planning (or forced into) a career move: listing Senior Member on your resume and in letters lets others know that you are at a higher skill level. So, it enhances your career progression.

What exactly is a Senior Member? It’s someone who has at least 5 years of significant performance in the practice of engineering and reflects a higher level of professional maturity. This probably includes you!

Applying to become a Senior Member is straightforward, and can be done online at the IEEE’s website, where you can read more about it and get started. However, it requires references from three Senior or Fellow Members – how do you find other engineers who’ll be your references?

The best place to look is in your workplace or institution: ask others if they belong to the IEEE and, if so, are they Senior Members. If you attend local Chapter meetings, ask there; most will be quite willing to endorse you. Similarly, if there is a conference you normally attend, ask others (organizers, presenters) if they are IEEE Senior/Fellow members and if they would be a reference for you. Then follow up with a copy of your resume or background, and refer them to the online page where they can submit a simple endorsement. Upgrade this year!

Paul Wesling, editor

NOTE: This PDF version of the IEEE GRID – the GRID.pdf – is a monthly publication and is issued a few days before the first of the month. It is not updated after that. Please refer to the Online edition and Interactive Calendar for the latest information: www.e-GRID.net

DIRECTORS

Santa Clara Valley Fred Jones

Tom Coughlin

Oakland East Bay Bill DeHope

Victor Stepanians

San Francisco Sandra Ellis Dan Sparks

OFFICERS Chair: Tom Coughlin

Secretary: Bill DeHope Treasurer: Dan Sparks

IEEE-SFBAC PO Box 2110

Cupertino, CA 95015-2110

IEEE GRID


Patent Agent Jay Chesavage, PE

MSEE Stanford 3833 Middlefield Road, Palo Alto 94303

[email protected]

www.File-EE-Patents.com TEL: 650-619-5270 FAX: 650-494-3835

Do you provide a service? Would you like more inquiries?

• Access 25,000 engineers and managers • IEEE Members across the Bay Area • Monthly and Annual Rates available

Visit our Marketplace (page 3)

Download Rates and Services information: www.e-grid.net/docs/marketplace-f lyer.pdf

GRID.pdf

e-GRID

ANSYS Channel Partner

• Multiphysics, Multidisciplinary Engng • CFD, Stress, Heat Transfer, Fracture • Fatigue, Creep, Electromagnetics • Dynamics, Design Optimization • Linear/Nonlinear Finite Element Analyses

Ozen Engineering (408) 732-4665

[email protected] www.ozeninc.com

Professional Services Marketplace – [email protected] for information

Say you found them in our GRID MARKETPLACE

MET Laboratories

EMC – Product Safety

US & Canada

• Electromagnetic Compatibility • Product Safety Cert. • Environmental Simulation • Full TCB Services • Design Consultations • MIL-STD testing • NEBS (Verizon ITL & FOC) • Telecom • Wireless, RFID (BQTF & EPCglobal Test Lab)

Facilities in Union City and Santa Clara

www.metlabs.com [email protected] 510-489-6300

Valon Technology, LLC

valontechnology.com

[email protected]

RF and Wireless Product Design & Development

- System Engineering - Test & Measurement - Schematic Capture & PCB layout- Expert Witness

Redwood City (650) 369-0575

VOICE COIL MOTORS Design - Control - Fabricate - Test

J. Arthur Wagner, Ph.D. 1649 Fair Orchard Ave.

San Jose, CA 95125

[email protected] (408) 269-7044 (408) 206-3049 cell

Bernie Siegal

650-961-5900

[email protected] www.thermengr.com

Device Thermal Characterization Package Thermal Characterization Thermal Test Boards Thermal Test Equipment & Fixtures

IEEE-CNSV Consultants' Network

of Silicon Valley

Become a member Find a Consultant Submit a Project

CaliforniaConsultants.org

M E S OIn t eg r at io n

Let us help you integrate your product and get it into production • MEMS & Sensors Experts • Product Design ▪ R&D ▪ Failure Analysis • Medical Devices ▪ High-Volume Manufacturing • Experienced Consultants www.MesoIntegration.com

[email protected] TEL: 949.278.0275

mailto:[email protected]?subject=GRID_Inquiry:

http://www.File-EE-Patents.com/

http://www.metlabs.com/


http://www.valontechnology.com/



http://www.thermengr.com/

http://www.MesoIntegration.com/



http://www.ozeninc.com/

mailto:[email protected]/subject=GRID_Inquiry:

http://www.CaliforniaConsultants.org/

http://www.e-grid.net/docs/marketplace-flyer.pdf


Co-Sponsor: Santa Clara Valley Section, IEEE

Design of Radio Frequency Integrated Circuits 12 week course, T/TH 6:00PM-9:00PM (Starts: Oct 9) A balance of communications, physics and IC design. Includes high-speed amplifiers, LNA, Mixer, VCO, PA, PLL and other RF blocks.

Analog CMOS Integrated Circuit Design 12 week course, M/W 2:00PM-5:00PM (Starts Oct 15) A detailed review of the principles, concepts, and design methods used for current state-of-the-art analog circuits; common analog building blocks; more complex analog circuits. HSPICE simulations are used extensively to augment the text/lecture material. MATLAB & Simulink for Design & Digital Signal Processing 12 week course, M/W 6:00PM-9:00PM (Starts Oct. 22) Hands-on, from basic concepts in discrete time systems, filter design and implementation all the way to advanced concepts of multi-rate systems; balanced mix of theory and practice.

Discount of $40 for IEEE Members on 12-week courses.

October 3, 2007 Holiday Inn San Jose With the APM/IEMT Symposium (Oct. 4-5) Separate (non-symposium) registrations are

encouraged Internationally-known experts coming to

Silicon Valley -- Four Morning Courses:

Nanotechnology Applications in Packaging, Florin Ciontu, NanoSPRINT (France)

Implementing Flip Chip and WLP Technology, Peter Elenius, E&G Technology Partners

Advanced Packaging Technology Solutions for Today's Leading Edge Microelectronics, Charles B. Woychik, GE Global Research

Achieving High Reliability for Lead-Free Solder Joints - Materials Considerations, Dr. Ning-Cheng Lee, Indium Corp.

Upcoming 1- and 2-day Seminars:

Nov 8-9: Advanced Semiconductor Technology & Fabrication

Nov 13: Design-for-Yield & Design-for-Manufacturing - Principles and Challenges

Nov 15: Practical Considerations for Low Power Design Implementation in CMOS

Nov 16: ESD Design for Nano-Scale CMOS Technologies

Nov 29: Device & Interconnect Reliability in Advanced CMOS

Discount of $30 for IEEE Members on Seminars. Get more information:

www.svtii.com/SVTI-calendar.htm

Review all SVTI offerings: www.svti.org -- Three Afternoon Courses:

Polymers & Nano-Composites for Electronic and Photonic Packaging: Recent Advances in Materials and Processes, Prof. C.P. Wong, Georgia Institute of Technology

3-Dimensional Semiconductor Packaging & Integration, Charles E. Bauer, Ph.D., and Herbert J. Neuhaus, Ph.D., TechLead Corporation

Failure Modes & Analysis of Flip Chip Assemblies, Prof. Daniel Baldwin, Georgia Institute of Technology Sign up Today:

www.cpmt.org/scv/

Bring a full team! (Ask about team discounts)

SILICON VALLEY TECHNICAL INSTITUTE

Autumn Courses with labs

IEEE Professional Development Courses Full Day of Materials and IC/System Packaging Courses

http://www.svtii.com/SVTI-calendar.htm

http://www.svtii.com/

http://www.cpmt.org/scv/


RoboDevelopment is a multifaceted educational forum and trade show dedicated to addressing the technical issues involved with the design and development of commercial robotic products. The exposition hall provides attendees with hands-on access to the latest design and development solutions for producing mobile robotics and intelligent systems technology, while the keynotes and general sessions are specifically designed to impart to technical professionals the information they need to develop the next generation of personal, service and mobile robots.

TECHNICAL TRACKS • Design, Development and Standards • Tools and Platforms • Enabling Technology

KEYNOTE SPEAKERS Tandy Trower, Prgm Manager, Microsoft Robotics Group Paolo Pirjanian, President and CEO, Evolution Robotics Lloyd Spencer, CEO, Coroware Dan Kara, President, Robotics Trends

IEEE Professional Skills Courses

Management Essentials – Date/Time: Thurs/Fri Oct 11-12, 8:30AM – 4:30PM – Location: – Trimble Navigation, Sunnyvale

Fee: $600 for IEEE Members; $675 non-members

Influential Communication – Date/Time: Tuesday, Oct 16, 8:30AM – 4:30PM – Location: Exar Corporation, Fremont

– Fee: $375 for IEEE Members; $450 non-members

Interviewing and Hiring the Best Talent

- Date/Time: Thursday, Oct 18, 8:30AM – 4:30PM – Location: Tibco, Palo Alto


Getting Things Done Across Organizational Borders

– Date/Time: Friday, Oct 26, 8:30AM – 4:30PM – Location: Synopsys, Sunnyvale

– Fee: $375 for IEEE Members; $450 non-members

Improve your skills – register for one of these classes, or for others coming up this fall and winter. Bring a team!

TOPICS COVERED IN THE SESSIONS ●·The Robotics Engineering Design Process ●·Robot Types and Form Factors ●·Localization, Navigation and Mapping ●·Robotic Control Architectures ●·Hardware and Software Architectures for Robotic Systems ●·Machine Learning ●·Data Acquisition and Sensor Fusion ●·CAD/CAM Tools For Robotics Development ●·Software Development Kits and Modeling Tools ●·Operating Systems: Linux, Windows, MTOS, VxWorks, QNX, Others ●·Robotics Kits and Component Suppliers ●·Drive Trains - DC Motors, Servo Motors and Stepper Motors ●·Locomotion - Wheeled, Tracked and Legged Systems ●·Batteries and Power Systems ●·Manipulators and End Effectors … and more More information, and to register:

www.robodevelopment.com

Contact us for exhibiting information: Dan Kara, [email protected], 508-663-1500 x329

SCV Chapters, Engineering Management & Components, Packaging and Manufacturing Technology Societies

Conquering Overwhelm – Managing Life in the Fast Lane

– Date/Time: Tuesday Nov 6, 8:30AM – 4:30PM – Location: – Exar Corporation, Fremont


Mastering Your Presentation Skills – Date/Time: Thurs/Fri Nov 8-9, 8:30AM – 4:30PM – Location: – Trimble Navigation, Sunnyvale


Breakthrough Project Management – Date/Time: Thurs/Fri Nov 8-9, 8:30AM – 4:30PM – Location: – TIBCO Software, Palo Alto


For complete course information, schedule, and registration form, see our website:

www.EffectiveTraining.com

The International Technical Design and Development Event for the Personal, Service and Mobile Robotics Industry

October 25-26, 2007San Jose McEnery Convention Center

http://www.robodevelopment.com/?utm_source=utm_source%3Dieee&utm_medium=utm_medium%3Dbanner&utm_content=utm_content%3Dbannerlink&utm_campaign=utm_campaign%3Dieeebanner


http://www.effectivetraining.com/calendar.php?loc=local


Short Courses: Saturday, Nov 3 & Friday, Nov 9 Tutorials: Sunday & Monday, Nov 4-5 Sessions: Tuesday-Thursday, Nov 6-8 Exposition: Tuesday-Wednesday, Nov 6-7

Returning to San Jose, the heart of Silicon Valley, ISTFA’07 combines technical sessions, tutorials, an exhibition, and user group meetings with a focus on making the full experience a strong benefit for the attendee. The limited number of selected, high-quality papers only requires two tracks throughout the program, for good access.

16 Technical Sessions & Panel Discussions: • In-line Metrology and Inspection • Emerging Concepts • System Level Analysis • Optical Techniques • Failure Analysis Process • Circuit Edit for FA, FI, and Debug • Case Histories • SPM Techniques • Sample Preparation • Nano Probe • Yield Enhancement • Photon Based Techniques • Package and Assembly • MEMS • Metrology and Materials Analysis • Test • plus Poster Papers

47 Educational Tutorials – 10 All New! We continuously update the tutorial sessions with new and cutting-edge topics related to failure analysis. • Materials Characterization – Surface Analysis in Assembly • Materials Characterization for Failure Analysis • Failure Localization with Active and Passive Voltage Contrast in FIB and SEM • Failure Analysis Flow Decision Tree • The Role of the AFM in Yield and Failure Analysis • The Pivotal Role of AFP Nanoscale Failure Analysis • Introduction to and Reliability in MEMS Packaging • Analog Building Blocks: Circuits and Devices • Diagnosing Analog Circuits • Yield Basics for Failure Analysis including 300mm Water and Cu Technology (and more!)

4 Technology-Specific User Groups User Group meetings on Tuesday evening and Wednesday morning, to provide a convenient forum for users of a specific technique to meet, share ideas, and discuss relevant issues in a non-commercial environment. Planned topics this year:

• Finding the Defect • Getting Inside the Chip • Focused Ion Beam (FIB) Techniques • Characterizing the Defect

5 One-Day Pre- & Post-conference Short Courses: • EOS & ESD Basics: Principles and Applications to

Failure Analysis • Fault Isolation • Finance and Management of Failure Analysis:

Principles and Applications • Focused Ion Beam (FIB) Systems: FAQs,

Principles, and Applications • Scanning Probe Microscopy: Introduction and

Applications

2007 Keynote Address: “New Technology: Silicon Photonics Opportunity, Challenges & Applications,” Dr. Mario Paniccia, Director, Photonics Technology Lab, Corporate Technology Group of Intel Corporation Dr. Paniccia currently directs a research group with activities in the area of Silicon Photonics. The team is focused on developing silicon-based photonic building blocks for future use in enterprise and data center communications.

ISTFA is the best venue for learning new failure analysis techniques, challenges and directions. It also provides ample opportunities for you to participate and network through the question-and-answer periods, the user groups, the panel discussions, the exhibition, and the networking poster luncheon. Additional information is on the ISTFA web site:

www.ISTFA.org

Register online at:

www.istfa.org/registration

Discounted fees for EDFAS and ASM Members. Non-members of EDFAS receive a full year’s membership with their registration. Tutorials and Symposium-only registrations are available. To exhibit at ISTFA, please contact Kelly Thomas at

[email protected]

EDFAS General Membership Meeting Wednesday, November 7, 12:25-1:45 pm

The Electronic Device Failure Analysis Society (EDFAS) annual General Membership Meeting is open to all current members, as well as interested prospective members.

33rd International Symposium for Testing and Failure Analysis

November 4-8, 2007 San Jose Convention Center

http://www.ISTFA.org/

http://www.istfa.org/registration



The fourth annual Printed Electronics USA is aimed at product developers, end-users, researchers, scientists and venture capitalists. This event is the only one to cover all of organic and printed inorganic electronics. In particular, we look at routes to commercialization with views from major adopters. Companies from around the world will present their progress in this technology. Over 65 presentations from leading global companies, including Kovio, Hasbro, Sony, Samsung, LG Philips, STMicroelectronics, T-Ink, PARC, Plastic ePrint. Investment Summit: High-quality printed electronics investment opportunities and perspectives Visit the world’s biggest exhibition for printed electronics with 50 exhibition booths showing printed electronics in action. Special tours to see several Bay Area companies including Fujifilm Dimatix, the Organic Electronics Group at the University of California, and other facilities.

16th Annual International Symposium on Semiconductor Manufacturing

October 15 – 17, 2007

Marriott Hotel, Santa Clara

Technical. Informative. Advancing. ISSM is the industry's largest assembly of semiconductor manufacturing professionals dedicated to driving technology innovation and operational excellence within the industry.

Industry leaders will share ideas and collaborate on new models for semiconductor manufacturing that redefine the value chain and demonstrate new levels of agility and efficiency in meeting the needs of their customers. The ISSM 2007 Conference features presentations and posters from leading device manufacturers, suppliers, and academia worldwide.

Program topics for this year’s symposium include: • Manufacturing Strategy & Operations Management • Manufacturing Control & Execution • Process & Material Optimization • The Green Factory - The Role of Environment, Health, Safety • Advanced Process & Metrology Equipment • Supply Chain Integration • Yield Enhancement & Contamination Control • Design for Manufacturing • Factory Design & Automated Material Handling • Process & Equipment Control • Advanced Packaging & Test

Nov 12-15, 2007

South San Francisco Conference Center

Full technological analysis is given on all areas of printed electronics including logic/memory, displays, power, sensors, materials, and manufacturing technologies. Detailed presentations include device roadmaps, performance, precious material supply, costs, and impediments to overcome.

Masterclasses The four optional expert-led masterclasses are interactive consultancy sessions. At each masterclass you will have the chance to handle many samples, and take away printed copies of presentations. They will ensure you get the most from the conference and leave with answers to your questions.

• Introduction to Printed Electronics • Displays & Lighting • Printing Technologies • RFID & Its Progress towards Being Printed

For more information and to register:

www.idtechex.com/printedelectronicsusa07 ISSM 2007: Maximizing Operational Efficiencies

at the Leading Edge Keynote Speakers: • “One Touch” Supply Chain

Susan Graham Johnston, VP, Sun Microsystems, Inc. • Twelve Types of Innovation That Will Save Your Company

Rich Karlgaard, Publisher of Forbes • Optimizing Fab Performance

Michael Splinter, CEO, Applied Materials • Technology and the Equipment Industry

Nick Bright, Executive VP, Lam Research Corporation • Optimizing Memory Operations at the Leading Edge

Mark Durcan, COO, Micron Technology, Inc. • Challenges and Opportunities Facing the Semiconductor Industry

Jackson Hu, Chairman and CEO, UMC Corporation • Increasing the Role of Indirect Materials for Semiconductor

Manufacturing Susumu Kohyama, President and CEO, Covalent Materials Corp

• Less is More Paul Westbrook, Sr. Technologist, Texas Instruments

Financial Panel: • Financial Panel Discussion: Remaining Public? Or Going Private?

Moderated by Mihir Parikh and Frank Quattrone, Aquest Systems Panelists from Morgan Stanley, The Blackstone Group, Bear Stearnes

Register. Early bird discounts for both IEEE members and non- members thru Sept. 17. Visit the ISSM website at

www.ISSM.com

Reach your target audience. For sponsorship opportunities visit: www.issm.com/sponsorship.htm

Printed Electronics USA 2007 Converging Printing with Electronics: Commercializing the Technology Organic & printed inorganic electronics

http://www.idtechex.com/printedelectronicsusa07

http://www.ISSM.com/

http://www.issm.com/sponsorship.htm


The third annual AdvancedTCA Summit brings you 3

power-packed days of up-to-date information on the state of the Advanced Telecommunications Computing Architecture and MicroTCA, the emerging standard platforms for communications equipment. Subjects include hardware, software, design methods, applications, standards, interfaces, and market research.

Now is the time to learn how AdvancedTCA will revolutionize telecom applications. Learn about the new spec that can handle the latest processors, the newest interfaces, and the most demanding high-availability applications including routers, switches, security devices, access devices, base-stations and telephony systems.

Join Industry Leaders from: ENEA, Intel, Motorola, Freescale, Emerson, GE Fanuc, Kontron, Wind River, Xilinx, Altera, Alcatel-Lucent, RadiSys, Texas Instruments, IBM, Schroff, and others!

This year’s program is full of NEW and timely information you can use today to develop and optimize solutions! The program includes: • Half-day Tutorials on Next-Generation Converged

Networks • Sessions focused on Open Architecture and

Standards Based Integration • Software Development Best Practices • Workshops on 10-Gig Ethernet, COTS ecosystem,

executive-level views and more • NEW! Ask the Experts: Meet and Speak with Experts

Face to face! • Venture Capital in the Telecom Equipment Industry

with the Business Plan Contest

Keynote Talks: “Adapt or Die: How Modular Platforms Deliver Breakthrough Services,” Keate Despain, Director of Marketing, Modular Communications Platform Division, Intel “Communications Servers Come of Age,” Brian Karr, Strategic Marketing Manager, Motorola Embedded Communications Computing

“You're in the Navy Now! Can AdvancedTCA Break the Ice in Military Applications?” John Walrod, Assistant VP, SAIC Advanced Systems Division

“NEPs and the COTS Ecosystem,” Magnus Karlson, Expert on Open Systems Software Architecture, Ericsson AB

Summit topics include: High-availability systems Cooling System development Power distribution Backplane design System interfaces AdvancedMC modules Wireless applications IP telephony Ethernet equip. design Switch fabrics Hot-swapping Storage Software MicroTCA Platform management Carrier-Grade Linux

AdvancedTCA Summit Best of Show Awards

The AdvancedTCA Summit announces the 1st annual Best of Show Awards to be held at the upcoming AdvancedTCA Summit. This is the premier opportunity for industry recognition for the innovation of your company’s technology and how it is being used in the marketplace.

The Summit is open to everyone involved in the

design, development, integration, marketing, use, or support of telecommunications equipment, or related hardware, software, or services.

Save $300 – Register by October 12th!

Free registration for Exhibits and Open Sessions.

For full information:

www.advancedtcasummit.com

To Participate as a Sponsor or Exhibitor, please contact:

Rudy Gentry, Exhibit Sales Manager

Email: [email protected]

Leading the Way to New Standards-based Solutions

Santa Clara – October 16-18, 2007 Santa Clara Convention Center/Hyatt

http://www.advancedtcasummit.com/



www.isqed.org

CALL FOR PAPERS

Leading Design for Quality & Manufacturability™

Paper Submission Deadline: October 29, 2007 Acceptance Notifications: November 23, 2007 Final Camera-Ready paper: January 3, 2008

The International Symposium on Quality Electronic Design (ISQED) is a premier Design & Design Automation conference, aimed at bridging the gap between and integration of, electronic design tools and processes, integrated circuit technologies, processes & manufacturing, to achieve design quality. ISQED is the pioneer and leading international conference dealing with the design for manufacturability and quality issues front-to-back. ISQED spans three days, Monday through Wednesday, in three parallel tracks, hosting near 100 technical presentations, several keynote speakers panel discussions, workshops /tutorials and other informal meetings. Conference proceedings are published by IEEE and hosted in the digital library. Proceedings CD ROMs are published by ACM. In addition, continuing the tradition of reaching a wider readership in the IC design community, ISQED will continue to publish special issues in leading journals. The authors of high quality papers will be invited to submit an extended version of their papers for the special journal issues.

A pioneer and leading multidisciplinary conference, ISQED accepts and promotes papers related to the manufacturing, VLSI design and EDA. Authors are invited to submit papers in the various disciplines of high level design, circuit design, test & verification, design automation tools; processes; flows, device modeling, semiconductor technology, and advance packaging.

Papers are requested in the following areas:

1. Manufacturing, Semiconductor Process and Devices 1.1 Design for Manufacturability/Yield & Quality (DFM/DFY/DFQ) 1.2 Effects of Technology on IC Design, Performance, Reliability, and Yield (TRD)

2. Design 2.1 System-level Design, Methodologies & Tools (SDM) 2.2 Package - Design Interactions & Co-Design (PDI) 2.3 Robust & Power-conscious Devices, Interconnects, and Circuits (PCC) 2.4 Emerging/Innovative Process & Device Technologies and Design Issues (EDT) 2.5 Design of Reliable Circuits and Systems (DFR)

3. EDA/CAD 3.1 EDA Methodologies, Tools, Flows & IP Cores; Interoperability and Reuse (EDA) 3.2 Design Verification and Design for Testability (DVFT) 3.3 Physical Design, Methodologies & Tools (PDM)

Submission of Papers

Paper submission must be done on-line via the conference web site at www.isqed.org. Authors should submit FULL-LENGTH, original, unpublished papers (Minimum 4, maximum 6 pages) along with an abstract of about 200 words. Please check the as-printed appearance of your paper before uploading. To permit a blind review, do not include name(s) or affiliation(s) of the author(s) on the manuscript and abstract. The complete contact author information needs to be entered separately. The guidelines for the final paper format are provided on the conference web site at www.isqed.org. Authors of the submitted papers must register and attend the conference for their paper to be published.

http://www.isqed.org/




ITC, the cornerstone of TestWeek™, is the world's premier conference dedicated to the electronic test of devices, boards and systems-covering the complete cycle from design verification, test, diagnosis, failure analysis and back to process and design improvement. At ITC, test and design professionals can confront the challenges the industry faces, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment suppliers, designers, and test engineers.

With the theme "Facing Nanometer-Technology Test Challenges," the 2007 conference will focus on breakthrough ideas to address the challenges of providing high-quality, cost-effective tests for nanometer-technology designs.

Keynote and Invited Addresses Managing Test, Yield, Quality, and Cost in the Fabless

Manufacturing Model, Chris Malachowsky, NVIDIA Fellow and Senior Vice President

The Impact of Globalization on Test and the Test Engineer, Greg Jordan, Sr. Director, Manufacturing Test Engineering, Cisco Systems, Inc.

On the Need for Convergence Between Design Validation, Siva Yerramilli, General Manager, Design and Technology Solutions Manufacturing Group, Intel Corporation

It's Not What You Can Make – It's What You Can Test, Robert Daasch, Professor, Electrical and Computer Engineering, Portland State University

Welcome Reception Tuesday, Oct. 23, 6:15 - 8:00 PM, Hyatt Regency Hotel

World-Class Exhibits Tuesday 10:30 AM – 4:00 PM

Wednesday 9:30 AM – 5:30 PM Thursday 9:30 AM – 2:00 PM

Free exhibits-only admission on Wednesday afternoon and all day Thursday.

Free Parking at the Santa Clara Convention Center

Sunday Full-day Tutorials DFX: The Convergence of Yield, Manufacturing, and Test Delay Testing: Theory and Practice Statistical Screening Methods Targeting “Zero Defect” IC

Quality and Reliability Dealing with Timing Issues for Sub-100-nm Designs – from

Modeling to Mass Production Practices in Analog, Mixed-Signal and RF Testing Test Strategies for System-in-Package Memory Test Challenges – A Practical and Implementation

View of BIST and Other DFT Techniques Digital Timing Measurements – From Scopes and Probes to

Timing and Jitter

Monday Full-day Tutorials IEEE 1500 – Building a Compliant Wrapper Delay Test: A Practical Approach Advanced Memory Testing Scan Compression Techniques: Theory and Practice Wafer Probe Test Technology Design-for-Manufacturability Understanding Failure Mechanisms and Test Methods in

Nanometer Technologies Design-for-Testability for RF Circuits and Systems

33 Technical Sessions ● Microprocessor Test ● Improving Test Quality ● Memory Testing ● New SERDES Test Techniques ● Getting Accustomed to Unknowns ● SOC Test ● Advanced Diagnosis Algorithms ● Breaking the 10-Gb/s Barrier ● Advances in ATPG and Delay Test ● HF in Volume Production ● Advanced Characterization Methods ● Power-aware Testing ● New Advances in Detecting PCBA ● Structural Defects ● Towards More Efficient Defect Diagnosis ● New Tests for PLLs ● Test and Debug Data Reduction ● Advances in DFT ● Functional and Outlier Test ● Characterization with Delay Test, IDDQ and Probing ● The New ATE: Protocol-aware ● Fault Simulation ● RF Test Methods ● Fault and Error Tolerance in Nanotechnologies ● System Issues with Test ● Defect Tolerance in Microprocessors … and more

Friday All-day Workshops ● Design-for-Manufacturability and Yield ● Current- and Defect-based Testing ● Automated Test Equipment Vision 2020

Download the full Advance Program today:

www.itctestweek.org

Exhibit at ITC! Contact Jim Monzel, IBM, [email protected]

http://www.itctestweek.org/



SCV Chapter, IEEE Communications Society

Orthogonal Frequency-Division Multiplexing (OFDM) implementation and Cross-layer Optimization have become topics of intense research interest in companies and universities around the world. Come to the OFDM Workshop at Santa Clara University to share your ideas in these areas or just to catch up. This year’s workshop contains eight outstanding industrial and academic speakers. Speakers

• Babak Daneshrad, UCLA • Alan Gatherer, Texas Instruments • George Ginis, ASSIA • Mike Fitz, Northrup Grumman • Ayman Naguib, QualComm • Milica Stojanovich, MIT • Lee Swindlehurst, ArrayComm • Steve Weinstein, Consultant

.

SCU Institute for Communications Circuit Design Plenty of free parking; lunch/reception provided.

$125 if pre-registered ($112 for IEEE members)

To get full information and the registration packet, please visit our website:

iccd.engr.scu.edu

OFDM Workshop Monday October 8, 2007 Santa Clara University, Santa Clara

UNIVERSITY OF CALIFORNIA, SANTA CRUZ COMPUTER ENGINEERING

Associate/Full Professor

The Computer Engineering Department, UC Santa Cruz, invites applications for a faculty position:

Position #808: The Computer Engineering Department invites applications for a tenured (Associate or Full Professor) position in Autonomous Systems. Potential areas of specialization include robotics, control, mechatronics, and assistive technology. The department is launching an initiative in autonomous systems and mechatronic engineering, and seeks an individual to join our core faculty in this area and lead the development of new research and degree programs.

MINIMUM QUALIFICATIONS: Ph.D. in Computer Engineering, Mechanical Engineering, Electrical Engineering, or related field; demonstrated excellence in innovative research; a strong record of publications; proven distinction in university teaching at the graduate and undergraduate levels; and a proven track record for securing extramural funding.

MORE DETAILS: www.soe.ucsc.edu/jobs, Position #808. To ensure full consideration, applications must arrive by Jan. 1, 2008. EEO/AA/IRCA Employer.

Submit: CV, statement of research and teaching plans, URLs of selected reprints, and names of three people who are willing to write letters of recommendation, by Jan. 1, 2008. We prefer electronic applications: www.soe.ucsc.edu/jobs/faculty/apply. Alternatively, applications may be mailed to: Computer Engineering Search Committee, University of California, 1156 High Street MS: SOE3, Santa Cruz, California 95064.

Clearly indicate position: #808 (Associate/Full Professor, Assistive Technology). UCSC is the UC campus nearest to Silicon Valley and has close research ties with the local industry. For

further details about the Baskin School of Engineering at UCSC, see www.soe.ucsc.edu

http://iccd.engr.scu.edu/

http://www.soe.ucsc.edu/jobs

http://www.soe.ucsc.edu/jobs/faculty/apply

http://www.soe.ucsc.edu/


Photonic Crystal Slab: a Tool for Manipulating Photons

and Lightwaves Speaker: Prof. Toshi Baba, Yokohama National

University, Japan, and IEEE LEOS Distinguished Lecturer

Time: Networking and Food: 7:00 PM, Presentation: 8:00 PM

Cost: donation for refreshments Place: National Semiconductor Building E

Conference Center, 2900 Semiconductor Drive, Santa Clara

RSVP: by email to [email protected]

Web: www.ewh.ieee.org/r6/scv/leos

Toshihiko Baba received the bachelor degree, master degree, and Ph.D. degree (Dr. of Engineering), In 1985, 1987 and 1990, respectively, all from the Department of Electrical and Computer Engineering, Yokohama National University, Japan. In 1990, he joined the Tokyo Institute of Technology, Precision and Intelligence Laboratory, as a research associate. He became a lecturer in 1993, an associate professor in 1994, and a full professor of Yokohama National University.

Through his Ph.D. program, he studied anti-resonant reflecting optical waveguides (ARROWs) including ARROW-“B”, a 3D integration for optical printed circuit boards and a bias sputtering technique for the monolithic integration of WDM filters. When he moved to Tokyo Institute of Technology, he started research on spontaneous emission control in microcavities and vertical cavity surface emitting lasers (VCSELs). In 1991 he reported the calculation of spontaneous emission factor in VCSELs. In 1993 he achieved the first room-temperature continuous wave (cw) operation of VCSELs for fiber communications using circular planar buried heterostructure epitaxy and a high Q dielectric cavity with Si/MgO thermal conductive mirror. Currently, his main interests are photonic crystals and nanocavities. Recently, his research also focuses on optical interconnection based on Si photonic wire waveguides, free space optical computing systems with novel smart pixels, and micro-electro-mechanical system devices.

Semiconductor photonic nanostructures, i.e. photonic crystals (PCs) and high index contrast structures (HICs), have become worldwide topics in this decade. They strongly control light emission and propagation, and so allow novel phenomena and device applications. Particularly in these years, they were discussed with various topics, e.g., nanolaser, slow light, negative index optics, and Si photonics. This presentation shows some of our recent activities on these technical areas.

In 1997, he realized the smallest laser diodes so

far reported and achieved the record low threshold operation in the longer wavelength range using the microdisk cavity. Now he holds the world record low threshold of 40 mA by current injection and 11 mW by photo-pumping in this wavelength range at room temperature under cw conditions. In 1999, he successfully observed the light propagation in photonic crystal waveguides, for the first time. He also reported various activities on photonic crystals including light emitters, filters, slow light devices, nonlinear devices, numerical simulations, etc.

He is a member of IEICE, JSAP, IEEE/LEOS, AIP/APS, OSA and IEE. He has been the author of more than 100 journal papers, a short course lecturer on photonic crystals at the LEOS Annual Meeting from 2003-2005 and invited speaker at more than 50 international conferences. He received The Niwa Memorial Prize in 1991, The Encouragement Award and The Paper Award, both from IEICE in 1994, the Best Paper Award from the Microoptic Conference in 1993 and 1999, and the Marubun Research Encouragement Award in 2000.

TUESDAY October 2SCV Lasers and Electro-Optics


Compact High-Repetition-Rate Soft X-ray Lasers on a Table-Top

Speaker: Prof. Jorge Rocca, Colorado State

University, and IEEE LEOS Distinguished Lecturer

Time: Networking and Food: 7:00 PM, Presentation: 8:00 PM

Cost: donation for refreshments Place: SPECIAL LOCATION: with IEMT

Symposium at the Holiday Inn San Jose, 1740 North First St, San Jose



Jorge J. Rocca is a Professor in the Departments of ECE and Physics at Colorado State University. He is also the director of the National Science Foundation Engineering Research Center for Extreme Ultraviolet Science and Technology. His research interests are in the development and physics of compact EUV and Soft X-Ray lasers, and their applications. He has conducted research and published more than 100 papers in peer review journals in topics related to short wavelength lasers and plasmas. In 1994 his research group demonstrated large EUV laser amplification in a discharge-created plasma, result that lead to the development of the first high average power tabletop coherent source in this spectral region. He was a National Science Foundation Presidential Young Investigator for 1985-1990. He is a Fellow of the Optical Society of America and of the Institute of Electrical and Electronics Engineers, and a Member of the American Physical Society. He has served as Associate Editor of the IEEE Journal of Quantum Electronics and Guess Editor of the IEEE Journal of Selected Topics in Quantum Electronics.

This talk will review recent advances in high

repetition rate soft x-ray lasers that allow the generation of very high brightness soft x-ray beams using table-top set ups. The peak spectral brightness of some of these new lasers can surpass that of third generation synchrotrons by orders of magnitude in the 25-100 eV photon energy region, enabling new applications. These advances include the demonstration of 5 Hz repetition rate table-top soft x-ray lasers producing intense beams at wavelengths ranging from 13.2 to 32.6 nm, and the observation of lasing at wavelengths down to 10.9 nm. The results were obtained by collisional electron impact excitation of highly ionized atoms in dense plasmas efficiently heated with picosecond optical laser pulses of only 1 J energy. In a separate development, the first of a new generation of extremely compact desk-top size capillary discharge soft x-ray lasers was demonstrated. It emits intense pulses of wavelength 46.9 nm light at 12 Hz repetition rate producing an average power of ~ 0.15 mW. The laser occupies a table area of about 0.4 x 0.4 square meters.

These new compact lasers are allowing a number of table-top experiments with intense soft x-ray light. These include the demonstration of broad area imaging with resolution down to 38 nm, nanoscale ablation of material, single photon ionization spectroscopy of molecules and nanoclusters, the metrology for the fabrication of the future generations of microprocessors using extreme ultraviolet lithography, and the diagnostics of dense plasmas by soft x-ray laser interferometry. Moreover the compact size of these new laser sources promises to make intense coherent soft x-ray light widely available, opening doorways to intense coherent soft x-ray science experiments on a table-top and to the development of new nanoscale metrology and processing tools for industry.

THURSDAY October 4SCV Lasers and Electro-Optics

MET Laboratories

EMC – Product Safety

US & Canada

• Electromagnetic Compatibility • Product Safety Cert. • Environmental Simulation • Full TCB Services • Design Consultations • MIL-STD testing • NEBS (Verizon ITL & FOC) • Telecom • Wireless, RFID (BQTF & EPCglobal Test Lab)

Facilities in Union City and Santa Clara

www.metlabs.com [email protected] 510-489-6300


Tour: Military Vehicle Technology Foundation Collection

Time: 10:00 AM Cost: none; limited to first 25 people, with

priority to PSES and VTS members Place: Portola Valley RSVP: by email to Gary Eldridge,

[email protected], to reserve a spot and receive instructions

Web: www.e-grid.net/docs/0710-scv-pses+vts.pdf

We are pleased to announce a very special fall

event! Join us on October 6 (Saturday) at 10:00 AM for a specially arranged private tour of the MVTF (Military Vehicle Technology Foundation) located in Portola Valley. This will be a rare opportunity to see one of the largest and most significant privately held collection of tanks, armored cars, and other military vehicles from around the world.

SATURDAY October 6SCV Product Safety Engineering + Vehicular Technology


Overview of Multimedia Signal Processing on Multi-Core Processors

Speaker: Yen-Kuang Chen, Ph.D., Principal

Engineer, Intel Corporation Time: Fast Food & drinks at 6:30 PM, Presentation

at 7:00 PM Cost: $2 donation for refreshments Place: National Semiconductor (north end of

Building E), 2900 Semiconductor Dr., Santa Clara

RSVP: not required Web: www.ewh.ieee.org/r6/scv/sps

Dr. Yen-Kuang Chen is a Principal Engineer at Intel Corporation. His research interests include developing innovative multimedia applications, studying the performance bottleneck in current computers, and designing next generation microprocessor/platforms --- including next-generation many-core processors. In particular, he is currently analyzing emerging multimedia applications and providing inputs to the definition of next-generation CPUs and GPUs with many cores. He received his Ph.D. from Princeton University. He has 10+ US patents, 25+ pending patent applications, and 75+ technical publications. He is one of the key contributors to Supplemental Streaming SIMD Extension 3. As an expert in video compression and computer architecture for emerging applications (e.g., SIMD and multi-threading), he was an invited speaker at the 2005 Emerging Information Technology Conference, 2005 New Technology Business Opportunities Forum, 2004 Sino-American Technology & Engineering Conference, and 2003 Workshop on Media and Signal Processors for Embedded Systems and SoCs. He is an associate editor of the Journal of VLSI Signal Processing Systems (including a special issue on "Multi-core Enabled Multimedia Applications & Architectures") and of IEEE Transactions on Circuits and Systems I.

This talk gives a basic overview of multi-core

processors, which represent a major development in computing technology recently. Traditionally, increasing clock frequency is one of the main dimensions for conventional processors to achieve higher performance gains. Today, increasing clock frequency has reached a point of diminishing returns — and even negative returns if power is taken into account. Multi-core processors, also known as chip multiprocessors (CMPs), promise a power-efficient way to increase performance and become prevalent in vendors' solutions – for example, IBM CELL Broadband Engine processors, Intel Core 2 Dual processors, Sun UltraSPARC T1 processors, and so on. Furthermore, placing many powerful computing cores on a single processor opens up a world of important possibilities for next-generation multimedia signal-processing applications and algorithms. Soon we would expect processors with tens or hundreds of cores, e.g., Nvidia Tesla platforms and Intel's 80-core research prototype. However, the trend of multi-core processors brings a paradigm shift in applications development. In order to fully explore the potential of many-core CPUs, GPUs, and DSPs, researchers and application developers must think about parallelism creatively. This talk will also discuss related challenges in application developments, especially focusing on multimedia signal processing applications.

Biography (continued) He has served as a program committee member of

20+ international conferences and workshops on multimedia, video communication, image processing, VLSI circuits and systems, parallel processing, and software optimization. As a Senior Member of IEEE, he is interested in bringing the awareness of the trends and the challenges of the many-core era to the signal processing society. For example, in ICME 2006 and ICME 2007, he organized the special sessions on "Processors and Multimedia" and "Multi-Core Enabled Multimedia Applications and Standards." In ICASSP 2007 and ICME 2007, and he gave tutorials on "Multimedia Signal Processing on Personal Computers."

MONDAY October 8SCV Signal Processing


The Four Most Confusing Principles In Signal Integrity And

How Not To Be Confused Speaker: Dr. Eric Bogatin, President, Bogatin

Enterprises, LLC Time: Social and Dinner at 5:30 PM,

Presentation: 6:30 PM Cost: none Place: Applied Materials Bowers Cafeteria, 3090

Bowers Ave., Santa Clara RSVP: not required Web: www.scvemc.org

Dr. Eric Bogatin received his BS in physics from MIT and MS and PhD in physics from the University of Arizona in Tucson. He has held senior engineering and management positions at Bell Labs, Raychem, Sun Microsystems, Ansoft and Interconnect Devices. He has written 4 books on signal integrity and interconnect design and over 200 papers. His latest book, Signal Integrity- Simplified, was published in 2004 by Prentice Hall. He has taught over 4,000 engineers in the last 20 years. Many of his papers and columns are posted on the www.BeTheSignal.com web site.

The words we use often affect our intuition and

how we think about concepts. In signal integrity we use some words either incorrectly or without enough qualifying and this confuses our intuition. In this lecture we look at four concepts at the heart of signal integrity problems: impedance, inductance, differential signals and loss. We look at why they are confusing and then the right way of using the terms to help feed our intuition for the important concepts.

TUESDAY October 9SCV Electromagnetic Compatibility

ANSYS Channel Partner

• Multiphysics, Multidisciplinary Engng • CFD, Stress, Heat Transfer, Fracture • Fatigue, Creep, Electromagnetics • Dynamics, Design Optimization • Linear/Nonlinear Finite Element Analyses

Ozen Engineering (408) 732-4665

[email protected] www.ozeninc.com


Metal Catalyzed Silicon Nanowires: Growth and Devices

Speaker: Ted Kamins, HP Labs Time: Social at 6:00 PM; Presentation at 6:15 PM Cost: none Place: National Semiconductor Corp. Building E-1

- Auditorium CMA, 2900 Semiconductor Drive, Santa Clara

RSVP: not required Web: www.ewh.ieee.org/r6/scv/eds

Ted Kamins is Principal Scientist in the Quantum Science Research group at Hewlett-Packard Laboratories in Palo Alto, where he is conducting research on advanced nanostructured electronic materials and devices. He is also a Consulting Professor in the Electrical Engineering Department at Stanford University. He received his degrees from the University of California, Berkeley. He then joined the Research and Development Laboratory of Fairchild Semiconductor, where he worked with epitaxial and polycrystalline silicon before moving to Hewlett-Packard, where he has worked on numerous semiconductor material and device topics.

Ted is co-author with R. S. Muller of the textbook "Device Electronics for Integrated Circuits" and is author of the book "Polycrystalline Silicon for Integrated Circuits and Displays." He is a Fellow of the IEEE and a Fellow of the Electrochemical Society.

Metal-catalyzed, self-assembled, one-dimensional semiconductor nanowires grown by chemical vapor deposition are being considered as possible device elements to augment and supplant conventional electronics and to extend the use of CMOS beyond the physical and economic limits of conventional technology. Such nanowires can create nanostructures without the complexity and cost of extremely fine-scale lithography. The well-known and controllable properties of silicon make silicon nanowires especially attractive. Easy integration with conventional electronics will aid their acceptance and incorporation.

The diameter of the nanowires depends on the size of the nanoparticles, which in turn can be controlled by varying the amount of catalyst deposited and the annealing conditions. The nanowires make good electrical connection to the substrate on which they are grown. They generally grow epitaxially along <111> directions. Connections can be formed to both ends of a nanowire by growing it laterally from a vertical (111) surface formed by etching the top Si(110) layer of a silicon-on-insulator structure into isolated electrodes. When the nanowire impinges on a second surface, it makes good mechanical and electrical connection to the second surface.

Field-effect structures are one class of devices that can be readily built in silicon nanowires. Because the ratio of surface to volume in a thin nanowire is high, conduction through the nanowire is very sensitive to surface conditions, making it effective as the channel of a field-effect transistor or as the transducing element of a gas or chemical sensor. As the nanowire diameter decreases, a greater fraction of the mobile charge can be modulated by a given external charge, increasing the sensitivity. Having the gate of a nanowire transistor completely surround the nanowire also enhances the sensitivity. For a field-effect sensor to be effective, the charge must be physically close to the nanowire so that the majority of the compensating charge is induced in the nanowire and so that ions in solution do not screen the charge. Because only induced charge is being sensed, a coating that selectively binds the target species should be added to the nanowire surface to distinguish between different species in the analyte.

THURSDAY October 9SCV Electron Devices

http://www.cpmt.org/apm/


High-Complexity, Low-Cost 3D Sub-Systems as a

Large-Scale BGA Speaker: Shawn Arnold, ChipStack Inc. Time: Optional dinner at 6:30 PM, Presentation at

7:30 PM Cost: Dinner $25 (by Oct. 7); no cost for meeting Place: Ramada Inn, 1217 Wildwood Ave (Fwy 101

frontage road, between Lawrence Expressway and Great America Parkway), Sunnyvale

RSVP: by email to Janis Karklins, [email protected]

Web: www.cpmt.org/scv

Shawn Arnold is currently the CTO of ChipStack Inc. and holds two patents with two in process. He has 24 years of industry experience ranging from Product Design to Manufacturing for Sigma Circuits/Tyco, Design Management for an EMS, Signal Integrity expertise, PCB Market Analyst for iSuppli, Business Development Manager for Cadence and Consulting for numerous Consumer Product related OEMs.

With the current drive towards increased IC

integration and reduced package size, previously low-technology printed circuit boards (PCBs) are now required to support these packages with higher technology manufacturing requirements. Solutions such as blind/buried vias, higher speed materials, distributed capacitance materials and thin traces/spaces are needed, thus increased costs for the base PCB. Due to increased chip capabilities, it is common to have a single high-technology IC drive the costing of the entire finished product. By isolating this high-tech circuit (the complex IC plus all of its supporting logic) into a much smaller discrete three-dimensional sub-system and allowing the base PCB to return to a lower technology, the overall product costing can be significantly reduced while compressing required PCB real estate.

WEDNESDAY October 10SCV Components, Packaging and Manufacturing Technology

M E S OIn t eg r at io n

Let us help you integrate your product and get it into production • MEMS & Sensors Experts • Product Design ▪ R&D ▪ Failure Analysis • Medical Devices ▪ High-Volume Manufacturing • Experienced Consultants www.MesoIntegration.com

[email protected] TEL: 949.278.0275


Recent Advances and Trends in Microwave Synthetic

Instrumentation Speaker: Peter Pragastis, President, Phase Matrix,

Inc. Time: Refreshments and Social Hour 6:00 PM,

Presentation at 6:30 PM Cost: none Place: National Semiconductor, Bldg #9,

Classroom #4, 2900 Semiconductor Dr, Santa Clara

RSVP: not required Web: www.mtt-scv.org/oct_mtg.html

Peter Pragastis is president and co-founder of Phase Matrix, Inc. Pete has a BS in Electrical Engineering from Santa Clara University and more than 20 years of in-depth technical and managerial experience in RF/Microwave Engineering in support of the design and development of instrumentation for commercial and aerospace/defense ATS applications for the TETS, F15, and the F16 IAIS programs. Pete’s primary areas of expertise are in RF/MW Up Converters, Down Converters, Frequency Synthesizers and Synthetic Instrumentation implementation.

Synthetic Instrumentation (SI) is an emerging technology in sync with the digital revolution. Microwave Synthetic Instruments in particular have been adopted by the Aerospace Defense community as the best way to minimize rack space, total test acquisition costs, as well as technology obsolescence. By leveraging on recent advances in Software Defined Radio (SDR), Microwave SI is beginning to be applied in the commercial market space and is being embraced by leading test & measurement instrument manufacturers.

This talk will familiarize engineering professionals with differences in various configurations of Microwave Synthetic Instrumentation including VXI, LXI, and PXI. Recent trends and a brief look at the future in this field will be covered.

THURSDAY October 11SCV Microwave Theory and Techniques

Valon Technology, LLC

valontechnology.com

[email protected]

RF and Wireless Product Design & Development

- System Engineering - Test & Measurement - Schematic Capture & PCB layout- Expert Witness

Redwood City (650) 369-0575


Full-Chip Electro-Thermal Simulation using Loosely Coupled Electrical and Thermal Simulators

Speaker: Ranjit Chandra, Gradient Design

Automation Time: Pizza/drinks at 6:30 PM, Presentation at

7:00 PM Cost: none Place: Cadence Design Systems, Building 5,

655 Seely Avenue, San Jose RSVP: not required Web: ewh.ieee.org/r6/scv/cas

Ranjit Chandra founded Gradient Design Automation in 2003. Previously, he was VP of technology at Magma Design Automation, where he focused on signal integrity, power and EM. He was a co-founder and VP of engineering of Moscape Inc., which was acquired by Magma in 2000. Rajit held key positions at Cadence Design where he developed tools for timing-driven designs and authored the industry standard format for timing data exchange (SDF). He worked as a performance verification team lead at Intel Corp. Rajit received his B.Tech and M.Tech in Radio Physics & Electronics from Calcutta University, India, and his PhD (EE) from London South Bank University, UK. He is a Senior Member of the IEEE, and was instrumental in re-forming the IEEE Santa Clara Valley Circuits and Systems chapter, serving as its first chair.

Current IC design trends calls for integration of

power transistors within high-performance mixed-signal designs. Because of the increased power densities caused by such trends, temperature variations within the chip need to be taken into account to achieve cost-effective and reliable chip designs. This session will discuss the following: (1) Potential temperature hazards in IC designs and the need for electrothermal analysis; (2) The challenges of full-chip 3D temperature analysis of IC designs; (3) A temperature- aware methodology that uses detailed temperature information for design improvements of mixed-signal chip designs; (4) An effective temperature- aware design flow at AMIS using Cadence Spectre electrical circuit simulation and thermal analysis tools from Gradient Design Automation.

AMIS and Gradient collaborated on a thermal analysis project that allows detailed 3D full-chip temperature distribution within the chip to be calculated and visualized early in the design cycle before taping out. Such temperature checking capability is useful for predicting potential temperature hazards under steady state and transient temperature conditions. Traditional methods of temperature estimates based on power and package parameters do not provide sufficient details while commercial mathematical software tools lack the accuracy needed in contemporary chip-level designs. Using layout and netlist data available in the Cadence design environment, an automated flow has been developed that annotates instance-specific temperatures to Spectre simulation to obtain true temperature- aware power from it. The resulting temperature information is used for floorplanning to reduce design guardbands and potential circuit malfunctions.

MONDAY October 15SCV Circuits and Systems

Bernie Siegal

650-961-5900

[email protected] www.thermengr.com

Device Thermal Characterization Package Thermal Characterization Thermal Test Boards Thermal Test Equipment & Fixtures

http://www.semi-therm.org/


Cyber Security for the Electric Utility Industry

Speaker: Joseph Weiss, Task Force Lead,

information security impacts on IEEE standards

Time: Light lunch and Presentation, Noon - 1:00 PM

Cost: Free for IEEE members, $5 for non-members

Place: Pacific Gas & Electric Office, 245 Market Street, Room 1417, San Francisco

RSVP: Required for admittance; to Shirin Tabatabai, [email protected], 415-973-1474

Web: www.e-grid.net/docs/0710-sf-pes.pdf

Joseph Weiss is an industry expert on control systems and electronic security of control systems, with more than 30 years of experience in the energy industry. He serves as a member of numerous organizations related to control system security. These include the North American Electric Reliability Council (NERC) Critical Infrastructure Protection Committee (CIPC), the Process Controls Security Requirements Forum, CIGRÉ Joint Working Group D2/B3/C2 01- Security for Information Systems and Intranets in Electric Power Systems, and other industry working groups. Mr. Weiss serves as the Task Force Lead for review of information security impacts on IEEE standards.

Joseph Weiss will discuss the NERC Cyber

Security Infrastructure requirement. He will discuss the critical connection between digital control systems, such as SCADA, and America’s infrastructure and how to protect these systems from intentional or unintentional cyber incidents. He will also discuss some actual case histories and their relevance to the electric utility industry. Mr. Weiss will also address some of the comments from the FERC NOPR on Cyber Security.

MONDAY October 15SF Power Engineering


Imaging Magnetic Surfaces with Atomic Resolution

Speaker: Dr. Matthias Bode, Argonne National

Laboratory Time: Cookies and drinks at 7:30 PM; Presentation

at 8:00 PM Cost: none Place: KOMAG, 1710 Automation Parkway,

San Jose RSVP: not required Web: www.ewh.ieee.org/r6/scv/mag

Matthias Bode received the diploma in physics from the Free University of Berlin, Germany, in 1993, and the Ph.D. degree in physics from the University of Hamburg, Germany, in 1996. Based on his works on spin-polarized scanning tunneling microscopy he received the habilitation in experimental physics from the University of Hamburg in 2003.

Since 1996 he is a Research Staff Member at the Institute of Applied Physics at the University of Hamburg. In 2007, he joined the Argonne National Laboratory, and is leading the Electronic and Magnetic Materials & Devices Group. In the past 10 years Dr. Bode developed spin-polarized scanning tunneling microscopy, a magnetic imaging technique with a resolution down to the atomic limit. His research explores correlations between structural, electronic, and magnetic properties of epitaxial nanostructures with a special interest in frustrated antiferromagnetic surfaces, superparamagnetism, and new magnetic phenomena.

Dr. Bode has published more than 80 peer-reviewed papers, three review articles, and three book chapters. In 2003 he was awarded the Philip-Morris Award for research.

Fueled by the ever increasing data density in magnetic storage technology and the need for a better understanding of the physical properties of magnetic nanostructures, there exists a strong demand for high resolution, magnetically sensitive microscopy techniques. The technique with the highest available resolution is spin-polarized scanning tunneling microscopy (SP-STM) which combines the atomic resolution capability of conventional STMs with spin sensitivity by making use of the tunneling magneto-resistance effect between a magnetic tip and a magnetic sample surface. Beyond the investigation of ferromagnetic surfaces, thin films, and epitaxial nanostructures with unforeseen precision, it also allows the achievement of a long-standing dream: the real space imaging of atomic spins in antiferromagnetic surfaces.

The lecture addresses a wide variety of phenomena in surface magnetism which in most cases could not be imaged directly before the advent of SP-STM. After starting with a brief introduction of the basics of the contrast mechanism, recent major achievements will be presented, like the direct observation of the atomic spin structure of domain walls in antiferromagnets and the visualization of thermally driven switching events in superpara-magnetic particles consisting of a few hundreds atoms only. To conclude the lecture, recently observed complex spin structures containing 15 or more atoms will be presented.

TUESDAY October 16SCV Magnetics


Surgery with the da Vinci Surgical System (Video)

Speaker: none (video supplied by Intuitive Surgical,

Sunnyvale) Time: Presentation at 7:30 PM Cost: none Place: Clark Center Auditorium, Stanford University

(parking free after 4 PM) RSVP: not required Web: www.ewh.ieee.org/r6/scv/embs

Intuitive Surgical, Sunnyvale, CA, has developed a

surgical system for assisting surgeons in performing complex, minimally-invasive procedures. The System provides the surgeon with a high-magnification, 3-dimensional view of the surgical site and him to precisely and rapidly control the position and orientation of the instruments with natural hand and arm motions. During this meeting we will present a video made during an actual procedure (a hysterectomy) on a real patient. The video is narrated by the surgeon and other personnel who explain the operation of the system and discuss the benefits to the patient as well as describe the procedure being performed. Although the video was made to "sell" the system to surgeons, it will interest engineers as well. The smooth movement of the instruments and the vivid imagery are particularly impressive. Although we do not expect to have a representative from Intuitive Surgical at this meeting, we have invited them to appear at a future meeting to discuss the engineering and development challenges presented by this system.

WEDNESDAY October 17SCV Engineering in Medicine and Biology


Power and Cooling Optimization Techniques for High Density

Data Centers Speaker: Dennis Shouldice, Global Account

Manager, APC/MGE Time: Dinner (optional) 6:00 PM, Presentation

7:00 PM Cost: $25.00 IEEE members, $30.00

nonmembers, $10.00 students (no cost for talk)

Place: Ramada Inn, 1217 Wildwood, Sunnyvale RSVP: to James Alvers,

[email protected], (925) 730-3105

Web: www.e-grid.net/docs/0710-scv-pes+ias.pdf

Dennis Shouldice is an Electrical Technologist, based in San Mateo, with16 years of field experience with American Power Conversion, now APC-MGE, a Schneider Electric Company.

This presentation will outline challenges facing

organizations that need to compress their IT loads through the use of dense IT servers. With the use of blade servers, high density data centers are using an unprecedented amount of power. Power densities between 25 and 35 KW per rack are now being designed.

How do you get power to the racks? How do you keep the servers running at optimum environmental conditions? How do you build and operate all of this at lowest capital cost while achieving minimal operating expenses? Techniques used to address these challenges will be outlined. Among the topics coved will be: the use of 3 phase power at the rack level as well as the importance and application of metering and monitoring

WEDNESDAY October 17SCV Power Engineering & Industry Applications

Patent Agent Jay Chesavage, PE

MSEE Stanford 3833 Middlefield Road, Palo Alto 94303

[email protected]

www.File-EE-Patents.com TEL: 650-619-5270 FAX: 650-494-3835


A 2x2 MIMO Baseband for High-Throughput Wireless Local-

Area Networking (802.11n) Speaker: Jason Trachewsky, Senior Technical

Director, Broadcom Time: Refreshments/networking at 6:00 PM;

Presentation at 6:30 PM Cost: Donation requested to partially cover food

cost Place: National Semiconductor Building E

Auditorium, 2900 Semiconductor Dr., Santa Clara


Web: www.ewh.ieee.org/r6/scv/ssc

Jason Trachewsky is currently a Broadcom Fellow and Senior Technical Director in Broadcom's Office of the CTO and is investigating new wireless technologies. Prior to his current position, he was Senior Director of Engineering for the Wireless LAN Business Unit at Broadcom. In that role, he was responsible for Broadcom's R&D for 802.11 products from 802.11b through the 802.11n MIMO wireless LAN standard and made several contributions to the 802.11n drafts. Prior to Broadcom, he was with Epigram, Inc., which was acquired by Broadcom in 1999, and Applied Signal Technology, Inc. He received a BSEE from Stanford University in 1991.

The new IEEE 802.11n draft introduces physical layer (PHY) and media access controller (MAC) layer improvements to enable transmission of two independent data streams of coded OFDM with constellations from BPSK to 64-QAM and code rates from 1/2 to 5/6 at average TCP throughputs 7 times greater than 802.11a or 802.11g using two transmit antennas and slightly more than double the bandwidth. In addition to the maximum data rate increase, the 802.11n draft provides modes to increase the range of moderate data rate links through diversity combining and spatial multiplexing and MAC aggregation techniques to reduce layer-2 overhead.

A flexible single-chip fully-integrated 2x2 MIMO baseband PHY and MAC is presented. The PHY is capable of transmitting up to two information streams generated from one rate-1/2 64-state convolutional encoder and fully-flexible MIMO block interleaver on up to two transmit antennas. The convolutional encoder includes a puncturing engine to create rate-2/3, 3/4, and 5/6 codes. Single-stream modes may use one or two active antennas with cyclic shift transmitter diversity employed when two antennas are simultaneously active and transmitter selection diversity employed when one antenna is active; the cyclic shift and selection algorithm are fully programmable. The PHY can receive transmissions of one information stream with a single-receiver-path maximum-likelihood decoder, with or without receiver selection diversity, or a maximal ratio combiner (MRC) followed by a maximum-likelihood decoder. It can receive two information streams with a novel dual-antenna maximum-likelihood decoder, providing second-order diversity for each stream. It also includes logic to map more than two receiver antennas to the two receiver RFIC inputs for additional selection diversity gains. The MAC includes standard-compliant frame aggregation and block acknowledgement capabilities to vastly improve efficiency at high PHY rates.

The talk will cover technical specifications of the baseband processor, an overview of some of the key algorithms that the high throughputs possible, and some measured results.

THURSDAY October 18SCV Solid State Circuits


All-Day Career Workshop 2007 Speakers: Ed Perkins, Paul Kostek, Jean Eason,

Russ Harrison Time: Registration at 8:00 AM; sessions/

networking/practice throughout day Cost: Students/Unemployed $20; IEEE Members

$30; Public $45 (includes lunch, breaks; $5 more at the door)

Place: Fairmont Hotel, San Jose RSVP: by email to Jonathan David,

[email protected] Web: ieee-jbdavid.blogspot.com/2007/09/

2007-career-workshop.html Session Details 8:30 – 10:20 Ed Perkins • Career Planning – Mapping your route to Success and Fulfillment in a changing work world. This interactive session will cover Elements of the Career Plan; Skills and Capability Assessments, Market Analysis, Understanding the State of the workplace, employer’s needs, the role of training and education. Understanding your values and motivators; Finding alignment with the market, and employers. 10:40 – 12:30 Paul Kostek • Interview Preparation. This presentation will describe the common interview types currently in vogue in the engineering workplace, and how to prepare for them. Exercises include preparing for a behavioral interview question. • Personal Positioning for Engineers. A workshop for engineers in all stages of their careers. The focus of this session is a discussion of Career Track options. It helps engineers understand what it is they are looking for from their career, and how this will impact their personal life. They need to understand their priorities and how these will impact their career. Lunch (included in fee) 1:00 – 2:50 Jean Eason • Painless Networking: Finding what you need with the help of your friends & aquaintences. It is so often quoted that the BEST way the BEST work is found is through the people you already know. Unfortunately for many engineers more comfortable with complex ideas than polite conversation, this statement strikes fear and dread into our hearts, as we expect our friends and relations to fade out of lives when we ask “help me find a job”. With a some basic information, and a few interactive exercises, Jean will show us how easy “networking” really is, and how to apply these skills not only to “job hunting”, but to improving communications in a wide variety of situations.

In today’s increasingly outsourced world, engineers must take responsibility for managing their own careers. The alternative is being surprised and unprepared when economic pressures force a change in their employment situation. We are lucky to have the opportunity, in conjunction with the IEEE-USA Operating Committee Meeting, to have Career Experts from throughout the IEEE here in town on Oct 19th. Please join us, take a day off work if needed, and use this opportunity to tune up your career plans. Discounts are available for those who are current “in transition” (the current euphemism for “laid off”, “fired”, ‘let go” or “not working”, etc).

The day is designed so that those who can’t take the full day off can join us for lunch and the afternoon sessions of the day.

Time: 8:00 Registration 8:30 Career Workshop 12:35 Lunch Line 1:00 Networking Skills and practice 3:00 Legislative activities 5:00 Membership Dev’t discussion -- note Parking is not included: that’s $10 at the

convention center, or light rail is also convenient.

3:10 – 5:00 Russ Harrison • Legislative Activities - Bridging the Gap. The reality is that our government will impact an engineer’s career and this impact can be positive or negative. Learn how you can influence your government to protect and enhance your profession and career prospects. Our elected leaders vote on legislation that will affect engineers all the time. For example, in 2007 the U.S. Congress voted on legislation that would:

• Dramatically increase federal spending on basic research, • Create new scholarship programs for engineering students, • Invest in alternative energy sources, • Expand high-skilled immigration, • Reform the patent system, and • Expand and restrict NASA’s manned mission to Mars (in

the same bill.) Join us for a discussion about these and other pieces of federal legislation that could affect you, your career and your profession. IEEE-USA Legislative Representative Russ Harrison will be here to discuss these and other things that Congress is trying to do for science and engineering. Then we will discuss ways that we can influence these decisions before the bills become law. • Membership Development - Which IEEE-USA services most increase Member Value? (Scott Grayson) Helping members get the most value from their IEEE/IEEE-USA

BIOGRAPHIES – next page ====>

FRIDAY October 19SCV Professional Activites Committee for Engineers (PACE)


Edward Perkins Ed has 30 years experience in the electronics

industry, including hardware design automation, program and project management, mixed-signal test development automation, design services management, chip architecture development, software development, and real time embedded systems programming. He was a program manager in the Virtual Test Division of IMS in Beaverton, OR, where he was responsible for leading their mixed-signal R&D development efforts. Ed also spent 10 years at Digital Equipment Corporation in the central engineering CAD department where he was responsible for development and deployment of CAE services and support to engineering groups worldwide. He has been an IEEE volunteer for 25+ years. He is a Senior Member of IEEE and is Past Chair of the Oregon Section, Region 6 Membership co-chair, and a member of the IEEE-USA Career and Workforce Policy Committee. He has a BSEE and MSCS from WPI (Worcester, MA) and most recently an MS ECE specializing in VLSI design and test from Portland State University (Portland, OR).

Paul Kostek

Paul is a Systems Engineer with Boeing. Prior to Boeing he worked for a systems engineering/project management-consulting firm. He worked with companies in defining system architecture and design, system requirements, and software development standards. He received his B.S. from the University of Massachusetts, Dartmouth, in 1979. Paul is a Senior Member of the IEEE, was the 1999 President of IEEE-USA, and a member of the IEEE Board of Directors. He also served as President of the IEEE Aerospace & Electronics Systems Society in 2000 & 2001. Paul is a Senior Member of the American Institute of Aeronautics and Astronautics, the International Council on Systems Engineering, SAE, and the Project Management Institute. He is also a director of the Washington Aerospace Alliance.

Jean M. Eason

Jean Eason received a BS in EE from the University of Texas in 1978, an MS in EE from Southern Methodist University in 1984 and an MBA from Texas Christian University in 1989. Her early career focused on the aerospace industry and she spent fifteen years working in avionics systems design and developing advanced cockpit displays for military and commercial, fixed and rotary wing aircraft. She is selfemployed, working with clients on specialized applications for small businesses and in technical communication and documentation.

Jean’s time in aerospace gave her particular insight into the issues affecting engineering

professionals. Her work in the area of employment assistance for engineers in North Texas was recognized by the State of Texas in the report, Defense Transition: Economic Promise for Texas from the Governor’s Task Force on Economic Transition (1993). This led directly to her involvement with IEEEUSA and its employment and career services.

Jean has been an active volunteer for more than twenty years, addressing member needs at every level from the local section to the Board of Directors.

Russell Harrison

Russell Harrison is the Legislative Representative for Grassroots Activities for IEEE-USA. In this capacity, he is responsible for helping members of IEEE-USA interact with, and ultimately influence, elected officials.

Prior to joining IEEE-USA, Mr. Harrison directed grassroots programs at the Institute of Scrap Recycling Industries and the American Iron and Steel Institute. During his tenure, he actively raised campaign contributions through both of the associations’ political action committees. Mr. Harrison also represented the recycling and steel industries on Capitol Hill, and in state capitols on a variety of issues as a professional lobbyist.

Mr. Harrison has a BA in Political Science, with minors in History and Communications, from Allegheny College, and a MS in Public Policy for the University of Maryland.

VOICE COIL MOTORS Design - Control - Fabricate - Test

J. Arthur Wagner, Ph.D. 1649 Fair Orchard Ave.

San Jose, CA 95125

[email protected] (408) 269-7044 (408) 206-3049 cell

http://www.cpmt.org/iemt/


Human-in-the-Loop Simulation at NASA Ames Research Center

Speaker: Kathleen Starmer, NASA Ames Research

Center Time: Refreshments at 6:30 PM; Presentation at

7:00 PM Cost: $5 for IEEE members, and $10 for

non-members Place: Hewlett Packard Oak Room, 19447

Pruneridge Avenue (Building 48), Cupertino RSVP: not required Web: ewh.ieee.org/r6/scv/ce

Kathleen Starmer has worked as a contractor at

NASA Ames Research Center for the past six years. Her formal education and graduate degrees are in the life sciences, but since arriving at Ames, she has turned her attention toward aeronautics and astronautics. She has a keen interest in both improving air transportation on this planet and in enabling transportation to realms outside of our atmosphere. In support of this, she currently conducts business development activities for both Ames’ Simulation Facilities and other related Ames facilities, sharing the myriad capabilities of the laboratories with a wide audience, from university researchers to military branches to private industry. Kathleen is also actively involved in public policy issues as they relate to the national research and development infrastructure. She currently serves on the public policy committee of the Ames Contractor Council and as Director of Public Policy for the San Francisco chapter of the American Institute of Aeronautics and Astronautics.

Simulation permits researchers to test concepts

without having to use the actual system being examined. Such simulations can involve proposed new vehicle controls, improved operating procedures, novel vehicle design concepts, pilot training, or any number of other scenarios. Additionally, simulation allows for investigation of emergency situations without any real risk to hardware or human life. In short, examining things in a simulation environment increases safety and saves developers both time and money. However, solutions developed under simulation are only as good as the simulation itself. To ensure the best-quality research data possible, NASA Ames’ Simulation Laboratories provide high-fidelity, human-in-the-loop customizable systems and powerful tools, offering scientists and engineers a path to generate quick and cost-effective solutions in both aerospace vehicle design and mission operations. The laboratories, systems, and supporting software that comprise the human-in-the-loop simulation facilities will be discussed, and highlights of the facilities’ benefits to the aerospace community will be addressed.

TUESDAY October 23SCV Consumer Electronics


Formation of a Warranty Chain Management Institute

and its Applicability for Reliability Engineers

Speaker: Glen Griffiths and Allison Griffiths,

Hewlett Packard Time: Refreshments at 6:30 PM; Presentation at

7:00 PM Cost: none Place: HP-Cupertino Oak Room, Bldg 48,

Pruneridge Ave. and Wolfe Rd., Cupertino RSVP: not required Web: www.ewh.ieee.org/r6/scv/rl/events.htm

Glen Griffiths is the director of Hewlett Packard’s Global Engineering Services responsible for providing engineering and regulatory support across all HP hardware businesses. He manages over 180 people spread across 24 countries with his teams supporting over $60B of products sales annually.

Glen’s professional experience has centered on electrical, avionic and reliability engineering as well as systems engineering. Glen retired from the UK Royal Air Force, after serving 22 years as an Engineering Officer. In his previous roles he was operations manager for a squadron of Jaguar strike attack aircraft, managed the software development and test teams for the Harrier aircraft (AV8B) fleet and managed a multi-national team of software reliability and engineering R&D advisors for the Typhoon aircraft. During his last 3 years in the military he was responsible for setting Reliability & Maintainability requirements for all United Kingdom Military Air systems procurement and he also acted as the UK reliability specialist advisor to the US Department of Defense Joint Strike Fighter Project.

Glen holds a Masters in Business Administration, a Masters in Reliability and Maintainability Engineering and an Honors degree in General Engineering. He is a Chartered Engineer in the IEEE and also holds the position of President of the Institute of Warranty Chain.

Warranty costs in the US alone run in the region of

$28B per annum [ref - Warranty Week, 3rd March 2007 edition]. Reliability Engineers have a significant influence on the failure rates of equipment, which is a key driver of warranty events and hence cost. Glen will outline the path he has taken, beginning with an investigation into how to improve reliability engineering practices in Hewlett Packard, that led to the creation of a new Warranty Conference series and culminated in the formation of the Institute of Warranty Chain Management (iWCM), of which he is currently President. Along the way, he will discuss the iWCM’s applicability and usefulness to reliability Engineers and introduce the Director of the Warranty Chain Management Conference series, Alison Griffiths.

Alison Griffiths is the President of the business

management consultancy ALG Associates, LLC, which she originally founded in the UK in 2002, transferring to the US in 2004. Alison has 15 years of business, management and consultancy experience; having worked in the public and private sector, manufacturing, retail and customer service industries. She has led a number of key process improvement initiatives and has key experience in assessing organizational needs, developing strategies and improvement plans, problem and conflict resolution, as well as staff training and development.

In 2004 Alison launched the Warranty Chain Management (WCM) series of conferences to address the important need for a forum where professionals can meet to discuss warranty issues and begin to develop warranty management as a recognized business discipline. Following a call to action for the development of a recognized warranty institute at the WCM 2006, Alison was instrumental in forming and serving on a Charter Team to create the Institute of Warranty Chain Management (iWCM). She incorporated the iWCM in California in December 2006 and now serves as the Executive Director to the Board of Directors.

Alison studied at Manchester Metropolitan University, UK and has a BA(Hons) in Business Studies and an MBA

WEDNESDAY October 24SCV Reliability


Prospects for Ultra-short Reach Optical Interconnects:

Bringing Light to the Chip Speaker: Ashok Krishnamoorthy, Sun Microsystems,

and IEEE LEOS Distinguished Lecturer Time: Networking and Food: 7:00 PM,

Presentation: 8:00 PM Cost: donation for refreshments Place: National Semiconductor Building E

Conference Center, 2900 Semiconductor Drive, Santa Clara

RSVP: by email to ieeescvleos-rsvp2007 @yahoo.com


TUESDAY November 6SCV Lasers and Electro-Optics


Experimental and Theoretical Analysis of Electromagnetic

Shielding of Cables and Connectors

Speaker: Dr. Lothar (Bud) O. Hoeft, Consultant,

Electromagnetic Effects Time: Social and Dinner at 5:30 PM, Presentation:

6:30 PM Cost: none Place: Applied Materials Bowers Cafeteria, 3090

Bowers Ave., Santa Clara RSVP: not required Web: www.scvemc.org

Dr. Bud Hoeft received a B.S. and M.S. in physics from the University of Wisconsin and a PhD in physics and biophysics from Pennsylvania State University. In 1979, he completed a 25-year R&D career in the U.S. Air Force working on acoustical noise control, bionics, nuclear weapon simulation, pulse power technology and international R&D coordination. He joined BDM, where he was primarily concerned with helping designers build and test systems that are hard to electromagnetic effects. In 1994, he retired from BDM and became a private consultant. Dr. Hoeft is a Certified EMC Engineer. He has presented numerous papers and tutorials on shielding and electromagnetic effects at IEEE-EMC, NEM, Zurick-EMC, Wroclaw-EMC, IEE-EMC, Lightning and IICIT symposia. In 2001, he was appointed Distinguished Lecturer of the IEEE EMC Society for 2001 and 2002. In 2007, he received the Richard R. Stoddard Award from the IEEE EMC Society.

Shielded cables and connectors have been

important techniques for keeping voltages and currents from causing problems by radiating from or by upsetting/damaging important electronic systems. The intrinsic electromagnetic property of a cable or connector shield is its surface transfer impedance. This is the ratio of the longitudinal open circuit voltage measured on one side of the shield (normally the inside) to the axial current on the other side (normally the outside). In cases where a high electric field is present at the surface of the shield, the transfer admittance or charge transfer elastance is also important. The surface transfer impedance of typical cables, connectors, backshells and cable terminations has been measured and can be explained by simple models.

TUESDAY November 11SCV Electromagnetic Compatibility


An Alternative Method for Manufacturing Robust Electronic

Assemblies Without Solder Speaker: Joseph (Joe) Fjelstad, President, Verdant

Electronics Time: Optional dinner at 6:30 PM, Presentation at

7:30 PM Cost: Dinner $25 (by Nov. 11); no cost for meeting Place: Ramada Inn, 1217 Wildwood Ave (Fwy 101

frontage road, between Lawrence Expressway and Great America Parkway), Sunnyvale

RSVP: by email to Janis Karklins, [email protected]

Web: www.cpmt.org/scv

Joseph (Joe) Fjelstad is founder and president of

Verdant Electronics. He has more than 35 years of international experience in electronic interconnection and packaging technology in a variety of capacities from chemist to process engineer and from international consultant to CEO. Mr. Fjelstad is also a well known author and magazine columnist writing on the subject of electronic interconnection technologies. Prior to founding Verdant, Mr. Fjelstad co-founded SiliconPipe, a leader in the development of high speed interconnection technologies. He was also formerly with Tessera Technologies, a global leader in chip-scale packaging, where he was appointed to the first corporate fellowship for his packaging innovations.

The electronics industry has assembled electronic components to printed circuit boards for more than 50 years. That relationship has been an enduring one, however with the transition from traditional tin-lead solder to new lead-free solders mandated by European legislation, the industry is being saddled with significant new expenses and plagued with problems not previously encountered. In this environment, an improved approach to electronics assembly without the use of solder is being developed. The process is being called the Occam Process in honor of the 14th century philosopher and logician, William of Occam, who stressed simplicity. The presentation will describe the process, its advantages, its challenges and its future and technology roadmap. The talk will include a review of the developers’ conference that will have been held a few weeks earlier in the month of October.

WEDNESDAY November 14 SCV Components, Packaging and Manufacturing Technology


Advancements in Transcoding for Optimized Unified Group

Communications

Speaker: Shaun Botha, Co-Founder and Chief

Technology Officer, Twisted Pair Solutions Time: 6:00 PM Cost: none Place: National Semiconductor, Building E,

Conference Room, 2900 Semiconductor Dr, Santa Clara

RSVP: not required Web: www.ewh.ieee.org/r6/scv/comsoc

As an expert in interoperable communications infrastructure, Shaun Botha is an original developer of the WAVE(tm) unified group communications software technology used within information critical military, federal, public safety, financial, utility and transportation environments around the world. Prior to co-founding Twisted Pair Solutions, Shaun led Research and Development for Williams Communications, developed financial trading software for IP Blue, and created database applications for Merrill Lynch. He also co-developed the world's first software for reading smart cards. Shaun is a graduate of Cape Technikon in South Africa and holds a graduate degree in Computer Science.

WEDNESDAY November 14SCV Communications


"TV 2.0" - Digital TV in the Networked Home

Speaker: Paolo Siccardo, President, Digital Keystone Time: Refreshments at 6:30 PM; Presentation at

7:00 PM Cost: $5 for IEEE members, and $10 for non-

members Place: Hewlett Packard Oak Room, 19447

Pruneridge Avenue (Building 48), Cupertino RSVP: not required Web: ewh.ieee.org/r6/scv/ce

Paolo Siccardo is the President and Chief Executive Officer of Digital Keystone, a world leader in digital entertainment solutions that bridge the personal computer, consumer electronics and content industries. Paolo Siccardo has over 20 years of experience in General Management and Business Development of high technology products. Prior to the inception of Digital Keystone, Paolo Siccardo was Executive Vice President and General Manager of Digital Television products with SCM Microsystems, a leading OEM supplier of security technology. Previously Paolo Siccardo held positions as Senior Vice President of Marketing and Business Development with SunUp, a leader in content management software for the satellite and cable-TV industry; Vice President of Engineering and then General Manager with Hyundai Electronics, where he launched the world's first Open TV Set Top Box; and Project Manager at Hewlett-Packard, where he managed the development of the world's first Video on Demand Server. With Compression Labs, Paolo Siccardo developed the world's first AT&T videophone and PC video conferencing product. Paolo Siccardo holds a MSEE degree from the University of Genoa, Italy. Several U.S and International patents have been awarded or are pending in his name.

TUESDAY December 4SCV Consumer Electronics

IEEE SF Bay Area GRID MagazineMATLAB & Simulink for Design & Digital Signal Processing 12 week...

Documents

Transcript of IEEE SF Bay Area GRID MagazineMATLAB & Simulink for Design & Digital Signal Processing 12 week...