WAFER-LEVEL ELECTROMIGRATION RELIABILITY TEST FOR DEEP-SUBMICRON INTERCONNECT METALLIZATION

' Wye Boon Loh and Man Siu Tse School of Electrical & Electronic Engineering,

Nanyang Technological University, Nanyang Avenue, Singapore 639798.

Lap Chan and Keng Foo Eo Chartered Semiconductor Manufacturing Etd.

60 Woodlands Industrial Park D, St 2, Singapore 738406

ABSTRACT An automatic Wafer-level Electromigration Test (WET) System with interactive interface was developed. The WET System has the advantages of reduced stressing time and hence cost over the conventional package-level EM test. The automatic EM test with parallel stressing on multiple devices was successfully implemented. Interconnection lines line- width of 0.32pm and 0.6pm and composite metal films AI-Cu (0.5%) with Ti/TiN top and bottom layer were processed and stressed. The activation energy E',, was found to be 0.76-0.86eV for 0.6pm metal lines over the temperature range from 235°C to 275°C. The values are compatible to those obtained using the package-level EM testing at 150 - 250 "C. For the 0.32pm metal lines, the activation energy El, was in the range of0.91-1.15eV.

INTRODUCTION

The reliability of metal interconnection line has been a great concern in semiconductor manufacturing. The typical reliability issue in metal interconnection is the Electromigration. Electromigration (EM) in metallization under current stress is caused by the movement of lead ions in the direction of electron flow due to momentum transfer from electrons to the metal ions[l]. Electromigration is usually monitored by the changes in the line resistance and is also thought of as an indirect measure of the metal ion flux. Electromigration is usually modeled by the empirical Black's formula which relates the Mean-Time-To-Failure (MTTF) to the stressing conditions and is given as

E kT

MTTF = AJ-" e x p ( 2 )

where A = process constant dependent on material and geometry of the strip, n = current exponent factor, T = absolute temperature, k = Boltzmann's constant, E, = activation energy.

The reliability of the metallization used in wafer fabrication is often monitored on a production lot basis as part of lot qualification by studying the electromigration sensitivity of special test structures. In conventional package-level electromigration test, the test structures have to be wire-bonded in ceramic package before being stressed at high temperature at around 1-50 to 250°C in oven and high current density without causing significant self-heating, on the order of lo6 Ncm2 [ 2 ] . The MTTF for conventional package-level devices electromigration tests is in the order of hundreds to thousands of hours,

which precludes timely feedback of results to the production line.

An alternative approach is to conduct wafer-level electromigration test [ 3 ] where joule heating of the test structure is used to raise the test structure temperature. Wafer-level EM test under very highly accelerated conditions offers the potential of significant cost saving and shorter test time over the less accelerated package- level EM tests.

We had developed an automatic Wafer-level EM Test (WET) System which contains interactive user interface for data acquisition and instrument control. The schematic WET System setup is shown in Fig. 1.

I I

I T k h u ; k

.. ~

Fig. 1. Schematic of Wafer-Level EM Test System

The WET System consists of a probing station, Source Measure Units (SMUs), high temperature 8 inch chuck and controller (max 3OO0C), and a computer.

' corresponding author's e-mail addresses : lohwb@csm.st.com.sg & pa2915198@ntu.edu.sg

(0-7803-4932-6/98/$10.00 1998 IEEE) 157

This paper presents our experimental results which show that wafer-level EM test is capable to collect reliable test results, life time data, on large quantity of deep sub- micron Em test structures in a shorter time. The temperature coefficient of resistance (TCR), change of line resistance with respect to time, MTTF, activation energy E, and current density factor n, will be presented.

X X X X

TEST STRUCTURE

X X X X X X X X X X X X

The classical single layer EM test structure as shown in Fig.2 was used. The test structure has metal line of 800pm in length. The line-width of metal lines is 0.32ym and 0.6ym respectively. The test structure is monitored through the current forcing pads (I+ & I-) and a set of voltage sensing pads (V+ & V-).

unMm

Fig.2 Single layer EM test structure

The test structures metal films were deposited by sputtering on silicon wafer covered with thermal oxide. The multilayered interconnect metal lines consisted of 50008, Al/Cu(O.S%) cladded in between 11008, TIN on top and bottom. The metal lines were passivated with 60008, PECVD SiO2.

CONVENTIONAL EM TEST METHOD

Conventional EM test was conducted on wafer level to determine the sample estimate of Mean-Time-To-Failure (MTTF) and standard deviation which describes the failure distribution of metallization test line subjected to current-density and temperature stress [4].

The Wafer-level EM test started with the chuck temperature set at low temperature T(TS)L, eg. 30°C. The test structure resistance R(TS)L was measured with low current (=lmA). Then the chuck was heated up to high temperature T(TS)H, eg. 250°C. The test structure resistance at high temperature was measured again with low current to prevent Joules heating, R(TS)H. Then the temperature coefficient of resistance(TCR) is computed by the following equation:

R ( W , - R(TS), W S ) L [ T ( W fz - T(TS ) L 1

TCR =

The test structures were then stressed with pre- determined stress current density. At every pre-set sampling interval, eg. Ssec, the intermediate resistance of the test structure R(TS)p were measured and compared with a predetermined failure criterion, eg. 5%. If the resistance change is greater than failure criterion, the failure time would be recorded. The EM test was terminated if resistance change was greater than 30% or open-circuited.

EXPERIMENTAL PROCEDURES

Pre-Stressing Annealing Condition

Before carrying out any electrical test, the wafer was annealed at around 200°C for at least 48 hours in order to heal any crystal defect during film deposition.

Stressing Condition

After wafer annealing, the EM tests were performed following a test matrix for a combination of temperature and stress current conditions, as shown in Table 1.

Temp 235°C 245°C 255°C 265°C

This test matrix was applied to two EM test structures with line width of 0.32ym and 0.6ym respectively. "X' represents the EM test condition with at lease 8 test structures being stressed.

The total time required to perform the test matrix as given in Table.1 is quite significant for a statistical acceptable lifetime measurement. The number of test structures to be tested must be well above 100. The actual lifetime of each structure can vary from few minutes to more than 24 hours, depending on the temperature and current setting, the total cycle time for such a matrix can be quite long.

The WET System is capable to perform the accelerated test on multiple test structure simultaneously and results in a much shorter cycle time. It also helps to reduce the effect of external factors on test structures, like unstable chuck temperature and different annealing cycle, since there are more devices being tested under the same stressing conditions. 5% change in resistance is chosen as the test termination criterion.

RESULTS & DISCUSSIONS

Temperature Coefficient of Resistance (TCR)

The test structure resistance and TCR measurements for the 0.32ym and 0.6ym wide test structures are shown in Fig. 3. The average TCR of 0.0036/"C at T(TS)L =30"C is repeatable over all the devices of this study.

158

400 Resistance (ohm)

T C R i 0.00368 I 'C

Re= 184.8 ohm

200

I TCR= 0.00364 1°C Ro= 77.6 ohm

-0.32um - - 0.60um 0 0 50 100 150 200 250

Temperature ("C)

Fig.3 Test structure resistance and TCR from 30-235°C.

Variution of Resistance with Stress Time

At the beginning of experiment, the conventional EM test procedure was followed and the failure criterion was set to 5%. However, as shown in. Fig.4a and 4b, for multilayered interconnect, the variation of resistance with stress time is not a gradual change as usually observed in single layer Al-alloy films. The resistance change is being characterized by some rapid drastically change in resistance of about 2% and then subsequent resistance oscillation. The sudden resistance jump in multilayered interconnect metal lines was attributed to the formation of local gap in the Al-layer. The electrical current was then sustained by the cladding TiN layers with higher resistivity. After a certain time, the resistance jumped back, signifying the A1 gap closing. The A1 gap closing was being induced by the stress gradient induced by A1 electromigration in the edge of the gap to fill up the void and caused the resistance oscillation.[7] A permanent Al- gap was formed if the metal line was stressed for long time, then following by another resistance oscillation again.

Based on the above results, it will be wrong to define the Failure Time of the test structure at the fixed percentage (say 5%) change of resistance from the initial value for the multilayered interconnect metal line. The extracted parameters like activation energy and current factor will be questionable as observed in our initial trials. It is thus more appropriate to use the first resistance-jump (the formation of the first gap in the Al-layer) as the failure criterion for the TiN/AlSiCu/TiN multilayered interconnect. All the subsequent lifetime analysis used this first resistance-jump as the failure criterion.

Mean-Time- To-Failure (MTTF)

MTTF of a test structure at pre-set stress temperature and current density is determined by plotting the Failure Times of several test structures with respect to cumulative percent failures P(t,). A best-fit straight line is then drawn through these data points. The MTTF is given by the intercept at the S O % cumulative failure frequency point, as shown in Fig.5. Table 2 and 3 give a summary of MTTF under different temperature and current density stressing conditions.

1 MlTF (0.32um: T=235C, J=6Wcm2)

I I I a 1 1 ( R - R o y "

' I

Fig.4a Variation of Resistance stressed at T=235'C.

2 4

ins) ~- $ 5 10 15 20 25

-1 - - ~~ -~~~ -~~~

Fig.4b Variation of Resistance stressed at T=265"C.

l o + - -A--- --I - -1 - I '

0 25 50 75 1001 Cumulative Failure P(tf) % -~ - I - - ~ - - - -

Fig.5 Typical log-normal plots of Failure Times against cumulative failure percentage. Test structure=0.3Q~m, T=235"C.

The EM lifetime is longer for 0.6pm metal lines than the 0.32pm test structures at all stress conditions. This is expected from the failure criterion used in our test, the formation of the first gap in the Al-layer. The probability of AI gap formation in wider metal lines is likely much lower than that in narrower metal line.

Table 2: MTTF (mins) of 0.32pm wide device

Temp I 6MA/cm2 7MA/cm2 8MA/cm2 9MA/cm2 Current Density

235°C 334 I 68.8 I 40.8 1 16.8 245°C 162 I 71.5 I 26.8 I 8.8

I I 255°C 1 125 I 41 I 20.8 1 8.05 1

159

265°C ] 62.2 33.5 I 11.3 I 4.84 1 Table 3: MTTF (mins) of 0.60pm wide device

255°C 265°C

Current Density

244 1 95 1 42.2 1 13.65 146 I 50.4 1 32.2 1 12.5

Temp 16MNcm’ 7MA/cm2 8MA/cm2 9MNcm2 235°C I 410 1 117.4 I 72.3 I 26 1 245°C I 290 1 132 1 35 I 21.6 I

Activation Energy E,, & C,urrent Factor n

The effect of self-heating due to stress current to the test structure had been taken into account in the calculation of Eu and n~ Fig.6 shows the typical pllot of ln(M7TF) against l/;r for the extraction of Eu at the corresponding stress current density. Fig.7 shows the comparison of extracted n values at different stress temperature. Table- 4 gives a summary of the E, obtained from the plots of In(MTTF) against l /T:

Table 4: E,(eV) of 0.32pm and 0.6pm devices

J (10’ Ucm’) I 0 . 3 2 p width I 0 . 6 p width 6 I 0.9138eV I 0.7897 eV

I 7 I 0.7108eV I 0.7721 eV I

i 8 I 1.1554eV I 0.7655 eV 9 [ 1.0114eV I 0.8644 eV

The Activation Energy E, and Current Factor n values obtained from this wafer-level EM test for the 0.6pm wide TiN/AlCu/TiN multilayered metal lines from the production line are compatible to those values extracted using the standard package-level method. However the E, and n values for the 0.32pm metal lines are typically higher. There is inherently higher uncertainty extraction of the n-values, especially for narrower metal line. This could be the result of using the average value of resistance for actual stress. temperature correction. He is expected that larger sample size may have improvement in the results. The reason for such variation is still under investigation.

CONCLUSION

An automatic Wafer-level EM Test (WET) system has been developed and its performance has been proven by actual measurement of the lifetime, E, and n-values of submicron multilayered TiN/AICu/TiN metal lines. The results are compatible to the package level EM test for the 0.6pm metal lines and reported results on Al metallization [2,5,6]. For deep sub-micron metallization, our results show that the E, and n-values of 0.32 pm metal lines are higher. The reason for such variation is subjected to further investigation.

REFERENCES

materials, technology, and applications.” Noyes 1993, p. 580.

lo i 9

8 ‘ ~ 1.7 1.72 1.74 1.76 1.78 1.8 1.82 1.84 1

Fig.6 Typical activation energy E, at J=6MA/cm2

4 n 3.2793

2.3496 3

2.541 1 \ 2.2754

‘A ~ ~ .~ -- 1.4085 1 -0- 0.32um

~ -& O60um, Temp. -- - _-- .__ o - - ~

T=235C T=245C T=255C T=265C c _____

Fig.7 Current Factor n at different chuck temperature

2.

3.

4.

5.

6.

7.

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