2009 5th International Colloquium on Signal Processing & Its Applications (CSPA)

DDCC-Based Full-Wave RectifierMontree Kumngem, Pongsakom Saengthong and Somyot Junnapiya

Teleconununications Engineering Department, Faculty of Engineering,King Mongkut's Institute of Teclmology Ladkrabang, Bangkok 10520, Thailand

Tel: +66-2-326 4238, +66-2-326 4242, fax: +66-2-326 4554E-mail: kkmontre@kmitl.ac.th.somyot@telecom.kmitl.ac.th

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Abstraet-A new fuD-wave rectifier circuit employing onlytwo differential difference current conveyors (DDCCs) ispresented. The proposed circuit exhibits high input impedance,good temperature stability and wide bandwidth. It is extremelysimple and compact, and suitable for IC implementation. Thecircuit also offers a low output impedance terminal, which issuitable for low impedance load. The simulation resultsdemonstrate the performance of the proposed circuit.

I. INTRODUCTION

Full-wave rectifier is used in RF demodulator, piecewiselinear function generator, AC voltmeter, watt meter, andvarious nonlinear analog signal processing circuits. A typicalrectifier realizes by using diodes but this device C3lUlot rectifysignals whose amplitudes are less than the threshold voltage(approximately 0.7V for silicon diode and approximately 0.3for gennanium diode). As a result diode-only rectifiers are usedin only those applications in which the precision in the range ofthreshold voltage is insignificant, such as RF demodulators andDC voltage supply rectifiers, but for applications requiringaccuracy the range of threshold voltage the diode-only rectifiercalUlot be used. This can be overcome by using integratedcircuit rectifiers instead. The precision rectifiers based onoperational amplifier (op-amp), diodes and resistors arepresented [1]-[4]. However, the classical problem withconventional precision rectifiers based on op-amps and diodesis that during the non-conduction/conduction transition of thediodes, the op-amps must recover with a finite small-signal,dv/dt, (slew-rate) resulting in significant distortion during therero crossing of the input signal. The use of the high slew-rateop-amps does not solve this problem because it is a smallsignal transient problem. The gain-bandwidth is a parameter ofop-amp that limits the high frequency perfonnance of thisscheme. Moreover, since these structures use the op-amp andthe resistors, it is not suitable for IC fabrication

Second-generation current conveyors (CClls) is possesseda very high slew rate and bandwidth if compared to thetraditional op-amp. This makes the CCII of primary importancein the design of modem analog integrated circuits. Severalcircuits based on CCII for realizing full-wave rectification havebeen proposed in the literature [5]-[11]. The circuits [5]-[7]employ diodes and resistors in addition to CClls. The circuit[8] employs bipolar current mirrors in addition to a CCII and anumber of resistors. The circuit [9] employs four CCClls andresistors. The circuit [10] employs two CCII and two MOStransistors. However, all of these circuits suffer from anexcessive number of active of passive components. Recently,the full-wave rectifier circuit realized by using all MOS

978-1-4244-4152-5/09/$25.00 ©2009 IEEE

transistors has been reported, it is suitable for implementationin monolithic form [11].

In this paper, a new full-wave rectifier circuit using onlytwo DDCCs is presented. The proposed circuit uses a recentlyproposed current conveyor, named differential differencecurrent conveyor (DDCC) [12]. The circuit is simple andsuitable for IC implementation. The circuit also offers high­input and low-output impedance terminals, which is suitablefor low impedance load. Simulation results verifying thetheoretical analysis are also included

IY1_--_VY1 ~ Y1

IY2 IzVY2 ~ Y2 DDCC Z ~ VZ

IY3VY3 ~ Y3 X

jlxVX

Fig. 1. Electrical symbol for DDCC

Voo

z

VB ~It-------""""------H-----II

Vss

Fig. 2. CMOS implementation for DDCC

II. CIRCUIT REALIZATION

The electrical symbol of DDCC is shown in Figure 1. Itwas proposed in 1997 [12] and it enjoys the advantages ofCCII and differential amplifier (DA) such as larger signalbandwidth, greater linearity, wider dynamic range, simplecircuitry, low power consumption, high-input impedance [12].The DDCC has three voltage input terminals: Yt , Yt2 and Y3,

which have high input impedance. Terminal X is a lowimpedance current input terminal. There is a high impedance

current output tenninal Z. The input-output characteristics ofthe DDCC is described as

III. APLICATION EXAMPLE

For application of proposed full-wave rectifier, we describea pseudo root-mean-square (rms)-to-dc conversion. The well­known average value ofa signal magnitude is defmed by

I -I I 0o 0 0 0 VY1

o 0 0 0 VY2

o 0 0 0 VY3

o 0 0 I Ix

(I)

Vavg = '!'fl V(t~dtT 0(4)

Vc

Vout

where V(t) is the ac signal, T is its period., and Vavg is theaverage value of the rectified signal of V(t). To perform thisoperation, the ac signal is frrst full-wave rectified and then low­pass filtered to extract the dc component. For the case of asinusoidal signal we have V(t)=Vrnsin(21tjt), where Vrn is thepeak amplitude andj=l!f is the frequency. Substituting into (4)and integrating yields

2Vavg = - Vm = 0.637Vm

1t(5)

It is customary to calibrate the averaging circuits so that, with asinusoidal input, the rms value is yield:

Substituting V(t)=Vrnsin(21tjt) and solving yields

which is the amount of amplification required to obtain VODS

from Vavg [13].By using proposed full-wave rectifier as building block, a

circuit capable both displaying both average and rms value ofsinusoidal waveforms can be readily implemented., as shown inFigure 4. It is seen that only grounded components arerequired. For more suitable IC implementation, all groundedresistors can be replaced by MOS resistors as presented byWang [12]. A frrst-order low-pass fIlter is achieved with aproperly specified RL and CL . Voltage Vout is converted to theinput current of the fIlter in which the ac components arefIltered through the capacitor CL . Vavg can be obtained bychoosing Rin and RLt identical. According to (8), VODS can beobtained by setting RL2/Rin=1.11. For a symmetrical squareinput, the ratio of (7) becomes unity thus Vavg of Figure 8 givesthe exact rms value because Rin, and RLt are identical. IfRLt /Rin=I.155, the circuit may indicate the ems value for eithersinusoidal or triangular current signals using a switcher. Thecriterion for specifying CL (i.e. CL=CLt =CL2) is that it must belarge enough to keep the residual output ripple within specifiedlimits, or

(8)

(6)

(7)

Vrms =.....!...~I.IIIVavg 2J2

Comparing (5) and (7) we have

(3)

Fig. 3. Proposed full-wave precision rectifier.

Yin > 0 : YOU! : Yin ~ DVCC\ : on} (2)Yin <0 ,Vout -- Vin . DVCC2 -on

Therefore, the proposed circuit provides the full-waverectification. Vc is the auxiliary voltage. It can note fromFigure 3 that the proposed circuit has high-input and low­output impedance, hence it easy to drive loads without using abuffering device.

The complete output voltage of Figure 3 can be expressed as

The output current (IJ follow the input current throughtenninal X. The voltage of X teoninal is related by the threeinputs voltage: Vx=Vyt -Vy2. The CMOS realization of theDDCC used in this paper for the proposed full-wave rectifiercircuit is shown in Figure 2 [12].

Figure 3 shows the proposed full-wave rectifier circuit. Theproposed circuit uses only two DDCCs. The positive outputvoltage of the DDCC t is connected to the negative outputvoltage of the DDCC2. The full-wave operation is as follows:when Vin>O, the voltage Yin is followed by the DDCC t to thevoltage Vout at X teoninal while the DDCC2 is tum-off. Inaddition, when Vin<O, the voltage Yin is followed by theDDCC2 to the voltage Vout at X teoninal while the DDCC t iscut-ofI. From the operation of the proposed full-wave rectifierexplained., the relations between the input voltage, Vin, and theoutput voltage, Vout, can be expressed as

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4(b). MOS resistor using two MOS transistors was presentedby Wang [14]. Assume MR1 and MR2 have the samecharacteristics remaining in the saturation region. Theresistance value of MOS resistor can be expressed as [14]:

(10)

where fin is the low end of the frequency range of interest. CLshould usually exceed the right-hand teon by the inverse of thefractional ripple error that can be tolerated at the output [13].

For more suitable IC implementation, all groundedresistors can be replaced by MOS resistors as shown in Figure

R = 1eq 2K(Voo - Vrn )

(11)

Voo

leqMR2

~ Req

~ veq -MR1

Vss

(b)

Vavg

RllrCll

RL2rCL2

.....---............- .......-0 VrmsVin Y1 Z

Vc Y3DDCC1

Y2 X Z

RiO

""Y3 X Z

Y2 DDCC2

Y1 Z

(a)

Fig. 4. (a) The nns voltage converter for both sinusoidal (output Vnns) and synunetrical square (output Vavg) wavefo~ (b) MOS resistor circuit.

where K=J.lnCox(WIL), J.ln is the carrier mobility, Cox is the gateoxide capacitance per unit area, VTH is the threshold voltageand VDD=I VsJ are the supply voltages. From (9), the value ofresistors can vary by setting the appropriate aspect ratio oftransistors MR1 and MR2.

TABLE IMOSFET MODEL USED rn THE SIMULATION.

.MODEL NMOS LEVEL=3 U0=460.S TOX=1.0E-8 TPG=1VTO=+0.62 JS=1.08E-6 XJ=O.ISU RS=417 RSH=2.73 LD=0.04UVMAX=130E3 NSUB=I.71EI7 PB=O.761 ETA=O.OO THETA=0.129PHI=0.90S GAMMA=O.69 KAPPA=O.IO CJ=76.4E-S MJ=0.3S7CJSW=S.68E-IO MJSW=O.302 CGSO=1.38E-IO CGDO=1.38E-IOCGBO=3.4SE-IO KF=3.07E-28 AF=1 WD=+O.IIU DELTA=+0.42NFS=1.2Ell DELL=OU LIS=2 ISTMP=IO TT=O.IE-9

.MODEL PMOS LEVEL=3 UO=IOO TOX=1.0E-8 TPG=1VTO=-0.S8 JS=0.38E-6 XJ=O.IOU RS=886 RSH=1.81 LD=O.03UVMAX=113E3 NSUB=2.08EI7 PB=0.911 ETA=OO THETA=0.120PHI=0.90S GAMMA=0.76 KAPPA=2 CJ=8SE-S MJ=0.429CJSW=4.67E-IO MJSW=O.631 CGSO=1.38E-IO CGDO=1.38E-IOCGBO=3.4SE-IO KF=1.08E-29 AF=1 WD=+0.14U DELTA=0.81NFS=0.S2Ell DELL=OU LIS=2 ISTMP=IO TT=O.IE

IV. SIMULATION RESULTS

The proposed full-wave rectifier in Figure 3 is simulatedusing PSPICE program to verify the given theoretical analysis.The device model parameters used for the PSPICE simulationare taken from MIETEC 0.5J.lm CMOS process [15] as shownin Table I. The DDCCs are simulated using CMOS structure ofFigure 2. The aspect ratios of the MOS transistors of theCMOS DDCC are given in Table II [15]. The supply voltagesare selected as VDD=-Vss=2.5V and the bias voltage is set asVB=-I.7V. The DC transfer characteristics of the proposed full­wave rectifier are shown in Figure 5, which shows theoperating voltage ranging from -1V to IV of the input voltage.

Applying the frequency of IMHz sine wave at the input ofthe proposed full-wave rectifier, the input and output signals atamplitudes of 200mVpeak and 50mVpeak are shown inFigures 6 and 7, respectively. This results is confmns theoperation that the proposed rectifier can provide the full-waverectification at the input signal amplitude lower than thethreshold voltage of gennanium diode «0.3V) and down to50mVpeak through the amplitude error increases.

TABLE IITRANSISTOR ASPECT RATIOS OF THE USED DDCC.

Transistor W (J.Ull) L (J.Ull)

MI-M4 1.6 1MS-M6 8 1M7-M8 20 1

M9-MIO 29 1MII-MI2 90 1

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vout1 ••IU-r-----~----__r_----~---____:lIo

Vout2.1IiIU-r---::---~-~-__r_-~-_:__-~____,-~-___,

2.5u52.1051.1115 1.5u51U.l---~L---...JI-===~..$L--~L-----'

Is '.5U5o A v U(UOUT)

1.1U'.5UIU+-----__+----........-----+---------t-1.1U -'.5U

o U(UOUT)

1 .. 75U ------ -------:----------------:----------------:-------- -------, , ,, , ,, , ,, , ,, , ,, , ,, , ,, , ,0.51U -------------- ---------------,---------------- ---------------

, ,0.25U - - - - - - - - - - - - - - -'- - - - - - - - - - - - - -~ - - - - - - - - - - - - - -~ - - - - - - - - - - - - - --, ,, ,, ,, ,, ,

, t, ,, ,

Fig. 5. Simulated results for DC transfer characteristic. Fig. 8. Operation of the proposed full-wave rectifier at different temperatures.

IV. CONCLUSIONS

At the frequency of IMHz, we simulate the temperatureperfonnance of the proposed full-wave rectifier in Figure 3 bychanging temperatures from 25°C to 100°C. Figure 8 showsthe output waveform of the proposed rectifier at temperaturesof 25°C, 75°C and 100°C. From simulation results in Figure 8,it shows that the proposed circuit provides excellencetemperature stability. This result is confirms equation (3).

It should be noted that the dc offset voltage at output nodeof proposed rectifier can be adjusted by voltage Vc. If thenegative or positive dc offset voltage is appeared at outputnode, it can eliminate by a bias voltage Vc. This makes thecircuit suitable for application to rms-to-dc conversion.

2.5u52.1051.5u51.005

IU

vout• Vin2.1IiIU~~ ~-~·-__r_-"r'IIttIE'"""-_r__~__~- ~__,.

-1'1IiIU

-2.1IIU+----__+-......a....oII:~-+----+__~""'--__+---___f

Is '.5U5o U(UOUT) A U(UIH)

REFERENCES

[I J J. Peyton, V. Walsh, Analog electronics with op amps: a source book ofpractical circuits, New York, Cambridge University Press, 1993.

[2J R. G. Irvine, Operational amplifier characteristics and applications,New Jersey, Prentice Hall International, 1994.

[3J Z. Wang, "Full-wave precision rectification that is performed in currentdomain and very suitable for CMOS implementation" IEEETransactions on Circuits and Systems-I, vol. 39, pp. 456-462, 1992.

[4J S. J. G. Gift, "A high-performance full-wave rectifier circuit"International Journal ofElectronics, vol. 89, pp. 467-476, 2000.

[5J C. Toumazou, F. J. Lidgey, and S. Chattong, "High frequency currentconveyor precision full-wave rectifier" Electronics Letters, vol. 30, pp.745-746, 1994.

In this paper, a full-wave precision voltage rectificationusing only two DDCCs has been presented. The circuitconfiguration described is very suitable for integrated circuitimplementation in CMOS technology. Compared to [1]-[10],the proposed rectifier is more suitable for IC implementationthan these rectifiers (i.e. it uses only two DDCCs and requiresno resistor). The proposed circuit has high-input and low­output impedance terminals, hence it easy to drive loadswithout using a buffering device. It can be applied in variousnonlinear analog signal processing circuits. The perfonnanceof the proposed circuit is confmned from PSPICE simulationresults. The application of proposed rectifier to pseudo rms-to­dc conversion is also discussed.

2.5u52.11151.5u51.005

IU

vout. Vin511i1U-r--___,.~____,---___;_-~-___:__---_r_____,.~____,

-25111U

-511i1U+----____lr--~'---__+_---_+_-~-+__--____l

Is 0.5U5o U(UOUT) A U(UIH)

Fig. 6. Operation of the proposed full-wave rectifier at 1MHz frequency forV..=200mVpeak.

Fig. 7. Operation of the proposed full-wave rectifier at IMHz frequency forVm=50mVpeak.

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