A Multi-Voltage Reference Source

Filipe G. R. Ramos

FreeScale filipe.ramos@freescale.com

Laércio Caldeira and Tales Cleber Pimenta

UNIFEI caldeira@unifei.edu.br, tales@unifei.edu.br

Abstract

A 3 bits programmable, low drift, high PSRR and high precision voltage reference, optimized to Power Management (PM) applications, is presented. The topology is based on a high performance bandgap voltage reference applied to a non-inverting amplifier stage, which generates an internal voltage reference of 2.4V, isolated by a buffer and derived by resistor dividers, generating eight selectable output voltages from 0 to 2.1V, chosen by an analog multiplexer. It has been successfully verified in a standard 0.35µm CMOS process. The experimental results have confirmed that, for power supply of 3.0V to 3.3V, and -20oC to 80oC temperature range, the programmable output voltage VREF has a worst case precision of ±3%. 1. Introduction

The modern Application Specific Integrated Circuits (ASICs) are systems usually composed by mixed-signal blocks (analog and digital), as shown on Fig. 1 [1]. The analog blocks, in particular, need to be biased by voltage and current references, which accuracy certainly determine the maximum performance of all blocks.

Figure 1 – A Generic Mixed-Signal ASIC [1].

The Power Management (PM) block is typically found on a commercial ASIC, which includes DC/DC converters (linear or switched) supplying regulated voltages for the remaining blocks of the integrated circuit. Nowadays, there are available a large variety of

microprocessors, operating at different core voltages. This work suggests a reference capable to bias multiple voltages to PM block and, as a consequence, the latter can supply 8 different levels of voltage to a microprocessor, as shown on Fig. 1.

The bandgap voltage reference, which was firstly proposed by Widlar [2] and was further developed by Kuijk [3] and Brokaw [4], is the one commonly used in many advanced designs and commercial products since it can provide a predictable reference voltage. Moreover, it is also possible for low dependency of power supply and temperature variations.

In the literatures [5] and [6], four main quality aspects of bandgap references can be found: the mean relative temperature dependency, the accuracy, the output impedance and the power consumption. The mean relative temperature dependency is generally expressed in parts per million per Celsius (ppm/K) and depends on the order of temperature compensation [6]. Depending on the temperature range, first-order compensated references have temperature dependency in 25 – 50ppm/K [7]. With a curvature correction or second-order compensation, the temperature dependency can be decreased to only a few ppm/K [8]. The accuracy is a measure of all the stochastic influences: matching errors of transistors and resistors and the variation of process parameters [8]. As bandgap is a voltage source, its output impedance must be low to have a negligible influence of the load on the reference voltage. Finally, the power consumption has to be low because of self-heating effects, power save (on portable applications) and efficiency.

This paper presents the design of a 3 bits programmable, low drift, high PSRR and high precision voltage reference. Firstly, Section II provides a brief review of bandgap voltage reference concepts, followed by description, specification and design of the chosen topology. Section III provides specification and design of the remaining cells of programmable voltage reference, Section IV presents its simulations and

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measures. Finally, Section V presents the conclusions of this work.

2. Bandgap Voltage Reference

The circuit of Fig. 2 shows a high-performance bandgap reference, chosen to evaluation of this work. Transistors Q1, Q2, M1, M2, and M3 form a VT-based bootstrap current reference, and the generated output current IOUT is mirrored by transistor M4 and it is expressed by Eq. (1) [9], where n is the ratio between transistors Q1 and Q2 (Q3).

( )R

nVI T

OUTln

= (1)

As transistor Q3 is configured as a diode, so VEC3 = VEB3, and current IOUT flows thru resistor xR, the output bandgap voltage can be expressed by Eq. (2) [9], where x is the ratio between resistors R and xR.

( ) ( ) ( ) ( )nxVTTTVTV ToEBoEBbg ln3 +−+= α (2)

Since VEB decreases approximately linearly with temperature at -2mV/K, while VT increases linearly at +86.6µV/K, low temperature dependence Vbg can be obtained by scaling up VT and summing it with VEB, as expressed on Eq. (2). This is done making the derivative of Eq. (2) equal zero, and then the optimum x ratio between resistors R and xR is calculated as:

( ) ( ) ( )nnKV

KmV

nqk

x EB

ln09.23

ln6.86

2

ln=

−−

=−

= µα

(3)

Analyzing the circuit of Fig. 2, observing the VT-based bootstrap current reference, the current mirrors formed by M2, M3 and M4 enforce branch currents IIN = IOUT, equal to a proportional-to-absolute-temperature (PTAT), which are generated by Q1, Q2 and R when VA = VB is enforced by a voltage-clamping. This is achieved when the input stage of an operational amplifier is added to nodes A and B, since it has a very large input resistance. Any mismatch between IIN and IOUT is compensated by the operational amplifier, making control of transistor M1 which operates on saturation region.

Yet, on the circuit of Fig. 2, transistors S1, S2 and capacitor CS form the start-up circuit of bandgap reference. Its principle of working is simple: when VDD is powered up, the equivalent circuit of CS is a short-circuit (considering it initially discharged), turning on S1 and S2, connecting to ground the gates of M2, M3 and M4, and making IIN = IOUT ≠ 0 until reach steady state and nominal value. Then, CS is charged to VDD, turning off S1 and S2, isolating start-up circuit from voltage reference. Transistors S1 and S2 are designed making them matched and operating at saturation region, during start-up time. The startup current for transistors S1 and S2 is calculated using Eq. (4), where tsup is the startup time.

( )( )

sup

22,1 t

VVCI tpDDS

SD

−⋅= (4)

Fig. 2 – Programmable Voltage Reference (Schematics and Micrograph).

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In order to obtain PSRR(s) of bandgap voltage reference, the equivalent AC small-signal circuit of Fig. 3 should be considered.

Observing the circuit of Fig. 3, it is easily demonstrated that PSRR(s) can be expressed by Eq. (5). A capacitor CF is added to Vbg node in order to make zero/pole cancellation, providing a high PSRR, since rds8 >> xR, for a wide frequency range.

Fig. 3 – AC Small-Signal Circuit of Bandgap Reference.

( ) ( )( )

+

+

+⋅+==

m

b

ds

Fds

ds

bg

DD

gCs

xRrxRCrs

xRxRr

svsvsPSRR

1

18

8

8

(5)

As introduced on Section I, the Vbg accuracy is a measure of all the stochastic influences: matching errors of transistors and resistors and the variation of process parameters [8]. The systematic mismatch of transistors and resistors is avoided using common-centroid layout technique [10]. Considering this technique, n = 8 is chosen to be the ratio between bipolar transistors Q1 and Q2 (Q3). Using Eq. (3), the ratio x between resistors R and xR is calculated as x = 11.1. Using Eq. (2), the bandgap output voltage Vbg, considering typical operation at T = 40oC (300K), is calculated:

( ) ( ) ( ) VmmKVbg 300.18ln3136.861.113003132700300 =⋅⋅⋅+−−= µ (6)

The calculated Vbg(300K) = 1.300V is a first-order approximation, since VBE has non-linear behavior at different temperatures, as demonstrated Tsividis [11].

The design of transistors M1 to M4 starts considering the bias current IIN = IOUT of VT-based bootstrap reference. For this, it is necessary to consider not only the cell power dissipation, but also the fact that the current gain of bipolar transistors depends of collector current density [9] and, as a consequence, the matching between Q1, Q2 and Q3 transistors. Based on these considerations, it was chosen IIN = IOUT = IC = 10µA. Then, making VDS1 = VSD3 and matching of

transistors M2, M3 and M4, they are designed considering operation at saturation region, as discussed for transistor M1. This work suggests (W/L)1 = 0.5 and (W/L)2,3,4 = 2.5, considering the chosen technology. Finally, substituting IOUT = 10µA and n = 8 on Eq. (1), it is found R = 5700Ω. R and xR are matched using common-centroid layout technique [10].

Once all MOSFETs and resistors were calculated, the last step is to attribute their real W/L values, based on parameters of chosen CMOS process and references [12] and [13]. For MOSFET mismatching modeling, reference [12] considers two types of parameters: process and electrical. Process parameters are those physically independent that control the electrical behavior of a device (i.e. flatband voltage Vfb, mobility µ, substrate dopant concentration Nsub, length offset ∆L, width offset ∆W, short channel effect Vtl, narrow width effect Vtw, gate oxide thickness tox and source/drain sheet resistance ρsh). Electrical parameters are those of interest of designer (i.e. drain current ID, input voltage VGS, transconductance gm and output conductance go). Considering [12] and (W/L)1 = 0.5, a linear system should be constructed:

2

2222

Dn

tw

twWI

V

Dn

nn

V

W

Dn

n ddI

WLddI

Lσ

σσ=

∆⋅+

∆

⋅∆ (7)

where σID1, σID2, ..., σIDn is a set of nID mismatch standard deviations collected across many dies for many biases and geometries, typically hundreds of combinations, provided by the chosen fabrication process. The terms (dIDn/d∆W)2 and (dIDn/d∆Vtw)2are squares of the sensivities of IDn, related to ∆W and Vtw parameters, numerically evaluated using SPICE (Monte Carlo analysis) at the bias and geometry conditions at which the corresponding σID is measured. Using linear regression, the terms σ∆W and σVtw are calculated.

Considering minimal matching [10] of M1, this mean a 1% mismatch between IIN = IOUT = IC currents (σID = 0.01IC = 100nA), evaluating ((dIDn/d∆W)2 and (dIDn/d∆Vtw)2 normalized to (W/L)4,5 = 0.5 and fabrication process data, it is obtained:

( ) ( )( )

2

2

5.0

22

5.0

2

11

satD

tw

twW

I

LWV

satDV

LWW

satD

ddI

LWddI

Lσ

σσ=

∆⋅+

∆

⋅=

=

∆

(8)

Solving Eq. (22), real W and L values of M1 is obtained. Analogically, considering [12] and (W/L)2,3,4 = 2.5, transistors M2, M3 and M4 should have only ∆W parameter as main contributor of mismatch between IIN = IOUT = IC currents. Real W and L values of M2, M3

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and M4 are obtained using the same procedures made for M1.

For evaluation of p-diffused integrated resistors design, sheet resistance ρ and width offset ∆W process parameters, and their related standard deviations of chosen standard CMOS process, should be considered. The diffused resistor mismatch is expressed by Eq. (9) [13], where σL, σW and σLW are mismatches caused by local variations of L, W and LW, respectively. The terms ∆gx and ∆gy take account of gradient effects found between two matched resistors, separated by orthogonal separations dx and dy.

22222

2

2

2

2

2

2

gyygxxLWWLR dd

LWWLR∆+∆+++= σσσσ

(9)

Yet, [13] shows the condition for minimum mismatch is achieved:

WLW

L

σσ

= (10)

Substituting Eq. (10) on Eq. (9), considering resistors matched using common-centroid technique (∆gx = ∆gy = 0):

LWWRLWWR2

2

2

min2

2

2 σσσ+=

(11)

Also, σLW/LW term should be calculated using Eq. (12):

LWLW2

2

2 σρσ ρ =

(12)

Adopting σW = ∆W, choosing a large enough W and substituting Eq. (12) on Eq. (11), it is checked if desired level of matching was reached. For σR/R = 1%, minimum matching is achieved, for σR/R = 0.1% moderated matching and, for σR/R = 0.01%, critical matching [10]. For bandgap designs, reference [10] recommends moderated matching.

The topology chosen for evaluation of operational amplifier is folded-cascode, whit an additional output common-source stage, as shown on Fig. 4. 3. Programmable Voltage Reference

Considering Fig. 2, the output voltage Vo of non-inverting amplifier stage is expressed as:

bgot

o VPR

RV

+

+=4

41 (13)

On this circuit, the potentiometer Pot calibrates reference voltage Vo to 2.4V, the same can be done by trimming techniques, out of the scope of this work. The output voltage VREF of programmable voltage reference has its accuracy ∆VREF directly dependent of Vo voltage accuracy ∆Vo, expressed by [14]:

2)(

2,

2,

2, efFroaorefoo VTCVVVV ∆+∆+∆+∆=∆ (14)

where ∆Vo,ref is the Vo dependency with bandgap reference, ∆Vo,a the dependency with operational amplifier, ∆Vo,r the dependency whit integrated resistors and potentiometer tolerance and ∆VTCF(eff) the dependency caused by drift, related to circuit effective temperature coefficient.

Fig. 4 – Folded Cascode Operational Amplifier.

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Because the folded-cascode operational amplifier, illustrated on Fig. 4 is designed with a high open-loop voltage gain AO ≥ 100dB, thus it has small offset of its output voltage, so the term ∆Vo,a should be ignored. Also, the potentiometer Pot calibrates reference voltage Vo to 2.4V, so the term ∆Vo,r should be ignored, and Eq. (14) is rewritten on Eq. (15), where TCF(eff) is the programmable voltage reference effective temperature coefficient, Tmax and Tmin the maximum and minimum temperature of operation, respectively.

( ) ( )[ ]2minmax

2

2)(

2, oeffFo

bg

bgefFrefoo VTTTCV

VV

VTCVV ⋅−⋅±+

⋅

∆±=∆+∆=∆ (15)

The analog multiplexer (AMUX) is composed by a decoder 1 of 8, which selects the appropriated analog switch MCH0..7 connected to resistor divider and, as a consequence, the output voltage. Due its simplicity of design, AMUX schematics are not considered on this text. In order to obtain PSRR(s) of programmable voltage reference, the equivalent AC small-signal circuit of Fig. 5 should be considered. The small signal AC model is extracted using the same procedures proposed by [14] for folded-cascode operational amplifier.

Fig. 5 – AC Small-Signal Circuit of Programmable Reference.

Observing the circuit of Fig. 5, it is easily demonstrated that PSRR(s) can be expressed by Eq. (16), where RCH is the selected analog switch equivalent resistance and Rte is expressed by Eq. (17), where 0 ≤ t ≤ 7 is the channel selected by c, b and a bits. A low pass filter composed by resistor RF2 and capacitor CF2 is added to VREF node in order to make zero/pole cancellation, providing a high PSRR, for a wide frequency range. This is very desirable for switched DC/DC converters application, which commercial ICs operate with switching frequencies of 200kHz to 3MHz range. Table I presents the design specifications of programmable voltage reference. They are derived from typical PM applications, which use DC/DC converters.

( ) ( )( ) ( )[ ]22

2

2 11

FFCHgdAte

gdAte

REF

DD CRRsCsR

CsRsvsvsPSRR ++⋅

+== (16)

( )RttRtRRte −+

=8

(17)

TABLE I - ELECTRICAL SPECIFICATIONS Supply Voltage VDD 3.0 3.3 3.6 V Output Voltage

Accuracy ∆VREF -3.0 --- 3.0 %

Dissipated Power Pd --- --- 2.0 mW Op. Temperature T 233 313 393 K Effective Temp.

Coefficient TCF(eff) --- 50 100 ppm/K

Power Supply Rejection Ratio @

100Hz PSRR 40 60 80 dB

4. Simulations and Measurements of Programmable Voltage Reference

Table II shows simulated (S) versus measured points (M) data of bandgap and programmable voltage reference. Laboratory measures were evaluated at -20oC to 80oC due intrinsically limitations of instruments. Electrical simulations were evaluated using HSPICE, with BSIM3v3 model, for TSMC 0.35µm standard CMOS process parameters. Experimental results data show that the circuit closely follows the simulation results and specifications, thus demonstrating its functionality and evaluated equations. The programmable voltage reference has an area of 1880µm x 1170µm. Fig. 6 shows a micrograph of programmable voltage reference.

TABLE II - SIMULATED VS. MEASURED VBG AND VREF

Temp. [oC] -20 0 20 40 60 80 M 1.3173 1.3180 1.3193 1.3195 1.3194 1.3188 Vbg

[V] S 1.3175 1.3187 1.3193 1.3195 1.3194 1.3189 M 298.46 299.17 300.03 300.74 301.35 301.57 VREF

[mV] S 298.16 299.18 300.03 300.74 301.35 301.87

5. Conclusions

This work presented a 3 bits programmable, low drift, high PSRR and high precision voltage reference, optimized for Power Management (PM) applications. The circuit is derived from a high performance bandgap voltage reference, evaluated on standard CMOS 0.35µm process.

The matching of integrated transistors and resistors, using layout and design techniques, were evaluated during the work and, as a consequence, all specifications concerning DC/DC converters applications were attended. The most important specification attended was output voltage accuracy, which certainly determines the maximum performance of all blocks from an ASIC.

REFERENCES

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[1] Philip K. T. Mok and Ka Nang Leung, “Design Considerations on Recent Advanced Low-Voltage Low-Temperature-Coefficient CMOS Bandgap Voltage Reference”, in IEEE Custom Integrated Circuits Conference, pp. 635-642, 2004.

[2] R. J. Widlar, “New Developments in IC Voltage Regulators”, IEEE Journal of Solid-State Circuits, vol. SC-16, pp. 2-7, Feb. 1971.

[3] K. E. Kuijk, “A Precision Voltage Source”, IEEE Journal of Solid-State Circuits, vol. SC-8, pp. 222-226, June 1973.

[4] A. P. Brokaw, “A Simple Three-Terminal IC Bandgap Reference”, IEEE Journal of Solid-State Circuits, vol. SC-9, pp. 388-393, Dec. 1974.

[5] M. Gunawan et al., “A Curvature-Corrected Low-Voltage Bandgap Reference”, IEEE Journal of Solid-State Circuits, vol. 28, pp. 667-670, June 1993.

[6] D. Hammerschmidt et al., “A CMOS Bandgap Reference for Low-Voltage Applications” in Proc. ESSCIRC 1993, Sevilla, Sept. 22-24, pp. 106-109.

[7] P. Miller and D. Moore, “Precision Voltage References”, Analog Application Journal, pp. 1-4, Texas-Instruments, Inc., Nov. 1999.

[8] G. C. M. Meijer, “Bandgap References and Temperature Transducers”, Ph.D. dissertation, Delft University of Technololgy, The Netherlands, 1982.

[9] P. Gray, P. J. Hurst, S. H. Lewis and R. G. Meyer, “Analysis and Design of Analog Integrated Circuits”, 4th Edition, Wiley, 2001.

[10] Alan Hastings, “The Art of Analog Layout”, Prentice-Hall, Inc., 2001.

[11] Y. P. Tsividis, “Accurate Analysis of Temperature Effects in IC-VBE Characteristics with Application to Bandgap Reference Sources”, IEEE Journal of Solid-State Circuits, vol. SC-15, pp. 1076-1084, Dec. 1980.

[12] Patrick G. Drennan, Colin C. McAndrew, “Understanding MOSFET Mismatch for Analog Design”, IEEE Journal of Solid-State Circuits, vol. 38, pp. 450-456, March 2003.

[13] Patrick G. Drennan, “Diffused Resistor Mismatch Modeling and Characterization”, IEEE BCTM 1.3, 1999.

[14] Philip E. Allen and Douglas R. Holberg, “CMOS Analog Circuits Design”, 2nd Edition, Oxford Univertisy Press, Inc., 2000.

[15] Bang S. Lee, “Technical Review of Low Dropout Voltage Regulator Operation and Performance”, Application Report, Texas Instruments, Inc., Aug. 1999.

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