International Conference on Communication and Signal Processing, April 3-5, 20 14, India

Design of Trellis Code Modulation Decoder Using

Hybrid Register Exchange Method

Mrs. Tejaswini Panse, Kshitij Saratkar.

Abstract- This paper presents the technique for designing the

area efficient trellis code modulation encoder and decoder. One

of the best encoding techniques is convolutional encoding as

convolutional encoding improves the error performance of

communicational channel. The trellis code modulation (TCM)

can achieve the better error performance without Bandwidth

expansion. Viterbi decoder is use in Trellis code modulation, to

decode a data which is encoded by a convolutional encoder. Here

TCM encoder and decoder are designed by using Xilinx ISE 13.2 design software and device use is Spartan 6. Proposed technique

is aims to reduce the hardware requires for designing the TCM

decoder by using hybrid register exchange method. Hybrid

register exchange method (HREM) is a combination of the

register exchange method (REM) and Traceback (TB) technique.

HREM is superior as compared to Register Exchange Method

(REM) and Traceback method (TB), where area requires for

designing of survivor memory unit is more as compare to the

proposed technique.

Keywords-trellis code modulation (TCM), Viterbi decoding,

Traceback method, Register Exchange Method, Hybrid Register

Exchange Method.

I. INTRODUCTION

Trellis code modulation (TCM) is combine technique which

is use for both modulation and error correction in digital

communication. Its aim is to achieve the better error

performance without Bandwidth expansion. In Trellis code

modulation convolutional encoder is use for encoding as it

provides the forward error correction, and viterbi decoder (i.e.,

the maximum likelihood decoder) is use to decode and recover

data at receiver end. This algorithm involves large amount of

computation and storage as it involves calculating the branch

costs of a survivor path.

Viterbi decoding was first introduced by Andrew J. Viterbi

in 1967 [ 1]. After that in 197 1 viterbi presents another paper

which mainly focuses on the convolutional code and

maximum likelihood decoder [2]. Other researchers are also

do lot of work for betterment of viterbi decoder. Anh dinh and

xiao hu publish a research paper which gives the concept of

look-up table, where Traceback method is use for designing a

Tejaswini Panse, Assistant Professor in the Department of Electronics Engineering, Yeshwantrao Chavan College of Engineering, an autonomous institute affiliated to Rashtrasant Tukadoji Maharaj Nagpur University, Nagpur, Maharashtra, India. (email: tejaswini.deshmukh@gmail.com)

Kshitij P. Saratkar, M. Tech (student) in VLSI Design from Yeshwantrao Chavan College of Engineering, an autonomous institute affiliated to Rashtrasant Tukadoji Maharaj Nagpur University, Nagpur, Maharashtra, India. (E-mail: kshitijpsaratkar808@gmail.com

978- 1-4799-3358-71 14/$31.00 ©20 14 IEEE

265

survivor memory unit [3]. Dalia A. EI-Dib proposed a register

exchange method (REM) in which separate register is

requiring to each stage [4]. So in case of register exchange

method number of register require are more.

This paper proposes a new technique to design a viterbi

decoder. Here we are using Hybrid Register Exchange Method

(HREM) for memory less operation which is advanced version

of register exchange method. In register exchange method

separate register is used for each stage of viterbi algorithm.

The main drawback of register exchange method is it requires

frequent switching activity while exchanging the decoded data

from one register to other register. This problem can be

resolved by using hybrid register exchange method (HREM)

which is a combination of the register exchange method

(REM) and Traceback (TB) technique to design the survivor

memory unit. Where length of register use is depending on the

number of stages requires for decoding.

Rest of the paper is organised as follows. In section II we deals with design of trellis code modulation encoder. Section III deals with design of TCM decoder i.e. viterbi decoder. Section IV shows the results of TCM encoder and decoder. While section V gives the conclusion of design of TCM encoder and decoder.

II. TCM ENCODER

Fig. I shows the proposed architecture of the TCM encoder.

TCM encoder is mainly consisting of convolutional encoder,

which is use for the forward error correction in the

communicational channel. Convolutional encoder is also

known as trellis encoder. In this method coding gain is

improve by simply increasing the density of constellation

while keeping the mllllmum distance between each

constellation point same.QAM is the method use to modulate

the digital data in to the analog signal.

Fig. I shown is TCM encoder which consists of five inputs

and seven outputs. Main part of a TCM encoder is 1/3

convolutional encoder, which have one bit input and three bits

output. This 3 bit output is depending on the current state and

input applied to the encoder. Let say input ( II ) is applied to

the encoder which gives the outputs ( YO , Y I, Y2 ) which

depend on the current state and input applied to the encoder.

Convolutional encoder is consist of shift register when we

apply one bit data to the convolutional encoder at positive

edge of the clock, at the same time data in the shift register is

shifted by one position and it will give the three bit output[4].

In this way five bit data is encoded in to seven bits in TCM

encoder. which then modulated by QAM modulation in which

+-IEEE Advancing Technology

for Humanity

Ii Y6

14 Yi UNCODED

13 Y4 BITS

12 IY3 I

F> Y2

11 113 CODED cOllloluoonal Yl

Encoder BITS

YO

I

Fig. I. TCM Encoder [3]

each combination of phase and amplitude is one of the 25 for

5-bit patterns. After a convolutional encoding, each symbol

has 7 bits, which requires a 27 point constellation. So distance

between constellations points is reduces and so error occurs in

the transition channel are reduce [3].

A. Convolutional Encoder Architecture

TCM encoder is nothing but the convolutional encoder.

Convolutional encoder is widely use for encoding as it

provides the forward error correction at receiving side. Here

convolutional encoder use is 113 convolutional encoder.

Which have one bit input and three bits output. This 3 bit

output is depending on the current state and input applied to

the encoder. Let's say input ( II ) is applied to the encoder

which gives the outputs (YO , YI, Y2 ) which is depending on

the current state and input applied to the encoder.

Convolutional encoder is consist of shift register when we

apply one bit data to the convolutional encoder at positive

edge of the clock, at the same time data in the shift register is

shifted by one position and it will give the three bit output.

Fig. 2 shows the structure of the proposed convolutional

encoder having constraint length of 5. And output of

convolutional encoder is given by

YO = XO (XOR) Xl

YI = Xl (XOR) X2 (XOR) X3

Y2 = XO (XOR) X2 (XOR) X3

Input data

VI

(-t-.}---------+ V2, V3

Fig. 2. Convolutional Encoder.

III. TCM DECODER

Decoding Unit

Fig. 3. Block diagram of viterbi decoder [5]

TCM decoder is nothing but the viterbi decoder (i.e., the

maximum likelihood decoder). This algorithm involves large

amount of computation and storage as it involves calculating

the branch costs of a survivor path, but inorder to reduce the

hardware requirement of viterbi decoder we are using Hybrid

Register Exchange Method (HREM) to design the survivor

memory unit. In register exchange method separate register is

use for each stage and main drawback of register exchange

method is it requires frequent switching activity while

exchanging the decoded data from one register to other

register. This problem can be resolved by using hybrid register

exchange method. which is combination of the register

exchange method (REM) and Traceback (TB) technique

The block diagram of proposed architecture is shown in

fig. 3. It is consist of branch metric unit (BMU), add compare

select unit (ACSU), survival memory unit (SMU), and a

decoding unit. Branch metric unit (BMU) is use to find

hamming distance of survivor path. ACSU is use to find the

survivor path i.e. path with minimum branch cost. Similarly

survivor memory unit (SMU) is use to decode survivor path

and place the decoded output in the register, Where length of

register is depend on the number of stages require.

A. Branch Metric Unit (Bmu)

BMU is use for calculating the hamming distance of

received sequence. It consist of three input bits (iO , iI, i2) each

of 3-bits which are ranging from -3 to +3, which then

generates eight, 8-bit branch metrics. Where These decision

bits are represented in the two's complement format.

266

+ + + , + + +

BMU

000

BMU

001

BMU

010

BMU

011

BMU

100

BMU

101

..... ,.....

BMU

110

Fig. 4. Schematic of branch metrics unit [5]

TABLE I

BRANCH METRICS TABLE [5]

BMU OOO (io+i1 +i2) 9

BMU 00 1 (io+i1-i2) 3

BMU OlO (io-i1 +i2) 3

BMU 0 1 1 (io-i1-i2) -3

BMU 100 (-io+i1 +i2) 3

BMU 10 1 ( -io+i1-i2) -3

BMU 1 10 (-io-i1+i2) -3

BMU III ( -io-i1-i2) -9

BMU

III

BMU Perfonn additions and subtractions inorder to

generate eight output bit. Table I represents computation

involve in finding the output of the BMU. Fig. 4 shows

schematic of BMU which consist of serial to parallel module

to generate the output of the BMU. These outputs of the BMU

is then applied to the ACSU which is use to find survivor path

i.e. path with minimum hamming distance.

B. Add-Compare-Select Unit (ACSU)

ACSU works in serial architecture style which is consists

of two ACS butterfly units as shown in fig. 5. Butterfly

structure for each state is Depends on structure of

convolutional encoder. ACSU finds the survivor path i.e. path

with minimum cost and other paths are rejected. For fmding

the survivor path for each state, the branch metric BM of a

given transition is added to corresponding path metric (PM).

Fig. 5 shows the structure of butterfly unit where all the

decisions are taken at destination states. Here state p and q

represents the destination state. Addition of path metric and branch metric is done and decision is taken to select survivor

path. This unit requires four adders and two comparators. If

Path Metric is of n bits then all adders and comparators

requires is also n-bits.

C. Decoding Technique

Decoding technique proposed here is hybrid register

exchange method (HREM), which is advanced version of

egister exchange method. In register exchange method

separate register is used for each stage of viterbi algorithm.

The main drawback of register exchange method is it requires

PMO) 1 - 1

Fig. 5. Structure ofbuttertly unit.

I 11 � 1 1011 1 1 000010 1 111011011 1

\ 0 � / � 110110 � 100000010 1

1 01 1 � 1101 r 1 101101 1 \ 111011001 1 1 00 1 1 0000 1 1 000000 1 � 11011000 I

T=2 T=4 T=6 T=8

Fig. 6. Hybrid Register Exchange Approach [5]

frequent switching activity while exchanging the decoded data

from one register to other register. This problem can be

resolved by using hybrid register exchange method (HREM)

which is combination of the register exchange method (REM)

and Traceback (TB) technique. Where initial state is first

traced back through an m cycle, after that content of initial

state is transfer to the current state. Fig. 6 shows the general

working scheme of hybrid register exchange method (HREM).

Where T represents the stage number of viterbi algorithm and

block represents the register which contains decoded data.

IV. RESULTS

A. Convolutional Encoder

Fig. 7 shows the simulation result of 113 convolutional

encoder, in which input data is random bits. When reset is set

to logic one, input register which is shift register is reset to

"00000" and it take the value of input data at every positive

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edge of clock, and output is depend on the content of the input RTL schematic of viterbi decoder using hybrid

register. register exchange method is given in fig 8.

Fig. 7. Simulation Result of convolutional Encoder

B. Add-compare select unit.

Table II gives Device Utilization Summary of the add

compare select unit (ACSU). Were VHDL code is use for

designing the ACSU of viterbi decoder, and Xilinx 13.2

design software is use for simulation where Targeted device

used is XC6SLX 16 which belongs to family Spartan-6.

TABLE II

DEVICE UTILIZATION SUMMARY

Nwnber of Slice LUTs used 167 out of 9 1 12

Nwnber of IOs 179

Number of bonded lOBs 179 out of 232

used

Multiplexers 12

C. Viterbi Decoder

Device Utilization Swnmary of the viterbi decoder is given

in Table III. Were VHDL code is use for designing the viterbi

decoder, and Xilinx 13.2 design software is use for simulation

where Targeted device used is XC6SLX 16 which belongs to

family Spartan-6. TABLE TIT

DEVICE UTILIZATION SUMMARY

Logic Utilization Used Available Utilization

Number of Slice 35 18224 0%

Registers

Number of Slice LUTs 1306 9 1 12 14%

Number of fully used 30 13 1 1 2%

LUT-FF pairs

Number of bonded lOBs 173 232 74%

Number of BUFG 1 16 6%

268

Fig. 8. RTL schematic of Viterbi Decoder

V. CONCLUSION

This paper proposed an improved structure of TCM

decoder, in which we are using hybrid register exchange

method (HREM) which is combination of the register

exchange method (REM) and Traceback (TB) technique. So

from Device utilization summery of viterbi decoder we can

conclude that proposed technique reduces the memory

requirement of viterbi decoder so ultimately area and power of

viterbi decoder is also reduce. Hence proposed TCM decoder

is efficient in area.

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