An open source Verilog front-end for digital design analysis at word level

Minh D. Nguyen*, Quan V. Dangt, Lam S. Nguyen+

School of Electronics and Telecommunications

Hanoi University of Science and Technology, Vietnam

* Email: minh.nguyenduc1@hust.edu.vn t quandvk54@edabk.org + lamnsk54@edabk.org

Abstract-We develop an open source Verilog front-end that compiles a digital circuit design into the circuit description at high level. Such description is a component net-list at a higher level than the gate net-list. In the component net-list, all high level information such as bit vector data-paths, finite state machines and counters are retained. Thus, the proposed front-end is suitable for newly proposed back-end algorithms that use high level information to synthesize, optimize and verify the circuit. Our front-end is able to parse large open-source designs.

Index Terms-Verilog, Ie design, HDL front-end, EDA

I. INTRODUCTION

A digital design analysis framework is often partitioned

into HDL front-ends and analysis back-ends. The Hardware

Description Language (HDL) front-end is used to parse and

convert the designs in Veri log or V HDL into internal data

structure that can be synthesized, optimized and verified by the

back-end algorithms. Due to the high complexity of modern

System on Chips, newly proposed algorithms analyze the

circuit at high level description. Such algorithms [10], [9], [8],

[6], [5], [4], [3] use high level circuit information to further

optimize and verify the circuits. Therefore, the HDL front-end

should be able to retain the high level information such as the

bit vector data-path, the control finite state machine, counter

when compiling the HDL description of the circuit.

There are several proposed front-ends which support high

level circuit information. In the followings, we briefly describe

other compilers. QuteRTL [12] can synthesize the design to

word-level circuit net-list. Although QuteRTL has numerous

advantages, it cannot parse several normal Veri log syntax. For

example, output without driven signal, "if' statement without

"else", "case" syntax without "default", "concatenation" syn­

tax in left-hand side assign and constant without unspecified

the number of bit cause errors. ODIN II [7] is a framework

for Veri log synthesis that allows approach/improvement in

different phases of HDL elaboration. Despite ODIN II can

synthesize designs to a target technology such as FPGA and

ASIC. However, ODIN-II does not accept x and z types and

does not parse Veri log modules in multiple files.

In this work, we propose an open source Verilog front-end

that allow us to compile Veri log 2005 [2] into the internal

data structure describing digital designs at word level. The

proposed framework uses the open source Veri log simulator

Verilator [11] as the language parser that converts the Verilog

978-1-4799-5051-5/14/$31.00 ©2014 IEEE

description into the Abstract Syntax Tree (AST). We then

develop a set of traversal functions that synthesize the AST

into the internal data structure describe the circuit. As same as

Verilator, the proposed front-end can support all synthesizable

Verilog as well as Property Specification Language (PSL),

Synstem Verilog. It is therefore very suitable for digital design

verification framework.

The paper is organized as follow. In Section 2, we describe

the system architecture and the data structure. Section 3

introduces to the system implementation. Section 4 is the

experimental results.

II. ARCHITECTURE AND DATA STRUCTURE

The proposed Verilog front-end is partitioned into two

independent components which are the language parser and

the synthesizer as shown in Figure 1. The language parser

parses the designs in Verilog HDL and constructs the Abstract

Syntax Tree that represents all Verilog language elements.

The synthesizer traverses the AST and converts its nodes into

corresponding circuit components. In the synthesis process,

we are able to retain all high level information such as bit

vector data-paths, the control finite state machines, counters.

In the following sections, we elaborate the AST data structure

and circuit component net-list as well as the operations of the

parser and the synthesizer in more detail.

\---.r Parser l---�

Fig. 1: Verilog front-end architecture

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A. Abstract Syntax Tree

The AST represents the Veri log language elements such

as assignments, always, initial blocks, control statements: if,

case. The AST consists of nodes connected as a tree. The

nodes are stored in the objects of the derived classes of the top

level class AstNode. Each kind of derived classes represents

the corresponding language elements. For example, the class

Astlf represents the Veri log if statement. The AST nodes are

connected as the tree via four member pointers: op1p· .. op4p

which are the addresses of the children nodes. For example,

in the Astlf node, the member op1p points to an object of the

class which stores the conditional Boolean expression of the if

statement. In addition, the member op2p points to the begin­

ning a double linked list of nodes that represent all statements

inside the true branch of the parent Ast1f node. Similarly, the

member op3p stores the list of nodes for statements inside

false branch. The double linked lists are implemented by two

pointers to the next and the previous nodes which represents

the next and previous statements in the same statement block

(surrounded by begin and end keywords). The class AstNode

also includes several key member such as name and type that

are the name and type of the node. Finally, the class AstNode

has five userp pointers that are used to store user's data.

Let us illustrate the AST data structure via an example.

Given a Veri log design in Listing 1, the corresponding AST

is shown in Figure 2. In that AST, node with label ALWAYS

is an object of the class ASTAlways representing the always

statement in lines 5. This ALWAYS node has three children

nodes 1, 2, 3 labeled as ASSIGN, ASSIGN, IF, respectively.

Those nodes 1,2,3 are stored in the doubled linked list pointed

by the member op2p of the ALWAYS node. Note that, in the

figure, the relation between the node ALWAYS and nodes 2, 3

are implicitly given via the next pointers of the doubled linked

list. The node 3 is an object of the class ASTlj representing the

if statement in lines 9. In the node 3, the member op1p points

to its children node 4 representing the conditional Boolean

expression for the if statement. The member op2p points to

the doubled linked list containing two nodes 5, 6 representing

two statements in the true branch of the if statement (lines 10,

11). Lastly, the member op3p points to the node 7 representing

the statement in the false branch (line 13).

1 module example (en, sel, in, f, g);

2 input en,sel;

3 input [2:0] in;

4 output reg [2:0] f,g;

5 always @(en, in, sell

6 begin

7 f=O;

8 g=O;

9 if (en) begin

10 g=3'd4;

11 if (sel) f=3' d5;

12 end

13 else g=3'd7+in;

14 end

15 endmodule

Listing 1: Verilog design example

�_ o_o _ _ 0_ 1 op2p 0 - 0 _ 2 0 - 0 - 0 - - _ _ _ 0 _ 3 � next � - - -next- - ��:

00N���H:j CONSTO

oplp op2p

Fig. 2: AST for Verilog design example

B. Circuit component net-list

op3p

In order to describe digital circuits at a higher level than the

gate level, we use component net-lists. The component net-list

is a directed acyclic graph of components. Each component

can be either an input, an output or a functional block such

as ADDER, SHIFTER, ITE, AND, OR,etc .. The components

are connected via directed signal buses which has certain bit­

width. A functional block defines the functional dependency

of its fanout on its fan-ins. Note that, different from the

gate net-list, the component net-list consists of high level

functional components such as adders, shifters, if-the-else,

etc. In addition, the signals that connected components are

at word-level so that they has bit-width. Components are

stored in objects of derived classes from the abstract class

Component as shown in Figure 3. For instance, the class

ITE (if-then-else) represents a word-level multiplexer, the class

ADD represents an adder. In the class Component, the member

mType is used for the type of components. The component's

name is given by the member mOutputName. The signals

that connect components in the net-list are specified by the

members mFanins and mFanouts.

Fig. 3: Component net-list class diagram

For example, the circuit being shown in Figure 4 includes

three INPUT components, an adder component and an ITE

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(if-then-else) component. The ITE component is named out,

has one fanout which is the OUTPUT component. Moreover, it

has two fan-ins which are the components INPUT and adder.

inl

in2

sel

out

Fig. 4: Component net-list example

C. Verilog parser

In order to parse synthesizable Verilog, we use Verilator,

which is a free Veri log HDL simulator. Verilator compiles

synthesizable Verilog (not test-bench code), plus some PSL,

System Veri log and Synthesis assertions into C++ or SystemC

code. Verilator supports the synthesis subset of Veri log, plus

initial statements, proper blocking/non-blocking assignments,

functions, tasks, multidimensional arrays, and signed num­

bers [11]. Within the scope of the project, we only use

Verilator as the parser. The parser flow is illustrated in Figure

5. Firstly, the parser reads a design which is written in Verilog

then it carries out lexical analysis by Flex and parsing by

Bison. Next, it constructs AST graph for the design.

Verilog design

--+ Lexical analysis

(Lexer) -----+

Parsing (parser)

Fig. 5: The parser flow

D. Synthesizer

--+ AST

graph

The synthesizer converts the AST graph into the component

net-list describing the design circuit. The synthesizer traverses

the AST, visits all AST nodes and converts them into corre­

sponding circuit components. This can be done by extending

the visitor design pattern [1] implemented in the Verilator.

The Figure 6 illustrates Visitor Design Pattern applied to AST

structure. The Verilator implements the visitor design pattern

via two pure virtual methods visit() in the abstract class Visitor

and accept() in the class AstNode. When a new operation on

the AST nodes is added, a concrete class is derived from the

Visitor class and the visit() method is overridden. The accept()

method in the AstNode class is also overridden by the one in

the derived classes which simply calls the visit() method on

the concrete derived instance of the Visitor class hierarchy.

III. SYNTHESIZE ALGORITHM

After the AST is generated, synthesis process will then be

carried out based on the AST traversing in order to convert

AST nodes into corresponding circuit components. Traversing

Visitor '" AstNode

+ Visit(AstNode) + Accept(Visitor)

t \ t '\ AstAnd Visitor AstNot Visitor AstAnd AstNot

+ Visit(AstNode) + Visit(AstNode) + Accept(Visitor) + Accept(Visitor)

Fig. 6: Visitor Design Pattern applied to AST structure

algorithm consists of a set of visit() functions for all types

of AstNode. The algorithm is a Depth-First Search (DFS)

algorithm in which visit function is recursively called. The

function visit() operates on AST nodes. For each node, it will

create the circuit component corresponding to the type of the

node. The created component will be stored in the member

user2p of the AstNode and will be used when the other node

are visited.

In order to create a new component, we need the information

about its name, type, bit-width and fanins. The name, type and

width are stored in the member m_name, m_type and m_ width

of the AstNode, respectively. The fan-ins of the component

have normally been created beforehand when the children

nodes (opIp, op2p, ... ) of the current node are visited. Those

fan-ins are stored in opIp---+user2p, op2p---+user2p, .... When a

node has the children nodes, but the number of fan-ins found

is not enough to create a new component, we must search

the missed fanins. The fanins are search in the nodes which

are in the same branch as the current node, i.e., the nodes

representing statements that are in the same statement block as

the current statement. The searching scope will be gradually

extend to the parent nodes (outside statement blocks) if the

needed fan-in is not found. As consequence, the proposed

algorithm is simpler and faster as we do not need to search

the whole AST to find the fan-ins.

We illustrate the proposed algorithm by the example de­

scribed in Section II-A. The Verilog design is given Listing 1,

its AST is shown in Figure 2. As described in Section II-A, the

ALWAYS node represents always statement in the Verilog code.

In the AST portion beginning from this node, two variables

f and g are assigned values. Therefore, we will create two

components whose names are g and f, respectively.

First, let us create the component g corresponding to the IF

node number 3. As in the children of the node 3, we can find

the nodes 4, 5, 7 corresponding to the condition, true branch

assignment to g and false branch assignment to g, respectively.

Therefore, the ITE component g can be immediately created

with three fan-ins.

Next, to create ITE component f, we must create ITE

component f corresponding to the the IF node number 6. For

the node 6, we can find only two children nodes 8, 9 which

correspond to the condition and the true branch assignment to

f, respectively. Thus, we must search the missing component

corresponding to false branch statement. Firstly, we search the

fan-ins in the brother nodes of the node 6, here is the node

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5. (The node 5 and 6 are in stored in the same double linked

list pointed by op2p). However, the node 5 does not assigned

value to f. Thus, we will continue to search the fan-ins in

the brother nodes of the node 3 which is parent of the node

6 in a similar way. This time, we find the node 1 that assigns

the value to f, and we consider the component created in the

node 1 as the needed fan-in. Therefore, we can create the ITE

component f corresponding to the node 6 and then for the

node 3. Finally, we obtain the circuit component net-list as

shown in Figure 7.

100 111 en sel 101 000

g

f

Fig. 7: Circuit component net-list

IV. RESULT AND EVALUATION

The proposed framework is built by GNU GCC package in

Ubuntu 12.04 with Veri log-Perl, Verilator, Bison, Flex, G++

packages. We tried to synthesize most of Verilog syntax and

four open source designs and obtained the results as shown

in Table II. The Table I demonstrates Verilog structures that

can be compiled. Moreover, in the Table II, the first two

columns illustrate the size of the experimental designs in term

of the lines of code (LOC) and the number of components.

The third column describes the compiling run-time and the

last column shows the compiling memory usage. As shown

in the tables, the proposed front-end can parse and convert

most of Veri log syntax and large designs into data structure at

high-level. We also tried to use QuteRTL [12] and ODIN [7]

to parse experimental designs. However, those tools failed to

compile the designs.

In addition, we develop a testing framework which uses

a equivalence checking tool to validate our synthesizer. The

testing framework is shown in Figure 8. The synthesized com­

ponent net-lists are written as a Verilog structure description

which are used as the implementation design inputs of the

equivalence checking tool. The Verilog designs are used as

the reference design inputs of the equivalence checking tool.

For four above designs, we can formally prove that the result

component net-lists are equivalent to the original designs.

Veri log structure Symbol logical operation !, I I,&& bitwise operation �, &, /\, /\ �

reduction operation &, I, /\, �&, � I , �/\ arithmetic operation +, -, *

shift operation « , » equality operation ==, !=

conditional ?: bit-select [ ]

slice [ : ] concatenation {}

replication {{}} blocking assignment =

non-blocking assignment <= if-then-else

case event-based

TABLE I: Evaluating result

Design LOC Components Runing time Memory usage (s) (KByte)

12C 1239 1149 0.270 4868 MIPS 16-bit 1514 2189 4.580 5172

Viterbi 1331 6364 36.330 7324 Dma_ahb32 10911 12685 266.320 37892

TABLE II: Evaluating result

V. CONCLUSION

We have developed the Verilog front-end that can compile

the Veri log designs into circuit component net-lists at higher

level description than the gate net-list. Our front-end uses

the open source Veri log simulator as the language parser that

convert the Verilog design into Abstract Syntax Tree. Then, the

AST traversal algorithm is proposed to synthesize the AST into

component net-list. The proposed front-end is able to compile

several large open source Verilog designs in a reasonable time.

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EQ?

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