A Power-efficient FPGA-based Mixture-of-Gaussian (MoG) BackgroundSubtraction for Full-HD Resolution

Hamed Tabkhi

Departement of Electrical andComputer EngineeringNortheastern University

Boston (MA), USAEmail: tabkhi@ece.neu.edu

Majid Sabbagh

Departement of Electrical andComputer EngineeringNortheastern University

Boston (MA), USAEmail: msabbagh@ece.neu.edu

Gunar Schirner

Departement of Electrical andComputer EngineeringNortheastern University

Boston (MA), USAEmail: schirner@ece.neu.edu

Abstract—This short paper briefly describes an FPGA-basedrealization of MoG background subtraction operating at full-HD frame resolution. Our HW hand-crafted MoG consists of77 pipeline stages operating at 148.5 MHz implemented on aZynq-7000 SoC. The results very high efficiency with a powerconsumption of less than 500 mW which is 600X more efficientthan an embedded software solution.

I. PRELIMINARIES

Among vision applications, background subtraction is

considered as a primary vision kernel for separating fore-

ground pixels (e.g., moving objects) from the background

scene [1]. Mixture of Gaussian (MoG) is widely used

algorithm for performing background subtraction with fixed

camera position [1][2]. Realization of MoG at Full-HD

(1080*1920 resolution) involves massive computation and

power consumption. Our initial profiling hints that 610

ARM Cortex-A9 cores at 666 MHz clock frequency would

be required for real-time MoG in Full-HD – that clearly

deems infeasible. Hence, customized hardware solutions are

necessary to provide the MoG required processing capability

at full-HD.full HD.

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Figure 1: Adaptive background subtraction by MoG.

In order to realize our efficient hand-crafted MoG solution,

we focus on manual hand-crafted RTL implementation

guided by the system-level specification. Alternatively, High-

Level Synthesis (HLS) tools, e.g., Xilinx Vivado, could be

employed. However, compared to hand-crafted design, HLS

are typically less efficient. We start with an Specificationmodel as a reference design model reflects all system-level

design decisions, as well as functional and non-functional

requirements (e.g., quality). The first stage of RTL design is a

direct translation of specification model into a behavioral RTL

model. To meet the Full-HD timing requirement (148 MHz),

we employ set of optimization techniques including algorithm

tuning, operation width sizing and deep pipe-lining. The final

RTL model includes seven macro stages which are further

divided into 77 Micro stages across 9 macro pipeline stages.

In this work, we mainly focus on the computation aspect

of design. A separate challenge is synchronization between

memory access for Gaussian parameters and streaming pixel

processing, which can be separately explored.

Figure 2: Experiment setup.II. RESULTS

We have implemented our design on the Zynq-7000

SoC XC7Z020-CLG484-1. The MoG design operates on

pixel stream received from the HDMI input interface. After

calculating FG/BG status of individual pixels, the FG mask

is directed to the HDMI output for displaying it on the output

monitor (highlighted in Fig. 2). Our design occupies 38%

of the slices, 8% of DSP blocks and 26% of 36-bit Block-

RAMs of Programmable Logic. Total on-chip system power

consumption of our design is 421 mW in which 92 mW

is consumed by the MoG core, and the remaining power

(329 mW) is consumed for accessing Gaussian parameters.

Overall, our solution consumes 600X less power than an SW

solution based on Cortex-A9 cores.

REFERENCES

[1] S. ching S. Cheung and et al., “Robust techniques for back-ground subtraction in urban traffic video,” SPIE ElectronicImaging, 2007.

[2] C. Stauffer and W. E. L. Grimson, “Adaptive background mix-ture models for real-time tracking,” in IEEE Computer SocietyConference on Computer Vision and Pattern Recognition, vol. 2,1999.

2014 IEEE 22nd International Symposium on Field-Programmable Custom Computing Machines

978-1-4799-5111-6/14 $31.00 © 2014 IEEE

DOI 10.1109/.74

241

2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines

978-1-4799-5111-6/14 $31.00 © 2014 IEEE

DOI 10.1109/FCCM.2014.76

241